1 /* $OpenBSD: devreg.c,v 1.3 2016/03/05 17:16:33 tobiasu Exp $ */
2 /* $NetBSD: devreg.c,v 1.6 2006/03/04 01:13:35 uwe Exp $ */
3
4 /*-
5 * Copyright (c) 2002 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/param.h>
31
32 #include <sh/cache_sh3.h>
33 #include <sh/cache_sh4.h>
34 #include <sh/mmu_sh3.h>
35 #include <sh/mmu_sh4.h>
36 #include <sh/trap.h>
37
38 #include <sh/ubcreg.h>
39 #include <sh/rtcreg.h>
40 #include <sh/tmureg.h>
41
42 /* MMU */
43 uint32_t __sh_PTEH;
44 uint32_t __sh_TTB;
45 uint32_t __sh_TEA;
46 uint32_t __sh_TRA;
47 uint32_t __sh_EXPEVT;
48 uint32_t __sh_INTEVT;
49
50 /* UBC */
51 uint32_t __sh_BARA;
52 uint32_t __sh_BAMRA;
53 uint32_t __sh_BASRA;
54 uint32_t __sh_BBRA;
55 uint32_t __sh_BARB;
56 uint32_t __sh_BAMRB;
57 uint32_t __sh_BASRB;
58 uint32_t __sh_BBRB;
59 uint32_t __sh_BDRB;
60 uint32_t __sh_BDMRB;
61 uint32_t __sh_BRCR;
62
63 /* RTC */
64 uint32_t __sh_R64CNT;
65 uint32_t __sh_RSECCNT;
66 uint32_t __sh_RMINCNT;
67 uint32_t __sh_RHRCNT;
68 uint32_t __sh_RWKCNT;
69 uint32_t __sh_RDAYCNT;
70 uint32_t __sh_RMONCNT;
71 uint32_t __sh_RYRCNT;
72 uint32_t __sh_RSECAR;
73 uint32_t __sh_RMINAR;
74 uint32_t __sh_RHRAR;
75 uint32_t __sh_RWKAR;
76 uint32_t __sh_RDAYAR;
77 uint32_t __sh_RMONAR;
78 uint32_t __sh_RCR1;
79 uint32_t __sh_RCR2;
80
81 /* TMU */
82 uint32_t __sh_TOCR;
83 uint32_t __sh_TSTR;
84 uint32_t __sh_TCOR0;
85 uint32_t __sh_TCNT0;
86 uint32_t __sh_TCR0;
87 uint32_t __sh_TCOR1;
88 uint32_t __sh_TCNT1;
89 uint32_t __sh_TCR1;
90 uint32_t __sh_TCOR2;
91 uint32_t __sh_TCNT2;
92 uint32_t __sh_TCR2;
93 uint32_t __sh_TCPR2;
94
95 #define SH3REG(x) __sh_ ## x = SH3_ ## x
96 #define SH4REG(x) __sh_ ## x = SH4_ ## x
97
98 #define SHREG(x) \
99 do { \
100 /* Exception */ \
101 SH ## x ## REG(TRA); \
102 SH ## x ## REG(EXPEVT); \
103 SH ## x ## REG(INTEVT); \
104 /* UBC */ \
105 SH ## x ## REG(BARA); \
106 SH ## x ## REG(BAMRA); \
107 SH ## x ## REG(BASRA); \
108 SH ## x ## REG(BBRA); \
109 SH ## x ## REG(BARB); \
110 SH ## x ## REG(BAMRB); \
111 SH ## x ## REG(BASRB); \
112 SH ## x ## REG(BBRB); \
113 SH ## x ## REG(BDRB); \
114 SH ## x ## REG(BDMRB); \
115 SH ## x ## REG(BRCR); \
116 /* MMU */ \
117 SH ## x ## REG(PTEH); \
118 SH ## x ## REG(TEA); \
119 SH ## x ## REG(TTB); \
120 /* RTC */ \
121 SH ## x ## REG(R64CNT); \
122 SH ## x ## REG(RSECCNT); \
123 SH ## x ## REG(RMINCNT); \
124 SH ## x ## REG(RHRCNT); \
125 SH ## x ## REG(RWKCNT); \
126 SH ## x ## REG(RDAYCNT); \
127 SH ## x ## REG(RMONCNT); \
128 SH ## x ## REG(RYRCNT); \
129 SH ## x ## REG(RSECAR); \
130 SH ## x ## REG(RMINAR); \
131 SH ## x ## REG(RHRAR); \
132 SH ## x ## REG(RWKAR); \
133 SH ## x ## REG(RDAYAR); \
134 SH ## x ## REG(RMONAR); \
135 SH ## x ## REG(RCR1); \
136 SH ## x ## REG(RCR2); \
137 /* TMU */ \
138 SH ## x ## REG(TOCR); \
139 SH ## x ## REG(TSTR); \
140 SH ## x ## REG(TCOR0); \
141 SH ## x ## REG(TCNT0); \
142 SH ## x ## REG(TCR0); \
143 SH ## x ## REG(TCOR1); \
144 SH ## x ## REG(TCNT1); \
145 SH ## x ## REG(TCR1); \
146 SH ## x ## REG(TCOR2); \
147 SH ## x ## REG(TCNT2); \
148 SH ## x ## REG(TCR2); \
149 SH ## x ## REG(TCPR2); \
150 } while (/*CONSTCOND*/0)
151
152 void
sh_devreg_init(void)153 sh_devreg_init(void)
154 {
155 if (CPU_IS_SH3)
156 SHREG(3);
157
158 if (CPU_IS_SH4)
159 SHREG(4);
160 }
161