1 /* $NetBSD: hd64465pcmcia.c,v 1.36 2023/04/05 21:53:56 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.36 2023/04/05 21:53:56 andvar Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/device.h>
38 #include <sys/kmem.h>
39 #include <sys/kthread.h>
40 #include <sys/boot_flag.h>
41 #include <sys/bus.h>
42
43 #include <uvm/uvm_extern.h>
44
45 #include <machine/intr.h>
46
47 #include <dev/pcmcia/pcmciareg.h>
48 #include <dev/pcmcia/pcmciavar.h>
49 #include <dev/pcmcia/pcmciachip.h>
50
51 #include <sh3/bscreg.h>
52 #include <sh3/mmu.h>
53
54 #include <hpcsh/dev/hd64465/hd64465reg.h>
55 #include <hpcsh/dev/hd64465/hd64465var.h>
56 #include <hpcsh/dev/hd64465/hd64465intcreg.h>
57 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h>
58
59 #include "locators.h"
60
61 #ifdef HD64465PCMCIA_DEBUG
62 #define DPRINTF_ENABLE
63 #define DPRINTF_DEBUG hd64465pcmcia_debug
64 #endif
65 #include <machine/debug.h>
66
67 enum memory_window_16 {
68 MEMWIN_16M_COMMON_0,
69 MEMWIN_16M_COMMON_1,
70 MEMWIN_16M_COMMON_2,
71 MEMWIN_16M_COMMON_3,
72 };
73 #define MEMWIN_16M_MAX 4
74
75 enum hd64465pcmcia_event_type {
76 EVENT_NONE,
77 EVENT_INSERT,
78 EVENT_REMOVE,
79 };
80 #define EVENT_QUEUE_MAX 5
81
82 struct hd64465pcmcia_softc; /* forward declaration */
83
84 struct hd64465pcmcia_window_cookie {
85 bus_space_tag_t wc_tag;
86 bus_space_handle_t wc_handle;
87 int wc_size;
88 int wc_window;
89 };
90
91 struct hd64465pcmcia_channel {
92 struct hd64465pcmcia_softc *ch_parent;
93 device_t ch_pcmcia;
94 int ch_channel;
95
96 /* memory space */
97 bus_space_tag_t ch_memt;
98 bus_space_handle_t ch_memh;
99 bus_addr_t ch_membase_addr;
100 bus_size_t ch_memsize;
101 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX];
102
103 /* I/O space */
104 bus_space_tag_t ch_iot;
105 bus_addr_t ch_iobase;
106 bus_size_t ch_iosize;
107
108 /* card interrupt */
109 int (*ch_ih_card_func)(void *);
110 void *ch_ih_card_arg;
111 int ch_attached;
112 };
113
114 struct hd64465pcmcia_event {
115 int __queued;
116 enum hd64465pcmcia_event_type pe_type;
117 struct hd64465pcmcia_channel *pe_ch;
118 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link;
119 };
120
121 struct hd64465pcmcia_softc {
122 device_t sc_dev;
123 enum hd64465_module_id sc_module_id;
124 int sc_shutdown;
125
126 /* kv mapped Area 5, 6 */
127 vaddr_t sc_area5;
128 vaddr_t sc_area6;
129
130 /* CSC event */
131 lwp_t *sc_event_thread;
132 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX];
133 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head;
134
135 struct hd64465pcmcia_channel sc_ch[2];
136 };
137
138 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
139 struct pcmcia_mem_handle *);
140 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t,
141 struct pcmcia_mem_handle *);
142 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
143 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
144 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int);
145 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
146 bus_size_t, bus_size_t, struct pcmcia_io_handle *);
147 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t,
148 struct pcmcia_io_handle *);
149 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
150 bus_size_t, struct pcmcia_io_handle *, int *);
151 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int);
152 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t);
153 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t);
154 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int);
155 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t,
156 struct pcmcia_function *, int, int (*)(void *), void *);
157 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t,
158 void *);
159
160 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = {
161 hd64465pcmcia_chip_mem_alloc,
162 hd64465pcmcia_chip_mem_free,
163 hd64465pcmcia_chip_mem_map,
164 hd64465pcmcia_chip_mem_unmap,
165 hd64465pcmcia_chip_io_alloc,
166 hd64465pcmcia_chip_io_free,
167 hd64465pcmcia_chip_io_map,
168 hd64465pcmcia_chip_io_unmap,
169 hd64465pcmcia_chip_intr_establish,
170 hd64465pcmcia_chip_intr_disestablish,
171 hd64465pcmcia_chip_socket_enable,
172 hd64465pcmcia_chip_socket_disable,
173 hd64465pcmcia_chip_socket_settype,
174 };
175
176 STATIC int hd64465pcmcia_match(device_t, cfdata_t, void *);
177 STATIC void hd64465pcmcia_attach(device_t, device_t, void *);
178 STATIC int hd64465pcmcia_print(void *, const char *);
179 STATIC int hd64465pcmcia_submatch(device_t, cfdata_t, const int *, void *);
180
181 CFATTACH_DECL_NEW(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc),
182 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL);
183
184 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int);
185 /* hot plug */
186 STATIC void hd64465pcmcia_event_thread(void *);
187 STATIC void __queue_event(struct hd64465pcmcia_channel *,
188 enum hd64465pcmcia_event_type);
189 /* interrupt handler */
190 STATIC int hd64465pcmcia_intr(void *);
191 /* card status */
192 STATIC enum hd64465pcmcia_event_type __detect_card(int);
193 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16);
194 /* bus width */
195 STATIC void __sh_set_bus_width(int, int);
196 /* bus space access */
197 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, uint32_t);
198 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t);
199
200 #define DELAY_MS(x) delay((x) * 1000)
201
202 int
hd64465pcmcia_match(device_t parent,cfdata_t cf,void * aux)203 hd64465pcmcia_match(device_t parent, cfdata_t cf, void *aux)
204 {
205 struct hd64465_attach_args *ha = aux;
206
207 return (ha->ha_module_id == HD64465_MODULE_PCMCIA);
208 }
209
210 void
hd64465pcmcia_attach(device_t parent,device_t self,void * aux)211 hd64465pcmcia_attach(device_t parent, device_t self, void *aux)
212 {
213 struct hd64465_attach_args *ha = aux;
214 struct hd64465pcmcia_softc *sc = device_private(self);
215 int error;
216
217 sc->sc_dev = self;
218 sc->sc_module_id = ha->ha_module_id;
219
220 printf("\n");
221
222 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */
223 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */
224
225 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) {
226 printf("%s: can't map memory.\n", device_xname(self));
227 if (sc->sc_area5)
228 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000,
229 UVM_KMF_VAONLY);
230 if (sc->sc_area6)
231 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000,
232 UVM_KMF_VAONLY);
233
234 return;
235 }
236
237 /* Channel 0/1 common CSC event queue */
238 SIMPLEQ_INIT (&sc->sc_event_head);
239
240 error = kthread_create(PRI_NONE, 0, NULL, hd64465pcmcia_event_thread,
241 sc, &sc->sc_event_thread, "%s", device_xname(self));
242 KASSERT(error == 0);
243
244 hd64465pcmcia_attach_channel(sc, 0);
245 hd64465pcmcia_attach_channel(sc, 1);
246 }
247
248 void
hd64465pcmcia_event_thread(void * arg)249 hd64465pcmcia_event_thread(void *arg)
250 {
251 struct hd64465pcmcia_softc *sc = arg;
252 struct hd64465pcmcia_event *pe;
253 int s;
254
255 while (!sc->sc_shutdown) {
256 tsleep(sc, PWAIT, "CSC wait", 0);
257 s = splhigh();
258 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) {
259 splx(s);
260 switch (pe->pe_type) {
261 default:
262 printf("%s: unknown event.\n", __func__);
263 break;
264 case EVENT_INSERT:
265 DPRINTF("insert event.\n");
266 pcmcia_card_attach(pe->pe_ch->ch_pcmcia);
267 break;
268 case EVENT_REMOVE:
269 DPRINTF("remove event.\n");
270 pcmcia_card_detach(pe->pe_ch->ch_pcmcia,
271 DETACH_FORCE);
272 break;
273 }
274 s = splhigh();
275 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link);
276 pe->__queued = 0;
277 }
278 splx(s);
279 }
280 /* NOTREACHED */
281 }
282
283 int
hd64465pcmcia_print(void * arg,const char * pnp)284 hd64465pcmcia_print(void *arg, const char *pnp)
285 {
286
287 if (pnp)
288 aprint_normal("pcmcia at %s", pnp);
289
290 return (UNCONF);
291 }
292
293 int
hd64465pcmcia_submatch(device_t parent,cfdata_t cf,const int * ldesc,void * aux)294 hd64465pcmcia_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
295 {
296 struct pcmciabus_attach_args *paa = aux;
297 struct hd64465pcmcia_channel *ch =
298 (struct hd64465pcmcia_channel *)paa->pch;
299
300 if (ch->ch_channel == 0) {
301 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] !=
302 PCMCIABUSCF_CONTROLLER_DEFAULT &&
303 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0)
304 return 0;
305 } else {
306 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] !=
307 PCMCIABUSCF_CONTROLLER_DEFAULT &&
308 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1)
309 return 0;
310 }
311 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions;
312
313 return (config_match(parent, cf, aux));
314 }
315
316 void
hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc * sc,int channel)317 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel)
318 {
319 device_t parent = sc->sc_dev;
320 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel];
321 struct pcmciabus_attach_args paa;
322 bus_addr_t baseaddr;
323 uint8_t r;
324 int i;
325
326 ch->ch_parent = sc;
327 ch->ch_channel = channel;
328
329 /*
330 * Continuous 16-MB Area Mode
331 */
332 /* set Continuous 16-MB Area Mode */
333 r = hd64465_reg_read_1(HD64461_PCCGCR(channel));
334 r &= ~HD64461_PCCGCR_MMOD;
335 r |= HD64461_PCCGCR_MMOD_16M;
336 hd64465_reg_write_1(HD64461_PCCGCR(channel), r);
337
338 /* Attibute/Common memory extent */
339 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5;
340
341 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory",
342 baseaddr, 0x01000000); /* 16MB */
343 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000,
344 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh);
345
346 /* Common memory space extent */
347 ch->ch_memsize = 0x01000000;
348 for (i = 0; i < MEMWIN_16M_MAX; i++) {
349 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory",
350 baseaddr + 0x01000000, ch->ch_memsize);
351 }
352
353 /* I/O port extent */
354 ch->ch_iobase = 0;
355 ch->ch_iosize = 0x01000000;
356 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port",
357 baseaddr + 0x01000000 * 2, ch->ch_iosize);
358
359 /* Interrupt */
360 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0,
361 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch);
362
363 paa.paa_busname = "pcmcia";
364 paa.pch = (pcmcia_chipset_handle_t)ch;
365
366 ch->ch_pcmcia = config_found(parent, &paa, hd64465pcmcia_print,
367 CFARGS(.submatch = hd64465pcmcia_submatch));
368
369 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) {
370 ch->ch_attached = 1;
371 pcmcia_card_attach(ch->ch_pcmcia);
372 }
373 }
374
375 int
hd64465pcmcia_intr(void * arg)376 hd64465pcmcia_intr(void *arg)
377 {
378 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg;
379 uint32_t cscr;
380 uint8_t r;
381 int ret = 0;
382
383 cscr = HD64461_PCCCSCR(ch->ch_channel);
384 r = hd64465_reg_read_1(cscr);
385
386 /* clear interrtupt (don't change power switch select) */
387 hd64465_reg_write_1(cscr, r & ~0x40);
388
389 if (r & (0x60 | 0x04/* for memory mapped mode*/)) {
390 if (ch->ch_ih_card_func) {
391 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg);
392 } else {
393 DPRINTF("spurious IREQ interrupt.\n");
394 }
395 }
396
397 if (r & HD64461_PCC0CSCR_P0CDC)
398 __queue_event(ch, __detect_card(ch->ch_channel));
399
400 return (ret);
401 }
402
403 void
__queue_event(struct hd64465pcmcia_channel * ch,enum hd64465pcmcia_event_type type)404 __queue_event(struct hd64465pcmcia_channel *ch,
405 enum hd64465pcmcia_event_type type)
406 {
407 struct hd64465pcmcia_event *pe, *pool;
408 struct hd64465pcmcia_softc *sc = ch->ch_parent;
409 int i;
410 int s = splhigh();
411
412 if (type == EVENT_NONE)
413 goto out;
414
415 pe = 0;
416 pool = sc->sc_event_pool;
417 for (i = 0; i < EVENT_QUEUE_MAX; i++) {
418 if (!pool[i].__queued) {
419 pe = &pool[i];
420 break;
421 }
422 }
423
424 if (pe == 0) {
425 printf("%s: event FIFO overflow (max %d).\n", __func__,
426 EVENT_QUEUE_MAX);
427 goto out;
428 }
429
430 if ((ch->ch_attached && (type == EVENT_INSERT)) ||
431 (!ch->ch_attached && (type == EVENT_REMOVE))) {
432 DPRINTF("spurious CSC interrupt.\n");
433 goto out;
434 }
435
436 ch->ch_attached = (type == EVENT_INSERT);
437 pe->__queued = 1;
438 pe->pe_type = type;
439 pe->pe_ch = ch;
440 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link);
441 wakeup(sc);
442 out:
443 splx(s);
444 }
445
446 /*
447 * Interface for pcmcia driver.
448 */
449 /*
450 * Interrupt.
451 */
452 void *
hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch,struct pcmcia_function * pf,int ipl,int (* ih_func)(void *),void * ih_arg)453 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch,
454 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg)
455 {
456 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
457 int channel = ch->ch_channel;
458 bus_addr_t cscier = HD64461_PCCCSCIER(channel);
459 uint8_t r;
460 int s = splhigh();
461
462 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1,
463 ipl);
464
465 ch->ch_ih_card_func = ih_func;
466 ch->ch_ih_card_arg = ih_arg;
467
468 /* Enable card interrupt */
469 r = hd64465_reg_read_1(cscier);
470 /* set level mode */
471 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK;
472 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL;
473 hd64465_reg_write_1(cscier, r);
474
475 splx(s);
476
477 return (void *)ih_func;
478 }
479
480 void
hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch,void * ih)481 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih)
482 {
483 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
484 int channel = ch->ch_channel;
485 bus_addr_t cscier = HD64461_PCCCSCIER(channel);
486 int s = splhigh();
487 uint8_t r;
488
489 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1,
490 IPL_TTY);
491
492 /* Disable card interrupt */
493 r = hd64465_reg_read_1(cscier);
494 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK;
495 r |= HD64461_PCC0CSCIER_P0IREQE_NONE;
496 hd64465_reg_write_1(cscier, r);
497
498 ch->ch_ih_card_func = 0;
499
500 splx(s);
501 }
502
503 /*
504 * Bus resources.
505 */
506 int
hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch,bus_size_t size,struct pcmcia_mem_handle * pcmhp)507 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
508 struct pcmcia_mem_handle *pcmhp)
509 {
510 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
511
512 pcmhp->memt = ch->ch_memt;
513 pcmhp->addr = ch->ch_membase_addr;
514 pcmhp->memh = ch->ch_memh;
515 pcmhp->size = size;
516 pcmhp->realsize = size;
517
518 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size);
519
520 return (0);
521 }
522
523 void
hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch,struct pcmcia_mem_handle * pcmhp)524 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch,
525 struct pcmcia_mem_handle *pcmhp)
526 {
527 /* NO-OP */
528 }
529
530 int
hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch,int kind,bus_addr_t card_addr,bus_size_t size,struct pcmcia_mem_handle * pcmhp,bus_size_t * offsetp,int * windowp)531 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind,
532 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp,
533 bus_size_t *offsetp, int *windowp)
534 {
535 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
536 struct hd64465pcmcia_window_cookie *cookie;
537 bus_addr_t ofs;
538
539 cookie = kmem_zalloc(sizeof(struct hd64465pcmcia_window_cookie),
540 KM_SLEEP);
541 KASSERT(cookie);
542
543 /* Address */
544 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) {
545 cookie->wc_tag = ch->ch_memt;
546 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr,
547 size, &cookie->wc_handle) != 0)
548 goto bad;
549
550 *offsetp = card_addr;
551 cookie->wc_window = -1;
552 } else {
553 int window = card_addr / ch->ch_memsize;
554 KASSERT(window < MEMWIN_16M_MAX);
555
556 cookie->wc_tag = ch->ch_cmemt[window];
557 ofs = card_addr - window * ch->ch_memsize;
558 if (bus_space_map(cookie->wc_tag, ofs, size, 0,
559 &cookie->wc_handle) != 0)
560 goto bad;
561
562 /* XXX bogus. check window per common memory access. */
563 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window);
564 *offsetp = ofs + 0x01000000; /* skip attribute area */
565 cookie->wc_window = window;
566 }
567 cookie->wc_size = size;
568 *windowp = (int)cookie;
569
570 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ?
571 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size);
572
573 return (0);
574 bad:
575 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size);
576 kmem_free(cookie, sizeof(*cookie));
577
578 return (1);
579 }
580
581 void
hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch,int window)582 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
583 {
584 struct hd64465pcmcia_window_cookie *cookie = (void *)window;
585
586 if (cookie->wc_window != -1)
587 bus_space_unmap(cookie->wc_tag, cookie->wc_handle,
588 cookie->wc_size);
589 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size);
590 kmem_free(cookie, sizeof(*cookie));
591 }
592
593 int
hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch,bus_addr_t start,bus_size_t size,bus_size_t align,struct pcmcia_io_handle * pcihp)594 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
595 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
596 {
597 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
598
599 if (start) {
600 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) {
601 DPRINTF("couldn't map %#lx+%#lx\n", start, size);
602 return (1);
603 }
604 pcihp->addr = pcihp->ioh;
605 DPRINTF("map %#lx+%#lx\n", start, size);
606 } else {
607 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase,
608 ch->ch_iobase + ch->ch_iosize - 1,
609 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) {
610 DPRINTF("couldn't allocate %#lx\n", size);
611 return (1);
612 }
613 pcihp->flags = PCMCIA_IO_ALLOCATED;
614 }
615 DPRINTF("%#lx from %#lx\n", size, pcihp->addr);
616
617 pcihp->iot = ch->ch_iot;
618 pcihp->size = size;
619
620 return (0);
621 }
622
623 int
hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch,int width,bus_addr_t offset,bus_size_t size,struct pcmcia_io_handle * pcihp,int * windowp)624 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width,
625 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp,
626 int *windowp)
627 {
628 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
629 #ifdef HD64465PCMCIA_DEBUG
630 static const char *width_names[] = { "auto", "io8", "io16" };
631 #endif
632
633 __sh_set_bus_width(ch->ch_channel, width);
634
635 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size,
636 width_names[width]);
637
638 return (0);
639 }
640
641 void
hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch,struct pcmcia_io_handle * pcihp)642 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch,
643 struct pcmcia_io_handle *pcihp)
644 {
645
646 if (pcihp->flags & PCMCIA_IO_ALLOCATED)
647 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size);
648 else
649 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size);
650
651 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size);
652 }
653
654 void
hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch,int window)655 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window)
656 {
657 /* nothing to do */
658 }
659
660 /*
661 * Enable/Disable
662 */
663 void
hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch)664 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch)
665 {
666 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
667 int channel = ch->ch_channel;
668 bus_addr_t gcr;
669 uint8_t r;
670
671 DPRINTF("enable channel %d\n", channel);
672 gcr = HD64461_PCCGCR(channel);
673
674 r = hd64465_reg_read_1(gcr);
675 r &= ~HD64461_PCC0GCR_P0PCCT;
676 hd64465_reg_write_1(gcr, r);
677
678 /* Set Common memory area #0. */
679 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0);
680
681 DPRINTF("OK.\n");
682 }
683
684 void
hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch,int type)685 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type)
686 {
687 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
688 int channel = ch->ch_channel;
689 bus_addr_t gcr;
690 uint8_t r;
691
692 DPRINTF("settype channel %d\n", channel);
693 gcr = HD64461_PCCGCR(channel);
694
695 /* Set the card type */
696 r = hd64465_reg_read_1(gcr);
697 if (type == PCMCIA_IFTYPE_IO)
698 r |= HD64461_PCC0GCR_P0PCCT;
699 else
700 r &= ~HD64461_PCC0GCR_P0PCCT;
701 hd64465_reg_write_1(gcr, r);
702
703 DPRINTF("OK.\n");
704 }
705
706 void
hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch)707 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch)
708 {
709 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch;
710 int channel = ch->ch_channel;
711
712 /* dont' disable CSC interrupt */
713 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE);
714 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0);
715 }
716
717 /*
718 * Card detect
719 */
720 enum hd64465pcmcia_event_type
__detect_card(int channel)721 __detect_card(int channel)
722 {
723 uint8_t r;
724
725 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) &
726 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1);
727
728 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) {
729 DPRINTF("remove\n");
730 return EVENT_REMOVE;
731 }
732 if (r == 0) {
733 DPRINTF("insert\n");
734 return EVENT_INSERT;
735 }
736 DPRINTF("transition\n");
737
738 return (EVENT_NONE);
739 }
740
741 /*
742 * Memory window access ops.
743 */
744 void
hd64465pcmcia_memory_window16_switch(int channel,enum memory_window_16 window)745 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window)
746 {
747 bus_addr_t a = HD64461_PCCGCR(channel);
748 uint8_t r;
749
750 r = hd64465_reg_read_1(a);
751 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24);
752
753 switch (window) {
754 case MEMWIN_16M_COMMON_0:
755 break;
756 case MEMWIN_16M_COMMON_1:
757 r |= HD64461_PCCGCR_PA24;
758 break;
759 case MEMWIN_16M_COMMON_2:
760 r |= HD64461_PCCGCR_PA25;
761 break;
762 case MEMWIN_16M_COMMON_3:
763 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24);
764 break;
765 }
766
767 hd64465_reg_write_1(a, r);
768 }
769
770 /*
771 * SH interface.
772 */
773 void
__sh_set_bus_width(int channel,int width)774 __sh_set_bus_width(int channel, int width)
775 {
776 uint16_t r16;
777
778 r16 = _reg_read_2(SH4_BCR2);
779 #ifdef HD64465PCMCIA_DEBUG
780 dbg_bit_print_msg(r16, "BCR2");
781 #endif
782 if (channel == 0) {
783 r16 &= ~((1 << 13)|(1 << 12));
784 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13);
785 } else {
786 r16 &= ~((1 << 11)|(1 << 10));
787 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11);
788 }
789 _reg_write_2(SH4_BCR2, r16);
790 }
791
792 vaddr_t
__sh_hd64465_map_2page(paddr_t pa)793 __sh_hd64465_map_2page(paddr_t pa)
794 {
795 static const uint32_t mode[] =
796 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO };
797 vaddr_t va, v;
798 int i;
799
800 /* allocate kernel virtual */
801 v = va = uvm_km_alloc(kernel_map, 0x03000000, 0, UVM_KMF_VAONLY);
802 if (va == 0) {
803 PRINTF("can't allocate virtual for paddr 0x%08x\n",
804 (unsigned)pa);
805
806 return (0);
807 }
808
809 /* map to physical address with specified memory type. */
810 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) {
811 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) {
812 pmap_kremove(v, 0x03000000);
813 uvm_km_free(kernel_map, v, 0x03000000, UVM_KMF_VAONLY);
814 return (0);
815 }
816 }
817
818 return (v);
819 }
820
821 int
__sh_hd64465_map(vaddr_t va,paddr_t pa,size_t sz,uint32_t flags)822 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, uint32_t flags)
823 {
824 pt_entry_t *pte;
825 paddr_t epa;
826
827 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) &&
828 ((sz & PAGE_MASK) == 0));
829
830 epa = pa + sz;
831 while (pa < epa) {
832 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0);
833 pte = __pmap_kpte_lookup(va);
834 KDASSERT(pte);
835 *pte |= flags; /* PTEA PCMCIA assistant bit */
836 sh_tlb_update(0, va, *pte);
837 pa += PAGE_SIZE;
838 va += PAGE_SIZE;
839 }
840
841 return (0);
842 }
843