| /linux/drivers/reset/sti/ |
| H A D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
20 #define STIH407_PDN_1(_bit) \ argument
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /linux/sound/soc/mediatek/mt8195/ |
| H A D | mt8195-audsys-clk.c | 28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
57 #define GATE_AUD6(_id, _name, _parent, _bit) \ argument
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| /linux/sound/soc/mediatek/mt8188/ |
| H A D | mt8188-audsys-clk.c | 28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
57 #define GATE_AUD6(_id, _name, _parent, _bit) \ argument
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| /linux/sound/soc/mediatek/mt8186/ |
| H A D | mt8186-audsys-clk.c | 27 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
37 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
41 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
44 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
47 #define GATE_AUD2(_id, _name, _parent, _bit) \ argument
|
| /linux/drivers/clk/meson/ |
| H A D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
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| H A D | c3-peripherals.c | 167 #define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ argument
184 #define C3_SYS_GATE(_name, _reg, _bit, _flags) \ argument
188 #define C3_SYS_GATE_RO(_name, _reg, _bit) \ argument
293 #define C3_AXI_GATE(_name, _reg, _bit, _flags) \ argument
561 #define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ argument
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| H A D | gxbb-aoclk.c | 26 #define GXBB_AO_GATE(_name, _bit) \ argument
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| H A D | axg-aoclk.c | 37 #define AXG_AO_GATE(_name, _bit) \ argument
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| H A D | g12a-aoclk.c | 46 #define AXG_AO_GATE(_name, _reg, _bit) \ argument
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| /linux/drivers/clk/renesas/ |
| H A D | rzg2l-cpg.h | 211 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ argument
221 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
224 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ argument
240 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
246 #define DEF_RST(_id, _off, _bit) \ argument
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| /linux/drivers/memory/tegra/ |
| H A D | tegra114.c | 1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \ argument
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| H A D | tegra210.c | 1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ argument
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| H A D | tegra124.c | 1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ argument
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| H A D | tegra30.c | 1189 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ argument
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| /linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-sh7366.c | 108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
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| H A D | clock-sh7343.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
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| H A D | clock-sh7757.c | 62 #define DIV4(_bit, _mask, _flags) \ argument
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| H A D | clock-shx3.c | 61 #define DIV4(_bit, _mask, _flags) \ argument
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| /linux/drivers/clk/mvebu/ |
| H A D | armada-37xx-periph.c | 129 #define PERIPH_GATE(_name, _bit) \ argument
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
|
| /linux/drivers/reset/ |
| H A D | reset-uniphier.c | 27 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
34 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| H A D | mlx5hws_internal.h | 35 #define IS_BIT_SET(_value, _bit) ((_value) & (1ULL << (_bit))) argument
|
| /linux/drivers/pinctrl/mediatek/ |
| H A D | pinctrl-mt2701.c | 30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
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| /linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | clock-sh7264.c | 77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
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| H A D | clock-sh7269.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 91 #define POLICY(_offset, _bit) \ argument
375 #define TRIGGER(_offset, _bit) \ argument
434 #define CCU_LVM_EN(_offset, _bit) \ argument
|