1 //
2 // Copyright 2011,2014,2016 Ettus Research LLC
3 // Copyright 2018 Ettus Research, a National Instruments Company
4 //
5 // SPDX-License-Identifier: GPL-3.0-or-later
6 //
7
8 #include "clock_ctrl.hpp"
9 #include "ad9522_regs.hpp"
10 #include "b100_regs.hpp" //spi slave constants
11 #include <uhd/exception.hpp>
12 #include <uhd/utils/assert_has.hpp>
13 #include <uhd/utils/log.hpp>
14 #include <uhd/utils/math.hpp>
15 #include <uhd/utils/safe_call.hpp>
16 #include <uhdlib/utils/narrow.hpp>
17 #include <stdint.h>
18 #include <boost/format.hpp>
19 #include <algorithm>
20 #include <chrono>
21 #include <thread>
22 #include <utility>
23
24 using namespace uhd;
25
26 /***********************************************************************
27 * Constants
28 **********************************************************************/
29 static const bool ENABLE_THE_TEST_OUT = true;
30 static const double REFERENCE_INPUT_RATE = 10e6;
31
32 /***********************************************************************
33 * Helpers
34 **********************************************************************/
35 template <typename div_type, typename bypass_type>
set_clock_divider(size_t divider,div_type & low,div_type & high,bypass_type & bypass)36 static void set_clock_divider(
37 size_t divider, div_type& low, div_type& high, bypass_type& bypass)
38 {
39 high = divider / 2 - 1;
40 low = divider - high - 2;
41 bypass = (divider == 1) ? 1 : 0;
42 }
43
44 /***********************************************************************
45 * Clock rate calculation stuff:
46 * Using the internal VCO between 1400 and 1800 MHz
47 **********************************************************************/
48 struct clock_settings_type
49 {
50 size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider,
51 chan_divider;
get_n_counterclock_settings_type52 size_t get_n_counter(void) const
53 {
54 return prescaler * b_counter + a_counter;
55 }
get_ref_rateclock_settings_type56 double get_ref_rate(void) const
57 {
58 return REFERENCE_INPUT_RATE * ref_clock_doubler;
59 }
get_vco_rateclock_settings_type60 double get_vco_rate(void) const
61 {
62 return get_ref_rate() / r_counter * get_n_counter();
63 }
get_chan_rateclock_settings_type64 double get_chan_rate(void) const
65 {
66 return get_vco_rate() / vco_divider;
67 }
get_out_rateclock_settings_type68 double get_out_rate(void) const
69 {
70 return get_chan_rate() / chan_divider;
71 }
to_pp_stringclock_settings_type72 std::string to_pp_string(void) const
73 {
74 return str(boost::format(" r_counter: %d\n"
75 " a_counter: %d\n"
76 " b_counter: %d\n"
77 " prescaler: %d\n"
78 " vco_divider: %d\n"
79 " chan_divider: %d\n"
80 " vco_rate: %fMHz\n"
81 " chan_rate: %fMHz\n"
82 " out_rate: %fMHz\n")
83 % r_counter % a_counter % b_counter % prescaler % vco_divider
84 % chan_divider % (get_vco_rate() / 1e6) % (get_chan_rate() / 1e6)
85 % (get_out_rate() / 1e6));
86 }
87 };
88
89 //! gives the greatest divisor of num between 1 and max inclusive
90 template <typename T>
greatest_divisor(T num,T max)91 static inline T greatest_divisor(T num, T max)
92 {
93 for (T i = max; i > 1; i--) {
94 if (num % i == 0) {
95 return i;
96 }
97 }
98 return 1;
99 }
100
101 //! gives the least divisor of num between min and num exclusive
102 template <typename T>
least_divisor(T num,T min)103 static inline T least_divisor(T num, T min)
104 {
105 for (T i = min; i < num; i++) {
106 if (num % i == 0) {
107 return i;
108 }
109 }
110 return 1;
111 }
112
get_clock_settings(double rate)113 static clock_settings_type get_clock_settings(double rate)
114 {
115 clock_settings_type cs;
116 cs.ref_clock_doubler = 2; // always doubling
117 cs.prescaler = 8; // set to 8 when input is under 2400 MHz
118
119 // basic formulas used below:
120 // out_rate*X = ref_rate*Y
121 // X = i*ref_rate/gcd
122 // Y = i*out_rate/gcd
123 // X = chan_div * vco_div * R
124 // Y = P*B + A
125
126 const uint64_t out_rate = uint64_t(rate);
127 const uint64_t ref_rate = uint64_t(cs.get_ref_rate());
128 const size_t gcd =
129 uhd::narrow_cast<size_t>((uhd::math::gcd<size_t>(ref_rate, out_rate)));
130
131 for (size_t i = 1; i <= 100; i++) {
132 const size_t X = size_t(i * ref_rate / gcd);
133 const size_t Y = size_t(i * out_rate / gcd);
134
135 // determine A and B (P is fixed)
136 cs.b_counter = Y / cs.prescaler;
137 cs.a_counter = Y - cs.b_counter * cs.prescaler;
138
139 static const double vco_bound_pad = 100e6;
140 for ( // calculate an r divider that fits into the bounds of the vco
141 cs.r_counter =
142 size_t(cs.get_n_counter() * cs.get_ref_rate() / (1800e6 - vco_bound_pad));
143 cs.r_counter <= size_t(cs.get_n_counter() * cs.get_ref_rate()
144 / (1400e6 + vco_bound_pad))
145 and cs.r_counter > 0;
146 cs.r_counter++) {
147 // determine chan_div and vco_div
148 // and fill in that order of preference
149 cs.chan_divider = greatest_divisor<size_t>(X / cs.r_counter, 32);
150 cs.vco_divider =
151 greatest_divisor<size_t>(X / cs.chan_divider / cs.r_counter, 6);
152
153 // avoid a vco divider of 1 (if possible)
154 if (cs.vco_divider == 1) {
155 cs.vco_divider = least_divisor<size_t>(cs.chan_divider, 2);
156 cs.chan_divider /= cs.vco_divider;
157 }
158
159 UHD_LOGGER_TRACE("B100")
160 << "gcd: " << gcd << " X: " << X << " Y: " << Y << cs.to_pp_string();
161
162 // filter limits on the counters
163 if (cs.vco_divider == 1)
164 continue;
165 if (cs.r_counter >= (1 << 14))
166 continue;
167 if (cs.b_counter == 2)
168 continue;
169 if (cs.b_counter == 1 and cs.a_counter != 0)
170 continue;
171 if (cs.b_counter >= (1 << 13))
172 continue;
173 if (cs.a_counter >= (1 << 6))
174 continue;
175 if (cs.get_vco_rate() > 1800e6 - vco_bound_pad)
176 continue;
177 if (cs.get_vco_rate() < 1400e6 + vco_bound_pad)
178 continue;
179 if (cs.get_out_rate() != rate)
180 continue;
181
182 UHD_LOGGER_TRACE("B100")
183 << "USRP-B100 clock control: " << i << cs.to_pp_string();
184 return cs;
185 }
186 }
187
188 throw uhd::value_error(str(
189 boost::format(
190 "USRP-B100 clock control: could not calculate settings for clock rate %fMHz")
191 % (rate / 1e6)));
192 }
193
~b100_clock_ctrl(void)194 b100_clock_ctrl::~b100_clock_ctrl(void)
195 {
196 /* NOP */
197 }
198
199 /***********************************************************************
200 * Clock Control Implementation
201 **********************************************************************/
202 class b100_clock_ctrl_impl : public b100_clock_ctrl
203 {
204 public:
b100_clock_ctrl_impl(i2c_iface::sptr iface,double master_clock_rate)205 b100_clock_ctrl_impl(i2c_iface::sptr iface, double master_clock_rate)
206 {
207 _iface = iface;
208 _chan_rate = 0.0;
209 _out_rate = 0.0;
210
211 // perform soft-reset
212 _ad9522_regs.soft_reset = 1;
213 this->send_reg(0x000);
214 this->latch_regs();
215 _ad9522_regs.soft_reset = 0;
216
217 // init the clock gen registers
218 _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO;
219 _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; // use status pin
220 _ad9522_regs.status_pin_control = 0x1; // n divider
221 _ad9522_regs.ld_pin_control = 0x00; // dld
222 _ad9522_regs.refmon_pin_control = 0x12; // show ref2
223 _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC;
224
225 this->use_internal_ref();
226
227 this->set_fpga_clock_rate(master_clock_rate); // initialize to something
228
229 this->enable_fpga_clock(true);
230 this->enable_test_clock(ENABLE_THE_TEST_OUT);
231 this->enable_rx_dboard_clock(false);
232 this->enable_tx_dboard_clock(false);
233 }
234
~b100_clock_ctrl_impl(void)235 ~b100_clock_ctrl_impl(void)
236 {
237 UHD_SAFE_CALL(this->enable_test_clock(ENABLE_THE_TEST_OUT);
238 this->enable_rx_dboard_clock(false);
239 this->enable_tx_dboard_clock(false);
240 // this->enable_fpga_clock(false); //FIXME
241 )
242 }
243
244 /***********************************************************************
245 * Clock rate control:
246 * - set clock rate w/ internal VCO
247 * - set clock rate w/ external VCXO
248 **********************************************************************/
set_clock_settings_with_internal_vco(double rate)249 void set_clock_settings_with_internal_vco(double rate)
250 {
251 const clock_settings_type cs = get_clock_settings(rate);
252
253 // set the rates to private variables so the implementation knows!
254 _chan_rate = cs.get_chan_rate();
255 _out_rate = cs.get_out_rate();
256
257 _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2) ? 1 : 0;
258
259 _ad9522_regs.set_r_counter(cs.r_counter);
260 _ad9522_regs.a_counter = cs.a_counter;
261 _ad9522_regs.set_b_counter(cs.b_counter);
262 UHD_ASSERT_THROW(cs.prescaler == 8); // assumes this below:
263 _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9;
264
265 _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL;
266 _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA;
267
268 _ad9522_regs.bypass_vco_divider = 0;
269 switch (cs.vco_divider) {
270 case 1:
271 _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1;
272 break;
273 case 2:
274 _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2;
275 break;
276 case 3:
277 _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3;
278 break;
279 case 4:
280 _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4;
281 break;
282 case 5:
283 _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5;
284 break;
285 case 6:
286 _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6;
287 break;
288 }
289 _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO;
290
291 // setup fpga master clock
292 _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
293 set_clock_divider(cs.chan_divider,
294 _ad9522_regs.divider0_low_cycles,
295 _ad9522_regs.divider0_high_cycles,
296 _ad9522_regs.divider0_bypass);
297
298 // setup codec clock
299 _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS;
300 set_clock_divider(cs.chan_divider,
301 _ad9522_regs.divider1_low_cycles,
302 _ad9522_regs.divider1_high_cycles,
303 _ad9522_regs.divider1_bypass);
304
305 this->send_all_regs();
306 calibrate_now();
307 }
308
set_clock_settings_with_external_vcxo(double rate)309 void set_clock_settings_with_external_vcxo(double rate)
310 {
311 // set the rates to private variables so the implementation knows!
312 _chan_rate = rate;
313 _out_rate = rate;
314
315 _ad9522_regs.enable_clock_doubler = 1; // doubler always on
316 const double ref_rate = REFERENCE_INPUT_RATE * 2;
317
318 // bypass prescaler such that N = B
319 long gcd = uhd::math::gcd(long(ref_rate), long(rate));
320 _ad9522_regs.set_r_counter(int(ref_rate / gcd));
321 _ad9522_regs.a_counter = 0;
322 _ad9522_regs.set_b_counter(int(rate / gcd));
323 _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1;
324
325 // setup external vcxo
326 _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL;
327 _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA;
328 _ad9522_regs.bypass_vco_divider = 1;
329 _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL;
330
331 // setup fpga master clock
332 _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
333 _ad9522_regs.divider0_bypass = 1;
334
335 // setup codec clock
336 _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS;
337 _ad9522_regs.divider1_bypass = 1;
338
339 this->send_all_regs();
340 }
341
set_fpga_clock_rate(double rate)342 void set_fpga_clock_rate(double rate)
343 {
344 if (_out_rate == rate)
345 return;
346 if (rate == 61.44e6)
347 set_clock_settings_with_external_vcxo(rate);
348 else
349 set_clock_settings_with_internal_vco(rate);
350 // clock rate changed! update dboard clocks and FPGA ticks per second
351 set_rx_dboard_clock_rate(rate);
352 set_tx_dboard_clock_rate(rate);
353 }
354
get_fpga_clock_rate(void)355 double get_fpga_clock_rate(void)
356 {
357 return this->_out_rate;
358 }
359
360 /***********************************************************************
361 * FPGA clock enable
362 **********************************************************************/
enable_fpga_clock(bool enb)363 void enable_fpga_clock(bool enb)
364 {
365 _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
366 _ad9522_regs.out0_lvds_power_down = !enb;
367 this->send_reg(0x0F0);
368 this->latch_regs();
369 }
370
371 /***********************************************************************
372 * Special test clock output
373 **********************************************************************/
enable_test_clock(bool enb)374 void enable_test_clock(bool enb)
375 {
376 // setup test clock (same divider as codec clock)
377 _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS;
378 _ad9522_regs.out4_cmos_configuration =
379 (enb) ? ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON
380 : ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF;
381 this->send_reg(0x0F4);
382 this->latch_regs();
383 }
384
385 /***********************************************************************
386 * RX Dboard Clock Control (output 9, divider 3)
387 **********************************************************************/
enable_rx_dboard_clock(bool enb)388 void enable_rx_dboard_clock(bool enb)
389 {
390 _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_LVDS;
391 _ad9522_regs.out9_lvds_power_down = !enb;
392 this->send_reg(0x0F9);
393 this->latch_regs();
394 }
395
get_rx_dboard_clock_rates(void)396 std::vector<double> get_rx_dboard_clock_rates(void)
397 {
398 std::vector<double> rates;
399 for (size_t div = 1; div <= 16 + 16; div++)
400 rates.push_back(this->_chan_rate / div);
401 return rates;
402 }
403
set_rx_dboard_clock_rate(double rate)404 void set_rx_dboard_clock_rate(double rate)
405 {
406 assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
407 _rx_clock_rate = rate;
408 size_t divider = size_t(this->_chan_rate / rate);
409 // set the divider registers
410 set_clock_divider(divider,
411 _ad9522_regs.divider3_low_cycles,
412 _ad9522_regs.divider3_high_cycles,
413 _ad9522_regs.divider3_bypass);
414 this->send_reg(0x199);
415 this->send_reg(0x19a);
416 this->soft_sync();
417 }
418
get_rx_clock_rate(void)419 double get_rx_clock_rate(void)
420 {
421 return _rx_clock_rate;
422 }
423
424 /***********************************************************************
425 * TX Dboard Clock Control (output 6, divider 2)
426 **********************************************************************/
enable_tx_dboard_clock(bool enb)427 void enable_tx_dboard_clock(bool enb)
428 {
429 _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_LVDS;
430 _ad9522_regs.out6_lvds_power_down = !enb;
431 this->send_reg(0x0F6);
432 this->latch_regs();
433 }
434
get_tx_dboard_clock_rates(void)435 std::vector<double> get_tx_dboard_clock_rates(void)
436 {
437 return get_rx_dboard_clock_rates(); // same master clock, same dividers...
438 }
439
set_tx_dboard_clock_rate(double rate)440 void set_tx_dboard_clock_rate(double rate)
441 {
442 assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
443 _tx_clock_rate = rate;
444 size_t divider = size_t(this->_chan_rate / rate);
445 // set the divider registers
446 set_clock_divider(divider,
447 _ad9522_regs.divider2_low_cycles,
448 _ad9522_regs.divider2_high_cycles,
449 _ad9522_regs.divider2_bypass);
450 this->send_reg(0x196);
451 this->send_reg(0x197);
452 this->soft_sync();
453 }
454
get_tx_clock_rate(void)455 double get_tx_clock_rate(void)
456 {
457 return _tx_clock_rate;
458 }
459
460 /***********************************************************************
461 * Clock reference control
462 **********************************************************************/
use_internal_ref(void)463 void use_internal_ref(void)
464 {
465 _ad9522_regs.enable_ref2 = 1;
466 _ad9522_regs.enable_ref1 = 0;
467 _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2;
468 _ad9522_regs.enb_auto_ref_switchover =
469 ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL;
470 this->send_reg(0x01C);
471 this->latch_regs();
472 }
473
use_external_ref(void)474 void use_external_ref(void)
475 {
476 _ad9522_regs.enable_ref2 = 0;
477 _ad9522_regs.enable_ref1 = 1;
478 _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1;
479 _ad9522_regs.enb_auto_ref_switchover =
480 ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL;
481 this->send_reg(0x01C);
482 this->latch_regs();
483 }
484
use_auto_ref(void)485 void use_auto_ref(void)
486 {
487 _ad9522_regs.enable_ref2 = 1;
488 _ad9522_regs.enable_ref1 = 1;
489 _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1;
490 _ad9522_regs.enb_auto_ref_switchover =
491 ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO;
492 this->send_reg(0x01C);
493 this->latch_regs();
494 }
495
get_locked(void)496 bool get_locked(void)
497 {
498 static const uint8_t addr = 0x01F;
499 uint32_t reg = this->read_reg(addr);
500 _ad9522_regs.set_reg(addr, reg);
501 return _ad9522_regs.digital_lock_detect != 0;
502 }
503
504 private:
505 i2c_iface::sptr _iface;
506 ad9522_regs_t _ad9522_regs;
507 double _out_rate; // rate at the fpga and codec
508 double _chan_rate; // rate before final dividers
509 double _rx_clock_rate, _tx_clock_rate;
510
latch_regs(void)511 void latch_regs(void)
512 {
513 _ad9522_regs.io_update = 1;
514 this->send_reg(0x232);
515 }
516
send_reg(uint16_t addr)517 void send_reg(uint16_t addr)
518 {
519 uint32_t reg = _ad9522_regs.get_write_reg(addr);
520 UHD_LOGGER_TRACE("B100") << "clock control write reg: " << std::hex << reg;
521 byte_vector_t buf;
522 buf.push_back(uint8_t(reg >> 16));
523 buf.push_back(uint8_t(reg >> 8));
524 buf.push_back(uint8_t(reg & 0xff));
525
526 _iface->write_i2c(0x5C, buf);
527 }
528
read_reg(uint16_t addr)529 uint8_t read_reg(uint16_t addr)
530 {
531 byte_vector_t buf;
532 buf.push_back(uint8_t(addr >> 8));
533 buf.push_back(uint8_t(addr & 0xff));
534 _iface->write_i2c(0x5C, buf);
535
536 buf = _iface->read_i2c(0x5C, 1);
537
538 return uint32_t(buf[0] & 0xFF);
539 }
540
calibrate_now(void)541 void calibrate_now(void)
542 {
543 // vco calibration routine:
544 _ad9522_regs.vco_calibration_now = 0;
545 this->send_reg(0x18);
546 this->latch_regs();
547 _ad9522_regs.vco_calibration_now = 1;
548 this->send_reg(0x18);
549 this->latch_regs();
550 // wait for calibration done:
551 static const uint8_t addr = 0x01F;
552 for (size_t ms10 = 0; ms10 < 100; ms10++) {
553 std::this_thread::sleep_for(std::chrono::milliseconds(10));
554 uint32_t reg = read_reg(addr);
555 _ad9522_regs.set_reg(addr, reg);
556 if (_ad9522_regs.vco_calibration_finished)
557 goto wait_for_ld;
558 }
559 UHD_LOGGER_ERROR("B100") << "USRP-B100 clock control: VCO calibration timeout";
560 wait_for_ld:
561 // wait for digital lock detect:
562 for (size_t ms10 = 0; ms10 < 100; ms10++) {
563 std::this_thread::sleep_for(std::chrono::milliseconds(10));
564 uint32_t reg = read_reg(addr);
565 _ad9522_regs.set_reg(addr, reg);
566 if (_ad9522_regs.digital_lock_detect)
567 return;
568 }
569 UHD_LOGGER_ERROR("B100") << "USRP-B100 clock control: lock detection timeout";
570 }
571
soft_sync(void)572 void soft_sync(void)
573 {
574 _ad9522_regs.soft_sync = 1;
575 this->send_reg(0x230);
576 this->latch_regs();
577 _ad9522_regs.soft_sync = 0;
578 this->send_reg(0x230);
579 this->latch_regs();
580 }
581
send_all_regs(void)582 void send_all_regs(void)
583 {
584 // setup a list of register ranges to write
585 typedef std::pair<uint16_t, uint16_t> range_t;
586 static const std::vector<range_t> ranges{range_t(0x000, 0x000),
587 range_t(0x010, 0x01F),
588 range_t(0x0F0, 0x0FD),
589 range_t(0x190, 0x19B),
590 range_t(0x1E0, 0x1E1),
591 range_t(0x230, 0x230)};
592
593 // write initial register values and latch/update
594 for (const range_t& range : ranges) {
595 for (uint16_t addr = range.first; addr <= range.second; addr++) {
596 this->send_reg(addr);
597 }
598 }
599 this->latch_regs();
600 }
601 };
602
603 /***********************************************************************
604 * Clock Control Make
605 **********************************************************************/
make(i2c_iface::sptr iface,double master_clock_rate)606 b100_clock_ctrl::sptr b100_clock_ctrl::make(
607 i2c_iface::sptr iface, double master_clock_rate)
608 {
609 return sptr(new b100_clock_ctrl_impl(iface, master_clock_rate));
610 }
611