1 /* $OpenBSD: pci_machdep.c,v 1.89 2025/01/23 11:24:34 kettenis Exp $ */
2 /* $NetBSD: pci_machdep.c,v 1.28 1997/06/06 23:29:17 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1997 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
36 * Copyright (c) 1994 Charles Hannum. All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 * 3. All advertising materials mentioning features or use of this software
47 * must display the following acknowledgement:
48 * This product includes software developed by Charles Hannum.
49 * 4. The name of the author may not be used to endorse or promote products
50 * derived from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 */
63
64 /*
65 * Machine-specific functions for PCI autoconfiguration.
66 *
67 * On PCs, there are two methods of generating PCI configuration cycles.
68 * We try to detect the appropriate mechanism for this machine and set
69 * up a few function pointers to access the correct method directly.
70 *
71 * The configuration method can be hard-coded in the config file by
72 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
73 * as defined section 3.6.4.1, `Generating Configuration Cycles'.
74 */
75
76 #include <sys/param.h>
77 #include <sys/time.h>
78 #include <sys/systm.h>
79 #include <sys/errno.h>
80 #include <sys/device.h>
81 #include <sys/extent.h>
82 #include <sys/malloc.h>
83
84 #include <uvm/uvm_extern.h>
85
86 #include <machine/bus.h>
87 #include <machine/pio.h>
88 #include <machine/i8259.h>
89 #include <machine/biosvar.h>
90
91 #include "bios.h"
92 #if NBIOS > 0
93 extern bios_pciinfo_t *bios_pciinfo;
94 #endif
95
96 #include <dev/isa/isavar.h>
97 #include <dev/pci/pcivar.h>
98 #include <dev/pci/pcireg.h>
99 #include <dev/pci/pcidevs.h>
100 #include <dev/pci/ppbreg.h>
101
102 #include "ioapic.h"
103
104 #include <machine/i82093var.h>
105 #include <machine/i82489reg.h>
106 #include <machine/i82489var.h>
107 #if NIOAPIC > 0
108 #include <machine/mpbiosvar.h>
109 #endif
110
111 #include "pcibios.h"
112 #if NPCIBIOS > 0
113 #include <i386/pci/pcibiosvar.h>
114 #endif
115
116 int pci_mode = -1;
117
118 /*
119 * Memory Mapped Configuration space access.
120 *
121 * Since mapping the whole configuration space will cost us up to
122 * 256MB of kernel virtual memory, we use separate mappings per bus.
123 * The mappings are created on-demand, such that we only use kernel
124 * virtual memory for busses that are actually present.
125 */
126 bus_addr_t pci_mcfg_addr;
127 int pci_mcfg_min_bus, pci_mcfg_max_bus;
128 bus_space_tag_t pci_mcfgt = I386_BUS_SPACE_MEM;
129 bus_space_handle_t pci_mcfgh[256];
130 void pci_mcfg_map_bus(int);
131
132 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH);
133
134 #define PCI_CONF_LOCK() \
135 do { \
136 mtx_enter(&pci_conf_lock); \
137 } while (0)
138
139 #define PCI_CONF_UNLOCK() \
140 do { \
141 mtx_leave(&pci_conf_lock); \
142 } while (0)
143
144 #define PCI_MODE1_ENABLE 0x80000000UL
145 #define PCI_MODE1_ADDRESS_REG 0x0cf8
146 #define PCI_MODE1_DATA_REG 0x0cfc
147
148 #define PCI_MODE2_ENABLE_REG 0x0cf8
149 #define PCI_MODE2_FORWARD_REG 0x0cfa
150
151 #define _m1tag(b, d, f) \
152 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8))
153 #define _qe(bus, dev, fcn, vend, prod) \
154 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)}
155 struct {
156 u_int32_t tag;
157 pcireg_t id;
158 } pcim1_quirk_tbl[] = {
159 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1),
160 /* XXX Triflex2 not tested */
161 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2),
162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4),
163 /* Triton needed for Connectix Virtual PC */
164 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
165 /* Connectix Virtual PC 5 has a 440BX */
166 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
167 {0, 0xffffffff} /* patchable */
168 };
169 #undef _m1tag
170 #undef _qe
171
172 /*
173 * PCI doesn't have any special needs; just use the generic versions
174 * of these functions.
175 */
176 struct bus_dma_tag pci_bus_dma_tag = {
177 NULL, /* _cookie */
178 _bus_dmamap_create,
179 _bus_dmamap_destroy,
180 _bus_dmamap_load,
181 _bus_dmamap_load_mbuf,
182 _bus_dmamap_load_uio,
183 _bus_dmamap_load_raw,
184 _bus_dmamap_unload,
185 _bus_dmamap_sync,
186 _bus_dmamem_alloc,
187 _bus_dmamem_alloc_range,
188 _bus_dmamem_free,
189 _bus_dmamem_map,
190 _bus_dmamem_unmap,
191 _bus_dmamem_mmap,
192 };
193
194 void
pci_mcfg_init(bus_space_tag_t iot,bus_addr_t addr,int segment,int min_bus,int max_bus)195 pci_mcfg_init(bus_space_tag_t iot, bus_addr_t addr, int segment,
196 int min_bus, int max_bus)
197 {
198 if (segment == 0) {
199 pci_mcfgt = iot;
200 pci_mcfg_addr = addr;
201 pci_mcfg_min_bus = min_bus;
202 pci_mcfg_max_bus = max_bus;
203 }
204 }
205
206 pci_chipset_tag_t
pci_lookup_segment(int segment,int bus)207 pci_lookup_segment(int segment, int bus)
208 {
209 KASSERT(segment == 0);
210 return NULL;
211 }
212
213 void
pci_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)214 pci_attach_hook(struct device *parent, struct device *self,
215 struct pcibus_attach_args *pba)
216 {
217 pci_chipset_tag_t pc = pba->pba_pc;
218 pcitag_t tag;
219 pcireg_t id, class;
220
221 #if NBIOS > 0
222 if (pba->pba_bus == 0)
223 printf(": configuration mode %d (%s)",
224 pci_mode, (bios_pciinfo?"bios":"no bios"));
225 #else
226 if (pba->pba_bus == 0)
227 printf(": configuration mode %d", pci_mode);
228 #endif
229
230 if (pba->pba_bus != 0)
231 return;
232
233 /*
234 * Machines that use the non-standard method of generating PCI
235 * configuration cycles are way too old to support MSI.
236 */
237 if (pci_mode == 2)
238 return;
239
240 /*
241 * In order to decide whether the system supports MSI we look
242 * at the host bridge, which should be device 0 function 0 on
243 * bus 0. It is better to not enable MSI on systems that
244 * support it than the other way around, so be conservative
245 * here. So we don't enable MSI if we don't find a host
246 * bridge there. We also deliberately don't enable MSI on
247 * chipsets from low-end manufacturers like VIA and SiS.
248 */
249 tag = pci_make_tag(pc, 0, 0, 0);
250 id = pci_conf_read(pc, tag, PCI_ID_REG);
251 class = pci_conf_read(pc, tag, PCI_CLASS_REG);
252
253 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
254 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST)
255 return;
256
257 switch (PCI_VENDOR(id)) {
258 case PCI_VENDOR_INTEL:
259 /*
260 * For Intel platforms, MSI support was introduced
261 * with the new Pentium 4 processor interrupt delivery
262 * mechanism, so we blacklist all PCI chipsets that
263 * support Pentium III and earlier CPUs.
264 */
265 switch (PCI_PRODUCT(id)) {
266 case PCI_PRODUCT_INTEL_PCMC: /* 82434LX/NX */
267 case PCI_PRODUCT_INTEL_82437FX:
268 case PCI_PRODUCT_INTEL_82437MX:
269 case PCI_PRODUCT_INTEL_82437VX:
270 case PCI_PRODUCT_INTEL_82439HX:
271 case PCI_PRODUCT_INTEL_82439TX:
272 case PCI_PRODUCT_INTEL_82440BX:
273 case PCI_PRODUCT_INTEL_82440BX_AGP:
274 case PCI_PRODUCT_INTEL_82440MX_HB:
275 case PCI_PRODUCT_INTEL_82441FX:
276 case PCI_PRODUCT_INTEL_82443BX:
277 case PCI_PRODUCT_INTEL_82443BX_AGP:
278 case PCI_PRODUCT_INTEL_82443BX_NOAGP:
279 case PCI_PRODUCT_INTEL_82443GX:
280 case PCI_PRODUCT_INTEL_82443LX:
281 case PCI_PRODUCT_INTEL_82443LX_AGP:
282 case PCI_PRODUCT_INTEL_82810_HB:
283 case PCI_PRODUCT_INTEL_82810E_HB:
284 case PCI_PRODUCT_INTEL_82815_HB:
285 case PCI_PRODUCT_INTEL_82820_HB:
286 case PCI_PRODUCT_INTEL_82830M_HB:
287 case PCI_PRODUCT_INTEL_82840_HB:
288 break;
289 default:
290 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED;
291 break;
292 }
293 break;
294 case PCI_VENDOR_NVIDIA:
295 /*
296 * Since NVIDIA chipsets are completely undocumented,
297 * we have to make a guess here. We assume that all
298 * chipsets that support PCIe include support for MSI,
299 * since support for MSI is mandated by the PCIe
300 * standard.
301 */
302 switch (PCI_PRODUCT(id)) {
303 case PCI_PRODUCT_NVIDIA_NFORCE_PCHB:
304 case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB:
305 break;
306 default:
307 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED;
308 break;
309 }
310 break;
311 case PCI_VENDOR_AMD:
312 /*
313 * The AMD-750 and AMD-760 chipsets don't support MSI.
314 */
315 switch (PCI_PRODUCT(id)) {
316 case PCI_PRODUCT_AMD_SC751_SC:
317 case PCI_PRODUCT_AMD_761_PCHB:
318 case PCI_PRODUCT_AMD_762_PCHB:
319 break;
320 default:
321 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED;
322 break;
323 }
324 break;
325 }
326
327 /* Enable MSI for QEMU */
328 id = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG);
329 if (PCI_VENDOR(id) == PCI_VENDOR_QUMRANET)
330 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED;
331
332 /*
333 * Don't enable MSI on a HyperTransport bus. In order to
334 * determine that bus 0 is a HyperTransport bus, we look at
335 * device 24 function 0, which is the HyperTransport
336 * host/primary interface integrated on most 64-bit AMD CPUs.
337 * If that device has a HyperTransport capability, bus 0 must
338 * be a HyperTransport bus and we disable MSI.
339 */
340 tag = pci_make_tag(pc, 0, 24, 0);
341 if (pci_get_capability(pc, tag, PCI_CAP_HT, NULL, NULL))
342 pba->pba_flags &= ~PCI_FLAGS_MSI_ENABLED;
343 }
344
345 int
pci_bus_maxdevs(pci_chipset_tag_t pc,int busno)346 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
347 {
348
349 /*
350 * Bus number is irrelevant. If Configuration Mechanism 2 is in
351 * use, can only have devices 0-15 on any bus. If Configuration
352 * Mechanism 1 is in use, can have devices 0-31 (i.e. the `normal'
353 * range).
354 */
355 if (pci_mode == 2)
356 return (16);
357 else
358 return (32);
359 }
360
361 pcitag_t
pci_make_tag(pci_chipset_tag_t pc,int bus,int device,int function)362 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
363 {
364 pcitag_t tag;
365
366 switch (pci_mode) {
367 case 1:
368 if (bus >= 256 || device >= 32 || function >= 8)
369 panic("pci_make_tag: bad request");
370
371 tag.mode1 = PCI_MODE1_ENABLE |
372 (bus << 16) | (device << 11) | (function << 8);
373 break;
374 case 2:
375 if (bus >= 256 || device >= 16 || function >= 8)
376 panic("pci_make_tag: bad request");
377
378 tag.mode2.port = 0xc000 | (device << 8);
379 tag.mode2.enable = 0xf0 | (function << 1);
380 tag.mode2.forward = bus;
381 break;
382 default:
383 panic("pci_make_tag: mode not configured");
384 }
385
386 return tag;
387 }
388
389 void
pci_decompose_tag(pci_chipset_tag_t pc,pcitag_t tag,int * bp,int * dp,int * fp)390 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
391 {
392 switch (pci_mode) {
393 case 1:
394 if (bp != NULL)
395 *bp = (tag.mode1 >> 16) & 0xff;
396 if (dp != NULL)
397 *dp = (tag.mode1 >> 11) & 0x1f;
398 if (fp != NULL)
399 *fp = (tag.mode1 >> 8) & 0x7;
400 break;
401 case 2:
402 if (bp != NULL)
403 *bp = tag.mode2.forward & 0xff;
404 if (dp != NULL)
405 *dp = (tag.mode2.port >> 8) & 0xf;
406 if (fp != NULL)
407 *fp = (tag.mode2.enable >> 1) & 0x7;
408 break;
409 default:
410 panic("pci_decompose_tag: mode not configured");
411 }
412 }
413
414 int
pci_conf_size(pci_chipset_tag_t pc,pcitag_t tag)415 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag)
416 {
417 int bus;
418
419 if (pci_mcfg_addr) {
420 pci_decompose_tag(pc, tag, &bus, NULL, NULL);
421 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus)
422 return PCIE_CONFIG_SPACE_SIZE;
423 }
424
425 return PCI_CONFIG_SPACE_SIZE;
426 }
427
428 void
pci_mcfg_map_bus(int bus)429 pci_mcfg_map_bus(int bus)
430 {
431 if (pci_mcfgh[bus])
432 return;
433
434 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20,
435 0, &pci_mcfgh[bus]))
436 panic("pci_conf_read: cannot map mcfg space");
437 }
438
439 pcireg_t
pci_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)440 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
441 {
442 pcireg_t data;
443 int bus;
444
445 KASSERT((reg & 0x3) == 0);
446
447 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
448 pci_decompose_tag(pc, tag, &bus, NULL, NULL);
449 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) {
450 pci_mcfg_map_bus(bus);
451 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus],
452 (tag.mode1 & 0x000ff00) << 4 | reg);
453 return data;
454 }
455 }
456
457 PCI_CONF_LOCK();
458 switch (pci_mode) {
459 case 1:
460 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
461 data = inl(PCI_MODE1_DATA_REG);
462 outl(PCI_MODE1_ADDRESS_REG, 0);
463 break;
464 case 2:
465 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
466 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
467 data = inl(tag.mode2.port | reg);
468 outb(PCI_MODE2_ENABLE_REG, 0);
469 break;
470 default:
471 panic("pci_conf_read: mode not configured");
472 }
473 PCI_CONF_UNLOCK();
474
475 return data;
476 }
477
478 void
pci_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)479 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
480 {
481 int bus;
482
483 KASSERT((reg & 0x3) == 0);
484
485 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
486 pci_decompose_tag(pc, tag, &bus, NULL, NULL);
487 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) {
488 pci_mcfg_map_bus(bus);
489 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus],
490 (tag.mode1 & 0x000ff00) << 4 | reg, data);
491 return;
492 }
493 }
494
495 PCI_CONF_LOCK();
496 switch (pci_mode) {
497 case 1:
498 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
499 outl(PCI_MODE1_DATA_REG, data);
500 outl(PCI_MODE1_ADDRESS_REG, 0);
501 break;
502 case 2:
503 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
504 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
505 outl(tag.mode2.port | reg, data);
506 outb(PCI_MODE2_ENABLE_REG, 0);
507 break;
508 default:
509 panic("pci_conf_write: mode not configured");
510 }
511 PCI_CONF_UNLOCK();
512 }
513
514 int
pci_mode_detect(void)515 pci_mode_detect(void)
516 {
517
518 #ifdef PCI_CONF_MODE
519 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2)
520 return (pci_mode = PCI_CONF_MODE);
521 #else
522 #error Invalid PCI configuration mode.
523 #endif
524 #else
525 u_int32_t sav, val;
526 int i;
527 pcireg_t idreg;
528
529 if (pci_mode != -1)
530 return (pci_mode);
531
532 #if NBIOS > 0
533 /*
534 * If we have PCI info passed from the BIOS, use the mode given there
535 * for all of this code. If not, pass on through to the previous tests
536 * to try and divine the correct mode.
537 */
538 if (bios_pciinfo != NULL) {
539 if (bios_pciinfo->pci_chars & 0x2)
540 return (pci_mode = 2);
541
542 if (bios_pciinfo->pci_chars & 0x1)
543 return (pci_mode = 1);
544
545 /* We should never get here, but if we do, fall through... */
546 }
547 #endif
548
549 /*
550 * We try to divine which configuration mode the host bridge wants.
551 *
552 * This should really be done using the PCI BIOS. If we get here, the
553 * PCI BIOS does not exist, or the boot blocks did not provide the
554 * information.
555 */
556
557 sav = inl(PCI_MODE1_ADDRESS_REG);
558
559 pci_mode = 1; /* assume this for now */
560 /*
561 * catch some known buggy implementations of mode 1
562 */
563 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]);
564 i++) {
565 pcitag_t t;
566
567 if (!pcim1_quirk_tbl[i].tag)
568 break;
569 t.mode1 = pcim1_quirk_tbl[i].tag;
570 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */
571 if (idreg == pcim1_quirk_tbl[i].id) {
572 #ifdef DEBUG
573 printf("known mode 1 PCI chipset (%08x)\n",
574 idreg);
575 #endif
576 return (pci_mode);
577 }
578 }
579
580 /*
581 * Strong check for standard compliant mode 1:
582 * 1. bit 31 ("enable") can be set
583 * 2. byte/word access does not affect register
584 */
585 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE);
586 outb(PCI_MODE1_ADDRESS_REG + 3, 0);
587 outw(PCI_MODE1_ADDRESS_REG + 2, 0);
588 val = inl(PCI_MODE1_ADDRESS_REG);
589 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
590 #ifdef DEBUG
591 printf("pci_mode_detect: mode 1 enable failed (%x)\n",
592 val);
593 #endif
594 goto not1;
595 }
596 outl(PCI_MODE1_ADDRESS_REG, 0);
597 val = inl(PCI_MODE1_ADDRESS_REG);
598 if ((val & 0x80fffffc) != 0)
599 goto not1;
600 return (pci_mode);
601 not1:
602 outl(PCI_MODE1_ADDRESS_REG, sav);
603
604 /*
605 * This mode 2 check is quite weak (and known to give false
606 * positives on some Compaq machines).
607 * However, this doesn't matter, because this is the
608 * last test, and simply no PCI devices will be found if
609 * this happens.
610 */
611 outb(PCI_MODE2_ENABLE_REG, 0);
612 outb(PCI_MODE2_FORWARD_REG, 0);
613 if (inb(PCI_MODE2_ENABLE_REG) != 0 ||
614 inb(PCI_MODE2_FORWARD_REG) != 0)
615 goto not2;
616 return (pci_mode = 2);
617 not2:
618 return (pci_mode = 0);
619 #endif
620 }
621
622 int
pci_intr_map_msi(struct pci_attach_args * pa,pci_intr_handle_t * ihp)623 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
624 {
625 pci_chipset_tag_t pc = pa->pa_pc;
626 pcitag_t tag = pa->pa_tag;
627
628 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL ||
629 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0)
630 return 1;
631
632 ihp->tag = tag;
633 ihp->line = APIC_INT_VIA_MSG;
634 ihp->pin = 0;
635 return 0;
636 }
637
638 int
pci_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)639 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
640 {
641 int pin = pa->pa_rawintrpin;
642 int line = pa->pa_intrline;
643 #if NIOAPIC > 0
644 struct mp_intr_map *mip;
645 int bus, dev, func;
646 #endif
647
648 if (pin == 0) {
649 /* No IRQ used. */
650 goto bad;
651 }
652
653 if (pin > PCI_INTERRUPT_PIN_MAX) {
654 printf("pci_intr_map: bad interrupt pin %d\n", pin);
655 goto bad;
656 }
657
658 ihp->tag = pa->pa_tag;
659 ihp->line = line;
660 ihp->pin = pin;
661
662 #if NIOAPIC > 0
663 pci_decompose_tag (pa->pa_pc, pa->pa_tag, &bus, &dev, &func);
664
665 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) {
666 int mpspec_pin = (dev << 2) | (pin - 1);
667
668 if (bus < mp_nbusses) {
669 for (mip = mp_busses[bus].mb_intrs;
670 mip != NULL; mip = mip->next) {
671 if (&mp_busses[bus] == mp_isa_bus ||
672 &mp_busses[bus] == mp_eisa_bus)
673 continue;
674 if (mip->bus_pin == mpspec_pin) {
675 ihp->line = mip->ioapic_ih | line;
676 return 0;
677 }
678 }
679 }
680
681 if (pa->pa_bridgetag) {
682 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev);
683 if (pa->pa_bridgeih[swizpin - 1].line != -1) {
684 ihp->line = pa->pa_bridgeih[swizpin - 1].line;
685 ihp->line |= line;
686 return 0;
687 }
688 }
689 /*
690 * No explicit PCI mapping found. This is not fatal,
691 * we'll try the ISA (or possibly EISA) mappings next.
692 */
693 }
694 #endif
695
696 #if NPCIBIOS > 0
697 pci_intr_header_fixup(pa->pa_pc, pa->pa_tag, ihp);
698 line = ihp->line & APIC_INT_LINE_MASK;
699 #endif
700
701 /*
702 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
703 * `unknown' or `no connection' on a PC. We assume that a device with
704 * `no connection' either doesn't have an interrupt (in which case the
705 * pin number should be 0, and would have been noticed above), or
706 * wasn't configured by the BIOS (in which case we punt, since there's
707 * no real way we can know how the interrupt lines are mapped in the
708 * hardware).
709 *
710 * XXX
711 * Since IRQ 0 is only used by the clock, and we can't actually be sure
712 * that the BIOS did its job, we also recognize that as meaning that
713 * the BIOS has not configured the device.
714 */
715 if (line == 0 || line == I386_PCI_INTERRUPT_LINE_NO_CONNECTION)
716 goto bad;
717
718 if (line >= ICU_LEN) {
719 printf("pci_intr_map: bad interrupt line %d\n", line);
720 goto bad;
721 }
722 if (line == 2) {
723 printf("pci_intr_map: changed line 2 to line 9\n");
724 line = 9;
725 }
726
727 #if NIOAPIC > 0
728 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) {
729 if (mip == NULL && mp_isa_bus) {
730 for (mip = mp_isa_bus->mb_intrs; mip != NULL;
731 mip = mip->next) {
732 if (mip->bus_pin == line) {
733 ihp->line = mip->ioapic_ih | line;
734 return 0;
735 }
736 }
737 }
738 if (mip == NULL && mp_eisa_bus) {
739 for (mip = mp_eisa_bus->mb_intrs; mip != NULL;
740 mip = mip->next) {
741 if (mip->bus_pin == line) {
742 ihp->line = mip->ioapic_ih | line;
743 return 0;
744 }
745 }
746 }
747 if (mip == NULL) {
748 printf("pci_intr_map: "
749 "bus %d dev %d func %d pin %d; line %d\n",
750 bus, dev, func, pin, line);
751 printf("pci_intr_map: no MP mapping found\n");
752 }
753 }
754 #endif
755
756 return 0;
757
758 bad:
759 ihp->line = -1;
760 return 1;
761 }
762
763 const char *
pci_intr_string(pci_chipset_tag_t pc,pci_intr_handle_t ih)764 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
765 {
766 static char irqstr[64];
767 int line = ih.line & APIC_INT_LINE_MASK;
768
769 if (ih.line & APIC_INT_VIA_MSG)
770 return ("msi");
771
772 #if NIOAPIC > 0
773 if (ih.line & APIC_INT_VIA_APIC) {
774 snprintf(irqstr, sizeof irqstr, "apic %d int %d",
775 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line));
776 return (irqstr);
777 }
778 #endif
779
780 if (line == 0 || line >= ICU_LEN || line == 2)
781 panic("pci_intr_string: bogus handle 0x%x", line);
782
783 snprintf(irqstr, sizeof irqstr, "irq %d", line);
784 return (irqstr);
785 }
786
787 #include "acpiprt.h"
788 #if NACPIPRT > 0
789 void acpiprt_route_interrupt(int bus, int dev, int pin);
790 #endif
791
792 extern struct intrhand *apic_intrhand[256];
793 extern int apic_maxlevel[256];
794
795 void *
pci_intr_establish_cpu(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,struct cpu_info * ci,int (* func)(void *),void * arg,const char * what)796 pci_intr_establish_cpu(pci_chipset_tag_t pc, pci_intr_handle_t ih,
797 int level, struct cpu_info *ci,
798 int (*func)(void *), void *arg, const char *what)
799 {
800 if (ci != NULL && ci != &cpu_info_primary)
801 return (NULL);
802
803 return pci_intr_establish(pc, ih, level, func, arg, what);
804 }
805
806 void *
pci_intr_establish(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg,const char * what)807 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
808 int (*func)(void *), void *arg, const char *what)
809 {
810 void *ret;
811 int bus, dev;
812 int l = ih.line & APIC_INT_LINE_MASK;
813 pcitag_t tag = ih.tag;
814 int irq = ih.line;
815
816 if (ih.line & APIC_INT_VIA_MSG) {
817 struct intrhand *ih;
818 pcireg_t reg, addr;
819 int off, vec;
820 int flags;
821
822 flags = level & IPL_MPSAFE;
823 level &= ~IPL_MPSAFE;
824
825 KASSERT(level <= IPL_TTY || flags & IPL_MPSAFE);
826
827 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
828 panic("%s: no msi capability", __func__);
829
830 vec = idt_vec_alloc(level, level + 15);
831 if (vec == 0)
832 return (NULL);
833
834 ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
835 if (ih == NULL)
836 panic("%s: can't malloc handler info", __func__);
837
838 ih->ih_fun = func;
839 ih->ih_arg = arg;
840 ih->ih_next = NULL;
841 ih->ih_level = level;
842 ih->ih_flags = flags;
843 ih->ih_irq = irq;
844 ih->ih_pin = tag.mode1;
845 ih->ih_vec = vec;
846 evcount_attach(&ih->ih_count, what, &ih->ih_vec);
847
848 apic_maxlevel[vec] = level;
849 apic_intrhand[vec] = ih;
850 idt_vec_set(vec, apichandler[vec & 0xf]);
851
852 addr = 0xfee00000UL | (cpu_info_primary.ci_apicid << 12);
853
854 if (reg & PCI_MSI_MC_C64) {
855 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr);
856 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0);
857 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec);
858 } else {
859 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr);
860 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec);
861 }
862 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
863 return (ih);
864 }
865
866 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL);
867 #if NACPIPRT > 0
868 acpiprt_route_interrupt(bus, dev, ih.pin);
869 #endif
870
871 #if NIOAPIC > 0
872 if (l != -1 && ih.line & APIC_INT_VIA_APIC)
873 return (apic_intr_establish(ih.line, IST_LEVEL, level, func,
874 arg, what));
875 #endif
876 if (l == 0 || l >= ICU_LEN || l == 2)
877 panic("pci_intr_establish: bogus handle 0x%x", l);
878
879 ret = isa_intr_establish(NULL, l, IST_LEVEL, level, func, arg, what);
880 #if NPCIBIOS > 0
881 if (ret)
882 pci_intr_route_link(pc, &ih);
883 #endif
884 return (ret);
885 }
886
887 void
pci_intr_disestablish(pci_chipset_tag_t pc,void * cookie)888 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
889 {
890 struct intrhand *ih = cookie;
891
892 if (ih->ih_irq & APIC_INT_VIA_MSG) {
893 pcitag_t tag = { .mode1 = ih->ih_pin };
894 pcireg_t reg;
895 int off;
896
897 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®))
898 pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE);
899
900 apic_maxlevel[ih->ih_vec] = 0;
901 apic_intrhand[ih->ih_vec] = NULL;
902 idt_vec_free(ih->ih_vec);
903
904 evcount_detach(&ih->ih_count);
905 free(ih, M_DEVBUF, sizeof *ih);
906 return;
907 }
908
909 /* XXX oh, unroute the pci int link? */
910 isa_intr_disestablish(NULL, cookie);
911 }
912
913 struct extent *pciio_ex;
914 struct extent *pcimem_ex;
915 struct extent *pcibus_ex;
916
917 void
pci_init_extents(void)918 pci_init_extents(void)
919 {
920 bios_memmap_t *bmp;
921 u_int64_t size;
922
923 if (pciio_ex == NULL) {
924 /*
925 * We only have 64K of addressable I/O space.
926 * However, since BARs may contain garbage, we cover
927 * the full 32-bit address space defined by PCI of
928 * which we only make the first 64K available.
929 */
930 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF,
931 NULL, 0, EX_NOWAIT | EX_FILLED);
932 if (pciio_ex == NULL)
933 return;
934 extent_free(pciio_ex, 0, 0x10000, EX_NOWAIT);
935 }
936
937 if (pcimem_ex == NULL) {
938 pcimem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF,
939 NULL, 0, EX_NOWAIT);
940 if (pcimem_ex == NULL)
941 return;
942
943 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) {
944 /*
945 * Ignore address space beyond 4G.
946 */
947 if (bmp->addr >= 0x100000000ULL)
948 continue;
949 size = bmp->size;
950 if (bmp->addr + size >= 0x100000000ULL)
951 size = 0x100000000ULL - bmp->addr;
952
953 /* Ignore zero-sized regions. */
954 if (size == 0)
955 continue;
956
957 if (extent_alloc_region(pcimem_ex, bmp->addr, size,
958 EX_NOWAIT))
959 printf("memory map conflict 0x%llx/0x%llx\n",
960 bmp->addr, bmp->size);
961 }
962
963 /* Take out the video buffer area and BIOS areas. */
964 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE,
965 EX_CONFLICTOK | EX_NOWAIT);
966 }
967
968 if (pcibus_ex == NULL) {
969 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF,
970 NULL, 0, EX_NOWAIT);
971 }
972 }
973
974 #include "acpi.h"
975 #if NACPI > 0
976 void acpi_pci_match(struct device *, struct pci_attach_args *);
977 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t);
978 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int);
979 #endif
980
981 void
pci_dev_postattach(struct device * dev,struct pci_attach_args * pa)982 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa)
983 {
984 #if NACPI > 0
985 acpi_pci_match(dev, pa);
986 #endif
987 }
988
989 pcireg_t
pci_min_powerstate(pci_chipset_tag_t pc,pcitag_t tag)990 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag)
991 {
992 #if NACPI > 0
993 return acpi_pci_min_powerstate(pc, tag);
994 #else
995 return pci_get_powerstate(pc, tag);
996 #endif
997 }
998
999 void
pci_set_powerstate_md(pci_chipset_tag_t pc,pcitag_t tag,int state,int pre)1000 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre)
1001 {
1002 #if NACPI > 0
1003 acpi_pci_set_powerstate(pc, tag, state, pre);
1004 #endif
1005 }
1006