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/dragonfly/sys/dev/netif/wpi/
H A Dif_wpivar.h281 #define WPI_LOCK_INIT(_sc) \ argument
288 #define WPI_RXON_LOCK_INIT(_sc) \ argument
295 #define WPI_TX_LOCK_INIT(_sc) \ argument
301 #define WPI_NT_LOCK_INIT(_sc) \ argument
307 #define WPI_TXQ_LOCK_INIT(_sc) \ argument
313 #define WPI_TXQ_STATE_LOCK_INIT(_sc) \ argument
321 #define WPI_LOCK_INIT(_sc) \ argument
329 #define WPI_RXON_LOCK_INIT(_sc) \ argument
336 #define WPI_TX_LOCK_INIT(_sc) \ argument
342 #define WPI_NT_LOCK_INIT(_sc) \ argument
[all …]
/dragonfly/sys/dev/netif/ath/ath/
H A Dif_ath_rx.h39 #define ath_stoprecv(_sc, _dodelay) \ argument
41 #define ath_startrecv(_sc) \ argument
43 #define ath_rx_flush(_sc) \ argument
45 #define ath_rxbuf_init(_sc, _bf) \ argument
47 #define ath_rxdma_setup(_sc) \ argument
49 #define ath_rxdma_teardown(_sc) \ argument
H A Dif_ath_tx.h155 #define ath_txdma_setup(_sc) \ argument
157 #define ath_txdma_teardown(_sc) \ argument
159 #define ath_txq_restart_dma(_sc, _txq) \ argument
161 #define ath_tx_handoff(_sc, _txq, _bf) \ argument
163 #define ath_draintxq(_sc, _rtype) \ argument
H A Dif_athvar.h412 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ argument
951 #define ATH_LOCK_INIT(_sc) \ argument
954 #define ATH_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_mtx) argument
964 #define ATH_TX_LOCK_INIT(_sc) do {\ argument
995 #define ATH_PCU_LOCK_INIT(_sc) do {\ argument
1015 #define ATH_RX_LOCK_INIT(_sc) do {\ argument
1031 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ argument
1039 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ argument
1041 #define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ argument
1044 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ argument
[all …]
H A Dif_ath_debug.h89 #define ATH_KTR(_sc, _km, _kf, ...) argument
93 #define ATH_KTR(_sc, _km, _kf, ...) do { \ argument
118 #define ATH_KTR(_sc, _km, _kf, ...) do { } while (0) argument
/dragonfly/sys/dev/virtual/virtio/scsi/
H A Dvirtio_scsivar.h147 #define VTSCSI_MTX(_sc) &(_sc)->vtscsi_mtx argument
148 #define VTSCSI_LOCK_INIT(_sc, _name) lockinit(VTSCSI_MTX(_sc), \ argument
150 #define VTSCSI_LOCK(_sc) lockmgr(VTSCSI_MTX(_sc), LK_EXCLUSIVE) argument
151 #define VTSCSI_UNLOCK(_sc) lockmgr(VTSCSI_MTX(_sc), LK_RELEASE) argument
152 #define VTSCSI_LOCK_OWNED(_sc) KKASSERT(lockowned(VTSCSI_MTX(_sc)) != 0) argument
153 #define VTSCSI_LOCK_NOTOWNED(_sc) KKASSERT(lockowned(VTSCSI_MTX(_sc)) == 0) argument
154 #define VTSCSI_LOCK_DESTROY(_sc) lockuninit(VTSCSI_MTX(_sc)) argument
175 #define vtscsi_dprintf(_sc, _level, _msg, _args ...) do { \ argument
/dragonfly/sys/dev/disk/mmcsd/
H A Dmmcsd.c107 #define MMCSD_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
108 #define MMCSD_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
109 #define MMCSD_LOCK_INIT(_sc) lockinit(&(_sc)->sc_lock, "mmcsd", 0, LK_CANRECURSE) argument
110 #define MMCSD_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lock); argument
111 #define MMCSD_ASSERT_LOCKED(_sc) KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) != 0); argument
112 #define MMCSD_ASSERT_UNLOCKED(_sc) KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) == 0); argument
/dragonfly/sys/net/lagg/
H A Dif_lagg.h272 #define LAGG_LOCK_INIT(_sc) lockinit(&(_sc)->sc_lock, "if_lagg rmlock", 0, LK_CANRECURSE) argument
273 #define LAGG_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lock) argument
274 #define LAGG_RLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_SHARED) argument
275 #define LAGG_WLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
276 #define LAGG_RUNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
277 #define LAGG_WUNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
278 #define LAGG_RLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) == LK_SHARED) argument
279 #define LAGG_WLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) == LK_EXCLUSIVE) argument
281 #define LAGG_CALLOUT_LOCK_INIT(_sc) \ argument
283 #define LAGG_CALLOUT_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_call_lock) argument
/dragonfly/sys/bus/u4b/net/
H A Dif_iphethvar.h80 #define IPHETH_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
81 #define IPHETH_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
82 #define IPHETH_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
H A Dif_cdcereg.h102 #define CDCE_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
103 #define CDCE_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
104 #define CDCE_LOCK_ASSERT(_sc, t) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
H A Dif_cuereg.h130 #define CUE_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
131 #define CUE_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
132 #define CUE_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
H A Dif_mosreg.h174 #define MOS_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
175 #define MOS_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
176 #define MOS_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
H A Dif_axgereg.h171 #define AXGE_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
172 #define AXGE_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
173 #define AXGE_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
H A Dif_kuereg.h139 #define KUE_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
140 #define KUE_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
141 #define KUE_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
H A Dif_udavreg.h165 #define UDAV_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
166 #define UDAV_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
167 #define UDAV_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->sc_lock)) argument
/dragonfly/sys/dev/netif/wi/
H A Dif_wivar.h179 #define WI_LOCK(_sc) lockmgr(&(_sc)->sc_lk, LK_EXCLUSIVE) argument
180 #define WI_UNLOCK(_sc) lockmgr(&(_sc)->sc_lk, LK_RELEASE) argument
181 #define WI_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_lk, curthread) == LK_EXCLUSIVE) argument
183 #define WI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
184 #define WI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
185 #define WI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
/dragonfly/sys/dev/netif/ae/
H A Dif_ae.c157 #define AE_WRITE_4(_sc, reg, val) \ argument
159 #define AE_WRITE_2(_sc, reg, val) \ argument
161 #define AE_WRITE_1(_sc, reg, val) \ argument
163 #define AE_READ_4(_sc, reg) \ argument
165 #define AE_READ_2(_sc, reg) \ argument
167 #define AE_READ_1(_sc, reg) \ argument
/dragonfly/sys/dev/netif/age/
H A Dif_agevar.h229 #define CSR_WRITE_4(_sc, reg, val) \ argument
231 #define CSR_WRITE_2(_sc, reg, val) \ argument
234 #define CSR_READ_4(_sc, reg) \ argument
236 #define CSR_READ_2(_sc, reg) \ argument
239 #define AGE_COMMIT_MBOX(_sc) \ argument
250 #define AGE_RXCHAIN_RESET(_sc) \ argument
/dragonfly/sys/dev/netif/iwn/
H A Dif_iwnvar.h435 #define IWN_LOCK_INIT(_sc) \ argument
437 #define IWN_LOCK(_sc) lockmgr(&(_sc)->sc_lk, LK_EXCLUSIVE) argument
438 #define IWN_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_lk, curthread) == LK_EXCLUSIVE); argument
439 #define IWN_UNLOCK(_sc) lockmgr(&(_sc)->sc_lk, LK_RELEASE) argument
440 #define IWN_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lk) argument
442 #define IWN_LOCK_INIT(_sc) \ argument
445 #define IWN_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
446 #define IWN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
447 #define IWN_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
448 #define IWN_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
/dragonfly/sys/dev/virtual/virtio/balloon/
H A Dvirtio_balloon.c126 #define vtballoon_dprintf(_sc, _level, _msg, _args ...) do { \ argument
199 #define VTBALLOON_SLZ(_sc) &(_sc)->vtballoon_slz argument
200 #define VTBALLOON_ENTER_SLZ(_sc) lwkt_serialize_enter(VTBALLOON_SLZ(sc)); argument
201 #define VTBALLOON_EXIT_SLZ(_sc) lwkt_serialize_exit(VTBALLOON_SLZ(sc)); argument
/dragonfly/sys/dev/virtual/vmware/vmxnet3/
H A Dif_vmxvar.h262 #define VMXNET3_CORE_LOCK_INIT(_sc, _name) \ argument
264 #define VMXNET3_CORE_LOCK_DESTROY(_sc) lockuninit(&(_sc)->vmx_lock) argument
265 #define VMXNET3_CORE_LOCK(_sc) lockmgr(&(_sc)->vmx_lock, LK_EXCLUSIVE) argument
266 #define VMXNET3_CORE_UNLOCK(_sc) lockmgr(&(_sc)->vmx_lock, LK_RELEASE) argument
267 #define VMXNET3_CORE_LOCK_ASSERT(_sc) KKASSERT(lockowned(&(_sc)->vmx_lock) != 0) argument
268 #define VMXNET3_CORE_LOCK_ASSERT_NOTOWNED(_sc) \ argument
/dragonfly/sys/bus/mmc/
H A Dmmc.c133 #define MMC_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) argument
134 #define MMC_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) argument
135 #define MMC_LOCK_INIT(_sc) lockinit(&(_sc)->sc_lock, "mmc", 0, LK_CANRECURSE) argument
136 #define MMC_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lock); argument
137 #define MMC_ASSERT_LOCKED(_sc) KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) != 0); argument
138 #define MMC_ASSERT_UNLOCKED(_sc) KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) == 0); argument
/dragonfly/sys/dev/netif/stge/
H A Dif_stgereg.h98 #define CSR_WRITE_4(_sc, reg, val) \ argument
100 #define CSR_WRITE_2(_sc, reg, val) \ argument
102 #define CSR_WRITE_1(_sc, reg, val) \ argument
105 #define CSR_READ_4(_sc, reg) \ argument
107 #define CSR_READ_2(_sc, reg) \ argument
109 #define CSR_READ_1(_sc, reg) \ argument
/dragonfly/sys/dev/netif/ale/
H A Dif_alevar.h229 #define CSR_WRITE_4(_sc, reg, val) \ argument
231 #define CSR_WRITE_2(_sc, reg, val) \ argument
233 #define CSR_WRITE_1(_sc, reg, val) \ argument
235 #define CSR_READ_2(_sc, reg) \ argument
237 #define CSR_READ_4(_sc, reg) \ argument
/dragonfly/sys/dev/sound/pci/
H A Datiixp.c137 #define atiixp_rd(_sc, _reg) \ argument
139 #define atiixp_wr(_sc, _reg, _val) \ argument
142 #define atiixp_lock(_sc) snd_mtxlock((_sc)->lock) argument
143 #define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock) argument
144 #define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) argument

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