1 /////////////////////////////////////////////////////////////////////////////// 2 // BSD 3-Clause License 3 // 4 // Copyright (c) 2019, Nefelus Inc 5 // All rights reserved. 6 // 7 // Redistribution and use in source and binary forms, with or without 8 // modification, are permitted provided that the following conditions are met: 9 // 10 // * Redistributions of source code must retain the above copyright notice, this 11 // list of conditions and the following disclaimer. 12 // 13 // * Redistributions in binary form must reproduce the above copyright notice, 14 // this list of conditions and the following disclaimer in the documentation 15 // and/or other materials provided with the distribution. 16 // 17 // * Neither the name of the copyright holder nor the names of its 18 // contributors may be used to endorse or promote products derived from 19 // this software without specific prior written permission. 20 // 21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 // POSSIBILITY OF SUCH DAMAGE. 32 33 #pragma once 34 35 #include <stdio.h> 36 #include <stdlib.h> 37 #include <string.h> 38 39 #include "ZInterface.h" 40 #include "array1.h" 41 #include "atypes.h" 42 #include "box.h" 43 #include "db.h" 44 #include "geom.h" 45 #include "gseq.h" 46 #include "rcx.h" 47 48 using namespace odb; 49 50 enum Ath__overlapAdjust 51 { 52 Z_noAdjust, 53 Z_merge, 54 Z_endAdjust 55 }; 56 57 58 class Ath__track; 59 60 class Ath__searchBox 61 { 62 private: 63 int _ll[2]; 64 int _ur[2]; 65 uint _level; 66 uint _dir; 67 uint _ownId; 68 uint _otherId; 69 uint _type; 70 71 public: 72 Ath__searchBox(int x1, int y1, int x2, int y2, uint l, int dir = -1); 73 Ath__searchBox(Ath__box* bb, uint l, int dir = -1); 74 Ath__searchBox(Ath__searchBox* bb, uint l, int dir = -1); 75 Ath__searchBox(); 76 void set(int x1, int y1, int x2, int y2, uint l, int dir); 77 void setMidPointSearch(); 78 int loXY(uint d); 79 int loXY(uint d, int loBound); 80 int hiXY(uint d); 81 int hiXY(uint d, int hiBound); 82 void setLo(uint d, int xy); 83 void setHi(uint d, int xy); 84 void setType(uint v); 85 uint getType(); 86 87 uint getDir(); 88 uint getLevel(); 89 void setDir(int v = -1); 90 void setLevel(uint v); 91 void setOwnerId(uint v, uint other = 0); 92 uint getOwnerId(); 93 uint getOtherId(); 94 uint getLength(); 95 }; 96 97 class Ath__wire 98 { 99 private: 100 uint _id; 101 uint _srcId; // TODO-OPTIMIZE 102 uint _boxId; 103 uint _otherId; 104 Ath__wire* _srcWire; // OpenRCX 105 106 Ath__track* _track; 107 Ath__wire* _next; 108 109 int _xy; // TODO offset from track start in large dimension 110 int _len; 111 int _ouLen; // OpenRCX 112 113 int _base; 114 int _width : 24; 115 116 uint _flags : 6; 117 // 0=wire, 2=obs, 1=pin, 3=power or SET BY USER 118 119 uint _dir : 1; 120 uint _ext : 1; 121 uint _visited : 1; // OpenRCX 122 123 public: 124 int getShapeProperty(int id); // OpenRCX 125 int getRsegId(); // OpenRCX 126 127 void reset(); 128 // void set(int xy1, int xy2); 129 void set(uint dir, int* ll, int* ur); 130 void search(int xy1, int xy2, uint& cnt, Ath__array1D<uint>* idTable); 131 void search1(int xy1, int xy2, uint& cnt, Ath__array1D<uint>* idTable); 132 setNext(Ath__wire * w)133 void setNext(Ath__wire* w) { _next = w; }; getNext()134 Ath__wire* getNext() { return _next; }; getFlags()135 uint getFlags() { return _flags; }; 136 uint getBoxId(); setExt(uint ext)137 void setExt(uint ext) { _ext = ext; }; getExt()138 uint getExt() { return _ext; }; getId()139 uint getId() { return _id; }; 140 void setOtherId(uint id); 141 uint getOtherId(); 142 bool isPower(); 143 bool isVia(); // OpenRCX 144 bool isTilePin(); 145 bool isTileBus(); 146 uint getOwnerId(); 147 uint getSrcId(); 148 void getCoords(Ath__searchBox* box); getXY()149 int getXY() { return _xy; } 150 void getCoords(int* x1, int* y1, int* x2, int* y2, uint* dir); 151 152 friend class Ath__track; 153 friend class Ath__grid; 154 friend class Ath__gridTable; 155 156 // Extraction 157 void printOneWire(FILE* ptfile); 158 void printWireNeighbor(uint met, 159 Ath__array1D<Ath__wire*>* topNeighbor, 160 Ath__array1D<Ath__wire*>* botNeighbor); 161 int wireOverlap(Ath__wire* w, int* len1, int* len2, int* len3); 162 Ath__wire* getPoolWire(AthPool<Ath__wire>* wirePool); 163 Ath__wire* makeWire(AthPool<Ath__wire>* wirePool, int xy1, uint len); 164 Ath__wire* makeCoupleWire(AthPool<Ath__wire>* wirePool, 165 int targetHighTracks, 166 Ath__wire* w2, 167 int xy1, 168 uint len, 169 uint wtype); 170 void setXY(int xy1, uint len); 171 dbNet* getNet(); 172 }; 173 174 class Ath__grid; 175 176 class Ath__track 177 { 178 private: 179 int _x; // you need only one 180 int _y; 181 182 int _base; 183 Ath__track* _hiTrack; 184 Ath__track* _lowTrack; 185 186 Ath__wire** _marker; 187 Ath__wire** _eMarker; 188 uint _markerCnt; 189 uint _searchMarkerIndex; 190 191 uint _targetMarker; 192 Ath__wire* _targetWire; 193 194 Ath__grid* _grid; 195 196 uint _num : 20; 197 198 int _width : 19; 199 uint _lowest : 1; 200 uint _shift : 4; 201 uint _centered : 1; 202 uint _blocked : 1; 203 uint _full : 1; 204 bool _ordered; 205 206 public: getTrackNum()207 uint getTrackNum() { 208 return _num; 209 }; 210 void set(Ath__grid* g, 211 int x, 212 int y, 213 uint n, 214 uint width, 215 uint markerLen, 216 uint markerCnt, 217 int base); 218 void freeWires(AthPool<Ath__wire>* pool); 219 bool place(Ath__wire* w, int markIndex1, int markIndex2); 220 bool place(Ath__wire* w, int markIndex1); 221 uint setExtrusionMarker(int markerCnt, int start, uint markerLen); 222 bool placeTrail(Ath__wire* w, uint m1, uint m2); 223 224 bool overlapCheck(Ath__wire* w, int markIndex1, int markIndex2); 225 bool isAscendingOrdered(uint markerCnt, uint* wCnt); 226 Ath__grid* getGrid(); 227 Ath__wire* getWire_Linear(uint markerCnt, uint id); 228 Ath__wire* getNextWire(Ath__wire* wire); 229 uint search(int xy1, 230 int xy2, 231 uint markIndex1, 232 uint markIndex2, 233 Ath__array1D<uint>* idtable); 234 uint search1(int xy1, 235 int xy2, 236 uint markIndex1, 237 uint markIndex2, 238 Ath__array1D<uint>* idTable); 239 240 bool checkAndplace(Ath__wire* w, int markIndex1); 241 bool checkMarker(int markIndex); 242 bool checkAndplacerOnMarker(Ath__wire* w, int markIndex); 243 uint getAllWires(Ath__array1D<Ath__wire*>* boxTable, uint markerCnt); 244 void resetExtFlag(uint markerCnt); 245 void linkWire(Ath__wire*& w1, Ath__wire*& w2); 246 247 Ath__track* getNextSubTrack(Ath__track* subt, bool tohi); getBase()248 int getBase() { return _base; }; 249 void setHiTrack(Ath__track* hitrack); 250 void setLowTrack(Ath__track* lowtrack); 251 Ath__track* getHiTrack(); 252 Ath__track* getLowTrack(); 253 Ath__track* nextTrackInRange(uint& delt, 254 uint trackDist, 255 uint srcTrack, 256 bool tohi); 257 int nextSubTrackInRange(Ath__track*& tstrack, 258 uint& delt, 259 uint trackDist, 260 uint srcTrack, 261 bool tohi); setLowest(uint lst)262 void setLowest(uint lst) { _lowest = lst; }; 263 264 friend class Ath__gridTable; 265 friend class Ath__grid; 266 friend class Ath__wire; 267 268 uint removeMarkedNetWires(); 269 270 // EXTRACTION 271 272 bool place2(Ath__wire* w, int mark1, int mark2); 273 void insertWire(Ath__wire* w, int mark1, int mark2); 274 uint initTargetTracks(uint sourceTrack, uint trackDist, bool tohi); 275 void findNeighborWire(Ath__wire*, Ath__array1D<Ath__wire*>*, bool); 276 void getTrackWires(std::vector<Ath__wire*>& ctxwire); 277 void buildDgContext(Ath__array1D<odb::SEQ*>* dgContext, 278 Ath__wire**& allWire, 279 int& awcnt, 280 int& a1wcnt); 281 int getBandWires(Ath__array1D<Ath__wire*>* bandWire); 282 uint couplingCaps(Ath__grid* resGrid, 283 uint currentTrack, 284 uint ccTrackDist, 285 uint ccDomain, 286 ZInterface* context, 287 Ath__array1D<uint>* ccTable, 288 uint met, 289 rcx::CoupleAndCompute coupleAndCompute, 290 void* compPtr); 291 292 uint findOverlap(Ath__wire* origWire, 293 uint ccDomain, 294 Ath__array1D<Ath__wire*>* wTable, 295 Ath__array1D<Ath__wire*>* nwTable, 296 Ath__grid* ccGrid, 297 Ath__array1D<Ath__wire*>* ccTable, 298 ZInterface* context, 299 uint met, 300 rcx::CoupleAndCompute coupleAndCompute, 301 void* compPtr); 302 303 void initTargetWire(int noPowerWire); 304 Ath__wire* nextTargetWire(int noPowerWire); 305 Ath__wire* getTargetWire(); 306 void adjustMetalFill(); 307 void adjustOverlapMakerEnd(uint markerCnt); 308 void adjustOverlapMakerEnd(uint markerCnt, int start, uint markerLen); 309 uint trackContextOn(int orig, 310 int end, 311 int base, 312 int width, 313 uint firstContextTrack, 314 Ath__array1D<int>* context); 315 316 void dealloc(AthPool<Ath__wire>* pool); 317 }; 318 class Ath__gridTable; 319 320 class Ath__grid 321 { 322 private: 323 Ath__gridTable* _gridtable; 324 Ath__track** _trackTable; 325 uint* _blockedTrackTable; 326 uint _trackCnt; 327 uint* _subTrackCnt; 328 int _base; 329 int _max; 330 331 int _start; // laterally 332 int _end; 333 334 int _lo[2]; 335 int _hi[2]; 336 337 int _width; 338 int _pitch; 339 uint _level; 340 uint _layer; 341 uint _dir; 342 int _markerLen; 343 uint _markerCnt; 344 uint _searchLowTrack; 345 uint _searchHiTrack; 346 uint _searchLowMarker; 347 uint _searchHiMarker; 348 349 uint _widthTable[8]; 350 uint _shiftTable[8]; 351 AthPool<Ath__track>* _trackPoolPtr; 352 AthPool<Ath__wire>* _wirePoolPtr; 353 354 uint _schema; 355 uint _wireType; 356 357 uint _currentTrack; 358 uint _lastFreeTrack; 359 360 public: 361 Ath__grid(Ath__gridTable* gt, 362 AthPool<Ath__track>* trackPool, 363 AthPool<Ath__wire>* wirePool, 364 Ath__box* bb, 365 uint level, 366 uint dir, 367 uint num, 368 uint width, 369 uint pitch, 370 uint markerCnt = 4); 371 Ath__grid(Ath__gridTable* gt, 372 AthPool<Ath__track>* trackPool, 373 AthPool<Ath__wire>* wirePool, 374 uint level, 375 uint num, 376 uint markerCnt); 377 ~Ath__grid(); 378 getGridTable()379 Ath__gridTable* getGridTable() { return _gridtable; }; 380 void setBoundaries(uint dir, int xlo, int ylo, int xhi, int yhi); 381 void setTracks(uint dir, 382 uint width, 383 uint pitch, 384 int xlo, 385 int ylo, 386 int xhi, 387 int yhi, 388 uint markerLen = 0); 389 void setPlaced(); 390 void setSchema(uint v); 391 bool isPlaced(); 392 393 bool anyTrackAvailable(); 394 395 uint addWireList(Ath__box* box); getTrackCnt()396 uint getTrackCnt() { return _trackCnt; }; getTrackPtr(uint n)397 Ath__track* getTrackPtr(uint n) { return _trackTable[n]; }; 398 uint getTrackNum1(int xy); 399 uint getWidth(); 400 int getXYbyWidth(int xy, uint* mark); 401 Ath__track* addTrack(uint ii, uint markerCnt, int base); 402 Ath__track* addTrack(uint ii, uint markerCnt); 403 void makeTracks(uint space, uint width); 404 void getBbox(Ath__box* bb); 405 void getBbox(Ath__searchBox* bb); 406 uint setExtrusionMarker(); 407 uint addWire(Ath__box* box, int check); 408 uint addWire(Ath__box* box); 409 410 uint placeWire(Ath__searchBox* bb); 411 uint placeBox(uint id, int x1, int y1, int x2, int y2); 412 uint placeBox(dbBox* box, uint wtype, uint id); 413 uint placeBox(Ath__box* box); 414 uint placeBox(Ath__searchBox* bb); 415 uint getBucketNum(int xy); 416 uint getTrackNum(int* ll, uint d, uint* marker); 417 Ath__wire* getWirePtr(uint wireId); 418 void getBoxIds(Ath__array1D<uint>* wireIdTable, Ath__array1D<uint>* idtable); 419 void getWireIds(Ath__array1D<uint>* wireIdTable, Ath__array1D<uint>* idtable); 420 421 int findEmptyTrack(int ll[2], int ur[2]); 422 uint getFirstTrack(uint divider); 423 int getClosestTrackCoord(int xy); 424 uint addWire(uint initTrack, Ath__box* box, int sortedOrder, int* height); 425 Ath__wire* getPoolWire(); 426 Ath__wire* makeWire(Ath__box* box, 427 uint* id, 428 uint* m1, 429 uint* m2, 430 uint fullTrack); 431 Ath__wire* makeWire(Ath__box* box, uint id, uint* m1); 432 Ath__wire* makeWire(int* ll, int* ur, uint id, uint* m1); 433 Ath__wire* makeWire(uint dir, 434 int* ll, 435 int* ur, 436 uint id1, 437 uint id2, 438 uint type = 0); 439 440 Ath__wire* makeWire(Ath__wire* w, uint type = 0); 441 442 void makeTrackTable(uint width, uint pitch, uint space = 0); 443 float updateFreeTracks(float v); 444 445 void freeTracksAndTables(); 446 uint getAbsTrackNum(int xy); 447 uint getMinMaxTrackNum(int xy); 448 bool addOnTrack(uint track, Ath__wire* w, uint mark1, uint mark2); 449 int getTrackHeight(uint track); 450 uint getTrackNum(Ath__box* box); 451 Ath__track* getTrackPtr(int* ll); 452 Ath__track* getTrackPtr(int xy); 453 Ath__track* getTrackPtr(uint ii, uint markerCnt, int base); 454 Ath__track* getTrackPtr(uint ii, uint markerCnt); 455 bool isOrdered(bool ascending, uint* cnt); 456 uint search(Ath__searchBox* bb, 457 Ath__array1D<uint>* idtable, 458 bool wireIdFlag = false); 459 460 uint placeWire(uint initTrack, 461 Ath__wire* w, 462 uint mark1, 463 uint mark2, 464 int sortedOrder, 465 int* height); 466 467 void getBoxes(Ath__array1D<uint>* table); 468 uint getBoxes(uint ii, Ath__array1D<uint>* table); 469 470 uint getDir(); 471 uint getLevel(); 472 Ath__wire* getWire_Linear(uint id); 473 474 void getBuses(Ath__array1D<Ath__box*>* boxtable, uint width); 475 476 friend class Ath__gridTable; 477 478 uint removeMarkedNetWires(); 479 void setSearchDomain(uint domainAdjust); searchLowMarker()480 uint searchLowMarker() { return _searchLowMarker; }; searchHiMarker()481 uint searchHiMarker() { return _searchHiMarker; }; 482 483 // EXTRACTION 484 void buildDgContext(int gridn, int base); 485 int getBandWires(int hiXY, 486 uint couplingDist, 487 uint& wireCnt, 488 Ath__array1D<Ath__wire*>* bandWire, 489 int* limitArray); 490 uint couplingCaps(Ath__grid* resGrid, 491 uint couplingDist, 492 ZInterface* context, 493 Ath__array1D<uint>* ccTable, 494 rcx::CoupleAndCompute coupleAndCompute, 495 void* compPtr); 496 AthPool<Ath__wire>* getWirePoolPtr(); 497 uint placeWire(Ath__wire* w); 498 uint defaultWireType(); 499 void setDefaultWireType(uint v); 500 uint search(Ath__searchBox* bb, 501 uint* gxy, 502 Ath__array1D<uint>* idtable, 503 Ath__grid* g); 504 void adjustMetalFill(); 505 void adjustOverlapMakerEnd(); 506 void initContextGrids(); 507 void initContextTracks(); 508 void contextsOn(int orig, int len, int base, int width); 509 void gridContextOn(int orig, int len, int base, int width); 510 511 int initCouplingCapLoops(uint couplingDist, 512 rcx::CoupleAndCompute coupleAndCompute, 513 void* compPtr, 514 bool startSearchTrack = true, 515 int startXY = 0); 516 int couplingCaps(int hiXY, 517 uint couplingDist, 518 uint& wireCnt, 519 rcx::CoupleAndCompute coupleAndCompute, 520 void* compPtr, 521 int* limitArray); 522 int dealloc(int hiXY); 523 void dealloc(); 524 }; 525 526 class Ath__gridTile 527 { 528 private: 529 Ath__grid** _gTable; 530 uint _levelCnt; 531 Rect _bb; 532 533 bool _poolFlag; 534 AthPool<Ath__track>* _trackPool; 535 AthPool<Ath__wire>* _wirePool; 536 537 public: 538 Ath__gridTile(uint levelCnt, 539 int x1, 540 int y1, 541 int x2, 542 int y2, 543 AthPool<Ath__track>* trackPoolPtr = NULL, 544 AthPool<Ath__wire>* wirePoolPtr = NULL); 545 ~Ath__gridTile(); 546 Ath__grid* addGrid(Ath__box* bb, 547 uint level, 548 uint dir, 549 uint layerNum, 550 uint width, 551 uint pitch); 552 Ath__grid* addGrid(int x1, 553 int y1, 554 int x2, 555 int y2, 556 uint level, 557 uint dir, 558 uint layerNum, 559 uint width, 560 uint pitch); 561 562 void getBounds(int* x1, int* y1, int* x2, int* y2); 563 Ath__grid* getGrid(uint level); 564 void addGrid(Ath__grid* g); 565 566 void getBuses(Ath__array1D<Ath__box*>* boxTable, dbTech* tech); 567 }; 568 569 class Ath__gridTable 570 { 571 private: 572 Ath__grid*** _gridTable; 573 Ath__box _bbox; 574 Ath__box _maxSearchBox; 575 bool _setMaxArea; 576 Rect _rectBB; 577 uint _rowCnt; 578 uint _colCnt; 579 uint _rowSize; 580 uint _colSize; 581 AthPool<Ath__track>* _trackPool; 582 AthPool<Ath__wire>* _wirePool; 583 uint _schema; 584 uint _overlapAdjust; 585 uint _powerMultiTrackWire; 586 uint _signalMultiTrackWire; 587 uint _overlapTouchCheck; 588 uint _noPowerSource; 589 uint _noPowerTarget; 590 uint _CCshorts; 591 uint _CCtargetHighTracks; 592 uint _CCtargetHighMarkedNet; 593 bool _targetTrackReversed; 594 bool _allNet; 595 bool _handleEmptyOnly; 596 bool _useDbSdb; 597 uint _ccFlag; 598 599 uint _ccContextDepth; 600 uint* _ccContextLength; 601 602 Ath__array1D<int>** _ccContextArray; 603 604 AthPool<odb::SEQ>* _seqPool; 605 Ath__array1D<odb::SEQ*>*** _dgContextArray; // array 606 607 uint* _dgContextDepth; // not array 608 uint* _dgContextPlanes; // not array 609 uint* _dgContextTracks; // not array 610 uint* _dgContextBaseLvl; // not array 611 int* _dgContextLowLvl; // not array 612 int* _dgContextHiLvl; // not array 613 uint* _dgContextBaseTrack; // array 614 int* _dgContextLowTrack; // array 615 int* _dgContextHiTrack; // array 616 int** _dgContextTrackBase; // array 617 618 int _signalPowerNotAlignedOverlap; 619 int _powerNotAlignedOverlap; 620 int _signalNotAlignedOverlap; 621 int _signalOverlap; 622 int _powerOverlap; 623 int _signalPowerOverlap; 624 int _powerSignalOverlap; 625 626 dbBlock* _block; 627 628 uint _wireCnt; 629 630 Ath__array1D<Ath__wire*>* _bandWire; 631 632 public: 633 Ath__gridTable(Ath__box* bb, 634 uint rowSize, 635 uint colSize, 636 uint layer, 637 uint dir, 638 uint width, 639 uint pitch); 640 Ath__gridTable(dbBox* bb, 641 uint rowSize, 642 uint colSize, 643 uint layer, 644 uint dir, 645 uint width, 646 uint pitch, 647 uint minWidth); 648 Ath__gridTable(Rect* bb, 649 uint layer, 650 uint dir, 651 uint width, 652 uint pitch, 653 uint minWidth); 654 Ath__gridTable(Rect* bb, 655 uint rowCnt, 656 uint colCnt, 657 uint* width, 658 uint* pitch, 659 uint* spacing, 660 int* X1 = NULL, 661 int* Y1 = NULL); 662 ~Ath__gridTable(); 663 Ath__grid* getGrid(uint row, uint col); 664 void init1(uint memChunk, uint rowSize, uint colSize, uint dx, uint dy); 665 uint getColCnt(); 666 uint getRowCnt(); 667 Ath__wire* getWirePtr(uint id); 668 void releaseWire(uint wireId); maxSearchBox()669 Ath__box* maxSearchBox() { return &_maxSearchBox; }; 670 int xMin(); 671 int xMax(); 672 int yMin(); 673 int yMax(); 674 uint getRowNum(int x); 675 uint getColNum(int y); 676 bool getRowCol(int x1, int y1, uint* row, uint* col); 677 Ath__wire* addBox(Ath__box* bb); 678 Ath__wire* addBox(dbBox* bb, uint wtype, uint id); 679 bool addBox(uint row, uint col, dbBox* bb); 680 uint setExtrusionMarker(uint startRow, uint startCol); 681 682 uint getBoxes(Ath__box* bb, Ath__array1D<Ath__box*>* table); 683 bool isOrdered(bool ascending); 684 uint search(Ath__searchBox* bb, 685 uint row, 686 uint col, 687 Ath__array1D<uint>* idTable, 688 bool wireIdFlag); 689 uint search(Ath__searchBox* bb, Ath__array1D<uint>* idTable); 690 uint search(Ath__box* bb); 691 Ath__wire* getWire_Linear(uint instId); 692 693 uint addBox(int x1, 694 int y1, 695 int x2, 696 int y2, 697 uint level, 698 uint id1, 699 uint id2, 700 uint wireType); 701 uint search(int x1, 702 int y1, 703 int x2, 704 int y2, 705 uint row, 706 uint col, 707 Ath__array1D<uint>* idTable, 708 bool wireIdFlag); 709 void getCoords(Ath__searchBox* bb, uint wireId); 710 void setMaxArea(int x1, int y1, int x2, int y2); 711 void resetMaxArea(); 712 713 void removeMarkedNetWires(); 714 715 // EXTRACTION 716 717 void setDefaultWireType(uint v); 718 void buildDgContext(int base, uint level, uint dir); 719 Ath__array1D<odb::SEQ*>* renewDgContext(uint gridn, uint trackn); 720 uint couplingCaps(Ath__gridTable* resGridTable, 721 uint couplingDist, 722 ZInterface* context, 723 Ath__array1D<uint>* ccTable, 724 rcx::CoupleAndCompute coupleAndCompute, 725 void* compPtr); 726 uint couplingCaps(uint row, 727 uint col, 728 Ath__grid* resGrid, 729 uint couplingDist, 730 ZInterface* context); 731 void getBox(uint wid, 732 int* x1, 733 int* y1, 734 int* x2, 735 int* y2, 736 uint* level, 737 uint* id1, 738 uint* id2, 739 uint* wireType); 740 void getCCdist(uint wid, uint* width, uint* level, uint* id1, uint* id2); 741 void getIds(uint wid, uint* id1, uint* id2, uint* wtype); 742 uint search(Ath__searchBox* bb, 743 uint* gxy, 744 uint row, 745 uint col, 746 Ath__array1D<uint>* idtable, 747 Ath__grid* g); getOverlapAdjust()748 uint getOverlapAdjust() { return _overlapAdjust; }; getOverlapTouchCheck()749 uint getOverlapTouchCheck() { return _overlapTouchCheck; }; targetHighTracks()750 uint targetHighTracks() { return _CCtargetHighTracks; }; targetHighMarkedNet()751 uint targetHighMarkedNet() { return _CCtargetHighMarkedNet; }; setCCFlag(uint ccflag)752 void setCCFlag(uint ccflag) { _ccFlag = ccflag; }; getCcFlag()753 uint getCcFlag() { return _ccFlag; }; contextDepth()754 uint contextDepth() { return _ccContextDepth; }; setContextLength(uint level,uint contextLength)755 void setContextLength(uint level, uint contextLength) 756 { 757 _ccContextLength[level] = contextLength; 758 }; contextArray()759 Ath__array1D<int>** contextArray() { return _ccContextArray; }; seqPool()760 AthPool<odb::SEQ>* seqPool() { return _seqPool; }; dgContextArray()761 Ath__array1D<odb::SEQ*>*** dgContextArray() { return _dgContextArray; }; dgContextTrackBase()762 int** dgContextTrackBase() { return _dgContextTrackBase; }; dgContextBaseTrack()763 uint* dgContextBaseTrack() { return _dgContextBaseTrack; }; dgContextLowTrack()764 int* dgContextLowTrack() { return _dgContextLowTrack; }; dgContextHiTrack()765 int* dgContextHiTrack() { return _dgContextHiTrack; }; allNet()766 bool allNet() { return _allNet; }; setAllNet(bool allnet)767 void setAllNet(bool allnet) { _allNet = allnet; }; handleEmptyOnly()768 bool handleEmptyOnly() { return _handleEmptyOnly; }; setHandleEmptyOnly(bool handleEmptyOnly)769 void setHandleEmptyOnly(bool handleEmptyOnly) 770 { 771 _handleEmptyOnly = handleEmptyOnly; 772 }; noPowerSource()773 uint noPowerSource() { return _noPowerSource; }; setNoPowerSource(uint nps)774 void setNoPowerSource(uint nps) { _noPowerSource = nps; }; noPowerTarget()775 uint noPowerTarget() { return _noPowerTarget; }; setNoPowerTarget(uint npt)776 void setNoPowerTarget(uint npt) { _noPowerTarget = npt; }; incrCCshorts()777 void incrCCshorts() { _CCshorts++; }; 778 void setExtControl(dbBlock* block, 779 bool useDbSdb, 780 uint adj, 781 uint npsrc, 782 uint nptgt, 783 uint ccUp, 784 bool allNet, 785 uint contextDepth, 786 Ath__array1D<int>** contextArray, 787 uint* contextLength, 788 Ath__array1D<odb::SEQ*>*** dgContextArray, 789 uint* dgContextDepth, 790 uint* dgContextPlanes, 791 uint* dgContextTracks, 792 uint* dgContextBaseLvl, 793 int* dgContextLowLvl, 794 int* dgContextHiLvl, 795 uint* dgContextBaseTrack, 796 int* dgContextLowTrack, 797 int* dgContextHiTrack, 798 int** dgContextTrackBase, 799 AthPool<odb::SEQ>* seqPool); usingDbSdb()800 bool usingDbSdb() { return _useDbSdb; } 801 void reverseTargetTrack(); targetTrackReversed()802 bool targetTrackReversed() { return _targetTrackReversed; }; 803 void adjustMetalFill(); 804 void incrNotAlignedOverlap(Ath__wire* w1, Ath__wire* w2); 805 void incrSignalOverlap(); 806 void incrPowerOverlap(); 807 void incrSignalToPowerOverlap(); 808 void incrPowerToSignallOverlap(); 809 void incrMultiTrackWireCnt(bool isPower); 810 void adjustOverlapMakerEnd(); 811 void dumpTrackCounts(FILE* fp); getBlock()812 dbBlock* getBlock() { return _block; }; setBlock(dbBlock * block)813 void setBlock(dbBlock* block) { _block = block; }; 814 815 int couplingCaps(int hiXY, 816 uint couplingDist, 817 uint dir, 818 uint& wireCnt, 819 rcx::CoupleAndCompute coupleAndCompute, 820 void* compPtr, 821 bool getBandWire, 822 int** limitArray); 823 void initCouplingCapLoops(uint dir, 824 uint couplingDist, 825 rcx::CoupleAndCompute coupleAndCompute, 826 void* compPtr, 827 int* startXY = NULL); 828 int dealloc(uint dir, int hiXY); 829 void dealloc(); 830 831 uint getWireCnt(); 832 }; 833