xref: /dragonfly/sys/dev/disk/sym/sym_fw1.h (revision 30702410)
1 /*-
2  *  Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3  *  PCI-SCSI controllers.
4  *
5  *  Copyright (C) 1999-2001  Gerard Roudier <groudier@free.fr>
6  *
7  *  This driver also supports the following Symbios/LSI PCI-SCSI chips:
8  *	53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9  *	53C810,  53C815,  53C825 and the 53C1510D is 53C8XX mode.
10  *
11  *
12  *  This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13  *  Copyright (C) 1998-1999  Gerard Roudier
14  *
15  *  The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16  *  a port of the FreeBSD ncr driver to Linux-1.2.13.
17  *
18  *  The original ncr driver has been written for 386bsd and FreeBSD by
19  *          Wolfgang Stanglmeier        <wolf@cologne.de>
20  *          Stefan Esser                <se@mi.Uni-Koeln.de>
21  *  Copyright (C) 1994  Wolfgang Stanglmeier
22  *
23  *  The initialisation code, and part of the code that addresses
24  *  FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25  *  written by Justin T. Gibbs.
26  *
27  *  Other major contributions:
28  *
29  *  NVRAM detection and reading.
30  *  Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31  *
32  *-----------------------------------------------------------------------------
33  *
34  * Redistribution and use in source and binary forms, with or without
35  * modification, are permitted provided that the following conditions
36  * are met:
37  * 1. Redistributions of source code must retain the above copyright
38  *    notice, this list of conditions and the following disclaimer.
39  * 2. Redistributions in binary form must reproduce the above copyright
40  *    notice, this list of conditions and the following disclaimer in the
41  *    documentation and/or other materials provided with the distribution.
42  * 3. The name of the author may not be used to endorse or promote products
43  *    derived from this software without specific prior written permission.
44  *
45  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55  * SUCH DAMAGE.
56  */
57 
58 /* $FreeBSD: src/sys/dev/sym/sym_fw1.h,v 1.12 2011/04/22 12:46:39 marius Exp $ */
59 
60 /*
61  *  Scripts for SYMBIOS-Processor
62  *
63  *  We have to know the offsets of all labels before we reach
64  *  them (for forward jumps). Therefore we declare a struct
65  *  here. If you make changes inside the script,
66  *
67  *  DONT FORGET TO CHANGE THE LENGTHS HERE!
68  */
69 
70 /*
71  *  Script fragments which are loaded into the on-chip RAM
72  *  of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
73  *  Must not exceed 4K bytes.
74  */
75 struct SYM_FWA_SCR {
76 	u32 start		[ 11];
77 	u32 getjob_begin	[  4];
78 	u32 _sms_a10		[  5];
79 	u32 getjob_end		[  4];
80 	u32 _sms_a20		[  4];
81 	u32 select		[  8];
82 	u32 _sms_a30		[  8];
83 	u32 wf_sel_done		[  2];
84 	u32 send_ident		[  2];
85 #ifdef SYM_CONF_IARB_SUPPORT
86 	u32 select2		[  8];
87 #else
88 	u32 select2		[  2];
89 #endif
90 	u32 command		[  2];
91 	u32 dispatch		[ 28];
92 	u32 sel_no_cmd		[ 10];
93 	u32 init		[  6];
94 	u32 clrack		[  4];
95 	u32 disp_status		[  4];
96 	u32 datai_done		[ 26];
97 	u32 datao_done		[ 12];
98 	u32 datai_phase		[  2];
99 	u32 datao_phase		[  2];
100 	u32 msg_in		[  2];
101 	u32 msg_in2		[ 10];
102 #ifdef SYM_CONF_IARB_SUPPORT
103 	u32 status		[ 14];
104 #else
105 	u32 status		[ 10];
106 #endif
107 	u32 complete		[  9];
108 	u32 complete2		[  8];
109 	u32 _sms_a40		[ 12];
110 	u32 complete_error	[  5];
111 	u32 done		[  5];
112 	u32 _sms_a50		[  5];
113 	u32 _sms_a60		[  2];
114 	u32 done_end		[  4];
115 	u32 save_dp		[  9];
116 	u32 restore_dp		[  5];
117 	u32 disconnect		[ 20];
118 	u32 disconnect2		[  5];
119 	u32 _sms_a65		[  3];
120 #ifdef SYM_CONF_IARB_SUPPORT
121 	u32 idle		[  4];
122 #else
123 	u32 idle		[  2];
124 #endif
125 #ifdef SYM_CONF_IARB_SUPPORT
126 	u32 ungetjob		[  7];
127 #else
128 	u32 ungetjob		[  5];
129 #endif
130 	u32 reselect		[  4];
131 	u32 reselected		[ 19];
132 	u32 _sms_a70		[  6];
133 	u32 _sms_a80		[  4];
134 	u32 reselected1		[ 25];
135 	u32 _sms_a90		[  4];
136 	u32 resel_lun0		[  7];
137 	u32 _sms_a100		[  4];
138 	u32 resel_tag		[  8];
139 #if   SYM_CONF_MAX_TASK*4 > 512
140 	u32 _sms_a110		[ 23];
141 #elif SYM_CONF_MAX_TASK*4 > 256
142 	u32 _sms_a110		[ 17];
143 #else
144 	u32 _sms_a110		[ 13];
145 #endif
146 	u32 _sms_a120		[  2];
147 	u32 resel_go		[  4];
148 	u32 _sms_a130		[  7];
149 	u32 resel_dsa		[  2];
150 	u32 resel_dsa1		[  4];
151 	u32 _sms_a140		[ 10];
152 	u32 resel_no_tag	[  4];
153 	u32 _sms_a145		[  7];
154 	u32 data_in		[SYM_CONF_MAX_SG * 2];
155 	u32 data_in2		[  4];
156 	u32 data_out		[SYM_CONF_MAX_SG * 2];
157 	u32 data_out2		[  4];
158 	u32 pm0_data		[ 12];
159 	u32 pm0_data_out	[  6];
160 	u32 pm0_data_end	[  7];
161 	u32 pm_data_end		[  4];
162 	u32 _sms_a150		[  4];
163 	u32 pm1_data		[ 12];
164 	u32 pm1_data_out	[  6];
165 	u32 pm1_data_end	[  9];
166 };
167 
168 /*
169  *  Script fragments which stay in main memory for all chips
170  *  except for chips that support 8K on-chip RAM.
171  */
172 struct SYM_FWB_SCR {
173 	u32 no_data		[  2];
174 	u32 sel_for_abort	[ 18];
175 	u32 sel_for_abort_1	[  2];
176 	u32 msg_in_etc		[ 12];
177 	u32 msg_received	[  5];
178 	u32 msg_weird_seen	[  5];
179 	u32 msg_extended	[ 17];
180 	u32 _sms_b10		[  4];
181 	u32 msg_bad		[  6];
182 	u32 msg_weird		[  4];
183 	u32 msg_weird1		[  8];
184 	u32 wdtr_resp		[  6];
185 	u32 send_wdtr		[  4];
186 	u32 sdtr_resp		[  6];
187 	u32 send_sdtr		[  4];
188 	u32 ppr_resp		[  6];
189 	u32 send_ppr		[  4];
190 	u32 nego_bad_phase	[  4];
191 	u32 msg_out		[  4];
192 	u32 msg_out_done	[  4];
193 	u32 data_ovrun		[  3];
194 	u32 data_ovrun1		[ 22];
195 	u32 data_ovrun2		[  8];
196 	u32 abort_resel		[ 16];
197 	u32 resend_ident	[  4];
198 	u32 ident_break		[  4];
199 	u32 ident_break_atn	[  4];
200 	u32 sdata_in		[  6];
201 	u32 resel_bad_lun	[  4];
202 	u32 bad_i_t_l		[  4];
203 	u32 bad_i_t_l_q		[  4];
204 	u32 bad_status		[  7];
205 	u32 wsr_ma_helper	[  4];
206 
207 	/* Data area */
208 	u32 zero		[  1];
209 	u32 scratch		[  1];
210 	u32 scratch1		[  1];
211 	u32 prev_done		[  1];
212 	u32 done_pos		[  1];
213 	u32 nextjob		[  1];
214 	u32 startpos		[  1];
215 	u32 targtbl		[  1];
216 	/* End of data area */
217 
218 	u32 snooptest		[  9];
219 	u32 snoopend		[  2];
220 };
221 
222 static const struct SYM_FWA_SCR SYM_FWA_SCR = {
223 /*--------------------------< START >----------------------------*/ {
224 	/*
225 	 *  Switch the LED on.
226 	 *  Will be patched with a NO_OP if LED
227 	 *  not needed or not desired.
228 	 */
229 	SCR_REG_REG (gpreg, SCR_AND, 0xfe),
230 		0,
231 	/*
232 	 *      Clear SIGP.
233 	 */
234 	SCR_FROM_REG (ctest2),
235 		0,
236 	/*
237 	 *  Stop here if the C code wants to perform
238 	 *  some error recovery procedure manually.
239 	 *  (Indicate this by setting SEM in ISTAT)
240 	 */
241 	SCR_FROM_REG (istat),
242 		0,
243 	/*
244 	 *  Report to the C code the next position in
245 	 *  the start queue the SCRIPTS will schedule.
246 	 *  The C code must not change SCRATCHA.
247 	 */
248 	SCR_COPY (4),
249 		PADDR_B (startpos),
250 		RADDR_1 (scratcha),
251 	SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
252 		SIR_SCRIPT_STOPPED,
253 	/*
254 	 *  Start the next job.
255 	 *
256 	 *  @DSA     = start point for this job.
257 	 *  SCRATCHA = address of this job in the start queue.
258 	 *
259 	 *  We will restore startpos with SCRATCHA if we fails the
260 	 *  arbitration or if it is the idle job.
261 	 *
262 	 *  The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
263 	 *  is a critical path. If it is partially executed, it then
264 	 *  may happen that the job address is not yet in the DSA
265 	 *  and the next queue position points to the next JOB.
266 	 */
267 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
268 	/*
269 	 *  Copy to a fixed location both the next STARTPOS
270 	 *  and the current JOB address, using self modifying
271 	 *  SCRIPTS.
272 	 */
273 	SCR_COPY (4),
274 		RADDR_1 (scratcha),
275 		PADDR_A (_sms_a10),
276 	SCR_COPY (8),
277 }/*-------------------------< _SMS_A10 >-------------------------*/,{
278 		0,
279 		PADDR_B (nextjob),
280 	/*
281 	 *  Move the start address to TEMP using self-
282 	 *  modifying SCRIPTS and jump indirectly to
283 	 *  that address.
284 	 */
285 	SCR_COPY (4),
286 		PADDR_B (nextjob),
287 		RADDR_1 (dsa),
288 }/*-------------------------< GETJOB_END >-----------------------*/,{
289 	SCR_COPY (4),
290 		RADDR_1 (dsa),
291 		PADDR_A (_sms_a20),
292 	SCR_COPY (4),
293 }/*-------------------------< _SMS_A20 >-------------------------*/,{
294 		0,
295 		RADDR_1 (temp),
296 	SCR_RETURN,
297 		0,
298 }/*-------------------------< SELECT >---------------------------*/,{
299 	/*
300 	 *  DSA	contains the address of a scheduled
301 	 *  	data structure.
302 	 *
303 	 *  SCRATCHA contains the address of the start queue
304 	 *  	entry which points to the next job.
305 	 *
306 	 *  Set Initiator mode.
307 	 *
308 	 *  (Target mode is left as an exercise for the reader)
309 	 */
310 	SCR_CLR (SCR_TRG),
311 		0,
312 	/*
313 	 *      And try to select this target.
314 	 */
315 	SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
316 		PADDR_A (ungetjob),
317 	/*
318 	 *  Now there are 4 possibilities:
319 	 *
320 	 *  (1) The chip loses arbitration.
321 	 *  This is ok, because it will try again,
322 	 *  when the bus becomes idle.
323 	 *  (But beware of the timeout function!)
324 	 *
325 	 *  (2) The chip is reselected.
326 	 *  Then the script processor takes the jump
327 	 *  to the RESELECT label.
328 	 *
329 	 *  (3) The chip wins arbitration.
330 	 *  Then it will execute SCRIPTS instruction until
331 	 *  the next instruction that checks SCSI phase.
332 	 *  Then will stop and wait for selection to be
333 	 *  complete or selection time-out to occur.
334 	 *
335 	 *  After having won arbitration, the SCRIPTS
336 	 *  processor is able to execute instructions while
337 	 *  the SCSI core is performing SCSI selection.
338 	 */
339 
340 	/*
341 	 *  Copy the CCB header to a fixed location
342 	 *  in the HCB using self-modifying SCRIPTS.
343 	 */
344 	SCR_COPY (4),
345 		RADDR_1 (dsa),
346 		PADDR_A (_sms_a30),
347 	SCR_COPY (sizeof(struct sym_ccbh)),
348 }/*-------------------------< _SMS_A30 >-------------------------*/,{
349 		0,
350 		HADDR_1 (ccb_head),
351 	/*
352 	 *  Load the savep (saved data pointer) into
353 	 *  the actual data pointer.
354 	 */
355 	SCR_COPY (4),
356 		HADDR_1 (ccb_head.savep),
357 		RADDR_1 (temp),
358 	/*
359 	 *  Initialize the status register
360 	 */
361 	SCR_COPY (4),
362 		HADDR_1 (ccb_head.status),
363 		RADDR_1 (scr0),
364 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
365 	SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
366 		SIR_SEL_ATN_NO_MSG_OUT,
367 }/*-------------------------< SEND_IDENT >-----------------------*/,{
368 	/*
369 	 *  Selection complete.
370 	 *  Send the IDENTIFY and possibly the TAG message
371 	 *  and negotiation message if present.
372 	 */
373 	SCR_MOVE_TBL ^ SCR_MSG_OUT,
374 		offsetof (struct sym_dsb, smsg),
375 }/*-------------------------< SELECT2 >--------------------------*/,{
376 #ifdef SYM_CONF_IARB_SUPPORT
377 	/*
378 	 *  Set IMMEDIATE ARBITRATION if we have been given
379 	 *  a hint to do so. (Some job to do after this one).
380 	 */
381 	SCR_FROM_REG (HF_REG),
382 		0,
383 	SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
384 		8,
385 	SCR_REG_REG (scntl1, SCR_OR, IARB),
386 		0,
387 #endif
388 	/*
389 	 *  Anticipate the COMMAND phase.
390 	 *  This is the PHASE we expect at this point.
391 	 */
392 	SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
393 		PADDR_A (sel_no_cmd),
394 }/*-------------------------< COMMAND >--------------------------*/,{
395 	/*
396 	 *  ... and send the command
397 	 */
398 	SCR_MOVE_TBL ^ SCR_COMMAND,
399 		offsetof (struct sym_dsb, cmd),
400 }/*-------------------------< DISPATCH >-------------------------*/,{
401 	/*
402 	 *  MSG_IN is the only phase that shall be
403 	 *  entered at least once for each (re)selection.
404 	 *  So we test it first.
405 	 */
406 	SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
407 		PADDR_A (msg_in),
408 	SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
409 		PADDR_A (datao_phase),
410 	SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
411 		PADDR_A (datai_phase),
412 	SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
413 		PADDR_A (status),
414 	SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
415 		PADDR_A (command),
416 	SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
417 		PADDR_B (msg_out),
418 	/*
419 	 *  Discard as many illegal phases as
420 	 *  required and tell the C code about.
421 	 */
422 	SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
423 		16,
424 	SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
425 		HADDR_1 (scratch),
426 	SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
427 		-16,
428 	SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
429 		16,
430 	SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
431 		HADDR_1 (scratch),
432 	SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
433 		-16,
434 	SCR_INT,
435 		SIR_BAD_PHASE,
436 	SCR_JUMP,
437 		PADDR_A (dispatch),
438 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
439 	/*
440 	 *  The target does not switch to command
441 	 *  phase after IDENTIFY has been sent.
442 	 *
443 	 *  If it stays in MSG OUT phase send it
444 	 *  the IDENTIFY again.
445 	 */
446 	SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
447 		PADDR_B (resend_ident),
448 	/*
449 	 *  If target does not switch to MSG IN phase
450 	 *  and we sent a negotiation, assert the
451 	 *  failure immediately.
452 	 */
453 	SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
454 		PADDR_A (dispatch),
455 	SCR_FROM_REG (HS_REG),
456 		0,
457 	SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
458 		SIR_NEGO_FAILED,
459 	/*
460 	 *  Jump to dispatcher.
461 	 */
462 	SCR_JUMP,
463 		PADDR_A (dispatch),
464 }/*-------------------------< INIT >-----------------------------*/,{
465 	/*
466 	 *  Wait for the SCSI RESET signal to be
467 	 *  inactive before restarting operations,
468 	 *  since the chip may hang on SEL_ATN
469 	 *  if SCSI RESET is active.
470 	 */
471 	SCR_FROM_REG (sstat0),
472 		0,
473 	SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
474 		-16,
475 	SCR_JUMP,
476 		PADDR_A (start),
477 }/*-------------------------< CLRACK >---------------------------*/,{
478 	/*
479 	 *  Terminate possible pending message phase.
480 	 */
481 	SCR_CLR (SCR_ACK),
482 		0,
483 	SCR_JUMP,
484 		PADDR_A (dispatch),
485 }/*-------------------------< DISP_STATUS >----------------------*/,{
486 	/*
487 	 *  Anticipate STATUS phase.
488 	 *
489 	 *  Does spare 3 SCRIPTS instructions when we have
490 	 *  completed the INPUT of the data.
491 	 */
492 	SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
493 		PADDR_A (status),
494 	SCR_JUMP,
495 		PADDR_A (dispatch),
496 }/*-------------------------< DATAI_DONE >-----------------------*/,{
497 	/*
498 	 *  If the device still wants to send us data,
499 	 *  we must count the extra bytes.
500 	 */
501 	SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)),
502 		PADDR_B (data_ovrun),
503 	/*
504 	 *  If the SWIDE is not full, jump to dispatcher.
505 	 *  We anticipate a STATUS phase.
506 	 */
507 	SCR_FROM_REG (scntl2),
508 		0,
509 	SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)),
510 		PADDR_A (disp_status),
511 	/*
512 	 *  The SWIDE is full.
513 	 *  Clear this condition.
514 	 */
515 	SCR_REG_REG (scntl2, SCR_OR, WSR),
516 		0,
517 	/*
518 	 *  We are expecting an IGNORE RESIDUE message
519 	 *  from the device, otherwise we are in data
520 	 *  overrun condition. Check against MSG_IN phase.
521 	 */
522 	SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
523 		SIR_SWIDE_OVERRUN,
524 	SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
525 		PADDR_A (disp_status),
526 	/*
527 	 *  We are in MSG_IN phase,
528 	 *  Read the first byte of the message.
529 	 *  If it is not an IGNORE RESIDUE message,
530 	 *  signal overrun and jump to message
531 	 *  processing.
532 	 */
533 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
534 		HADDR_1 (msgin[0]),
535 	SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
536 		SIR_SWIDE_OVERRUN,
537 	SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
538 		PADDR_A (msg_in2),
539 	/*
540 	 *  We got the message we expected.
541 	 *  Read the 2nd byte, and jump to dispatcher.
542 	 */
543 	SCR_CLR (SCR_ACK),
544 		0,
545 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
546 		HADDR_1 (msgin[1]),
547 	SCR_CLR (SCR_ACK),
548 		0,
549 	SCR_JUMP,
550 		PADDR_A (disp_status),
551 }/*-------------------------< DATAO_DONE >-----------------------*/,{
552 	/*
553 	 *  If the device wants us to send more data,
554 	 *  we must count the extra bytes.
555 	 */
556 	SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)),
557 		PADDR_B (data_ovrun),
558 	/*
559 	 *  If the SODL is not full jump to dispatcher.
560 	 *  We anticipate a STATUS phase.
561 	 */
562 	SCR_FROM_REG (scntl2),
563 		0,
564 	SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)),
565 		PADDR_A (disp_status),
566 	/*
567 	 *  The SODL is full, clear this condition.
568 	 */
569 	SCR_REG_REG (scntl2, SCR_OR, WSS),
570 		0,
571 	/*
572 	 *  And signal a DATA UNDERRUN condition
573 	 *  to the C code.
574 	 */
575 	SCR_INT,
576 		SIR_SODL_UNDERRUN,
577 	SCR_JUMP,
578 		PADDR_A (dispatch),
579 }/*-------------------------< DATAI_PHASE >----------------------*/,{
580 	SCR_RETURN,
581 		0,
582 }/*-------------------------< DATAO_PHASE >----------------------*/,{
583 	SCR_RETURN,
584 		0,
585 }/*-------------------------< MSG_IN >---------------------------*/,{
586 	/*
587 	 *  Get the first byte of the message.
588 	 *
589 	 *  The script processor doesn't negate the
590 	 *  ACK signal after this transfer.
591 	 */
592 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
593 		HADDR_1 (msgin[0]),
594 }/*-------------------------< MSG_IN2 >--------------------------*/,{
595 	/*
596 	 *  Check first against 1 byte messages
597 	 *  that we handle from SCRIPTS.
598 	 */
599 	SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
600 		PADDR_A (complete),
601 	SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
602 		PADDR_A (disconnect),
603 	SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
604 		PADDR_A (save_dp),
605 	SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
606 		PADDR_A (restore_dp),
607 	/*
608 	 *  We handle all other messages from the
609 	 *  C code, so no need to waste on-chip RAM
610 	 *  for those ones.
611 	 */
612 	SCR_JUMP,
613 		PADDR_B (msg_in_etc),
614 }/*-------------------------< STATUS >---------------------------*/,{
615 	/*
616 	 *  get the status
617 	 */
618 	SCR_MOVE_ABS (1) ^ SCR_STATUS,
619 		HADDR_1 (scratch),
620 #ifdef SYM_CONF_IARB_SUPPORT
621 	/*
622 	 *  If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
623 	 *  since we may have to tamper the start queue from
624 	 *  the C code.
625 	 */
626 	SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
627 		8,
628 	SCR_REG_REG (scntl1, SCR_AND, ~IARB),
629 		0,
630 #endif
631 	/*
632 	 *  save status to scsi_status.
633 	 *  mark as complete.
634 	 */
635 	SCR_TO_REG (SS_REG),
636 		0,
637 	SCR_LOAD_REG (HS_REG, HS_COMPLETE),
638 		0,
639 	/*
640 	 *  Anticipate the MESSAGE PHASE for
641 	 *  the TASK COMPLETE message.
642 	 */
643 	SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
644 		PADDR_A (msg_in),
645 	SCR_JUMP,
646 		PADDR_A (dispatch),
647 }/*-------------------------< COMPLETE >-------------------------*/,{
648 	/*
649 	 *  Complete message.
650 	 *
651 	 *  Copy the data pointer to LASTP.
652 	 */
653 	SCR_COPY (4),
654 		RADDR_1 (temp),
655 		HADDR_1 (ccb_head.lastp),
656 	/*
657 	 *  When we terminate the cycle by clearing ACK,
658 	 *  the target may disconnect immediately.
659 	 *
660 	 *  We don't want to be told of an "unexpected disconnect",
661 	 *  so we disable this feature.
662 	 */
663 	SCR_REG_REG (scntl2, SCR_AND, 0x7f),
664 		0,
665 	/*
666 	 *  Terminate cycle ...
667 	 */
668 	SCR_CLR (SCR_ACK|SCR_ATN),
669 		0,
670 	/*
671 	 *  ... and wait for the disconnect.
672 	 */
673 	SCR_WAIT_DISC,
674 		0,
675 }/*-------------------------< COMPLETE2 >------------------------*/,{
676 	/*
677 	 *  Save host status.
678 	 */
679 	SCR_COPY (4),
680 		RADDR_1 (scr0),
681 		HADDR_1 (ccb_head.status),
682 	/*
683 	 *  Move back the CCB header using self-modifying
684 	 *  SCRIPTS.
685 	 */
686 	SCR_COPY (4),
687 		RADDR_1 (dsa),
688 		PADDR_A (_sms_a40),
689 	SCR_COPY (sizeof(struct sym_ccbh)),
690 		HADDR_1 (ccb_head),
691 }/*-------------------------< _SMS_A40 >-------------------------*/,{
692 		0,
693 	/*
694 	 *  Some bridges may reorder DMA writes to memory.
695 	 *  We donnot want the CPU to deal with completions
696 	 *  without all the posted write having been flushed
697 	 *  to memory. This DUMMY READ should flush posted
698 	 *  buffers prior to the CPU having to deal with
699 	 *  completions.
700 	 */
701 	SCR_COPY (4),			/* DUMMY READ */
702 		HADDR_1 (ccb_head.status),
703 		RADDR_1 (scr0),
704 	/*
705 	 *  If command resulted in not GOOD status,
706 	 *  call the C code if needed.
707 	 */
708 	SCR_FROM_REG (SS_REG),
709 		0,
710 	SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
711 		PADDR_B (bad_status),
712 	/*
713 	 *  If we performed an auto-sense, call
714 	 *  the C code to synchronyze task aborts
715 	 *  with UNIT ATTENTION conditions.
716 	 */
717 	SCR_FROM_REG (HF_REG),
718 		0,
719 	SCR_JUMP ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
720 		PADDR_A (done),
721 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
722 	SCR_COPY (4),
723 		PADDR_B (startpos),
724 		RADDR_1 (scratcha),
725 	SCR_INT,
726 		SIR_COMPLETE_ERROR,
727 }/*-------------------------< DONE >-----------------------------*/,{
728 	/*
729 	 *  Copy the DSA to the DONE QUEUE and
730 	 *  signal completion to the host.
731 	 *  If we are interrupted between DONE
732 	 *  and DONE_END, we must reset, otherwise
733 	 *  the completed CCB may be lost.
734 	 */
735 	SCR_COPY (4),
736 		PADDR_B (done_pos),
737 		PADDR_A (_sms_a50),
738 	SCR_COPY (4),
739 		RADDR_1 (dsa),
740 }/*-------------------------< _SMS_A50 >-------------------------*/,{
741 		0,
742 	SCR_COPY (4),
743 		PADDR_B (done_pos),
744 		PADDR_A (_sms_a60),
745 	/*
746 	 *  The instruction below reads the DONE QUEUE next
747 	 *  free position from memory.
748 	 *  In addition it ensures that all PCI posted writes
749 	 *  are flushed and so the DSA value of the done
750 	 *  CCB is visible by the CPU before INTFLY is raised.
751 	 */
752 	SCR_COPY (8),
753 }/*-------------------------< _SMS_A60 >-------------------------*/,{
754 		0,
755 		PADDR_B (prev_done),
756 }/*-------------------------< DONE_END >-------------------------*/,{
757 	SCR_INT_FLY,
758 		0,
759 	SCR_JUMP,
760 		PADDR_A (start),
761 }/*-------------------------< SAVE_DP >--------------------------*/,{
762 	/*
763 	 *  Clear ACK immediately.
764 	 *  No need to delay it.
765 	 */
766 	SCR_CLR (SCR_ACK),
767 		0,
768 	/*
769 	 *  Keep track we received a SAVE DP, so
770 	 *  we will switch to the other PM context
771 	 *  on the next PM since the DP may point
772 	 *  to the current PM context.
773 	 */
774 	SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
775 		0,
776 	/*
777 	 *  SAVE_DP message:
778 	 *  Copy the data pointer to SAVEP.
779 	 */
780 	SCR_COPY (4),
781 		RADDR_1 (temp),
782 		HADDR_1 (ccb_head.savep),
783 	SCR_JUMP,
784 		PADDR_A (dispatch),
785 }/*-------------------------< RESTORE_DP >-----------------------*/,{
786 	/*
787 	 *  RESTORE_DP message:
788 	 *  Copy SAVEP to actual data pointer.
789 	 */
790 	SCR_COPY (4),
791 		HADDR_1 (ccb_head.savep),
792 		RADDR_1 (temp),
793 	SCR_JUMP,
794 		PADDR_A (clrack),
795 }/*-------------------------< DISCONNECT >-----------------------*/,{
796 	/*
797 	 *  DISCONNECTing  ...
798 	 *
799 	 *  disable the "unexpected disconnect" feature,
800 	 *  and remove the ACK signal.
801 	 */
802 	SCR_REG_REG (scntl2, SCR_AND, 0x7f),
803 		0,
804 	SCR_CLR (SCR_ACK|SCR_ATN),
805 		0,
806 	/*
807 	 *  Wait for the disconnect.
808 	 */
809 	SCR_WAIT_DISC,
810 		0,
811 	/*
812 	 *  Status is: DISCONNECTED.
813 	 */
814 	SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
815 		0,
816 	/*
817 	 *  Save host status.
818 	 */
819 	SCR_COPY (4),
820 		RADDR_1 (scr0),
821 		HADDR_1 (ccb_head.status),
822 	/*
823 	 *  If QUIRK_AUTOSAVE is set,
824 	 *  do a "save pointer" operation.
825 	 */
826 	SCR_FROM_REG (QU_REG),
827 		0,
828 	SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)),
829 		PADDR_A (disconnect2),
830 	/*
831 	 *  like SAVE_DP message:
832 	 *  Remember we saved the data pointer.
833 	 *  Copy data pointer to SAVEP.
834 	 */
835 	SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
836 		0,
837 	SCR_COPY (4),
838 		RADDR_1 (temp),
839 		HADDR_1 (ccb_head.savep),
840 }/*-------------------------< DISCONNECT2 >----------------------*/,{
841 	/*
842 	 *  Move back the CCB header using self-modifying
843 	 *  SCRIPTS.
844 	 */
845 	SCR_COPY (4),
846 		RADDR_1 (dsa),
847 		PADDR_A (_sms_a65),
848 	SCR_COPY (sizeof(struct sym_ccbh)),
849 		HADDR_1 (ccb_head),
850 }/*-------------------------< _SMS_A65 >-------------------------*/,{
851 		0,
852 	SCR_JUMP,
853 		PADDR_A (start),
854 }/*-------------------------< IDLE >-----------------------------*/,{
855 	/*
856 	 *  Nothing to do?
857 	 *  Switch the LED off and wait for reselect.
858 	 *  Will be patched with a NO_OP if LED
859 	 *  not needed or not desired.
860 	 */
861 	SCR_REG_REG (gpreg, SCR_OR, 0x01),
862 		0,
863 #ifdef SYM_CONF_IARB_SUPPORT
864 	SCR_JUMPR,
865 		8,
866 #endif
867 }/*-------------------------< UNGETJOB >-------------------------*/,{
868 #ifdef SYM_CONF_IARB_SUPPORT
869 	/*
870 	 *  Set IMMEDIATE ARBITRATION, for the next time.
871 	 *  This will give us better chance to win arbitration
872 	 *  for the job we just wanted to do.
873 	 */
874 	SCR_REG_REG (scntl1, SCR_OR, IARB),
875 		0,
876 #endif
877 	/*
878 	 *  We are not able to restart the SCRIPTS if we are
879 	 *  interrupted and these instruction haven't been
880 	 *  all executed. BTW, this is very unlikely to
881 	 *  happen, but we check that from the C code.
882 	 */
883 	SCR_LOAD_REG (dsa, 0xff),
884 		0,
885 	SCR_COPY (4),
886 		RADDR_1 (scratcha),
887 		PADDR_B (startpos),
888 }/*-------------------------< RESELECT >-------------------------*/,{
889 	/*
890 	 *  Make sure we are in initiator mode.
891 	 */
892 	SCR_CLR (SCR_TRG),
893 		0,
894 	/*
895 	 *  Sleep waiting for a reselection.
896 	 */
897 	SCR_WAIT_RESEL,
898 		PADDR_A(start),
899 }/*-------------------------< RESELECTED >-----------------------*/,{
900 	/*
901 	 *  Switch the LED on.
902 	 *  Will be patched with a NO_OP if LED
903 	 *  not needed or not desired.
904 	 */
905 	SCR_REG_REG (gpreg, SCR_AND, 0xfe),
906 		0,
907 	/*
908 	 *  load the target id into the sdid
909 	 */
910 	SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
911 		0,
912 	SCR_TO_REG (sdid),
913 		0,
914 	/*
915 	 *  Load the target control block address
916 	 */
917 	SCR_COPY (4),
918 		PADDR_B (targtbl),
919 		RADDR_1 (dsa),
920 	SCR_SFBR_REG (dsa, SCR_SHL, 0),
921 		0,
922 	SCR_REG_REG (dsa, SCR_SHL, 0),
923 		0,
924 	SCR_REG_REG (dsa, SCR_AND, 0x3c),
925 		0,
926 	SCR_COPY (4),
927 		RADDR_1 (dsa),
928 		PADDR_A (_sms_a70),
929 	SCR_COPY (4),
930 }/*-------------------------< _SMS_A70 >-------------------------*/,{
931 		0,
932 		RADDR_1 (dsa),
933 	/*
934 	 *  Copy the TCB header to a fixed place in
935 	 *  the HCB.
936 	 */
937 	SCR_COPY (4),
938 		RADDR_1 (dsa),
939 		PADDR_A (_sms_a80),
940 	SCR_COPY (sizeof(struct sym_tcbh)),
941 }/*-------------------------< _SMS_A80 >-------------------------*/,{
942 		0,
943 		HADDR_1 (tcb_head),
944 	/*
945 	 *  We expect MESSAGE IN phase.
946 	 *  If not, get help from the C code.
947 	 */
948 	SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
949 		SIR_RESEL_NO_MSG_IN,
950 }/*-------------------------< RESELECTED1 >----------------------*/,{
951 	/*
952 	 *  Load the synchronous transfer registers.
953 	 */
954 	SCR_COPY (1),
955 		HADDR_1 (tcb_head.wval),
956 		RADDR_1 (scntl3),
957 	SCR_COPY (1),
958 		HADDR_1 (tcb_head.sval),
959 		RADDR_1 (sxfer),
960 	/*
961 	 *  Get the IDENTIFY message.
962 	 */
963 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
964 		HADDR_1 (msgin),
965 	/*
966 	 *  If IDENTIFY LUN #0, use a faster path
967 	 *  to find the LCB structure.
968 	 */
969 	SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
970 		PADDR_A (resel_lun0),
971 	/*
972 	 *  If message isn't an IDENTIFY,
973 	 *  tell the C code about.
974 	 */
975 	SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
976 		SIR_RESEL_NO_IDENTIFY,
977 	/*
978 	 *  It is an IDENTIFY message,
979 	 *  Load the LUN control block address.
980 	 */
981 	SCR_COPY (4),
982 		HADDR_1 (tcb_head.luntbl_sa),
983 		RADDR_1 (dsa),
984 	SCR_SFBR_REG (dsa, SCR_SHL, 0),
985 		0,
986 	SCR_REG_REG (dsa, SCR_SHL, 0),
987 		0,
988 	SCR_REG_REG (dsa, SCR_AND, 0xfc),
989 		0,
990 	SCR_COPY (4),
991 		RADDR_1 (dsa),
992 		PADDR_A (_sms_a90),
993 	SCR_COPY (4),
994 }/*-------------------------< _SMS_A90 >-------------------------*/,{
995 		0,
996 		RADDR_1 (dsa),
997 	SCR_JUMPR,
998 		12,
999 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
1000 	/*
1001 	 *  LUN 0 special case (but usual one :))
1002 	 */
1003 	SCR_COPY (4),
1004 		HADDR_1 (tcb_head.lun0_sa),
1005 		RADDR_1 (dsa),
1006 	/*
1007 	 *  Jump indirectly to the reselect action for this LUN.
1008 	 *  (lcb.head.resel_sa assumed at offset zero of lcb).
1009 	 */
1010 	SCR_COPY (4),
1011 		RADDR_1 (dsa),
1012 		PADDR_A (_sms_a100),
1013 	SCR_COPY (4),
1014 }/*-------------------------< _SMS_A100 >------------------------*/,{
1015 		0,
1016 		RADDR_1 (temp),
1017 	SCR_RETURN,
1018 		0,
1019 	/* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
1020 }/*-------------------------< RESEL_TAG >------------------------*/,{
1021 	/*
1022 	 *  ACK the IDENTIFY previously received.
1023 	 */
1024 	SCR_CLR (SCR_ACK),
1025 		0,
1026 	/*
1027 	 *  It shall be a tagged command.
1028 	 *  Read SIMPLE+TAG.
1029 	 *  The C code will deal with errors.
1030 	 *  Aggressive optimization, isn't it? :)
1031 	 */
1032 	SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
1033 		HADDR_1 (msgin),
1034 	/*
1035 	 *  Copy the LCB header to a fixed place in
1036 	 *  the HCB using self-modifying SCRIPTS.
1037 	 */
1038 	SCR_COPY (4),
1039 		RADDR_1 (dsa),
1040 		PADDR_A (_sms_a110),
1041 	SCR_COPY (sizeof(struct sym_lcbh)),
1042 }/*-------------------------< _SMS_A110 >------------------------*/,{
1043 		0,
1044 		HADDR_1 (lcb_head),
1045 	/*
1046 	 *  Load the pointer to the tagged task
1047 	 *  table for this LUN.
1048 	 */
1049 	SCR_COPY (4),
1050 		HADDR_1 (lcb_head.itlq_tbl_sa),
1051 		RADDR_1 (dsa),
1052 	/*
1053 	 *  The SIDL still contains the TAG value.
1054 	 *  Aggressive optimization, isn't it? :):)
1055 	 */
1056 	SCR_REG_SFBR (sidl, SCR_SHL, 0),
1057 		0,
1058 #if SYM_CONF_MAX_TASK*4 > 512
1059 	SCR_JUMPR ^ IFFALSE (CARRYSET),
1060 		8,
1061 	SCR_REG_REG (dsa1, SCR_OR, 2),
1062 		0,
1063 	SCR_REG_REG (sfbr, SCR_SHL, 0),
1064 		0,
1065 	SCR_JUMPR ^ IFFALSE (CARRYSET),
1066 		8,
1067 	SCR_REG_REG (dsa1, SCR_OR, 1),
1068 		0,
1069 #elif SYM_CONF_MAX_TASK*4 > 256
1070 	SCR_JUMPR ^ IFFALSE (CARRYSET),
1071 		8,
1072 	SCR_REG_REG (dsa1, SCR_OR, 1),
1073 		0,
1074 #endif
1075 	/*
1076 	 *  Retrieve the DSA of this task.
1077 	 *  JUMP indirectly to the restart point of the CCB.
1078 	 */
1079 	SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
1080 		0,
1081 	SCR_COPY (4),
1082 		RADDR_1 (dsa),
1083 		PADDR_A (_sms_a120),
1084 	SCR_COPY (4),
1085 }/*-------------------------< _SMS_A120 >------------------------*/,{
1086 		0,
1087 		RADDR_1 (dsa),
1088 }/*-------------------------< RESEL_GO >-------------------------*/,{
1089 	SCR_COPY (4),
1090 		RADDR_1 (dsa),
1091 		PADDR_A (_sms_a130),
1092 	/*
1093 	 *  Move 'ccb.phys.head.go' action to
1094 	 *  scratch/scratch1. So scratch1 will
1095 	 *  contain the 'restart' field of the
1096 	 *  'go' structure.
1097 	 */
1098 	SCR_COPY (8),
1099 }/*-------------------------< _SMS_A130 >------------------------*/,{
1100 		0,
1101 		PADDR_B (scratch),
1102 	SCR_COPY (4),
1103 		PADDR_B (scratch1), /* phys.head.go.restart */
1104 		RADDR_1 (temp),
1105 	SCR_RETURN,
1106 		0,
1107 	/* In normal situations we branch to RESEL_DSA */
1108 }/*-------------------------< RESEL_DSA >------------------------*/,{
1109 	/*
1110 	 *  ACK the IDENTIFY or TAG previously received.
1111 	 */
1112 	SCR_CLR (SCR_ACK),
1113 		0,
1114 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1115 	/*
1116 	 *  Copy the CCB header to a fixed location
1117 	 *  in the HCB using self-modifying SCRIPTS.
1118 	 */
1119 	SCR_COPY (4),
1120 		RADDR_1 (dsa),
1121 		PADDR_A (_sms_a140),
1122 	SCR_COPY (sizeof(struct sym_ccbh)),
1123 }/*-------------------------< _SMS_A140 >------------------------*/,{
1124 		0,
1125 		HADDR_1 (ccb_head),
1126 	/*
1127 	 *  Load the savep (saved data pointer) into
1128 	 *  the actual data pointer.
1129 	 */
1130 	SCR_COPY (4),
1131 		HADDR_1 (ccb_head.savep),
1132 		RADDR_1 (temp),
1133 	/*
1134 	 *  Initialize the status register
1135 	 */
1136 	SCR_COPY (4),
1137 		HADDR_1 (ccb_head.status),
1138 		RADDR_1 (scr0),
1139 	/*
1140 	 *  Jump to dispatcher.
1141 	 */
1142 	SCR_JUMP,
1143 		PADDR_A (dispatch),
1144 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1145 	/*
1146 	 *  Copy the LCB header to a fixed place in
1147 	 *  the HCB using self-modifying SCRIPTS.
1148 	 */
1149 	SCR_COPY (4),
1150 		RADDR_1 (dsa),
1151 		PADDR_A (_sms_a145),
1152 	SCR_COPY (sizeof(struct sym_lcbh)),
1153 }/*-------------------------< _SMS_A145 >------------------------*/,{
1154 		0,
1155 		HADDR_1 (lcb_head),
1156 	/*
1157 	 *  Load the DSA with the unique ITL task.
1158 	 */
1159 	SCR_COPY (4),
1160 		HADDR_1 (lcb_head.itl_task_sa),
1161 		RADDR_1 (dsa),
1162 	SCR_JUMP,
1163 		PADDR_A (resel_go),
1164 }/*-------------------------< DATA_IN >--------------------------*/,{
1165 /*
1166  *  Because the size depends on the
1167  *  #define SYM_CONF_MAX_SG parameter,
1168  *  it is filled in at runtime.
1169  *
1170  *  ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1171  *  ||	SCR_CHMOV_TBL ^ SCR_DATA_IN,
1172  *  ||		offsetof (struct sym_dsb, data[ i]),
1173  *  ##==========================================
1174  */
1175 0
1176 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1177 	SCR_CALL,
1178 		PADDR_A (datai_done),
1179 	SCR_JUMP,
1180 		PADDR_B (data_ovrun),
1181 }/*-------------------------< DATA_OUT >-------------------------*/,{
1182 /*
1183  *  Because the size depends on the
1184  *  #define SYM_CONF_MAX_SG parameter,
1185  *  it is filled in at runtime.
1186  *
1187  *  ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1188  *  ||	SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1189  *  ||		offsetof (struct sym_dsb, data[ i]),
1190  *  ##==========================================
1191  */
1192 0
1193 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1194 	SCR_CALL,
1195 		PADDR_A (datao_done),
1196 	SCR_JUMP,
1197 		PADDR_B (data_ovrun),
1198 }/*-------------------------< PM0_DATA >-------------------------*/,{
1199 	/*
1200 	 *  Read our host flags to SFBR, so we will be able
1201 	 *  to check against the data direction we expect.
1202 	 */
1203 	SCR_FROM_REG (HF_REG),
1204 		0,
1205 	/*
1206 	 *  Check against actual DATA PHASE.
1207 	 */
1208 	SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1209 		PADDR_A (pm0_data_out),
1210 	/*
1211 	 *  Actual phase is DATA IN.
1212 	 *  Check against expected direction.
1213 	 */
1214 	SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1215 		PADDR_B (data_ovrun),
1216 	/*
1217 	 *  Keep track we are moving data from the
1218 	 *  PM0 DATA mini-script.
1219 	 */
1220 	SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1221 		0,
1222 	/*
1223 	 *  Move the data to memory.
1224 	 */
1225 	SCR_CHMOV_TBL ^ SCR_DATA_IN,
1226 		offsetof (struct sym_ccb, phys.pm0.sg),
1227 	SCR_JUMP,
1228 		PADDR_A (pm0_data_end),
1229 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1230 	/*
1231 	 *  Actual phase is DATA OUT.
1232 	 *  Check against expected direction.
1233 	 */
1234 	SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1235 		PADDR_B (data_ovrun),
1236 	/*
1237 	 *  Keep track we are moving data from the
1238 	 *  PM0 DATA mini-script.
1239 	 */
1240 	SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1241 		0,
1242 	/*
1243 	 *  Move the data from memory.
1244 	 */
1245 	SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1246 		offsetof (struct sym_ccb, phys.pm0.sg),
1247 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1248 	/*
1249 	 *  Clear the flag that told we were moving
1250 	 *  data from the PM0 DATA mini-script.
1251 	 */
1252 	SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1253 		0,
1254 	/*
1255 	 *  Return to the previous DATA script which
1256 	 *  is guaranteed by design (if no bug) to be
1257 	 *  the main DATA script for this transfer.
1258 	 */
1259 	SCR_COPY (4),
1260 		RADDR_1 (dsa),
1261 		RADDR_1 (scratcha),
1262 	SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)),
1263 		0,
1264 }/*-------------------------< PM_DATA_END >----------------------*/,{
1265 	SCR_COPY (4),
1266 		RADDR_1 (scratcha),
1267 		PADDR_A (_sms_a150),
1268 	SCR_COPY (4),
1269 }/*-------------------------< _SMS_A150 >------------------------*/,{
1270 		0,
1271 		RADDR_1 (temp),
1272 	SCR_RETURN,
1273 		0,
1274 }/*-------------------------< PM1_DATA >-------------------------*/,{
1275 	/*
1276 	 *  Read our host flags to SFBR, so we will be able
1277 	 *  to check against the data direction we expect.
1278 	 */
1279 	SCR_FROM_REG (HF_REG),
1280 		0,
1281 	/*
1282 	 *  Check against actual DATA PHASE.
1283 	 */
1284 	SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1285 		PADDR_A (pm1_data_out),
1286 	/*
1287 	 *  Actual phase is DATA IN.
1288 	 *  Check against expected direction.
1289 	 */
1290 	SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1291 		PADDR_B (data_ovrun),
1292 	/*
1293 	 *  Keep track we are moving data from the
1294 	 *  PM1 DATA mini-script.
1295 	 */
1296 	SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1297 		0,
1298 	/*
1299 	 *  Move the data to memory.
1300 	 */
1301 	SCR_CHMOV_TBL ^ SCR_DATA_IN,
1302 		offsetof (struct sym_ccb, phys.pm1.sg),
1303 	SCR_JUMP,
1304 		PADDR_A (pm1_data_end),
1305 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1306 	/*
1307 	 *  Actual phase is DATA OUT.
1308 	 *  Check against expected direction.
1309 	 */
1310 	SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1311 		PADDR_B (data_ovrun),
1312 	/*
1313 	 *  Keep track we are moving data from the
1314 	 *  PM1 DATA mini-script.
1315 	 */
1316 	SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1317 		0,
1318 	/*
1319 	 *  Move the data from memory.
1320 	 */
1321 	SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1322 		offsetof (struct sym_ccb, phys.pm1.sg),
1323 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1324 	/*
1325 	 *  Clear the flag that told we were moving
1326 	 *  data from the PM1 DATA mini-script.
1327 	 */
1328 	SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1329 		0,
1330 	/*
1331 	 *  Return to the previous DATA script which
1332 	 *  is guaranteed by design (if no bug) to be
1333 	 *  the main DATA script for this transfer.
1334 	 */
1335 	SCR_COPY (4),
1336 		RADDR_1 (dsa),
1337 		RADDR_1 (scratcha),
1338 	SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)),
1339 		0,
1340 	SCR_JUMP,
1341 		PADDR_A (pm_data_end),
1342 }/*--------------------------<>----------------------------------*/
1343 };
1344 
1345 static const struct SYM_FWB_SCR SYM_FWB_SCR = {
1346 /*-------------------------< NO_DATA >--------------------------*/ {
1347 	SCR_JUMP,
1348 		PADDR_B (data_ovrun),
1349 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1350 	/*
1351 	 *  We are jumped here by the C code, if we have
1352 	 *  some target to reset or some disconnected
1353 	 *  job to abort. Since error recovery is a serious
1354 	 *  busyness, we will really reset the SCSI BUS, if
1355 	 *  case of a SCSI interrupt occurring in this path.
1356 	 */
1357 
1358 	/*
1359 	 *  Set initiator mode.
1360 	 */
1361 	SCR_CLR (SCR_TRG),
1362 		0,
1363 	/*
1364 	 *      And try to select this target.
1365 	 */
1366 	SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1367 		PADDR_A (reselect),
1368 	/*
1369 	 *  Wait for the selection to complete or
1370 	 *  the selection to time out.
1371 	 */
1372 	SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1373 		-8,
1374 	/*
1375 	 *  Call the C code.
1376 	 */
1377 	SCR_INT,
1378 		SIR_TARGET_SELECTED,
1379 	/*
1380 	 *  The C code should let us continue here.
1381 	 *  Send the 'kiss of death' message.
1382 	 *  We expect an immediate disconnect once
1383 	 *  the target has eaten the message.
1384 	 */
1385 	SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1386 		0,
1387 	SCR_MOVE_TBL ^ SCR_MSG_OUT,
1388 		offsetof (struct sym_hcb, abrt_tbl),
1389 	SCR_CLR (SCR_ACK|SCR_ATN),
1390 		0,
1391 	SCR_WAIT_DISC,
1392 		0,
1393 	/*
1394 	 *  Tell the C code that we are done.
1395 	 */
1396 	SCR_INT,
1397 		SIR_ABORT_SENT,
1398 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1399 	/*
1400 	 *  Jump at scheduler.
1401 	 */
1402 	SCR_JUMP,
1403 		PADDR_A (start),
1404 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1405 	/*
1406 	 *  If it is an EXTENDED (variable size message)
1407 	 *  Handle it.
1408 	 */
1409 	SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1410 		PADDR_B (msg_extended),
1411 	/*
1412 	 *  Let the C code handle any other
1413 	 *  1 byte message.
1414 	 */
1415 	SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1416 		PADDR_B (msg_received),
1417 	SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1418 		PADDR_B (msg_received),
1419 	/*
1420 	 *  We donnot handle 2 bytes messages from SCRIPTS.
1421 	 *  So, let the C code deal with these ones too.
1422 	 */
1423 	SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1424 		PADDR_B (msg_weird_seen),
1425 	SCR_CLR (SCR_ACK),
1426 		0,
1427 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1428 		HADDR_1 (msgin[1]),
1429 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1430 	SCR_COPY (4),			/* DUMMY READ */
1431 		HADDR_1 (cache),
1432 		RADDR_1 (scratcha),
1433 	SCR_INT,
1434 		SIR_MSG_RECEIVED,
1435 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1436 	SCR_COPY (4),			/* DUMMY READ */
1437 		HADDR_1 (cache),
1438 		RADDR_1 (scratcha),
1439 	SCR_INT,
1440 		SIR_MSG_WEIRD,
1441 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1442 	/*
1443 	 *  Clear ACK and get the next byte
1444 	 *  assumed to be the message length.
1445 	 */
1446 	SCR_CLR (SCR_ACK),
1447 		0,
1448 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1449 		HADDR_1 (msgin[1]),
1450 	/*
1451 	 *  Try to catch some unlikely situations as 0 length
1452 	 *  or too large the length.
1453 	 */
1454 	SCR_JUMP ^ IFTRUE (DATA (0)),
1455 		PADDR_B (msg_weird_seen),
1456 	SCR_TO_REG (scratcha),
1457 		0,
1458 	SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1459 		0,
1460 	SCR_JUMP ^ IFTRUE (CARRYSET),
1461 		PADDR_B (msg_weird_seen),
1462 	/*
1463 	 *  We donnot handle extended messages from SCRIPTS.
1464 	 *  Read the amount of data corresponding to the
1465 	 *  message length and call the C code.
1466 	 */
1467 	SCR_COPY (1),
1468 		RADDR_1 (scratcha),
1469 		PADDR_B (_sms_b10),
1470 	SCR_CLR (SCR_ACK),
1471 		0,
1472 }/*-------------------------< _SMS_B10 >-------------------------*/,{
1473 	SCR_MOVE_ABS (0) ^ SCR_MSG_IN,
1474 		HADDR_1 (msgin[2]),
1475 	SCR_JUMP,
1476 		PADDR_B (msg_received),
1477 }/*-------------------------< MSG_BAD >--------------------------*/,{
1478 	/*
1479 	 *  unimplemented message - reject it.
1480 	 */
1481 	SCR_INT,
1482 		SIR_REJECT_TO_SEND,
1483 	SCR_SET (SCR_ATN),
1484 		0,
1485 	SCR_JUMP,
1486 		PADDR_A (clrack),
1487 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1488 	/*
1489 	 *  weird message received
1490 	 *  ignore all MSG IN phases and reject it.
1491 	 */
1492 	SCR_INT,
1493 		SIR_REJECT_TO_SEND,
1494 	SCR_SET (SCR_ATN),
1495 		0,
1496 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1497 	SCR_CLR (SCR_ACK),
1498 		0,
1499 	SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1500 		PADDR_A (dispatch),
1501 	SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1502 		HADDR_1 (scratch),
1503 	SCR_JUMP,
1504 		PADDR_B (msg_weird1),
1505 }/*-------------------------< WDTR_RESP >------------------------*/,{
1506 	/*
1507 	 *  let the target fetch our answer.
1508 	 */
1509 	SCR_SET (SCR_ATN),
1510 		0,
1511 	SCR_CLR (SCR_ACK),
1512 		0,
1513 	SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1514 		PADDR_B (nego_bad_phase),
1515 }/*-------------------------< SEND_WDTR >------------------------*/,{
1516 	/*
1517 	 *  Send the M_X_WIDE_REQ
1518 	 */
1519 	SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1520 		HADDR_1 (msgout),
1521 	SCR_JUMP,
1522 		PADDR_B (msg_out_done),
1523 }/*-------------------------< SDTR_RESP >------------------------*/,{
1524 	/*
1525 	 *  let the target fetch our answer.
1526 	 */
1527 	SCR_SET (SCR_ATN),
1528 		0,
1529 	SCR_CLR (SCR_ACK),
1530 		0,
1531 	SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1532 		PADDR_B (nego_bad_phase),
1533 }/*-------------------------< SEND_SDTR >------------------------*/,{
1534 	/*
1535 	 *  Send the M_X_SYNC_REQ
1536 	 */
1537 	SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1538 		HADDR_1 (msgout),
1539 	SCR_JUMP,
1540 		PADDR_B (msg_out_done),
1541 }/*-------------------------< PPR_RESP >-------------------------*/,{
1542 	/*
1543 	 *  let the target fetch our answer.
1544 	 */
1545 	SCR_SET (SCR_ATN),
1546 		0,
1547 	SCR_CLR (SCR_ACK),
1548 		0,
1549 	SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1550 		PADDR_B (nego_bad_phase),
1551 }/*-------------------------< SEND_PPR >-------------------------*/,{
1552 	/*
1553 	 *  Send the M_X_PPR_REQ
1554 	 */
1555 	SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1556 		HADDR_1 (msgout),
1557 	SCR_JUMP,
1558 		PADDR_B (msg_out_done),
1559 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1560 	SCR_INT,
1561 		SIR_NEGO_PROTO,
1562 	SCR_JUMP,
1563 		PADDR_A (dispatch),
1564 }/*-------------------------< MSG_OUT >--------------------------*/,{
1565 	/*
1566 	 *  The target requests a message.
1567 	 *  We donnot send messages that may
1568 	 *  require the device to go to bus free.
1569 	 */
1570 	SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1571 		HADDR_1 (msgout),
1572 	/*
1573 	 *  ... wait for the next phase
1574 	 *  if it's a message out, send it again, ...
1575 	 */
1576 	SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1577 		PADDR_B (msg_out),
1578 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1579 	/*
1580 	 *  Let the C code be aware of the
1581 	 *  sent message and clear the message.
1582 	 */
1583 	SCR_INT,
1584 		SIR_MSG_OUT_DONE,
1585 	/*
1586 	 *  ... and process the next phase
1587 	 */
1588 	SCR_JUMP,
1589 		PADDR_A (dispatch),
1590 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1591 	/*
1592 	 *  Zero scratcha that will count the
1593 	 *  extras bytes.
1594 	 */
1595 	SCR_COPY (4),
1596 		PADDR_B (zero),
1597 		RADDR_1 (scratcha),
1598 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1599 	/*
1600 	 *  The target may want to transfer too much data.
1601 	 *
1602 	 *  If phase is DATA OUT write 1 byte and count it.
1603 	 */
1604 	SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1605 		16,
1606 	SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1607 		HADDR_1 (scratch),
1608 	SCR_JUMP,
1609 		PADDR_B (data_ovrun2),
1610 	/*
1611 	 *  If WSR is set, clear this condition, and
1612 	 *  count this byte.
1613 	 */
1614 	SCR_FROM_REG (scntl2),
1615 		0,
1616 	SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1617 		16,
1618 	SCR_REG_REG (scntl2, SCR_OR, WSR),
1619 		0,
1620 	SCR_JUMP,
1621 		PADDR_B (data_ovrun2),
1622 	/*
1623 	 *  Finally check against DATA IN phase.
1624 	 *  Signal data overrun to the C code
1625 	 *  and jump to dispatcher if not so.
1626 	 *  Read 1 byte otherwise and count it.
1627 	 */
1628 	SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1629 		16,
1630 	SCR_INT,
1631 		SIR_DATA_OVERRUN,
1632 	SCR_JUMP,
1633 		PADDR_A (dispatch),
1634 	SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1635 		HADDR_1 (scratch),
1636 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1637 	/*
1638 	 *  Count this byte.
1639 	 *  This will allow to return a negative
1640 	 *  residual to user.
1641 	 */
1642 	SCR_REG_REG (scratcha,  SCR_ADD,  0x01),
1643 		0,
1644 	SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1645 		0,
1646 	SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1647 		0,
1648 	/*
1649 	 *  .. and repeat as required.
1650 	 */
1651 	SCR_JUMP,
1652 		PADDR_B (data_ovrun1),
1653 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1654 	SCR_SET (SCR_ATN),
1655 		0,
1656 	SCR_CLR (SCR_ACK),
1657 		0,
1658 	/*
1659 	 *  send the abort/abortag/reset message
1660 	 *  we expect an immediate disconnect
1661 	 */
1662 	SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1663 		0,
1664 	SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1665 		HADDR_1 (msgout),
1666 	SCR_CLR (SCR_ACK|SCR_ATN),
1667 		0,
1668 	SCR_WAIT_DISC,
1669 		0,
1670 	SCR_INT,
1671 		SIR_RESEL_ABORTED,
1672 	SCR_JUMP,
1673 		PADDR_A (start),
1674 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1675 	/*
1676 	 *  The target stays in MSG OUT phase after having acked
1677 	 *  Identify [+ Tag [+ Extended message ]]. Targets shall
1678 	 *  behave this way on parity error.
1679 	 *  We must send it again all the messages.
1680 	 */
1681 	SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the  */
1682 		0,         /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1683 	SCR_JUMP,
1684 		PADDR_A (send_ident),
1685 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1686 	SCR_CLR (SCR_ATN),
1687 		0,
1688 	SCR_JUMP,
1689 		PADDR_A (select2),
1690 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1691 	SCR_SET (SCR_ATN),
1692 		0,
1693 	SCR_JUMP,
1694 		PADDR_A (select2),
1695 }/*-------------------------< SDATA_IN >-------------------------*/,{
1696 	SCR_CHMOV_TBL ^ SCR_DATA_IN,
1697 		offsetof (struct sym_dsb, sense),
1698 	SCR_CALL,
1699 		PADDR_A (datai_done),
1700 	SCR_JUMP,
1701 		PADDR_B (data_ovrun),
1702 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1703 	/*
1704 	 *  Message is an IDENTIFY, but lun is unknown.
1705 	 *  Signal problem to C code for logging the event.
1706 	 *  Send a M_ABORT to clear all pending tasks.
1707 	 */
1708 	SCR_INT,
1709 		SIR_RESEL_BAD_LUN,
1710 	SCR_JUMP,
1711 		PADDR_B (abort_resel),
1712 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1713 	/*
1714 	 *  We donnot have a task for that I_T_L.
1715 	 *  Signal problem to C code for logging the event.
1716 	 *  Send a M_ABORT message.
1717 	 */
1718 	SCR_INT,
1719 		SIR_RESEL_BAD_I_T_L,
1720 	SCR_JUMP,
1721 		PADDR_B (abort_resel),
1722 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1723 	/*
1724 	 *  We donnot have a task that matches the tag.
1725 	 *  Signal problem to C code for logging the event.
1726 	 *  Send a M_ABORTTAG message.
1727 	 */
1728 	SCR_INT,
1729 		SIR_RESEL_BAD_I_T_L_Q,
1730 	SCR_JUMP,
1731 		PADDR_B (abort_resel),
1732 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1733 	/*
1734 	 *  Anything different from INTERMEDIATE
1735 	 *  CONDITION MET should be a bad SCSI status,
1736 	 *  given that GOOD status has already been tested.
1737 	 *  Call the C code.
1738 	 */
1739 	SCR_COPY (4),
1740 		PADDR_B (startpos),
1741 		RADDR_1 (scratcha),
1742 	SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1743 		SIR_BAD_SCSI_STATUS,
1744 	SCR_RETURN,
1745 		0,
1746 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1747 	/*
1748 	 *  Helper for the C code when WSR bit is set.
1749 	 *  Perform the move of the residual byte.
1750 	 */
1751 	SCR_CHMOV_TBL ^ SCR_DATA_IN,
1752 		offsetof (struct sym_ccb, phys.wresid),
1753 	SCR_JUMP,
1754 		PADDR_A (dispatch),
1755 }/*-------------------------< ZERO >-----------------------------*/,{
1756 	SCR_DATA_ZERO,
1757 }/*-------------------------< SCRATCH >--------------------------*/,{
1758 	SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */
1759 }/*-------------------------< SCRATCH1 >-------------------------*/,{
1760 	SCR_DATA_ZERO,
1761 }/*-------------------------< PREV_DONE >------------------------*/,{
1762 	SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */
1763 }/*-------------------------< DONE_POS >-------------------------*/,{
1764 	SCR_DATA_ZERO,
1765 }/*-------------------------< NEXTJOB >--------------------------*/,{
1766 	SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */
1767 }/*-------------------------< STARTPOS >-------------------------*/,{
1768 	SCR_DATA_ZERO,
1769 }/*-------------------------< TARGTBL >--------------------------*/,{
1770 	SCR_DATA_ZERO,
1771 
1772 }/*-------------------------< SNOOPTEST >------------------------*/,{
1773 	/*
1774 	 *  Read the variable.
1775 	 */
1776 	SCR_COPY (4),
1777 		HADDR_1 (cache),
1778 		RADDR_1 (scratcha),
1779 	/*
1780 	 *  Write the variable.
1781 	 */
1782 	SCR_COPY (4),
1783 		RADDR_1 (temp),
1784 		HADDR_1 (cache),
1785 	/*
1786 	 *  Read back the variable.
1787 	 */
1788 	SCR_COPY (4),
1789 		HADDR_1 (cache),
1790 		RADDR_1 (temp),
1791 }/*-------------------------< SNOOPEND >-------------------------*/,{
1792 	/*
1793 	 *  And stop.
1794 	 */
1795 	SCR_INT,
1796 		99,
1797 }/*--------------------------<>----------------------------------*/
1798 };
1799