1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2000 Doug Rabson
5 * Copyright (c) 2000 Ruslan Ermilov
6 * Copyright (c) 2011 The FreeBSD Foundation
7 * All rights reserved.
8 *
9 * Portions of this software were developed by Konstantin Belousov
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /*
35 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
36 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
37 *
38 * This is generic Intel GTT handling code, morphed from the AGP
39 * bridge code.
40 */
41
42 #include <sys/cdefs.h>
43 #if 0
44 #define KTR_AGP_I810 KTR_DEV
45 #else
46 #define KTR_AGP_I810 0
47 #endif
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/ktr.h>
54 #include <sys/module.h>
55 #include <sys/bus.h>
56 #include <sys/lock.h>
57 #include <sys/mutex.h>
58 #include <sys/proc.h>
59 #include <sys/rwlock.h>
60
61 #include <dev/agp/agppriv.h>
62 #include <dev/agp/agpreg.h>
63 #include <dev/agp/agp_i810.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pci_private.h>
67
68 #include <vm/vm.h>
69 #include <vm/vm_extern.h>
70 #include <vm/vm_kern.h>
71 #include <vm/vm_param.h>
72 #include <vm/vm_object.h>
73 #include <vm/vm_page.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/pmap.h>
76
77 #include <machine/bus.h>
78 #include <machine/resource.h>
79 #include <machine/md_var.h>
80 #include <sys/rman.h>
81
82 MALLOC_DECLARE(M_AGP);
83
84 struct agp_i810_match;
85
86 static int agp_i810_check_active(device_t bridge_dev);
87 static int agp_i830_check_active(device_t bridge_dev);
88 static int agp_i915_check_active(device_t bridge_dev);
89
90 static void agp_82852_set_desc(device_t dev,
91 const struct agp_i810_match *match);
92 static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match);
93
94 static void agp_i810_dump_regs(device_t dev);
95 static void agp_i830_dump_regs(device_t dev);
96 static void agp_i855_dump_regs(device_t dev);
97 static void agp_i915_dump_regs(device_t dev);
98 static void agp_i965_dump_regs(device_t dev);
99
100 static int agp_i810_get_stolen_size(device_t dev);
101 static int agp_i830_get_stolen_size(device_t dev);
102 static int agp_i915_get_stolen_size(device_t dev);
103
104 static int agp_i810_get_gtt_mappable_entries(device_t dev);
105 static int agp_i830_get_gtt_mappable_entries(device_t dev);
106 static int agp_i915_get_gtt_mappable_entries(device_t dev);
107
108 static int agp_i810_get_gtt_total_entries(device_t dev);
109 static int agp_i965_get_gtt_total_entries(device_t dev);
110 static int agp_gen5_get_gtt_total_entries(device_t dev);
111
112 static int agp_i810_install_gatt(device_t dev);
113 static int agp_i830_install_gatt(device_t dev);
114 static int agp_i965_install_gatt(device_t dev);
115 static int agp_g4x_install_gatt(device_t dev);
116
117 static void agp_i810_deinstall_gatt(device_t dev);
118 static void agp_i830_deinstall_gatt(device_t dev);
119
120 static void agp_i810_install_gtt_pte(device_t dev, u_int index,
121 vm_offset_t physical, int flags);
122 static void agp_i830_install_gtt_pte(device_t dev, u_int index,
123 vm_offset_t physical, int flags);
124 static void agp_i915_install_gtt_pte(device_t dev, u_int index,
125 vm_offset_t physical, int flags);
126 static void agp_i965_install_gtt_pte(device_t dev, u_int index,
127 vm_offset_t physical, int flags);
128 static void agp_g4x_install_gtt_pte(device_t dev, u_int index,
129 vm_offset_t physical, int flags);
130
131 static void agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte);
132 static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte);
133 static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte);
134 static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte);
135
136 static u_int32_t agp_i810_read_gtt_pte(device_t dev, u_int index);
137 static u_int32_t agp_i915_read_gtt_pte(device_t dev, u_int index);
138 static u_int32_t agp_i965_read_gtt_pte(device_t dev, u_int index);
139 static u_int32_t agp_g4x_read_gtt_pte(device_t dev, u_int index);
140
141 static vm_paddr_t agp_i810_read_gtt_pte_paddr(device_t dev, u_int index);
142 static vm_paddr_t agp_i915_read_gtt_pte_paddr(device_t dev, u_int index);
143
144 static int agp_i810_set_aperture(device_t dev, u_int32_t aperture);
145 static int agp_i830_set_aperture(device_t dev, u_int32_t aperture);
146 static int agp_i915_set_aperture(device_t dev, u_int32_t aperture);
147
148 static int agp_i810_chipset_flush_setup(device_t dev);
149 static int agp_i915_chipset_flush_setup(device_t dev);
150 static int agp_i965_chipset_flush_setup(device_t dev);
151
152 static void agp_i810_chipset_flush_teardown(device_t dev);
153 static void agp_i915_chipset_flush_teardown(device_t dev);
154 static void agp_i965_chipset_flush_teardown(device_t dev);
155
156 static void agp_i810_chipset_flush(device_t dev);
157 static void agp_i830_chipset_flush(device_t dev);
158 static void agp_i915_chipset_flush(device_t dev);
159
160 enum {
161 CHIP_I810, /* i810/i815 */
162 CHIP_I830, /* 830M/845G */
163 CHIP_I855, /* 852GM/855GM/865G */
164 CHIP_I915, /* 915G/915GM */
165 CHIP_I965, /* G965 */
166 CHIP_G33, /* G33/Q33/Q35 */
167 CHIP_IGD, /* Pineview */
168 CHIP_G4X, /* G45/Q45 */
169 };
170
171 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
172 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
173 * start of the stolen memory, and should only be accessed by the OS through
174 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
175 * is registers, second 512KB is GATT.
176 */
177 static struct resource_spec agp_i810_res_spec[] = {
178 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
179 { -1, 0 }
180 };
181
182 static struct resource_spec agp_i915_res_spec[] = {
183 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
184 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
185 { -1, 0 }
186 };
187
188 static struct resource_spec agp_i965_res_spec[] = {
189 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
190 { SYS_RES_MEMORY, AGP_I965_APBASE, RF_ACTIVE | RF_SHAREABLE },
191 { -1, 0 }
192 };
193
194 struct agp_i810_softc {
195 struct agp_softc agp;
196 u_int32_t initial_aperture; /* aperture size at startup */
197 struct agp_gatt *gatt;
198 u_int32_t dcache_size; /* i810 only */
199 u_int32_t stolen; /* number of i830/845 gtt
200 entries for stolen memory */
201 u_int stolen_size; /* BIOS-reserved graphics memory */
202 u_int gtt_total_entries; /* Total number of gtt ptes */
203 u_int gtt_mappable_entries; /* Number of gtt ptes mappable by CPU */
204 device_t bdev; /* bridge device */
205 void *argb_cursor; /* contigmalloc area for ARGB cursor */
206 struct resource *sc_res[2];
207 const struct agp_i810_match *match;
208 int sc_flush_page_rid;
209 struct resource *sc_flush_page_res;
210 void *sc_flush_page_vaddr;
211 int sc_bios_allocated_flush_page;
212 };
213
214 static device_t intel_agp;
215
216 struct agp_i810_driver {
217 int chiptype;
218 int gen;
219 int busdma_addr_mask_sz;
220 struct resource_spec *res_spec;
221 int (*check_active)(device_t);
222 void (*set_desc)(device_t, const struct agp_i810_match *);
223 void (*dump_regs)(device_t);
224 int (*get_stolen_size)(device_t);
225 int (*get_gtt_total_entries)(device_t);
226 int (*get_gtt_mappable_entries)(device_t);
227 int (*install_gatt)(device_t);
228 void (*deinstall_gatt)(device_t);
229 void (*write_gtt)(device_t, u_int, uint32_t);
230 void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int);
231 u_int32_t (*read_gtt_pte)(device_t, u_int);
232 vm_paddr_t (*read_gtt_pte_paddr)(device_t , u_int);
233 int (*set_aperture)(device_t, u_int32_t);
234 int (*chipset_flush_setup)(device_t);
235 void (*chipset_flush_teardown)(device_t);
236 void (*chipset_flush)(device_t);
237 };
238
239 static struct {
240 struct intel_gtt base;
241 } intel_private;
242
243 static const struct agp_i810_driver agp_i810_i810_driver = {
244 .chiptype = CHIP_I810,
245 .gen = 1,
246 .busdma_addr_mask_sz = 32,
247 .res_spec = agp_i810_res_spec,
248 .check_active = agp_i810_check_active,
249 .set_desc = agp_i810_set_desc,
250 .dump_regs = agp_i810_dump_regs,
251 .get_stolen_size = agp_i810_get_stolen_size,
252 .get_gtt_mappable_entries = agp_i810_get_gtt_mappable_entries,
253 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
254 .install_gatt = agp_i810_install_gatt,
255 .deinstall_gatt = agp_i810_deinstall_gatt,
256 .write_gtt = agp_i810_write_gtt,
257 .install_gtt_pte = agp_i810_install_gtt_pte,
258 .read_gtt_pte = agp_i810_read_gtt_pte,
259 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
260 .set_aperture = agp_i810_set_aperture,
261 .chipset_flush_setup = agp_i810_chipset_flush_setup,
262 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
263 .chipset_flush = agp_i810_chipset_flush,
264 };
265
266 static const struct agp_i810_driver agp_i810_i815_driver = {
267 .chiptype = CHIP_I810,
268 .gen = 2,
269 .busdma_addr_mask_sz = 32,
270 .res_spec = agp_i810_res_spec,
271 .check_active = agp_i810_check_active,
272 .set_desc = agp_i810_set_desc,
273 .dump_regs = agp_i810_dump_regs,
274 .get_stolen_size = agp_i810_get_stolen_size,
275 .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
276 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
277 .install_gatt = agp_i810_install_gatt,
278 .deinstall_gatt = agp_i810_deinstall_gatt,
279 .write_gtt = agp_i810_write_gtt,
280 .install_gtt_pte = agp_i810_install_gtt_pte,
281 .read_gtt_pte = agp_i810_read_gtt_pte,
282 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
283 .set_aperture = agp_i810_set_aperture,
284 .chipset_flush_setup = agp_i810_chipset_flush_setup,
285 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
286 .chipset_flush = agp_i830_chipset_flush,
287 };
288
289 static const struct agp_i810_driver agp_i810_i830_driver = {
290 .chiptype = CHIP_I830,
291 .gen = 2,
292 .busdma_addr_mask_sz = 32,
293 .res_spec = agp_i810_res_spec,
294 .check_active = agp_i830_check_active,
295 .set_desc = agp_i810_set_desc,
296 .dump_regs = agp_i830_dump_regs,
297 .get_stolen_size = agp_i830_get_stolen_size,
298 .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
299 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
300 .install_gatt = agp_i830_install_gatt,
301 .deinstall_gatt = agp_i830_deinstall_gatt,
302 .write_gtt = agp_i810_write_gtt,
303 .install_gtt_pte = agp_i830_install_gtt_pte,
304 .read_gtt_pte = agp_i810_read_gtt_pte,
305 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
306 .set_aperture = agp_i830_set_aperture,
307 .chipset_flush_setup = agp_i810_chipset_flush_setup,
308 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
309 .chipset_flush = agp_i830_chipset_flush,
310 };
311
312 static const struct agp_i810_driver agp_i810_i855_driver = {
313 .chiptype = CHIP_I855,
314 .gen = 2,
315 .busdma_addr_mask_sz = 32,
316 .res_spec = agp_i810_res_spec,
317 .check_active = agp_i830_check_active,
318 .set_desc = agp_82852_set_desc,
319 .dump_regs = agp_i855_dump_regs,
320 .get_stolen_size = agp_i915_get_stolen_size,
321 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
322 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
323 .install_gatt = agp_i830_install_gatt,
324 .deinstall_gatt = agp_i830_deinstall_gatt,
325 .write_gtt = agp_i810_write_gtt,
326 .install_gtt_pte = agp_i830_install_gtt_pte,
327 .read_gtt_pte = agp_i810_read_gtt_pte,
328 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
329 .set_aperture = agp_i830_set_aperture,
330 .chipset_flush_setup = agp_i810_chipset_flush_setup,
331 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
332 .chipset_flush = agp_i830_chipset_flush,
333 };
334
335 static const struct agp_i810_driver agp_i810_i865_driver = {
336 .chiptype = CHIP_I855,
337 .gen = 2,
338 .busdma_addr_mask_sz = 32,
339 .res_spec = agp_i810_res_spec,
340 .check_active = agp_i830_check_active,
341 .set_desc = agp_i810_set_desc,
342 .dump_regs = agp_i855_dump_regs,
343 .get_stolen_size = agp_i915_get_stolen_size,
344 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
345 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
346 .install_gatt = agp_i830_install_gatt,
347 .deinstall_gatt = agp_i830_deinstall_gatt,
348 .write_gtt = agp_i810_write_gtt,
349 .install_gtt_pte = agp_i830_install_gtt_pte,
350 .read_gtt_pte = agp_i810_read_gtt_pte,
351 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
352 .set_aperture = agp_i915_set_aperture,
353 .chipset_flush_setup = agp_i810_chipset_flush_setup,
354 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
355 .chipset_flush = agp_i830_chipset_flush,
356 };
357
358 static const struct agp_i810_driver agp_i810_i915_driver = {
359 .chiptype = CHIP_I915,
360 .gen = 3,
361 .busdma_addr_mask_sz = 32,
362 .res_spec = agp_i915_res_spec,
363 .check_active = agp_i915_check_active,
364 .set_desc = agp_i810_set_desc,
365 .dump_regs = agp_i915_dump_regs,
366 .get_stolen_size = agp_i915_get_stolen_size,
367 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
368 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
369 .install_gatt = agp_i830_install_gatt,
370 .deinstall_gatt = agp_i830_deinstall_gatt,
371 .write_gtt = agp_i915_write_gtt,
372 .install_gtt_pte = agp_i915_install_gtt_pte,
373 .read_gtt_pte = agp_i915_read_gtt_pte,
374 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
375 .set_aperture = agp_i915_set_aperture,
376 .chipset_flush_setup = agp_i915_chipset_flush_setup,
377 .chipset_flush_teardown = agp_i915_chipset_flush_teardown,
378 .chipset_flush = agp_i915_chipset_flush,
379 };
380
381 static const struct agp_i810_driver agp_i810_g33_driver = {
382 .chiptype = CHIP_G33,
383 .gen = 3,
384 .busdma_addr_mask_sz = 36,
385 .res_spec = agp_i915_res_spec,
386 .check_active = agp_i915_check_active,
387 .set_desc = agp_i810_set_desc,
388 .dump_regs = agp_i965_dump_regs,
389 .get_stolen_size = agp_i915_get_stolen_size,
390 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
391 .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
392 .install_gatt = agp_i830_install_gatt,
393 .deinstall_gatt = agp_i830_deinstall_gatt,
394 .write_gtt = agp_i915_write_gtt,
395 .install_gtt_pte = agp_i915_install_gtt_pte,
396 .read_gtt_pte = agp_i915_read_gtt_pte,
397 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
398 .set_aperture = agp_i915_set_aperture,
399 .chipset_flush_setup = agp_i965_chipset_flush_setup,
400 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
401 .chipset_flush = agp_i915_chipset_flush,
402 };
403
404 static const struct agp_i810_driver agp_i810_igd_driver = {
405 .chiptype = CHIP_IGD,
406 .gen = 3,
407 .busdma_addr_mask_sz = 36,
408 .res_spec = agp_i915_res_spec,
409 .check_active = agp_i915_check_active,
410 .set_desc = agp_i810_set_desc,
411 .dump_regs = agp_i915_dump_regs,
412 .get_stolen_size = agp_i915_get_stolen_size,
413 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
414 .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
415 .install_gatt = agp_i830_install_gatt,
416 .deinstall_gatt = agp_i830_deinstall_gatt,
417 .write_gtt = agp_i915_write_gtt,
418 .install_gtt_pte = agp_i915_install_gtt_pte,
419 .read_gtt_pte = agp_i915_read_gtt_pte,
420 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
421 .set_aperture = agp_i915_set_aperture,
422 .chipset_flush_setup = agp_i965_chipset_flush_setup,
423 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
424 .chipset_flush = agp_i915_chipset_flush,
425 };
426
427 static const struct agp_i810_driver agp_i810_g965_driver = {
428 .chiptype = CHIP_I965,
429 .gen = 4,
430 .busdma_addr_mask_sz = 36,
431 .res_spec = agp_i965_res_spec,
432 .check_active = agp_i915_check_active,
433 .set_desc = agp_i810_set_desc,
434 .dump_regs = agp_i965_dump_regs,
435 .get_stolen_size = agp_i915_get_stolen_size,
436 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
437 .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
438 .install_gatt = agp_i965_install_gatt,
439 .deinstall_gatt = agp_i830_deinstall_gatt,
440 .write_gtt = agp_i965_write_gtt,
441 .install_gtt_pte = agp_i965_install_gtt_pte,
442 .read_gtt_pte = agp_i965_read_gtt_pte,
443 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
444 .set_aperture = agp_i915_set_aperture,
445 .chipset_flush_setup = agp_i965_chipset_flush_setup,
446 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
447 .chipset_flush = agp_i915_chipset_flush,
448 };
449
450 static const struct agp_i810_driver agp_i810_g4x_driver = {
451 .chiptype = CHIP_G4X,
452 .gen = 5,
453 .busdma_addr_mask_sz = 36,
454 .res_spec = agp_i965_res_spec,
455 .check_active = agp_i915_check_active,
456 .set_desc = agp_i810_set_desc,
457 .dump_regs = agp_i965_dump_regs,
458 .get_stolen_size = agp_i915_get_stolen_size,
459 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
460 .get_gtt_total_entries = agp_gen5_get_gtt_total_entries,
461 .install_gatt = agp_g4x_install_gatt,
462 .deinstall_gatt = agp_i830_deinstall_gatt,
463 .write_gtt = agp_g4x_write_gtt,
464 .install_gtt_pte = agp_g4x_install_gtt_pte,
465 .read_gtt_pte = agp_g4x_read_gtt_pte,
466 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
467 .set_aperture = agp_i915_set_aperture,
468 .chipset_flush_setup = agp_i965_chipset_flush_setup,
469 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
470 .chipset_flush = agp_i915_chipset_flush,
471 };
472
473 /* For adding new devices, devid is the id of the graphics controller
474 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
475 * second head should never be added. The bridge_offset is the offset to
476 * subtract from devid to get the id of the hostb that the device is on.
477 */
478 static const struct agp_i810_match {
479 int devid;
480 char *name;
481 const struct agp_i810_driver *driver;
482 } agp_i810_matches[] = {
483 {
484 .devid = 0x71218086,
485 .name = "Intel 82810 (i810 GMCH) SVGA controller",
486 .driver = &agp_i810_i810_driver
487 },
488 {
489 .devid = 0x71238086,
490 .name = "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller",
491 .driver = &agp_i810_i810_driver
492 },
493 {
494 .devid = 0x71258086,
495 .name = "Intel 82810E (i810E GMCH) SVGA controller",
496 .driver = &agp_i810_i810_driver
497 },
498 {
499 .devid = 0x11328086,
500 .name = "Intel 82815 (i815 GMCH) SVGA controller",
501 .driver = &agp_i810_i815_driver
502 },
503 {
504 .devid = 0x35778086,
505 .name = "Intel 82830M (830M GMCH) SVGA controller",
506 .driver = &agp_i810_i830_driver
507 },
508 {
509 .devid = 0x25628086,
510 .name = "Intel 82845M (845M GMCH) SVGA controller",
511 .driver = &agp_i810_i830_driver
512 },
513 {
514 .devid = 0x35828086,
515 .name = "Intel 82852/855GM SVGA controller",
516 .driver = &agp_i810_i855_driver
517 },
518 {
519 .devid = 0x25728086,
520 .name = "Intel 82865G (865G GMCH) SVGA controller",
521 .driver = &agp_i810_i865_driver
522 },
523 {
524 .devid = 0x25828086,
525 .name = "Intel 82915G (915G GMCH) SVGA controller",
526 .driver = &agp_i810_i915_driver
527 },
528 {
529 .devid = 0x258A8086,
530 .name = "Intel E7221 SVGA controller",
531 .driver = &agp_i810_i915_driver
532 },
533 {
534 .devid = 0x25928086,
535 .name = "Intel 82915GM (915GM GMCH) SVGA controller",
536 .driver = &agp_i810_i915_driver
537 },
538 {
539 .devid = 0x27728086,
540 .name = "Intel 82945G (945G GMCH) SVGA controller",
541 .driver = &agp_i810_i915_driver
542 },
543 {
544 .devid = 0x27A28086,
545 .name = "Intel 82945GM (945GM GMCH) SVGA controller",
546 .driver = &agp_i810_i915_driver
547 },
548 {
549 .devid = 0x27AE8086,
550 .name = "Intel 945GME SVGA controller",
551 .driver = &agp_i810_i915_driver
552 },
553 {
554 .devid = 0x29728086,
555 .name = "Intel 946GZ SVGA controller",
556 .driver = &agp_i810_g965_driver
557 },
558 {
559 .devid = 0x29828086,
560 .name = "Intel G965 SVGA controller",
561 .driver = &agp_i810_g965_driver
562 },
563 {
564 .devid = 0x29928086,
565 .name = "Intel Q965 SVGA controller",
566 .driver = &agp_i810_g965_driver
567 },
568 {
569 .devid = 0x29A28086,
570 .name = "Intel G965 SVGA controller",
571 .driver = &agp_i810_g965_driver
572 },
573 {
574 .devid = 0x29B28086,
575 .name = "Intel Q35 SVGA controller",
576 .driver = &agp_i810_g33_driver
577 },
578 {
579 .devid = 0x29C28086,
580 .name = "Intel G33 SVGA controller",
581 .driver = &agp_i810_g33_driver
582 },
583 {
584 .devid = 0x29D28086,
585 .name = "Intel Q33 SVGA controller",
586 .driver = &agp_i810_g33_driver
587 },
588 {
589 .devid = 0xA0018086,
590 .name = "Intel Pineview SVGA controller",
591 .driver = &agp_i810_igd_driver
592 },
593 {
594 .devid = 0xA0118086,
595 .name = "Intel Pineview (M) SVGA controller",
596 .driver = &agp_i810_igd_driver
597 },
598 {
599 .devid = 0x2A028086,
600 .name = "Intel GM965 SVGA controller",
601 .driver = &agp_i810_g965_driver
602 },
603 {
604 .devid = 0x2A128086,
605 .name = "Intel GME965 SVGA controller",
606 .driver = &agp_i810_g965_driver
607 },
608 {
609 .devid = 0x2A428086,
610 .name = "Intel GM45 SVGA controller",
611 .driver = &agp_i810_g4x_driver
612 },
613 {
614 .devid = 0x2E028086,
615 .name = "Intel Eaglelake SVGA controller",
616 .driver = &agp_i810_g4x_driver
617 },
618 {
619 .devid = 0x2E128086,
620 .name = "Intel Q45 SVGA controller",
621 .driver = &agp_i810_g4x_driver
622 },
623 {
624 .devid = 0x2E228086,
625 .name = "Intel G45 SVGA controller",
626 .driver = &agp_i810_g4x_driver
627 },
628 {
629 .devid = 0x2E328086,
630 .name = "Intel G41 SVGA controller",
631 .driver = &agp_i810_g4x_driver
632 },
633 {
634 .devid = 0x00428086,
635 .name = "Intel Ironlake (D) SVGA controller",
636 .driver = &agp_i810_g4x_driver
637 },
638 {
639 .devid = 0x00468086,
640 .name = "Intel Ironlake (M) SVGA controller",
641 .driver = &agp_i810_g4x_driver
642 },
643 {
644 .devid = 0,
645 }
646 };
647
648 static const struct agp_i810_match*
agp_i810_match(device_t dev)649 agp_i810_match(device_t dev)
650 {
651 int i, devid;
652
653 if (pci_get_class(dev) != PCIC_DISPLAY
654 || (pci_get_subclass(dev) != PCIS_DISPLAY_VGA &&
655 pci_get_subclass(dev) != PCIS_DISPLAY_OTHER))
656 return (NULL);
657
658 devid = pci_get_devid(dev);
659 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
660 if (agp_i810_matches[i].devid == devid)
661 break;
662 }
663 if (agp_i810_matches[i].devid == 0)
664 return (NULL);
665 else
666 return (&agp_i810_matches[i]);
667 }
668
669 /*
670 * Find bridge device.
671 */
672 static device_t
agp_i810_find_bridge(device_t dev)673 agp_i810_find_bridge(device_t dev)
674 {
675
676 return (pci_find_dbsf(0, 0, 0, 0));
677 }
678
679 static void
agp_i810_identify(driver_t * driver,device_t parent)680 agp_i810_identify(driver_t *driver, device_t parent)
681 {
682
683 if (device_find_child(parent, "agp", -1) == NULL &&
684 agp_i810_match(parent))
685 device_add_child(parent, "agp", -1);
686 }
687
688 static int
agp_i810_check_active(device_t bridge_dev)689 agp_i810_check_active(device_t bridge_dev)
690 {
691 u_int8_t smram;
692
693 smram = pci_read_config(bridge_dev, AGP_I810_SMRAM, 1);
694 if ((smram & AGP_I810_SMRAM_GMS) == AGP_I810_SMRAM_GMS_DISABLED)
695 return (ENXIO);
696 return (0);
697 }
698
699 static int
agp_i830_check_active(device_t bridge_dev)700 agp_i830_check_active(device_t bridge_dev)
701 {
702 int gcc1;
703
704 gcc1 = pci_read_config(bridge_dev, AGP_I830_GCC1, 1);
705 if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED)
706 return (ENXIO);
707 return (0);
708 }
709
710 static int
agp_i915_check_active(device_t bridge_dev)711 agp_i915_check_active(device_t bridge_dev)
712 {
713 int deven;
714
715 deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
716 if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED)
717 return (ENXIO);
718 return (0);
719 }
720
721 static void
agp_82852_set_desc(device_t dev,const struct agp_i810_match * match)722 agp_82852_set_desc(device_t dev, const struct agp_i810_match *match)
723 {
724
725 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
726 case AGP_I855_GME:
727 device_set_desc(dev,
728 "Intel 82855GME (855GME GMCH) SVGA controller");
729 break;
730 case AGP_I855_GM:
731 device_set_desc(dev,
732 "Intel 82855GM (855GM GMCH) SVGA controller");
733 break;
734 case AGP_I852_GME:
735 device_set_desc(dev,
736 "Intel 82852GME (852GME GMCH) SVGA controller");
737 break;
738 case AGP_I852_GM:
739 device_set_desc(dev,
740 "Intel 82852GM (852GM GMCH) SVGA controller");
741 break;
742 default:
743 device_set_desc(dev,
744 "Intel 8285xM (85xGM GMCH) SVGA controller");
745 break;
746 }
747 }
748
749 static void
agp_i810_set_desc(device_t dev,const struct agp_i810_match * match)750 agp_i810_set_desc(device_t dev, const struct agp_i810_match *match)
751 {
752
753 device_set_desc(dev, match->name);
754 }
755
756 static int
agp_i810_probe(device_t dev)757 agp_i810_probe(device_t dev)
758 {
759 device_t bdev;
760 const struct agp_i810_match *match;
761 int err;
762
763 if (resource_disabled("agp", device_get_unit(dev)))
764 return (ENXIO);
765 match = agp_i810_match(dev);
766 if (match == NULL)
767 return (ENXIO);
768
769 bdev = agp_i810_find_bridge(dev);
770 if (bdev == NULL) {
771 if (bootverbose)
772 printf("I810: can't find bridge device\n");
773 return (ENXIO);
774 }
775
776 /*
777 * checking whether internal graphics device has been activated.
778 */
779 err = match->driver->check_active(bdev);
780 if (err != 0) {
781 if (bootverbose)
782 printf("i810: disabled, not probing\n");
783 return (err);
784 }
785
786 match->driver->set_desc(dev, match);
787 return (BUS_PROBE_DEFAULT);
788 }
789
790 static void
agp_i810_dump_regs(device_t dev)791 agp_i810_dump_regs(device_t dev)
792 {
793 struct agp_i810_softc *sc = device_get_softc(dev);
794
795 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
796 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
797 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
798 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
799 }
800
801 static void
agp_i830_dump_regs(device_t dev)802 agp_i830_dump_regs(device_t dev)
803 {
804 struct agp_i810_softc *sc = device_get_softc(dev);
805
806 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
807 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
808 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
809 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
810 }
811
812 static void
agp_i855_dump_regs(device_t dev)813 agp_i855_dump_regs(device_t dev)
814 {
815 struct agp_i810_softc *sc = device_get_softc(dev);
816
817 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
818 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
819 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
820 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
821 }
822
823 static void
agp_i915_dump_regs(device_t dev)824 agp_i915_dump_regs(device_t dev)
825 {
826 struct agp_i810_softc *sc = device_get_softc(dev);
827
828 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
829 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
830 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
831 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
832 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
833 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
834 }
835
836 static void
agp_i965_dump_regs(device_t dev)837 agp_i965_dump_regs(device_t dev)
838 {
839 struct agp_i810_softc *sc = device_get_softc(dev);
840
841 device_printf(dev, "AGP_I965_PGTBL_CTL2: %08x\n",
842 bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2));
843 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
844 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
845 device_printf(dev, "AGP_I965_MSAC: 0x%02x\n",
846 pci_read_config(sc->bdev, AGP_I965_MSAC, 1));
847 }
848
849 static int
agp_i810_get_stolen_size(device_t dev)850 agp_i810_get_stolen_size(device_t dev)
851 {
852 struct agp_i810_softc *sc;
853
854 sc = device_get_softc(dev);
855 sc->stolen = 0;
856 sc->stolen_size = 0;
857 return (0);
858 }
859
860 static int
agp_i830_get_stolen_size(device_t dev)861 agp_i830_get_stolen_size(device_t dev)
862 {
863 struct agp_i810_softc *sc;
864 unsigned int gcc1;
865
866 sc = device_get_softc(dev);
867
868 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
869 switch (gcc1 & AGP_I830_GCC1_GMS) {
870 case AGP_I830_GCC1_GMS_STOLEN_512:
871 sc->stolen = (512 - 132) * 1024 / 4096;
872 sc->stolen_size = 512 * 1024;
873 break;
874 case AGP_I830_GCC1_GMS_STOLEN_1024:
875 sc->stolen = (1024 - 132) * 1024 / 4096;
876 sc->stolen_size = 1024 * 1024;
877 break;
878 case AGP_I830_GCC1_GMS_STOLEN_8192:
879 sc->stolen = (8192 - 132) * 1024 / 4096;
880 sc->stolen_size = 8192 * 1024;
881 break;
882 default:
883 sc->stolen = 0;
884 device_printf(dev,
885 "unknown memory configuration, disabling (GCC1 %x)\n",
886 gcc1);
887 return (EINVAL);
888 }
889 return (0);
890 }
891
892 static int
agp_i915_get_stolen_size(device_t dev)893 agp_i915_get_stolen_size(device_t dev)
894 {
895 struct agp_i810_softc *sc;
896 unsigned int gcc1, stolen, gtt_size;
897
898 sc = device_get_softc(dev);
899
900 /*
901 * Stolen memory is set up at the beginning of the aperture by
902 * the BIOS, consisting of the GATT followed by 4kb for the
903 * BIOS display.
904 */
905 switch (sc->match->driver->chiptype) {
906 case CHIP_I855:
907 gtt_size = 128;
908 break;
909 case CHIP_I915:
910 gtt_size = 256;
911 break;
912 case CHIP_I965:
913 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
914 AGP_I810_PGTBL_SIZE_MASK) {
915 case AGP_I810_PGTBL_SIZE_128KB:
916 gtt_size = 128;
917 break;
918 case AGP_I810_PGTBL_SIZE_256KB:
919 gtt_size = 256;
920 break;
921 case AGP_I810_PGTBL_SIZE_512KB:
922 gtt_size = 512;
923 break;
924 case AGP_I965_PGTBL_SIZE_1MB:
925 gtt_size = 1024;
926 break;
927 case AGP_I965_PGTBL_SIZE_2MB:
928 gtt_size = 2048;
929 break;
930 case AGP_I965_PGTBL_SIZE_1_5MB:
931 gtt_size = 1024 + 512;
932 break;
933 default:
934 device_printf(dev, "Bad PGTBL size\n");
935 return (EINVAL);
936 }
937 break;
938 case CHIP_G33:
939 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
940 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
941 case AGP_G33_MGGC_GGMS_SIZE_1M:
942 gtt_size = 1024;
943 break;
944 case AGP_G33_MGGC_GGMS_SIZE_2M:
945 gtt_size = 2048;
946 break;
947 default:
948 device_printf(dev, "Bad PGTBL size\n");
949 return (EINVAL);
950 }
951 break;
952 case CHIP_IGD:
953 case CHIP_G4X:
954 gtt_size = 0;
955 break;
956 default:
957 device_printf(dev, "Bad chiptype\n");
958 return (EINVAL);
959 }
960
961 /* GCC1 is called MGGC on i915+ */
962 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
963 switch (gcc1 & AGP_I855_GCC1_GMS) {
964 case AGP_I855_GCC1_GMS_STOLEN_1M:
965 stolen = 1024;
966 break;
967 case AGP_I855_GCC1_GMS_STOLEN_4M:
968 stolen = 4 * 1024;
969 break;
970 case AGP_I855_GCC1_GMS_STOLEN_8M:
971 stolen = 8 * 1024;
972 break;
973 case AGP_I855_GCC1_GMS_STOLEN_16M:
974 stolen = 16 * 1024;
975 break;
976 case AGP_I855_GCC1_GMS_STOLEN_32M:
977 stolen = 32 * 1024;
978 break;
979 case AGP_I915_GCC1_GMS_STOLEN_48M:
980 stolen = sc->match->driver->gen > 2 ? 48 * 1024 : 0;
981 break;
982 case AGP_I915_GCC1_GMS_STOLEN_64M:
983 stolen = sc->match->driver->gen > 2 ? 64 * 1024 : 0;
984 break;
985 case AGP_G33_GCC1_GMS_STOLEN_128M:
986 stolen = sc->match->driver->gen > 2 ? 128 * 1024 : 0;
987 break;
988 case AGP_G33_GCC1_GMS_STOLEN_256M:
989 stolen = sc->match->driver->gen > 2 ? 256 * 1024 : 0;
990 break;
991 case AGP_G4X_GCC1_GMS_STOLEN_96M:
992 if (sc->match->driver->chiptype == CHIP_I965 ||
993 sc->match->driver->chiptype == CHIP_G4X)
994 stolen = 96 * 1024;
995 else
996 stolen = 0;
997 break;
998 case AGP_G4X_GCC1_GMS_STOLEN_160M:
999 if (sc->match->driver->chiptype == CHIP_I965 ||
1000 sc->match->driver->chiptype == CHIP_G4X)
1001 stolen = 160 * 1024;
1002 else
1003 stolen = 0;
1004 break;
1005 case AGP_G4X_GCC1_GMS_STOLEN_224M:
1006 if (sc->match->driver->chiptype == CHIP_I965 ||
1007 sc->match->driver->chiptype == CHIP_G4X)
1008 stolen = 224 * 1024;
1009 else
1010 stolen = 0;
1011 break;
1012 case AGP_G4X_GCC1_GMS_STOLEN_352M:
1013 if (sc->match->driver->chiptype == CHIP_I965 ||
1014 sc->match->driver->chiptype == CHIP_G4X)
1015 stolen = 352 * 1024;
1016 else
1017 stolen = 0;
1018 break;
1019 default:
1020 device_printf(dev,
1021 "unknown memory configuration, disabling (GCC1 %x)\n",
1022 gcc1);
1023 return (EINVAL);
1024 }
1025
1026 gtt_size += 4;
1027 sc->stolen_size = stolen * 1024;
1028 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
1029
1030 return (0);
1031 }
1032
1033 static int
agp_i810_get_gtt_mappable_entries(device_t dev)1034 agp_i810_get_gtt_mappable_entries(device_t dev)
1035 {
1036 struct agp_i810_softc *sc;
1037 uint32_t ap;
1038 uint16_t miscc;
1039
1040 sc = device_get_softc(dev);
1041 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
1042 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
1043 ap = 32;
1044 else
1045 ap = 64;
1046 sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT;
1047 return (0);
1048 }
1049
1050 static int
agp_i830_get_gtt_mappable_entries(device_t dev)1051 agp_i830_get_gtt_mappable_entries(device_t dev)
1052 {
1053 struct agp_i810_softc *sc;
1054 uint32_t ap;
1055 uint16_t gmch_ctl;
1056
1057 sc = device_get_softc(dev);
1058 gmch_ctl = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1059 if ((gmch_ctl & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
1060 ap = 64;
1061 else
1062 ap = 128;
1063 sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT;
1064 return (0);
1065 }
1066
1067 static int
agp_i915_get_gtt_mappable_entries(device_t dev)1068 agp_i915_get_gtt_mappable_entries(device_t dev)
1069 {
1070 struct agp_i810_softc *sc;
1071 uint32_t ap;
1072
1073 sc = device_get_softc(dev);
1074 ap = AGP_GET_APERTURE(dev);
1075 sc->gtt_mappable_entries = ap >> AGP_PAGE_SHIFT;
1076 return (0);
1077 }
1078
1079 static int
agp_i810_get_gtt_total_entries(device_t dev)1080 agp_i810_get_gtt_total_entries(device_t dev)
1081 {
1082 struct agp_i810_softc *sc;
1083
1084 sc = device_get_softc(dev);
1085 sc->gtt_total_entries = sc->gtt_mappable_entries;
1086 return (0);
1087 }
1088
1089 static int
agp_i965_get_gtt_total_entries(device_t dev)1090 agp_i965_get_gtt_total_entries(device_t dev)
1091 {
1092 struct agp_i810_softc *sc;
1093 uint32_t pgetbl_ctl;
1094 int error;
1095
1096 sc = device_get_softc(dev);
1097 error = 0;
1098 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1099 switch (pgetbl_ctl & AGP_I810_PGTBL_SIZE_MASK) {
1100 case AGP_I810_PGTBL_SIZE_128KB:
1101 sc->gtt_total_entries = 128 * 1024 / 4;
1102 break;
1103 case AGP_I810_PGTBL_SIZE_256KB:
1104 sc->gtt_total_entries = 256 * 1024 / 4;
1105 break;
1106 case AGP_I810_PGTBL_SIZE_512KB:
1107 sc->gtt_total_entries = 512 * 1024 / 4;
1108 break;
1109 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
1110 case AGP_I810_PGTBL_SIZE_1MB:
1111 sc->gtt_total_entries = 1024 * 1024 / 4;
1112 break;
1113 case AGP_I810_PGTBL_SIZE_2MB:
1114 sc->gtt_total_entries = 2 * 1024 * 1024 / 4;
1115 break;
1116 case AGP_I810_PGTBL_SIZE_1_5MB:
1117 sc->gtt_total_entries = (1024 + 512) * 1024 / 4;
1118 break;
1119 default:
1120 device_printf(dev, "Unknown page table size\n");
1121 error = ENXIO;
1122 }
1123 return (error);
1124 }
1125
1126 static void
agp_gen5_adjust_pgtbl_size(device_t dev,uint32_t sz)1127 agp_gen5_adjust_pgtbl_size(device_t dev, uint32_t sz)
1128 {
1129 struct agp_i810_softc *sc;
1130 uint32_t pgetbl_ctl, pgetbl_ctl2;
1131
1132 sc = device_get_softc(dev);
1133
1134 /* Disable per-process page table. */
1135 pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2);
1136 pgetbl_ctl2 &= ~AGP_I810_PGTBL_ENABLED;
1137 bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2);
1138
1139 /* Write the new ggtt size. */
1140 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1141 pgetbl_ctl &= ~AGP_I810_PGTBL_SIZE_MASK;
1142 pgetbl_ctl |= sz;
1143 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl);
1144 }
1145
1146 static int
agp_gen5_get_gtt_total_entries(device_t dev)1147 agp_gen5_get_gtt_total_entries(device_t dev)
1148 {
1149 struct agp_i810_softc *sc;
1150 uint16_t gcc1;
1151
1152 sc = device_get_softc(dev);
1153
1154 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1155 switch (gcc1 & AGP_G4x_GCC1_SIZE_MASK) {
1156 case AGP_G4x_GCC1_SIZE_1M:
1157 case AGP_G4x_GCC1_SIZE_VT_1M:
1158 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1MB);
1159 break;
1160 case AGP_G4x_GCC1_SIZE_VT_1_5M:
1161 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1_5MB);
1162 break;
1163 case AGP_G4x_GCC1_SIZE_2M:
1164 case AGP_G4x_GCC1_SIZE_VT_2M:
1165 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_2MB);
1166 break;
1167 default:
1168 device_printf(dev, "Unknown page table size\n");
1169 return (ENXIO);
1170 }
1171
1172 return (agp_i965_get_gtt_total_entries(dev));
1173 }
1174
1175 static int
agp_i810_install_gatt(device_t dev)1176 agp_i810_install_gatt(device_t dev)
1177 {
1178 struct agp_i810_softc *sc;
1179
1180 sc = device_get_softc(dev);
1181
1182 /* Some i810s have on-chip memory called dcache. */
1183 if ((bus_read_1(sc->sc_res[0], AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
1184 != 0)
1185 sc->dcache_size = 4 * 1024 * 1024;
1186 else
1187 sc->dcache_size = 0;
1188
1189 /* According to the specs the gatt on the i810 must be 64k. */
1190 sc->gatt->ag_virtual = kmem_alloc_contig(64 * 1024, M_NOWAIT |
1191 M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_WRITE_COMBINING);
1192 if (sc->gatt->ag_virtual == NULL) {
1193 if (bootverbose)
1194 device_printf(dev, "contiguous allocation failed\n");
1195 return (ENOMEM);
1196 }
1197
1198 sc->gatt->ag_physical = vtophys((vm_offset_t)sc->gatt->ag_virtual);
1199 /* Install the GATT. */
1200 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1201 sc->gatt->ag_physical | 1);
1202 return (0);
1203 }
1204
1205 static void
agp_i830_install_gatt_init(struct agp_i810_softc * sc)1206 agp_i830_install_gatt_init(struct agp_i810_softc *sc)
1207 {
1208 uint32_t pgtblctl;
1209
1210 /*
1211 * The i830 automatically initializes the 128k gatt on boot.
1212 * GATT address is already in there, make sure it's enabled.
1213 */
1214 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1215 pgtblctl |= 1;
1216 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1217
1218 sc->gatt->ag_physical = pgtblctl & ~1;
1219 }
1220
1221 static int
agp_i830_install_gatt(device_t dev)1222 agp_i830_install_gatt(device_t dev)
1223 {
1224 struct agp_i810_softc *sc;
1225
1226 sc = device_get_softc(dev);
1227 agp_i830_install_gatt_init(sc);
1228 return (0);
1229 }
1230
1231 static int
agp_gen4_install_gatt(device_t dev,const vm_size_t gtt_offset)1232 agp_gen4_install_gatt(device_t dev, const vm_size_t gtt_offset)
1233 {
1234 struct agp_i810_softc *sc;
1235
1236 sc = device_get_softc(dev);
1237 pmap_change_attr((vm_offset_t)rman_get_virtual(sc->sc_res[0]) +
1238 gtt_offset, rman_get_size(sc->sc_res[0]) - gtt_offset,
1239 VM_MEMATTR_WRITE_COMBINING);
1240 agp_i830_install_gatt_init(sc);
1241 return (0);
1242 }
1243
1244 static int
agp_i965_install_gatt(device_t dev)1245 agp_i965_install_gatt(device_t dev)
1246 {
1247
1248 return (agp_gen4_install_gatt(dev, 512 * 1024));
1249 }
1250
1251 static int
agp_g4x_install_gatt(device_t dev)1252 agp_g4x_install_gatt(device_t dev)
1253 {
1254
1255 return (agp_gen4_install_gatt(dev, 2 * 1024 * 1024));
1256 }
1257
1258 static int
agp_i810_attach(device_t dev)1259 agp_i810_attach(device_t dev)
1260 {
1261 struct agp_i810_softc *sc;
1262 int error;
1263
1264 sc = device_get_softc(dev);
1265 sc->bdev = agp_i810_find_bridge(dev);
1266 if (sc->bdev == NULL)
1267 return (ENOENT);
1268
1269 sc->match = agp_i810_match(dev);
1270
1271 agp_set_aperture_resource(dev, sc->match->driver->gen <= 2 ?
1272 AGP_APBASE : AGP_I915_GMADR);
1273 error = agp_generic_attach(dev);
1274 if (error)
1275 return (error);
1276
1277 if (ptoa((vm_paddr_t)Maxmem) >
1278 (1ULL << sc->match->driver->busdma_addr_mask_sz) - 1) {
1279 device_printf(dev, "agp_i810 does not support physical "
1280 "memory above %ju.\n", (uintmax_t)(1ULL <<
1281 sc->match->driver->busdma_addr_mask_sz) - 1);
1282 return (ENOENT);
1283 }
1284
1285 if (bus_alloc_resources(dev, sc->match->driver->res_spec, sc->sc_res)) {
1286 agp_generic_detach(dev);
1287 return (ENODEV);
1288 }
1289
1290 sc->initial_aperture = AGP_GET_APERTURE(dev);
1291 sc->gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_WAITOK);
1292 sc->gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
1293
1294 if ((error = sc->match->driver->get_stolen_size(dev)) != 0 ||
1295 (error = sc->match->driver->install_gatt(dev)) != 0 ||
1296 (error = sc->match->driver->get_gtt_mappable_entries(dev)) != 0 ||
1297 (error = sc->match->driver->get_gtt_total_entries(dev)) != 0 ||
1298 (error = sc->match->driver->chipset_flush_setup(dev)) != 0) {
1299 bus_release_resources(dev, sc->match->driver->res_spec,
1300 sc->sc_res);
1301 free(sc->gatt, M_AGP);
1302 agp_generic_detach(dev);
1303 return (error);
1304 }
1305
1306 intel_agp = dev;
1307 device_printf(dev, "aperture size is %dM",
1308 sc->initial_aperture / 1024 / 1024);
1309 if (sc->stolen > 0)
1310 printf(", detected %dk stolen memory\n", sc->stolen * 4);
1311 else
1312 printf("\n");
1313 if (bootverbose) {
1314 sc->match->driver->dump_regs(dev);
1315 device_printf(dev, "Mappable GTT entries: %d\n",
1316 sc->gtt_mappable_entries);
1317 device_printf(dev, "Total GTT entries: %d\n",
1318 sc->gtt_total_entries);
1319 }
1320 return (0);
1321 }
1322
1323 static void
agp_i810_deinstall_gatt(device_t dev)1324 agp_i810_deinstall_gatt(device_t dev)
1325 {
1326 struct agp_i810_softc *sc;
1327
1328 sc = device_get_softc(dev);
1329 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
1330 kmem_free(sc->gatt->ag_virtual, 64 * 1024);
1331 }
1332
1333 static void
agp_i830_deinstall_gatt(device_t dev)1334 agp_i830_deinstall_gatt(device_t dev)
1335 {
1336 struct agp_i810_softc *sc;
1337 unsigned int pgtblctl;
1338
1339 sc = device_get_softc(dev);
1340 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1341 pgtblctl &= ~1;
1342 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1343 }
1344
1345 static int
agp_i810_detach(device_t dev)1346 agp_i810_detach(device_t dev)
1347 {
1348 struct agp_i810_softc *sc;
1349
1350 sc = device_get_softc(dev);
1351 agp_free_cdev(dev);
1352
1353 /* Clear the GATT base. */
1354 sc->match->driver->deinstall_gatt(dev);
1355
1356 sc->match->driver->chipset_flush_teardown(dev);
1357
1358 /* Put the aperture back the way it started. */
1359 AGP_SET_APERTURE(dev, sc->initial_aperture);
1360
1361 free(sc->gatt, M_AGP);
1362 bus_release_resources(dev, sc->match->driver->res_spec, sc->sc_res);
1363 agp_free_res(dev);
1364
1365 return (0);
1366 }
1367
1368 static int
agp_i810_resume(device_t dev)1369 agp_i810_resume(device_t dev)
1370 {
1371 struct agp_i810_softc *sc;
1372 sc = device_get_softc(dev);
1373
1374 AGP_SET_APERTURE(dev, sc->initial_aperture);
1375
1376 /* Install the GATT. */
1377 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1378 sc->gatt->ag_physical | 1);
1379
1380 return (bus_generic_resume(dev));
1381 }
1382
1383 /**
1384 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
1385 * while returning failure on later chipsets when an actual change is
1386 * requested.
1387 *
1388 * This whole function is likely bogus, as the kernel would probably need to
1389 * reconfigure the placement of the AGP aperture if a larger size is requested,
1390 * which doesn't happen currently.
1391 */
1392 static int
agp_i810_set_aperture(device_t dev,u_int32_t aperture)1393 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
1394 {
1395 struct agp_i810_softc *sc;
1396 u_int16_t miscc;
1397
1398 sc = device_get_softc(dev);
1399 /*
1400 * Double check for sanity.
1401 */
1402 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
1403 device_printf(dev, "bad aperture size %d\n", aperture);
1404 return (EINVAL);
1405 }
1406
1407 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
1408 miscc &= ~AGP_I810_MISCC_WINSIZE;
1409 if (aperture == 32 * 1024 * 1024)
1410 miscc |= AGP_I810_MISCC_WINSIZE_32;
1411 else
1412 miscc |= AGP_I810_MISCC_WINSIZE_64;
1413
1414 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
1415 return (0);
1416 }
1417
1418 static int
agp_i830_set_aperture(device_t dev,u_int32_t aperture)1419 agp_i830_set_aperture(device_t dev, u_int32_t aperture)
1420 {
1421 struct agp_i810_softc *sc;
1422 u_int16_t gcc1;
1423
1424 sc = device_get_softc(dev);
1425
1426 if (aperture != 64 * 1024 * 1024 &&
1427 aperture != 128 * 1024 * 1024) {
1428 device_printf(dev, "bad aperture size %d\n", aperture);
1429 return (EINVAL);
1430 }
1431 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1432 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
1433 if (aperture == 64 * 1024 * 1024)
1434 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
1435 else
1436 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
1437
1438 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
1439 return (0);
1440 }
1441
1442 static int
agp_i915_set_aperture(device_t dev,u_int32_t aperture)1443 agp_i915_set_aperture(device_t dev, u_int32_t aperture)
1444 {
1445
1446 return (agp_generic_set_aperture(dev, aperture));
1447 }
1448
1449 static int
agp_i810_method_set_aperture(device_t dev,u_int32_t aperture)1450 agp_i810_method_set_aperture(device_t dev, u_int32_t aperture)
1451 {
1452 struct agp_i810_softc *sc;
1453
1454 sc = device_get_softc(dev);
1455 return (sc->match->driver->set_aperture(dev, aperture));
1456 }
1457
1458 /**
1459 * Writes a GTT entry mapping the page at the given offset from the
1460 * beginning of the aperture to the given physical address. Setup the
1461 * caching mode according to flags.
1462 *
1463 * For gen 1, 2 and 3, GTT start is located at AGP_I810_GTT offset
1464 * from corresponding BAR start. For gen 4, offset is 512KB +
1465 * AGP_I810_GTT, for gen 5 and 6 it is 2MB + AGP_I810_GTT.
1466 *
1467 * Also, the bits of the physical page address above 4GB needs to be
1468 * placed into bits 40-32 of PTE.
1469 */
1470 static void
agp_i810_install_gtt_pte(device_t dev,u_int index,vm_offset_t physical,int flags)1471 agp_i810_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1472 int flags)
1473 {
1474 uint32_t pte;
1475
1476 pte = (u_int32_t)physical | I810_PTE_VALID;
1477 if (flags == AGP_DCACHE_MEMORY)
1478 pte |= I810_PTE_LOCAL;
1479 else if (flags == AGP_USER_CACHED_MEMORY)
1480 pte |= I830_PTE_SYSTEM_CACHED;
1481 agp_i810_write_gtt(dev, index, pte);
1482 }
1483
1484 static void
agp_i810_write_gtt(device_t dev,u_int index,uint32_t pte)1485 agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte)
1486 {
1487 struct agp_i810_softc *sc;
1488
1489 sc = device_get_softc(dev);
1490 bus_write_4(sc->sc_res[0], AGP_I810_GTT + index * 4, pte);
1491 CTR2(KTR_AGP_I810, "810_pte %x %x", index, pte);
1492 }
1493
1494 static void
agp_i830_install_gtt_pte(device_t dev,u_int index,vm_offset_t physical,int flags)1495 agp_i830_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1496 int flags)
1497 {
1498 uint32_t pte;
1499
1500 pte = (u_int32_t)physical | I810_PTE_VALID;
1501 if (flags == AGP_USER_CACHED_MEMORY)
1502 pte |= I830_PTE_SYSTEM_CACHED;
1503 agp_i810_write_gtt(dev, index, pte);
1504 }
1505
1506 static void
agp_i915_install_gtt_pte(device_t dev,u_int index,vm_offset_t physical,int flags)1507 agp_i915_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1508 int flags)
1509 {
1510 uint32_t pte;
1511
1512 pte = (u_int32_t)physical | I810_PTE_VALID;
1513 if (flags == AGP_USER_CACHED_MEMORY)
1514 pte |= I830_PTE_SYSTEM_CACHED;
1515 pte |= (physical & 0x0000000f00000000ull) >> 28;
1516 agp_i915_write_gtt(dev, index, pte);
1517 }
1518
1519 static void
agp_i915_write_gtt(device_t dev,u_int index,uint32_t pte)1520 agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte)
1521 {
1522 struct agp_i810_softc *sc;
1523
1524 sc = device_get_softc(dev);
1525 bus_write_4(sc->sc_res[1], index * 4, pte);
1526 CTR2(KTR_AGP_I810, "915_pte %x %x", index, pte);
1527 }
1528
1529 static void
agp_i965_install_gtt_pte(device_t dev,u_int index,vm_offset_t physical,int flags)1530 agp_i965_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1531 int flags)
1532 {
1533 uint32_t pte;
1534
1535 pte = (u_int32_t)physical | I810_PTE_VALID;
1536 if (flags == AGP_USER_CACHED_MEMORY)
1537 pte |= I830_PTE_SYSTEM_CACHED;
1538 pte |= (physical & 0x0000000f00000000ull) >> 28;
1539 agp_i965_write_gtt(dev, index, pte);
1540 }
1541
1542 static void
agp_i965_write_gtt(device_t dev,u_int index,uint32_t pte)1543 agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte)
1544 {
1545 struct agp_i810_softc *sc;
1546
1547 sc = device_get_softc(dev);
1548 bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte);
1549 CTR2(KTR_AGP_I810, "965_pte %x %x", index, pte);
1550 }
1551
1552 static void
agp_g4x_install_gtt_pte(device_t dev,u_int index,vm_offset_t physical,int flags)1553 agp_g4x_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1554 int flags)
1555 {
1556 uint32_t pte;
1557
1558 pte = (u_int32_t)physical | I810_PTE_VALID;
1559 if (flags == AGP_USER_CACHED_MEMORY)
1560 pte |= I830_PTE_SYSTEM_CACHED;
1561 pte |= (physical & 0x0000000f00000000ull) >> 28;
1562 agp_g4x_write_gtt(dev, index, pte);
1563 }
1564
1565 static void
agp_g4x_write_gtt(device_t dev,u_int index,uint32_t pte)1566 agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte)
1567 {
1568 struct agp_i810_softc *sc;
1569
1570 sc = device_get_softc(dev);
1571 bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
1572 CTR2(KTR_AGP_I810, "g4x_pte %x %x", index, pte);
1573 }
1574
1575 static int
agp_i810_bind_page(device_t dev,vm_offset_t offset,vm_offset_t physical)1576 agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
1577 {
1578 struct agp_i810_softc *sc = device_get_softc(dev);
1579 u_int index;
1580
1581 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
1582 device_printf(dev, "failed: offset is 0x%08jx, "
1583 "shift is %d, entries is %d\n", (intmax_t)offset,
1584 AGP_PAGE_SHIFT, sc->gatt->ag_entries);
1585 return (EINVAL);
1586 }
1587 index = offset >> AGP_PAGE_SHIFT;
1588 if (sc->stolen != 0 && index < sc->stolen) {
1589 device_printf(dev, "trying to bind into stolen memory\n");
1590 return (EINVAL);
1591 }
1592 sc->match->driver->install_gtt_pte(dev, index, physical, 0);
1593 return (0);
1594 }
1595
1596 static int
agp_i810_unbind_page(device_t dev,vm_offset_t offset)1597 agp_i810_unbind_page(device_t dev, vm_offset_t offset)
1598 {
1599 struct agp_i810_softc *sc;
1600 u_int index;
1601
1602 sc = device_get_softc(dev);
1603 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
1604 return (EINVAL);
1605 index = offset >> AGP_PAGE_SHIFT;
1606 if (sc->stolen != 0 && index < sc->stolen) {
1607 device_printf(dev, "trying to unbind from stolen memory\n");
1608 return (EINVAL);
1609 }
1610 sc->match->driver->install_gtt_pte(dev, index, 0, 0);
1611 return (0);
1612 }
1613
1614 static u_int32_t
agp_i810_read_gtt_pte(device_t dev,u_int index)1615 agp_i810_read_gtt_pte(device_t dev, u_int index)
1616 {
1617 struct agp_i810_softc *sc;
1618 u_int32_t pte;
1619
1620 sc = device_get_softc(dev);
1621 pte = bus_read_4(sc->sc_res[0], AGP_I810_GTT + index * 4);
1622 return (pte);
1623 }
1624
1625 static u_int32_t
agp_i915_read_gtt_pte(device_t dev,u_int index)1626 agp_i915_read_gtt_pte(device_t dev, u_int index)
1627 {
1628 struct agp_i810_softc *sc;
1629 u_int32_t pte;
1630
1631 sc = device_get_softc(dev);
1632 pte = bus_read_4(sc->sc_res[1], index * 4);
1633 return (pte);
1634 }
1635
1636 static u_int32_t
agp_i965_read_gtt_pte(device_t dev,u_int index)1637 agp_i965_read_gtt_pte(device_t dev, u_int index)
1638 {
1639 struct agp_i810_softc *sc;
1640 u_int32_t pte;
1641
1642 sc = device_get_softc(dev);
1643 pte = bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024));
1644 return (pte);
1645 }
1646
1647 static u_int32_t
agp_g4x_read_gtt_pte(device_t dev,u_int index)1648 agp_g4x_read_gtt_pte(device_t dev, u_int index)
1649 {
1650 struct agp_i810_softc *sc;
1651 u_int32_t pte;
1652
1653 sc = device_get_softc(dev);
1654 pte = bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024));
1655 return (pte);
1656 }
1657
1658 static vm_paddr_t
agp_i810_read_gtt_pte_paddr(device_t dev,u_int index)1659 agp_i810_read_gtt_pte_paddr(device_t dev, u_int index)
1660 {
1661 struct agp_i810_softc *sc;
1662 u_int32_t pte;
1663 vm_paddr_t res;
1664
1665 sc = device_get_softc(dev);
1666 pte = sc->match->driver->read_gtt_pte(dev, index);
1667 res = pte & ~PAGE_MASK;
1668 return (res);
1669 }
1670
1671 static vm_paddr_t
agp_i915_read_gtt_pte_paddr(device_t dev,u_int index)1672 agp_i915_read_gtt_pte_paddr(device_t dev, u_int index)
1673 {
1674 struct agp_i810_softc *sc;
1675 u_int32_t pte;
1676 vm_paddr_t res;
1677
1678 sc = device_get_softc(dev);
1679 pte = sc->match->driver->read_gtt_pte(dev, index);
1680 res = (pte & ~PAGE_MASK) | ((pte & 0xf0) << 28);
1681 return (res);
1682 }
1683
1684 /*
1685 * Writing via memory mapped registers already flushes all TLBs.
1686 */
1687 static void
agp_i810_flush_tlb(device_t dev)1688 agp_i810_flush_tlb(device_t dev)
1689 {
1690 }
1691
1692 static int
agp_i810_enable(device_t dev,u_int32_t mode)1693 agp_i810_enable(device_t dev, u_int32_t mode)
1694 {
1695
1696 return (0);
1697 }
1698
1699 static struct agp_memory *
agp_i810_alloc_memory(device_t dev,int type,vm_size_t size)1700 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
1701 {
1702 struct agp_i810_softc *sc;
1703 struct agp_memory *mem;
1704 vm_page_t m;
1705
1706 sc = device_get_softc(dev);
1707
1708 if ((size & (AGP_PAGE_SIZE - 1)) != 0 ||
1709 sc->agp.as_allocated + size > sc->agp.as_maxmem)
1710 return (0);
1711
1712 if (type == 1) {
1713 /*
1714 * Mapping local DRAM into GATT.
1715 */
1716 if (sc->match->driver->chiptype != CHIP_I810)
1717 return (0);
1718 if (size != sc->dcache_size)
1719 return (0);
1720 } else if (type == 2) {
1721 /*
1722 * Type 2 is the contiguous physical memory type, that hands
1723 * back a physical address. This is used for cursors on i810.
1724 * Hand back as many single pages with physical as the user
1725 * wants, but only allow one larger allocation (ARGB cursor)
1726 * for simplicity.
1727 */
1728 if (size != AGP_PAGE_SIZE) {
1729 if (sc->argb_cursor != NULL)
1730 return (0);
1731
1732 /* Allocate memory for ARGB cursor, if we can. */
1733 sc->argb_cursor = contigmalloc(size, M_AGP,
1734 0, 0, ~0, PAGE_SIZE, 0);
1735 if (sc->argb_cursor == NULL)
1736 return (0);
1737 }
1738 }
1739
1740 mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
1741 mem->am_id = sc->agp.as_nextid++;
1742 mem->am_size = size;
1743 mem->am_type = type;
1744 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
1745 mem->am_obj = vm_object_allocate(OBJT_SWAP,
1746 atop(round_page(size)));
1747 else
1748 mem->am_obj = 0;
1749
1750 if (type == 2) {
1751 if (size == AGP_PAGE_SIZE) {
1752 /*
1753 * Allocate and wire down the page now so that we can
1754 * get its physical address.
1755 */
1756 VM_OBJECT_WLOCK(mem->am_obj);
1757 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
1758 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1759 VM_OBJECT_WUNLOCK(mem->am_obj);
1760 mem->am_physical = VM_PAGE_TO_PHYS(m);
1761 } else {
1762 /* Our allocation is already nicely wired down for us.
1763 * Just grab the physical address.
1764 */
1765 mem->am_physical = vtophys(sc->argb_cursor);
1766 }
1767 } else
1768 mem->am_physical = 0;
1769
1770 mem->am_offset = 0;
1771 mem->am_is_bound = 0;
1772 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
1773 sc->agp.as_allocated += size;
1774
1775 return (mem);
1776 }
1777
1778 static int
agp_i810_free_memory(device_t dev,struct agp_memory * mem)1779 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1780 {
1781 struct agp_i810_softc *sc;
1782 vm_page_t m;
1783
1784 if (mem->am_is_bound)
1785 return (EBUSY);
1786
1787 sc = device_get_softc(dev);
1788
1789 if (mem->am_type == 2) {
1790 if (mem->am_size == AGP_PAGE_SIZE) {
1791 /*
1792 * Unwire the page which we wired in alloc_memory.
1793 */
1794 VM_OBJECT_WLOCK(mem->am_obj);
1795 m = vm_page_lookup(mem->am_obj, 0);
1796 vm_page_unwire(m, PQ_INACTIVE);
1797 VM_OBJECT_WUNLOCK(mem->am_obj);
1798 } else {
1799 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1800 sc->argb_cursor = NULL;
1801 }
1802 }
1803
1804 sc->agp.as_allocated -= mem->am_size;
1805 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1806 if (mem->am_obj)
1807 vm_object_deallocate(mem->am_obj);
1808 free(mem, M_AGP);
1809 return (0);
1810 }
1811
1812 static int
agp_i810_bind_memory(device_t dev,struct agp_memory * mem,vm_offset_t offset)1813 agp_i810_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset)
1814 {
1815 struct agp_i810_softc *sc;
1816 vm_offset_t i;
1817
1818 /* Do some sanity checks first. */
1819 if ((offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1820 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1821 device_printf(dev, "binding memory at bad offset %#x\n",
1822 (int)offset);
1823 return (EINVAL);
1824 }
1825
1826 sc = device_get_softc(dev);
1827 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1828 mtx_lock(&sc->agp.as_lock);
1829 if (mem->am_is_bound) {
1830 mtx_unlock(&sc->agp.as_lock);
1831 return (EINVAL);
1832 }
1833 /* The memory's already wired down, just stick it in the GTT. */
1834 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1835 sc->match->driver->install_gtt_pte(dev, (offset + i) >>
1836 AGP_PAGE_SHIFT, mem->am_physical + i, 0);
1837 }
1838 mem->am_offset = offset;
1839 mem->am_is_bound = 1;
1840 mtx_unlock(&sc->agp.as_lock);
1841 return (0);
1842 }
1843
1844 if (mem->am_type != 1)
1845 return (agp_generic_bind_memory(dev, mem, offset));
1846
1847 /*
1848 * Mapping local DRAM into GATT.
1849 */
1850 if (sc->match->driver->chiptype != CHIP_I810)
1851 return (EINVAL);
1852 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1853 bus_write_4(sc->sc_res[0],
1854 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1855
1856 return (0);
1857 }
1858
1859 static int
agp_i810_unbind_memory(device_t dev,struct agp_memory * mem)1860 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1861 {
1862 struct agp_i810_softc *sc;
1863 vm_offset_t i;
1864
1865 sc = device_get_softc(dev);
1866
1867 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1868 mtx_lock(&sc->agp.as_lock);
1869 if (!mem->am_is_bound) {
1870 mtx_unlock(&sc->agp.as_lock);
1871 return (EINVAL);
1872 }
1873
1874 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1875 sc->match->driver->install_gtt_pte(dev,
1876 (mem->am_offset + i) >> AGP_PAGE_SHIFT, 0, 0);
1877 }
1878 mem->am_is_bound = 0;
1879 mtx_unlock(&sc->agp.as_lock);
1880 return (0);
1881 }
1882
1883 if (mem->am_type != 1)
1884 return (agp_generic_unbind_memory(dev, mem));
1885
1886 if (sc->match->driver->chiptype != CHIP_I810)
1887 return (EINVAL);
1888 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1889 sc->match->driver->install_gtt_pte(dev, i >> AGP_PAGE_SHIFT,
1890 0, 0);
1891 }
1892 return (0);
1893 }
1894
1895 static device_method_t agp_i810_methods[] = {
1896 /* Device interface */
1897 DEVMETHOD(device_identify, agp_i810_identify),
1898 DEVMETHOD(device_probe, agp_i810_probe),
1899 DEVMETHOD(device_attach, agp_i810_attach),
1900 DEVMETHOD(device_detach, agp_i810_detach),
1901 DEVMETHOD(device_suspend, bus_generic_suspend),
1902 DEVMETHOD(device_resume, agp_i810_resume),
1903
1904 /* AGP interface */
1905 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1906 DEVMETHOD(agp_set_aperture, agp_i810_method_set_aperture),
1907 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1908 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1909 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1910 DEVMETHOD(agp_enable, agp_i810_enable),
1911 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1912 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1913 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1914 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1915 DEVMETHOD(agp_chipset_flush, agp_intel_gtt_chipset_flush),
1916 { 0, 0 }
1917 };
1918
1919 static driver_t agp_i810_driver = {
1920 "agp",
1921 agp_i810_methods,
1922 sizeof(struct agp_i810_softc),
1923 };
1924
1925 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, 0, 0);
1926 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1927 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
1928
1929 void
agp_intel_gtt_clear_range(device_t dev,u_int first_entry,u_int num_entries)1930 agp_intel_gtt_clear_range(device_t dev, u_int first_entry, u_int num_entries)
1931 {
1932 struct agp_i810_softc *sc;
1933 u_int i;
1934
1935 sc = device_get_softc(dev);
1936 for (i = 0; i < num_entries; i++)
1937 sc->match->driver->install_gtt_pte(dev, first_entry + i,
1938 VM_PAGE_TO_PHYS(bogus_page), 0);
1939 sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1);
1940 }
1941
1942 void
agp_intel_gtt_insert_pages(device_t dev,u_int first_entry,u_int num_entries,vm_page_t * pages,u_int flags)1943 agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, u_int num_entries,
1944 vm_page_t *pages, u_int flags)
1945 {
1946 struct agp_i810_softc *sc;
1947 u_int i;
1948
1949 sc = device_get_softc(dev);
1950 for (i = 0; i < num_entries; i++) {
1951 MPASS(pages[i]->valid == VM_PAGE_BITS_ALL);
1952 MPASS(pages[i]->ref_count > 0);
1953 sc->match->driver->install_gtt_pte(dev, first_entry + i,
1954 VM_PAGE_TO_PHYS(pages[i]), flags);
1955 }
1956 sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1);
1957 }
1958
1959 struct intel_gtt
agp_intel_gtt_get(device_t dev)1960 agp_intel_gtt_get(device_t dev)
1961 {
1962 struct agp_i810_softc *sc;
1963 struct intel_gtt res;
1964
1965 sc = device_get_softc(dev);
1966 res.stolen_size = sc->stolen_size;
1967 res.gtt_total_entries = sc->gtt_total_entries;
1968 res.gtt_mappable_entries = sc->gtt_mappable_entries;
1969 res.do_idle_maps = 0;
1970 res.scratch_page_dma = VM_PAGE_TO_PHYS(bogus_page);
1971 if (sc->agp.as_aperture != NULL)
1972 res.gma_bus_addr = rman_get_start(sc->agp.as_aperture);
1973 else
1974 res.gma_bus_addr = 0;
1975 return (res);
1976 }
1977
1978 static int
agp_i810_chipset_flush_setup(device_t dev)1979 agp_i810_chipset_flush_setup(device_t dev)
1980 {
1981
1982 return (0);
1983 }
1984
1985 static void
agp_i810_chipset_flush_teardown(device_t dev)1986 agp_i810_chipset_flush_teardown(device_t dev)
1987 {
1988
1989 /* Nothing to do. */
1990 }
1991
1992 static void
agp_i810_chipset_flush(device_t dev)1993 agp_i810_chipset_flush(device_t dev)
1994 {
1995
1996 /* Nothing to do. */
1997 }
1998
1999 static void
agp_i830_chipset_flush(device_t dev)2000 agp_i830_chipset_flush(device_t dev)
2001 {
2002 struct agp_i810_softc *sc;
2003 uint32_t hic;
2004 int i;
2005
2006 sc = device_get_softc(dev);
2007 pmap_invalidate_cache();
2008 hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
2009 bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31));
2010 for (i = 0; i < 20000 /* 1 sec */; i++) {
2011 hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
2012 if ((hic & (1U << 31)) == 0)
2013 break;
2014 DELAY(50);
2015 }
2016 }
2017
2018 static int
agp_i915_chipset_flush_alloc_page(device_t dev,uint64_t start,uint64_t end)2019 agp_i915_chipset_flush_alloc_page(device_t dev, uint64_t start, uint64_t end)
2020 {
2021 struct agp_i810_softc *sc;
2022 device_t vga;
2023
2024 sc = device_get_softc(dev);
2025 vga = device_get_parent(dev);
2026 sc->sc_flush_page_rid = 100;
2027 sc->sc_flush_page_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), dev,
2028 SYS_RES_MEMORY, &sc->sc_flush_page_rid, start, end, PAGE_SIZE,
2029 RF_ACTIVE);
2030 if (sc->sc_flush_page_res == NULL) {
2031 device_printf(dev, "Failed to allocate flush page at 0x%jx\n",
2032 (uintmax_t)start);
2033 return (EINVAL);
2034 }
2035 sc->sc_flush_page_vaddr = rman_get_virtual(sc->sc_flush_page_res);
2036 if (bootverbose) {
2037 device_printf(dev, "Allocated flush page phys 0x%jx virt %p\n",
2038 (uintmax_t)rman_get_start(sc->sc_flush_page_res),
2039 sc->sc_flush_page_vaddr);
2040 }
2041 return (0);
2042 }
2043
2044 static void
agp_i915_chipset_flush_free_page(device_t dev)2045 agp_i915_chipset_flush_free_page(device_t dev)
2046 {
2047 struct agp_i810_softc *sc;
2048 device_t vga;
2049
2050 sc = device_get_softc(dev);
2051 vga = device_get_parent(dev);
2052 if (sc->sc_flush_page_res == NULL)
2053 return;
2054 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev,
2055 sc->sc_flush_page_res);
2056 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev,
2057 sc->sc_flush_page_res);
2058 }
2059
2060 static int
agp_i915_chipset_flush_setup(device_t dev)2061 agp_i915_chipset_flush_setup(device_t dev)
2062 {
2063 struct agp_i810_softc *sc;
2064 uint32_t temp;
2065 int error;
2066
2067 sc = device_get_softc(dev);
2068 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
2069 if ((temp & 1) != 0) {
2070 temp &= ~1;
2071 if (bootverbose)
2072 device_printf(dev,
2073 "Found already configured flush page at 0x%jx\n",
2074 (uintmax_t)temp);
2075 sc->sc_bios_allocated_flush_page = 1;
2076 /*
2077 * In the case BIOS initialized the flush pointer (?)
2078 * register, expect that BIOS also set up the resource
2079 * for the page.
2080 */
2081 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2082 temp + PAGE_SIZE - 1);
2083 if (error != 0)
2084 return (error);
2085 } else {
2086 sc->sc_bios_allocated_flush_page = 0;
2087 error = agp_i915_chipset_flush_alloc_page(dev, 0, 0xffffffff);
2088 if (error != 0)
2089 return (error);
2090 temp = rman_get_start(sc->sc_flush_page_res);
2091 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp | 1, 4);
2092 }
2093 return (0);
2094 }
2095
2096 static void
agp_i915_chipset_flush_teardown(device_t dev)2097 agp_i915_chipset_flush_teardown(device_t dev)
2098 {
2099 struct agp_i810_softc *sc;
2100 uint32_t temp;
2101
2102 sc = device_get_softc(dev);
2103 if (sc->sc_flush_page_res == NULL)
2104 return;
2105 if (!sc->sc_bios_allocated_flush_page) {
2106 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
2107 temp &= ~1;
2108 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp, 4);
2109 }
2110 agp_i915_chipset_flush_free_page(dev);
2111 }
2112
2113 static int
agp_i965_chipset_flush_setup(device_t dev)2114 agp_i965_chipset_flush_setup(device_t dev)
2115 {
2116 struct agp_i810_softc *sc;
2117 uint64_t temp;
2118 uint32_t temp_hi, temp_lo;
2119 int error;
2120
2121 sc = device_get_softc(dev);
2122
2123 temp_hi = pci_read_config(sc->bdev, AGP_I965_IFPADDR + 4, 4);
2124 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2125
2126 if ((temp_lo & 1) != 0) {
2127 temp = ((uint64_t)temp_hi << 32) | (temp_lo & ~1);
2128 if (bootverbose)
2129 device_printf(dev,
2130 "Found already configured flush page at 0x%jx\n",
2131 (uintmax_t)temp);
2132 sc->sc_bios_allocated_flush_page = 1;
2133 /*
2134 * In the case BIOS initialized the flush pointer (?)
2135 * register, expect that BIOS also set up the resource
2136 * for the page.
2137 */
2138 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2139 temp + PAGE_SIZE - 1);
2140 if (error != 0)
2141 return (error);
2142 } else {
2143 sc->sc_bios_allocated_flush_page = 0;
2144 error = agp_i915_chipset_flush_alloc_page(dev, 0, ~0);
2145 if (error != 0)
2146 return (error);
2147 temp = rman_get_start(sc->sc_flush_page_res);
2148 pci_write_config(sc->bdev, AGP_I965_IFPADDR + 4,
2149 (temp >> 32) & UINT32_MAX, 4);
2150 pci_write_config(sc->bdev, AGP_I965_IFPADDR,
2151 (temp & UINT32_MAX) | 1, 4);
2152 }
2153 return (0);
2154 }
2155
2156 static void
agp_i965_chipset_flush_teardown(device_t dev)2157 agp_i965_chipset_flush_teardown(device_t dev)
2158 {
2159 struct agp_i810_softc *sc;
2160 uint32_t temp_lo;
2161
2162 sc = device_get_softc(dev);
2163 if (sc->sc_flush_page_res == NULL)
2164 return;
2165 if (!sc->sc_bios_allocated_flush_page) {
2166 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2167 temp_lo &= ~1;
2168 pci_write_config(sc->bdev, AGP_I965_IFPADDR, temp_lo, 4);
2169 }
2170 agp_i915_chipset_flush_free_page(dev);
2171 }
2172
2173 static void
agp_i915_chipset_flush(device_t dev)2174 agp_i915_chipset_flush(device_t dev)
2175 {
2176 struct agp_i810_softc *sc;
2177
2178 sc = device_get_softc(dev);
2179 *(uint32_t *)sc->sc_flush_page_vaddr = 1;
2180 }
2181
2182 int
agp_intel_gtt_chipset_flush(device_t dev)2183 agp_intel_gtt_chipset_flush(device_t dev)
2184 {
2185 struct agp_i810_softc *sc;
2186
2187 sc = device_get_softc(dev);
2188 sc->match->driver->chipset_flush(dev);
2189 return (0);
2190 }
2191
2192 void
agp_intel_gtt_unmap_memory(device_t dev,struct sglist * sg_list)2193 agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list)
2194 {
2195 }
2196
2197 int
agp_intel_gtt_map_memory(device_t dev,vm_page_t * pages,u_int num_entries,struct sglist ** sg_list)2198 agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries,
2199 struct sglist **sg_list)
2200 {
2201 #if 0
2202 struct agp_i810_softc *sc;
2203 #endif
2204 struct sglist *sg;
2205 int i;
2206 #if 0
2207 int error;
2208 bus_dma_tag_t dmat;
2209 #endif
2210
2211 if (*sg_list != NULL)
2212 return (0);
2213 #if 0
2214 sc = device_get_softc(dev);
2215 #endif
2216 sg = sglist_alloc(num_entries, M_WAITOK /* XXXKIB */);
2217 for (i = 0; i < num_entries; i++) {
2218 sg->sg_segs[i].ss_paddr = VM_PAGE_TO_PHYS(pages[i]);
2219 sg->sg_segs[i].ss_len = PAGE_SIZE;
2220 }
2221
2222 #if 0
2223 error = bus_dma_tag_create(bus_get_dma_tag(dev),
2224 1 /* alignment */, 0 /* boundary */,
2225 1ULL << sc->match->busdma_addr_mask_sz /* lowaddr */,
2226 BUS_SPACE_MAXADDR /* highaddr */,
2227 NULL /* filtfunc */, NULL /* filtfuncarg */,
2228 BUS_SPACE_MAXADDR /* maxsize */,
2229 BUS_SPACE_UNRESTRICTED /* nsegments */,
2230 BUS_SPACE_MAXADDR /* maxsegsz */,
2231 0 /* flags */, NULL /* lockfunc */, NULL /* lockfuncarg */,
2232 &dmat);
2233 if (error != 0) {
2234 sglist_free(sg);
2235 return (error);
2236 }
2237 /* XXXKIB */
2238 #endif
2239 *sg_list = sg;
2240 return (0);
2241 }
2242
2243 static void
agp_intel_gtt_install_pte(device_t dev,u_int index,vm_paddr_t addr,u_int flags)2244 agp_intel_gtt_install_pte(device_t dev, u_int index, vm_paddr_t addr,
2245 u_int flags)
2246 {
2247 struct agp_i810_softc *sc;
2248
2249 sc = device_get_softc(dev);
2250 sc->match->driver->install_gtt_pte(dev, index, addr, flags);
2251 }
2252
2253 void
agp_intel_gtt_insert_sg_entries(device_t dev,struct sglist * sg_list,u_int first_entry,u_int flags)2254 agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list,
2255 u_int first_entry, u_int flags)
2256 {
2257 struct agp_i810_softc *sc;
2258 vm_paddr_t spaddr;
2259 size_t slen;
2260 u_int i, j;
2261
2262 sc = device_get_softc(dev);
2263 for (i = j = 0; j < sg_list->sg_nseg; j++) {
2264 spaddr = sg_list->sg_segs[i].ss_paddr;
2265 slen = sg_list->sg_segs[i].ss_len;
2266 for (; slen > 0; i++) {
2267 sc->match->driver->install_gtt_pte(dev, first_entry + i,
2268 spaddr, flags);
2269 spaddr += AGP_PAGE_SIZE;
2270 slen -= AGP_PAGE_SIZE;
2271 }
2272 }
2273 sc->match->driver->read_gtt_pte(dev, first_entry + i - 1);
2274 }
2275
2276 void
intel_gtt_clear_range(u_int first_entry,u_int num_entries)2277 intel_gtt_clear_range(u_int first_entry, u_int num_entries)
2278 {
2279
2280 agp_intel_gtt_clear_range(intel_agp, first_entry, num_entries);
2281 }
2282
2283 void
intel_gtt_insert_pages(u_int first_entry,u_int num_entries,vm_page_t * pages,u_int flags)2284 intel_gtt_insert_pages(u_int first_entry, u_int num_entries, vm_page_t *pages,
2285 u_int flags)
2286 {
2287
2288 agp_intel_gtt_insert_pages(intel_agp, first_entry, num_entries,
2289 pages, flags);
2290 }
2291
2292 struct intel_gtt *
intel_gtt_get(void)2293 intel_gtt_get(void)
2294 {
2295
2296 intel_private.base = agp_intel_gtt_get(intel_agp);
2297 return (&intel_private.base);
2298 }
2299
2300 int
intel_gtt_chipset_flush(void)2301 intel_gtt_chipset_flush(void)
2302 {
2303
2304 return (agp_intel_gtt_chipset_flush(intel_agp));
2305 }
2306
2307 void
intel_gtt_unmap_memory(struct sglist * sg_list)2308 intel_gtt_unmap_memory(struct sglist *sg_list)
2309 {
2310
2311 agp_intel_gtt_unmap_memory(intel_agp, sg_list);
2312 }
2313
2314 int
intel_gtt_map_memory(vm_page_t * pages,u_int num_entries,struct sglist ** sg_list)2315 intel_gtt_map_memory(vm_page_t *pages, u_int num_entries,
2316 struct sglist **sg_list)
2317 {
2318
2319 return (agp_intel_gtt_map_memory(intel_agp, pages, num_entries,
2320 sg_list));
2321 }
2322
2323 void
intel_gtt_insert_sg_entries(struct sglist * sg_list,u_int first_entry,u_int flags)2324 intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int first_entry,
2325 u_int flags)
2326 {
2327
2328 agp_intel_gtt_insert_sg_entries(intel_agp, sg_list, first_entry, flags);
2329 }
2330
2331 void
intel_gtt_install_pte(u_int index,vm_paddr_t addr,u_int flags)2332 intel_gtt_install_pte(u_int index, vm_paddr_t addr, u_int flags)
2333 {
2334
2335 agp_intel_gtt_install_pte(intel_agp, index, addr, flags);
2336 }
2337
2338 device_t
intel_gtt_get_bridge_device(void)2339 intel_gtt_get_bridge_device(void)
2340 {
2341 struct agp_i810_softc *sc;
2342
2343 sc = device_get_softc(intel_agp);
2344 return (sc->bdev);
2345 }
2346
2347 vm_paddr_t
intel_gtt_read_pte_paddr(u_int entry)2348 intel_gtt_read_pte_paddr(u_int entry)
2349 {
2350 struct agp_i810_softc *sc;
2351
2352 sc = device_get_softc(intel_agp);
2353 return (sc->match->driver->read_gtt_pte_paddr(intel_agp, entry));
2354 }
2355
2356 u_int32_t
intel_gtt_read_pte(u_int entry)2357 intel_gtt_read_pte(u_int entry)
2358 {
2359 struct agp_i810_softc *sc;
2360
2361 sc = device_get_softc(intel_agp);
2362 return (sc->match->driver->read_gtt_pte(intel_agp, entry));
2363 }
2364
2365 void
intel_gtt_write(u_int entry,uint32_t val)2366 intel_gtt_write(u_int entry, uint32_t val)
2367 {
2368 struct agp_i810_softc *sc;
2369
2370 sc = device_get_softc(intel_agp);
2371 return (sc->match->driver->write_gtt(intel_agp, entry, val));
2372 }
2373