xref: /dragonfly/sys/dev/netif/ale/if_ale.c (revision 4e4d812d)
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $
28  */
29 
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
31 
32 #include <sys/param.h>
33 #include <sys/endian.h>
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/interrupt.h>
37 #include <sys/malloc.h>
38 #include <sys/proc.h>
39 #include <sys/rman.h>
40 #include <sys/serialize.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
44 
45 #include <net/ethernet.h>
46 #include <net/if.h>
47 #include <net/bpf.h>
48 #include <net/if_arp.h>
49 #include <net/if_dl.h>
50 #include <net/if_llc.h>
51 #include <net/if_media.h>
52 #include <net/ifq_var.h>
53 #include <net/vlan/if_vlan_var.h>
54 #include <net/vlan/if_vlan_ether.h>
55 
56 #include <netinet/ip.h>
57 
58 #include <dev/netif/mii_layer/mii.h>
59 #include <dev/netif/mii_layer/miivar.h>
60 
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include "pcidevs.h"
64 
65 #include <dev/netif/ale/if_alereg.h>
66 #include <dev/netif/ale/if_alevar.h>
67 
68 /* "device miibus" required.  See GENERIC if you get errors here. */
69 #include "miibus_if.h"
70 
71 /* For more information about Tx checksum offload issues see ale_encap(). */
72 #define	ALE_CSUM_FEATURES	(CSUM_TCP | CSUM_UDP)
73 
74 struct ale_dmamap_ctx {
75 	int			nsegs;
76 	bus_dma_segment_t	*segs;
77 };
78 
79 static int	ale_probe(device_t);
80 static int	ale_attach(device_t);
81 static int	ale_detach(device_t);
82 static int	ale_shutdown(device_t);
83 static int	ale_suspend(device_t);
84 static int	ale_resume(device_t);
85 
86 static int	ale_miibus_readreg(device_t, int, int);
87 static int	ale_miibus_writereg(device_t, int, int, int);
88 static void	ale_miibus_statchg(device_t);
89 
90 static void	ale_init(void *);
91 static void	ale_start(struct ifnet *, struct ifaltq_subque *);
92 static int	ale_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
93 static void	ale_watchdog(struct ifnet *);
94 static int	ale_mediachange(struct ifnet *);
95 static void	ale_mediastatus(struct ifnet *, struct ifmediareq *);
96 
97 static void	ale_intr(void *);
98 static int	ale_rxeof(struct ale_softc *sc);
99 static void	ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
100 		    uint32_t, uint32_t *);
101 static void	ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
102 static void	ale_txeof(struct ale_softc *);
103 
104 static int	ale_dma_alloc(struct ale_softc *);
105 static void	ale_dma_free(struct ale_softc *);
106 static int	ale_check_boundary(struct ale_softc *);
107 static void	ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
108 static void	ale_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
109 		    bus_size_t, int);
110 static int	ale_encap(struct ale_softc *, struct mbuf **);
111 static void	ale_init_rx_pages(struct ale_softc *);
112 static void	ale_init_tx_ring(struct ale_softc *);
113 
114 static void	ale_stop(struct ale_softc *);
115 static void	ale_tick(void *);
116 static void	ale_get_macaddr(struct ale_softc *);
117 static void	ale_mac_config(struct ale_softc *);
118 static void	ale_phy_reset(struct ale_softc *);
119 static void	ale_reset(struct ale_softc *);
120 static void	ale_rxfilter(struct ale_softc *);
121 static void	ale_rxvlan(struct ale_softc *);
122 static void	ale_stats_clear(struct ale_softc *);
123 static void	ale_stats_update(struct ale_softc *);
124 static void	ale_stop_mac(struct ale_softc *);
125 #ifdef notyet
126 static void	ale_setlinkspeed(struct ale_softc *);
127 static void	ale_setwol(struct ale_softc *);
128 #endif
129 
130 static void	ale_sysctl_node(struct ale_softc *);
131 static int	sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
132 
133 /*
134  * Devices supported by this driver.
135  */
136 static struct ale_dev {
137 	uint16_t	ale_vendorid;
138 	uint16_t	ale_deviceid;
139 	const char	*ale_name;
140 } ale_devs[] = {
141     { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
142     "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
143 };
144 
145 static device_method_t ale_methods[] = {
146 	/* Device interface. */
147 	DEVMETHOD(device_probe,		ale_probe),
148 	DEVMETHOD(device_attach,	ale_attach),
149 	DEVMETHOD(device_detach,	ale_detach),
150 	DEVMETHOD(device_shutdown,	ale_shutdown),
151 	DEVMETHOD(device_suspend,	ale_suspend),
152 	DEVMETHOD(device_resume,	ale_resume),
153 
154 	/* Bus interface. */
155 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
156 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
157 
158 	/* MII interface. */
159 	DEVMETHOD(miibus_readreg,	ale_miibus_readreg),
160 	DEVMETHOD(miibus_writereg,	ale_miibus_writereg),
161 	DEVMETHOD(miibus_statchg,	ale_miibus_statchg),
162 
163 	{ NULL, NULL }
164 };
165 
166 static driver_t ale_driver = {
167 	"ale",
168 	ale_methods,
169 	sizeof(struct ale_softc)
170 };
171 
172 static devclass_t ale_devclass;
173 
174 DECLARE_DUMMY_MODULE(if_ale);
175 MODULE_VERSION(if_ale, 1);
176 MODULE_DEPEND(if_ale, miibus, 1, 1, 1);
177 DRIVER_MODULE(if_ale, pci, ale_driver, ale_devclass, NULL, NULL);
178 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL);
179 
180 static int
ale_miibus_readreg(device_t dev,int phy,int reg)181 ale_miibus_readreg(device_t dev, int phy, int reg)
182 {
183 	struct ale_softc *sc;
184 	uint32_t v;
185 	int i;
186 
187 	sc = device_get_softc(dev);
188 
189 	if (phy != sc->ale_phyaddr)
190 		return (0);
191 
192 	if (sc->ale_flags & ALE_FLAG_FASTETHER) {
193 		if (reg == MII_100T2CR || reg == MII_100T2SR ||
194 		    reg == MII_EXTSR)
195 			return (0);
196 	}
197 
198 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
199 	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
200 	for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
201 		DELAY(5);
202 		v = CSR_READ_4(sc, ALE_MDIO);
203 		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
204 			break;
205 	}
206 
207 	if (i == 0) {
208 		device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
209 		return (0);
210 	}
211 
212 	return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
213 }
214 
215 static int
ale_miibus_writereg(device_t dev,int phy,int reg,int val)216 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
217 {
218 	struct ale_softc *sc;
219 	uint32_t v;
220 	int i;
221 
222 	sc = device_get_softc(dev);
223 
224 	if (phy != sc->ale_phyaddr)
225 		return (0);
226 
227 	if (sc->ale_flags & ALE_FLAG_FASTETHER) {
228 		if (reg == MII_100T2CR || reg == MII_100T2SR ||
229 		    reg == MII_EXTSR)
230 			return (0);
231 	}
232 
233 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
234 	    (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
235 	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
236 	for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
237 		DELAY(5);
238 		v = CSR_READ_4(sc, ALE_MDIO);
239 		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
240 			break;
241 	}
242 
243 	if (i == 0)
244 		device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
245 
246 	return (0);
247 }
248 
249 static void
ale_miibus_statchg(device_t dev)250 ale_miibus_statchg(device_t dev)
251 {
252 	struct ale_softc *sc = device_get_softc(dev);
253 	struct ifnet *ifp = &sc->arpcom.ac_if;
254 	struct mii_data *mii;
255 	uint32_t reg;
256 
257 	ASSERT_SERIALIZED(ifp->if_serializer);
258 
259 	if ((ifp->if_flags & IFF_RUNNING) == 0)
260 		return;
261 
262 	mii = device_get_softc(sc->ale_miibus);
263 
264 	sc->ale_flags &= ~ALE_FLAG_LINK;
265 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
266 	    (IFM_ACTIVE | IFM_AVALID)) {
267 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
268 		case IFM_10_T:
269 		case IFM_100_TX:
270 			sc->ale_flags |= ALE_FLAG_LINK;
271 			break;
272 
273 		case IFM_1000_T:
274 			if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
275 				sc->ale_flags |= ALE_FLAG_LINK;
276 			break;
277 
278 		default:
279 			break;
280 		}
281 	}
282 
283 	/* Stop Rx/Tx MACs. */
284 	ale_stop_mac(sc);
285 
286 	/* Program MACs with resolved speed/duplex/flow-control. */
287 	if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
288 		ale_mac_config(sc);
289 		/* Reenable Tx/Rx MACs. */
290 		reg = CSR_READ_4(sc, ALE_MAC_CFG);
291 		reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
292 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
293 	}
294 }
295 
296 static void
ale_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)297 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
298 {
299 	struct ale_softc *sc = ifp->if_softc;
300 	struct mii_data *mii = device_get_softc(sc->ale_miibus);
301 
302 	ASSERT_SERIALIZED(ifp->if_serializer);
303 
304 	mii_pollstat(mii);
305 	ifmr->ifm_status = mii->mii_media_status;
306 	ifmr->ifm_active = mii->mii_media_active;
307 }
308 
309 static int
ale_mediachange(struct ifnet * ifp)310 ale_mediachange(struct ifnet *ifp)
311 {
312 	struct ale_softc *sc = ifp->if_softc;
313 	struct mii_data *mii = device_get_softc(sc->ale_miibus);
314 	int error;
315 
316 	ASSERT_SERIALIZED(ifp->if_serializer);
317 
318 	if (mii->mii_instance != 0) {
319 		struct mii_softc *miisc;
320 
321 		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
322 			mii_phy_reset(miisc);
323 	}
324 	error = mii_mediachg(mii);
325 
326 	return (error);
327 }
328 
329 static int
ale_probe(device_t dev)330 ale_probe(device_t dev)
331 {
332 	struct ale_dev *sp;
333 	int i;
334 	uint16_t vendor, devid;
335 
336 	vendor = pci_get_vendor(dev);
337 	devid = pci_get_device(dev);
338 	sp = ale_devs;
339 	for (i = 0; i < NELEM(ale_devs); i++) {
340 		if (vendor == sp->ale_vendorid &&
341 		    devid == sp->ale_deviceid) {
342 			device_set_desc(dev, sp->ale_name);
343 			return (0);
344 		}
345 		sp++;
346 	}
347 
348 	return (ENXIO);
349 }
350 
351 static void
ale_get_macaddr(struct ale_softc * sc)352 ale_get_macaddr(struct ale_softc *sc)
353 {
354 	uint32_t ea[2], reg;
355 	int i, vpdc;
356 
357 	reg = CSR_READ_4(sc, ALE_SPI_CTRL);
358 	if ((reg & SPI_VPD_ENB) != 0) {
359 		reg &= ~SPI_VPD_ENB;
360 		CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
361 	}
362 
363 	vpdc = pci_get_vpdcap_ptr(sc->ale_dev);
364 	if (vpdc) {
365 		/*
366 		 * PCI VPD capability found, let TWSI reload EEPROM.
367 		 * This will set ethernet address of controller.
368 		 */
369 		CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
370 		    TWSI_CTRL_SW_LD_START);
371 		for (i = 100; i > 0; i--) {
372 			DELAY(1000);
373 			reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
374 			if ((reg & TWSI_CTRL_SW_LD_START) == 0)
375 				break;
376 		}
377 		if (i == 0)
378 			device_printf(sc->ale_dev,
379 			    "reloading EEPROM timeout!\n");
380 	} else {
381 		if (bootverbose)
382 			device_printf(sc->ale_dev,
383 			    "PCI VPD capability not found!\n");
384 	}
385 
386 	ea[0] = CSR_READ_4(sc, ALE_PAR0);
387 	ea[1] = CSR_READ_4(sc, ALE_PAR1);
388 	sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
389 	sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
390 	sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
391 	sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
392 	sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
393 	sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
394 }
395 
396 static void
ale_phy_reset(struct ale_softc * sc)397 ale_phy_reset(struct ale_softc *sc)
398 {
399 	/* Reset magic from Linux. */
400 	CSR_WRITE_2(sc, ALE_GPHY_CTRL,
401 	    GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
402 	    GPHY_CTRL_PHY_PLL_ON);
403 	DELAY(1000);
404 	CSR_WRITE_2(sc, ALE_GPHY_CTRL,
405 	    GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
406 	    GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
407 	DELAY(1000);
408 
409 #define	ATPHY_DBG_ADDR		0x1D
410 #define	ATPHY_DBG_DATA		0x1E
411 
412 	/* Enable hibernation mode. */
413 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
414 	    ATPHY_DBG_ADDR, 0x0B);
415 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
416 	    ATPHY_DBG_DATA, 0xBC00);
417 	/* Set Class A/B for all modes. */
418 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
419 	    ATPHY_DBG_ADDR, 0x00);
420 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
421 	    ATPHY_DBG_DATA, 0x02EF);
422 	/* Enable 10BT power saving. */
423 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
424 	    ATPHY_DBG_ADDR, 0x12);
425 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
426 	    ATPHY_DBG_DATA, 0x4C04);
427 	/* Adjust 1000T power. */
428 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
429 	    ATPHY_DBG_ADDR, 0x04);
430 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
431 	    ATPHY_DBG_ADDR, 0x8BBB);
432 	/* 10BT center tap voltage. */
433 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
434 	    ATPHY_DBG_ADDR, 0x05);
435 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
436 	    ATPHY_DBG_ADDR, 0x2C46);
437 
438 #undef	ATPHY_DBG_ADDR
439 #undef	ATPHY_DBG_DATA
440 	DELAY(1000);
441 }
442 
443 static int
ale_attach(device_t dev)444 ale_attach(device_t dev)
445 {
446 	struct ale_softc *sc = device_get_softc(dev);
447 	struct ifnet *ifp = &sc->arpcom.ac_if;
448 	int error = 0;
449 	uint32_t rxf_len, txf_len;
450 	uint8_t pcie_ptr;
451 
452 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
453 	sc->ale_dev = dev;
454 
455 	callout_init(&sc->ale_tick_ch);
456 
457 #ifndef BURN_BRIDGES
458 	if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
459 		uint32_t irq, mem;
460 
461 		irq = pci_read_config(dev, PCIR_INTLINE, 4);
462 		mem = pci_read_config(dev, ALE_PCIR_BAR, 4);
463 
464 		device_printf(dev, "chip is in D%d power mode "
465 		    "-- setting to D0\n", pci_get_powerstate(dev));
466 
467 		pci_set_powerstate(dev, PCI_POWERSTATE_D0);
468 
469 		pci_write_config(dev, PCIR_INTLINE, irq, 4);
470 		pci_write_config(dev, ALE_PCIR_BAR, mem, 4);
471 	}
472 #endif	/* !BURN_BRIDGE */
473 
474 	/* Enable bus mastering */
475 	pci_enable_busmaster(dev);
476 
477 	/*
478 	 * Allocate memory mapped IO
479 	 */
480 	sc->ale_mem_rid = ALE_PCIR_BAR;
481 	sc->ale_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
482 						 &sc->ale_mem_rid, RF_ACTIVE);
483 	if (sc->ale_mem_res == NULL) {
484 		device_printf(dev, "can't allocate IO memory\n");
485 		return ENXIO;
486 	}
487 	sc->ale_mem_bt = rman_get_bustag(sc->ale_mem_res);
488 	sc->ale_mem_bh = rman_get_bushandle(sc->ale_mem_res);
489 
490 	/*
491 	 * Allocate IRQ
492 	 */
493 	sc->ale_irq_rid = 0;
494 	sc->ale_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
495 						 &sc->ale_irq_rid,
496 						 RF_SHAREABLE | RF_ACTIVE);
497 	if (sc->ale_irq_res == NULL) {
498 		device_printf(dev, "can't allocate irq\n");
499 		error = ENXIO;
500 		goto fail;
501 	}
502 
503 	/* Set PHY address. */
504 	sc->ale_phyaddr = ALE_PHY_ADDR;
505 
506 	/* Reset PHY. */
507 	ale_phy_reset(sc);
508 
509 	/* Reset the ethernet controller. */
510 	ale_reset(sc);
511 
512 	/* Get PCI and chip id/revision. */
513 	sc->ale_rev = pci_get_revid(dev);
514 	if (sc->ale_rev >= 0xF0) {
515 		/* L2E Rev. B. AR8114 */
516 		sc->ale_flags |= ALE_FLAG_FASTETHER;
517 	} else {
518 		if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
519 			/* L1E AR8121 */
520 			sc->ale_flags |= ALE_FLAG_JUMBO;
521 		} else {
522 			/* L2E Rev. A. AR8113 */
523 			sc->ale_flags |= ALE_FLAG_FASTETHER;
524 		}
525 	}
526 
527 	/*
528 	 * All known controllers seems to require 4 bytes alignment
529 	 * of Tx buffers to make Tx checksum offload with custom
530 	 * checksum generation method work.
531 	 */
532 	sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
533 
534 	/*
535 	 * All known controllers seems to have issues on Rx checksum
536 	 * offload for fragmented IP datagrams.
537 	 */
538 	sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
539 
540 	/*
541 	 * Don't use Tx CMB. It is known to cause RRS update failure
542 	 * under certain circumstances. Typical phenomenon of the
543 	 * issue would be unexpected sequence number encountered in
544 	 * Rx handler.
545 	 */
546 	sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
547 	sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
548 	    MASTER_CHIP_REV_SHIFT;
549 	if (bootverbose) {
550 		device_printf(dev, "PCI device revision : 0x%04x\n",
551 		    sc->ale_rev);
552 		device_printf(dev, "Chip id/revision : 0x%04x\n",
553 		    sc->ale_chip_rev);
554 	}
555 
556 	/*
557 	 * Uninitialized hardware returns an invalid chip id/revision
558 	 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
559 	 */
560 	txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
561 	rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
562 	if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
563 	    rxf_len == 0xFFFFFFF) {
564 		device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
565 		    "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
566 		    txf_len, rxf_len);
567 		error = ENXIO;
568 		goto fail;
569 	}
570 	device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
571 
572 	/* Get DMA parameters from PCIe device control register. */
573 	pcie_ptr = pci_get_pciecap_ptr(dev);
574 	if (pcie_ptr) {
575 		uint16_t devctl;
576 
577 		sc->ale_flags |= ALE_FLAG_PCIE;
578 		devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
579 		/* Max read request size. */
580 		sc->ale_dma_rd_burst = ((devctl >> 12) & 0x07) <<
581 		    DMA_CFG_RD_BURST_SHIFT;
582 		/* Max payload size. */
583 		sc->ale_dma_wr_burst = ((devctl >> 5) & 0x07) <<
584 		    DMA_CFG_WR_BURST_SHIFT;
585 		if (bootverbose) {
586 			device_printf(dev, "Read request size : %d bytes.\n",
587 			    128 << ((devctl >> 12) & 0x07));
588 			device_printf(dev, "TLP payload size : %d bytes.\n",
589 			    128 << ((devctl >> 5) & 0x07));
590 		}
591 	} else {
592 		sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
593 		sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
594 	}
595 
596 	/* Create device sysctl node. */
597 	ale_sysctl_node(sc);
598 
599 	if ((error = ale_dma_alloc(sc)) != 0)
600 		goto fail;
601 
602 	/* Load station address. */
603 	ale_get_macaddr(sc);
604 
605 	ifp->if_softc = sc;
606 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
607 	ifp->if_ioctl = ale_ioctl;
608 	ifp->if_start = ale_start;
609 	ifp->if_init = ale_init;
610 	ifp->if_watchdog = ale_watchdog;
611 	ifq_set_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1);
612 	ifq_set_ready(&ifp->if_snd);
613 
614 	ifp->if_capabilities = IFCAP_RXCSUM |
615 			       IFCAP_VLAN_MTU |
616 			       IFCAP_VLAN_HWTAGGING;
617 #ifdef notyet
618 	ifp->if_capabilities |= IFCAP_TXCSUM;
619 	ifp->if_hwassist = ALE_CSUM_FEATURES;
620 #endif
621 	ifp->if_capenable = ifp->if_capabilities;
622 
623 	/* Set up MII bus. */
624 	if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
625 	    ale_mediastatus)) != 0) {
626 		device_printf(dev, "no PHY found!\n");
627 		goto fail;
628 	}
629 
630 	ether_ifattach(ifp, sc->ale_eaddr, NULL);
631 
632 	/* Tell the upper layer(s) we support long frames. */
633 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
634 
635 	ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->ale_irq_res));
636 
637 	error = bus_setup_intr(dev, sc->ale_irq_res, INTR_MPSAFE, ale_intr, sc,
638 			       &sc->ale_irq_handle, ifp->if_serializer);
639 	if (error) {
640 		device_printf(dev, "could not set up interrupt handler.\n");
641 		ether_ifdetach(ifp);
642 		goto fail;
643 	}
644 
645 	return 0;
646 fail:
647 	ale_detach(dev);
648 	return (error);
649 }
650 
651 static int
ale_detach(device_t dev)652 ale_detach(device_t dev)
653 {
654 	struct ale_softc *sc = device_get_softc(dev);
655 
656 	if (device_is_attached(dev)) {
657 		struct ifnet *ifp = &sc->arpcom.ac_if;
658 
659 		lwkt_serialize_enter(ifp->if_serializer);
660 		sc->ale_flags |= ALE_FLAG_DETACH;
661 		ale_stop(sc);
662 		bus_teardown_intr(dev, sc->ale_irq_res, sc->ale_irq_handle);
663 		lwkt_serialize_exit(ifp->if_serializer);
664 
665 		ether_ifdetach(ifp);
666 	}
667 
668 	if (sc->ale_miibus != NULL)
669 		device_delete_child(dev, sc->ale_miibus);
670 	bus_generic_detach(dev);
671 
672 	if (sc->ale_irq_res != NULL) {
673 		bus_release_resource(dev, SYS_RES_IRQ, sc->ale_irq_rid,
674 				     sc->ale_irq_res);
675 	}
676 	if (sc->ale_mem_res != NULL) {
677 		bus_release_resource(dev, SYS_RES_MEMORY, sc->ale_mem_rid,
678 				     sc->ale_mem_res);
679 	}
680 
681 	ale_dma_free(sc);
682 
683 	return (0);
684 }
685 
686 #define	ALE_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
687 	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
688 #define	ALE_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
689 	    SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
690 
691 static void
ale_sysctl_node(struct ale_softc * sc)692 ale_sysctl_node(struct ale_softc *sc)
693 {
694 	struct sysctl_ctx_list *ctx;
695 	struct sysctl_oid_list *child, *parent;
696 	struct sysctl_oid *tree;
697 	struct ale_hw_stats *stats;
698 	int error;
699 
700 	stats = &sc->ale_stats;
701 	ctx = device_get_sysctl_ctx(sc->ale_dev);
702 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
703 
704 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
705 	    CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
706 	    sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
707 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
708 	    CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
709 	    sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
710 
711 	/*
712 	 * Pull in device tunables.
713 	 */
714 	sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
715 	error = resource_int_value(device_get_name(sc->ale_dev),
716 	    device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
717 	if (error == 0) {
718 		if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
719 		    sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
720 			device_printf(sc->ale_dev, "int_rx_mod value out of "
721 			    "range; using default: %d\n",
722 			    ALE_IM_RX_TIMER_DEFAULT);
723 			sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
724 		}
725 	}
726 
727 	sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
728 	error = resource_int_value(device_get_name(sc->ale_dev),
729 	    device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
730 	if (error == 0) {
731 		if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
732 		    sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
733 			device_printf(sc->ale_dev, "int_tx_mod value out of "
734 			    "range; using default: %d\n",
735 			    ALE_IM_TX_TIMER_DEFAULT);
736 			sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
737 		}
738 	}
739 
740 	/* Misc statistics. */
741 	ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
742 	    &stats->reset_brk_seq,
743 	    "Controller resets due to broken Rx sequnce number");
744 
745 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
746 	    NULL, "ATE statistics");
747 	parent = SYSCTL_CHILDREN(tree);
748 
749 	/* Rx statistics. */
750 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
751 	    NULL, "Rx MAC statistics");
752 	child = SYSCTL_CHILDREN(tree);
753 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
754 	    &stats->rx_frames, "Good frames");
755 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
756 	    &stats->rx_bcast_frames, "Good broadcast frames");
757 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
758 	    &stats->rx_mcast_frames, "Good multicast frames");
759 	ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
760 	    &stats->rx_pause_frames, "Pause control frames");
761 	ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
762 	    &stats->rx_control_frames, "Control frames");
763 	ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
764 	    &stats->rx_crcerrs, "CRC errors");
765 	ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
766 	    &stats->rx_lenerrs, "Frames with length mismatched");
767 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
768 	    &stats->rx_bytes, "Good octets");
769 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
770 	    &stats->rx_bcast_bytes, "Good broadcast octets");
771 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
772 	    &stats->rx_mcast_bytes, "Good multicast octets");
773 	ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
774 	    &stats->rx_runts, "Too short frames");
775 	ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
776 	    &stats->rx_fragments, "Fragmented frames");
777 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
778 	    &stats->rx_pkts_64, "64 bytes frames");
779 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
780 	    &stats->rx_pkts_65_127, "65 to 127 bytes frames");
781 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
782 	    &stats->rx_pkts_128_255, "128 to 255 bytes frames");
783 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
784 	    &stats->rx_pkts_256_511, "256 to 511 bytes frames");
785 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
786 	    &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
787 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
788 	    &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
789 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
790 	    &stats->rx_pkts_1519_max, "1519 to max frames");
791 	ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
792 	    &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
793 	ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
794 	    &stats->rx_fifo_oflows, "FIFO overflows");
795 	ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
796 	    &stats->rx_rrs_errs, "Return status write-back errors");
797 	ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
798 	    &stats->rx_alignerrs, "Alignment errors");
799 	ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
800 	    &stats->rx_pkts_filtered,
801 	    "Frames dropped due to address filtering");
802 
803 	/* Tx statistics. */
804 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
805 	    NULL, "Tx MAC statistics");
806 	child = SYSCTL_CHILDREN(tree);
807 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
808 	    &stats->tx_frames, "Good frames");
809 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
810 	    &stats->tx_bcast_frames, "Good broadcast frames");
811 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
812 	    &stats->tx_mcast_frames, "Good multicast frames");
813 	ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
814 	    &stats->tx_pause_frames, "Pause control frames");
815 	ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
816 	    &stats->tx_control_frames, "Control frames");
817 	ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
818 	    &stats->tx_excess_defer, "Frames with excessive derferrals");
819 	ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
820 	    &stats->tx_excess_defer, "Frames with derferrals");
821 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
822 	    &stats->tx_bytes, "Good octets");
823 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
824 	    &stats->tx_bcast_bytes, "Good broadcast octets");
825 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
826 	    &stats->tx_mcast_bytes, "Good multicast octets");
827 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
828 	    &stats->tx_pkts_64, "64 bytes frames");
829 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
830 	    &stats->tx_pkts_65_127, "65 to 127 bytes frames");
831 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
832 	    &stats->tx_pkts_128_255, "128 to 255 bytes frames");
833 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
834 	    &stats->tx_pkts_256_511, "256 to 511 bytes frames");
835 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
836 	    &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
837 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
838 	    &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
839 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
840 	    &stats->tx_pkts_1519_max, "1519 to max frames");
841 	ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
842 	    &stats->tx_single_colls, "Single collisions");
843 	ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
844 	    &stats->tx_multi_colls, "Multiple collisions");
845 	ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
846 	    &stats->tx_late_colls, "Late collisions");
847 	ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
848 	    &stats->tx_excess_colls, "Excessive collisions");
849 	ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
850 	    &stats->tx_abort, "Aborted frames due to Excessive collisions");
851 	ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
852 	    &stats->tx_underrun, "FIFO underruns");
853 	ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
854 	    &stats->tx_desc_underrun, "Descriptor write-back errors");
855 	ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
856 	    &stats->tx_lenerrs, "Frames with length mismatched");
857 	ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
858 	    &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
859 }
860 
861 #undef ALE_SYSCTL_STAT_ADD32
862 #undef ALE_SYSCTL_STAT_ADD64
863 
864 struct ale_dmamap_arg {
865 	bus_addr_t	ale_busaddr;
866 };
867 
868 static void
ale_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)869 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
870 {
871 	struct ale_dmamap_arg *ctx;
872 
873 	if (error != 0)
874 		return;
875 
876 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
877 
878 	ctx = (struct ale_dmamap_arg *)arg;
879 	ctx->ale_busaddr = segs[0].ds_addr;
880 }
881 
882 /*
883  * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
884  * which specifies high address region of DMA blocks. Therefore these
885  * blocks should have the same high address of given 4GB address
886  * space(i.e. crossing 4GB boundary is not allowed).
887  */
888 static int
ale_check_boundary(struct ale_softc * sc)889 ale_check_boundary(struct ale_softc *sc)
890 {
891 	bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
892 	bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
893 
894 	rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
895 	    sc->ale_pagesize;
896 	rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
897 	    sc->ale_pagesize;
898 	tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
899 	tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
900 	rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
901 	rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
902 
903 	if ((ALE_ADDR_HI(tx_ring_end) !=
904 	    ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
905 	    (ALE_ADDR_HI(rx_page_end[0]) !=
906 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
907 	    (ALE_ADDR_HI(rx_page_end[1]) !=
908 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
909 	    (ALE_ADDR_HI(tx_cmb_end) !=
910 	    ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
911 	    (ALE_ADDR_HI(rx_cmb_end[0]) !=
912 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
913 	    (ALE_ADDR_HI(rx_cmb_end[1]) !=
914 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
915 		return (EFBIG);
916 
917 	if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
918 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
919 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
920 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
921 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
922 		return (EFBIG);
923 
924 	return (0);
925 }
926 
927 static int
ale_dma_alloc(struct ale_softc * sc)928 ale_dma_alloc(struct ale_softc *sc)
929 {
930 	struct ale_txdesc *txd;
931 	bus_addr_t lowaddr;
932 	struct ale_dmamap_arg ctx;
933 	int error, guard_size, i;
934 
935 	if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
936 		guard_size = ALE_JUMBO_FRAMELEN;
937 	else
938 		guard_size = ALE_MAX_FRAMELEN;
939 	sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
940 	    ALE_RX_PAGE_ALIGN);
941 	lowaddr = BUS_SPACE_MAXADDR;
942 again:
943 	/* Create parent DMA tag. */
944 	error = bus_dma_tag_create(
945 	    NULL,			/* parent */
946 	    1, 0,			/* alignment, boundary */
947 	    lowaddr,			/* lowaddr */
948 	    BUS_SPACE_MAXADDR,		/* highaddr */
949 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
950 	    0,				/* nsegments */
951 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
952 	    0,				/* flags */
953 	    &sc->ale_cdata.ale_parent_tag);
954 	if (error != 0) {
955 		device_printf(sc->ale_dev,
956 		    "could not create parent DMA tag.\n");
957 		goto fail;
958 	}
959 
960 	/* Create DMA tag for Tx descriptor ring. */
961 	error = bus_dma_tag_create(
962 	    sc->ale_cdata.ale_parent_tag, /* parent */
963 	    ALE_TX_RING_ALIGN, 0,	/* alignment, boundary */
964 	    BUS_SPACE_MAXADDR,		/* lowaddr */
965 	    BUS_SPACE_MAXADDR,		/* highaddr */
966 	    ALE_TX_RING_SZ,		/* maxsize */
967 	    1,				/* nsegments */
968 	    ALE_TX_RING_SZ,		/* maxsegsize */
969 	    0,				/* flags */
970 	    &sc->ale_cdata.ale_tx_ring_tag);
971 	if (error != 0) {
972 		device_printf(sc->ale_dev,
973 		    "could not create Tx ring DMA tag.\n");
974 		goto fail;
975 	}
976 
977 	/* Create DMA tag for Rx pages. */
978 	for (i = 0; i < ALE_RX_PAGES; i++) {
979 		error = bus_dma_tag_create(
980 		    sc->ale_cdata.ale_parent_tag, /* parent */
981 		    ALE_RX_PAGE_ALIGN, 0,	/* alignment, boundary */
982 		    BUS_SPACE_MAXADDR,		/* lowaddr */
983 		    BUS_SPACE_MAXADDR,		/* highaddr */
984 		    sc->ale_pagesize,		/* maxsize */
985 		    1,				/* nsegments */
986 		    sc->ale_pagesize,		/* maxsegsize */
987 		    0,				/* flags */
988 		    &sc->ale_cdata.ale_rx_page[i].page_tag);
989 		if (error != 0) {
990 			device_printf(sc->ale_dev,
991 			    "could not create Rx page %d DMA tag.\n", i);
992 			goto fail;
993 		}
994 	}
995 
996 	/* Create DMA tag for Tx coalescing message block. */
997 	error = bus_dma_tag_create(
998 	    sc->ale_cdata.ale_parent_tag, /* parent */
999 	    ALE_CMB_ALIGN, 0,		/* alignment, boundary */
1000 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1001 	    BUS_SPACE_MAXADDR,		/* highaddr */
1002 	    ALE_TX_CMB_SZ,		/* maxsize */
1003 	    1,				/* nsegments */
1004 	    ALE_TX_CMB_SZ,		/* maxsegsize */
1005 	    0,				/* flags */
1006 	    &sc->ale_cdata.ale_tx_cmb_tag);
1007 	if (error != 0) {
1008 		device_printf(sc->ale_dev,
1009 		    "could not create Tx CMB DMA tag.\n");
1010 		goto fail;
1011 	}
1012 
1013 	/* Create DMA tag for Rx coalescing message block. */
1014 	for (i = 0; i < ALE_RX_PAGES; i++) {
1015 		error = bus_dma_tag_create(
1016 		    sc->ale_cdata.ale_parent_tag, /* parent */
1017 		    ALE_CMB_ALIGN, 0,		/* alignment, boundary */
1018 		    BUS_SPACE_MAXADDR,		/* lowaddr */
1019 		    BUS_SPACE_MAXADDR,		/* highaddr */
1020 		    ALE_RX_CMB_SZ,		/* maxsize */
1021 		    1,				/* nsegments */
1022 		    ALE_RX_CMB_SZ,		/* maxsegsize */
1023 		    0,				/* flags */
1024 		    &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1025 		if (error != 0) {
1026 			device_printf(sc->ale_dev,
1027 			    "could not create Rx page %d CMB DMA tag.\n", i);
1028 			goto fail;
1029 		}
1030 	}
1031 
1032 	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
1033 	error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1034 	    (void **)&sc->ale_cdata.ale_tx_ring,
1035 	    BUS_DMA_WAITOK | BUS_DMA_ZERO,
1036 	    &sc->ale_cdata.ale_tx_ring_map);
1037 	if (error != 0) {
1038 		device_printf(sc->ale_dev,
1039 		    "could not allocate DMA'able memory for Tx ring.\n");
1040 		goto fail;
1041 	}
1042 	ctx.ale_busaddr = 0;
1043 	error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1044 	    sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1045 	    ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1046 	if (error != 0 || ctx.ale_busaddr == 0) {
1047 		device_printf(sc->ale_dev,
1048 		    "could not load DMA'able memory for Tx ring.\n");
1049 		goto fail;
1050 	}
1051 	sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1052 
1053 	/* Rx pages. */
1054 	for (i = 0; i < ALE_RX_PAGES; i++) {
1055 		error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1056 		    (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1057 		    BUS_DMA_WAITOK | BUS_DMA_ZERO,
1058 		    &sc->ale_cdata.ale_rx_page[i].page_map);
1059 		if (error != 0) {
1060 			device_printf(sc->ale_dev,
1061 			    "could not allocate DMA'able memory for "
1062 			    "Rx page %d.\n", i);
1063 			goto fail;
1064 		}
1065 		ctx.ale_busaddr = 0;
1066 		error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1067 		    sc->ale_cdata.ale_rx_page[i].page_map,
1068 		    sc->ale_cdata.ale_rx_page[i].page_addr,
1069 		    sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1070 		if (error != 0 || ctx.ale_busaddr == 0) {
1071 			device_printf(sc->ale_dev,
1072 			    "could not load DMA'able memory for "
1073 			    "Rx page %d.\n", i);
1074 			goto fail;
1075 		}
1076 		sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1077 	}
1078 
1079 	/* Tx CMB. */
1080 	error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1081 	    (void **)&sc->ale_cdata.ale_tx_cmb,
1082 	    BUS_DMA_WAITOK | BUS_DMA_ZERO,
1083 	    &sc->ale_cdata.ale_tx_cmb_map);
1084 	if (error != 0) {
1085 		device_printf(sc->ale_dev,
1086 		    "could not allocate DMA'able memory for Tx CMB.\n");
1087 		goto fail;
1088 	}
1089 	ctx.ale_busaddr = 0;
1090 	error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1091 	    sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1092 	    ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1093 	if (error != 0 || ctx.ale_busaddr == 0) {
1094 		device_printf(sc->ale_dev,
1095 		    "could not load DMA'able memory for Tx CMB.\n");
1096 		goto fail;
1097 	}
1098 	sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1099 
1100 	/* Rx CMB. */
1101 	for (i = 0; i < ALE_RX_PAGES; i++) {
1102 		error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1103 		    (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1104 		    BUS_DMA_WAITOK | BUS_DMA_ZERO,
1105 		    &sc->ale_cdata.ale_rx_page[i].cmb_map);
1106 		if (error != 0) {
1107 			device_printf(sc->ale_dev, "could not allocate "
1108 			    "DMA'able memory for Rx page %d CMB.\n", i);
1109 			goto fail;
1110 		}
1111 		ctx.ale_busaddr = 0;
1112 		error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1113 		    sc->ale_cdata.ale_rx_page[i].cmb_map,
1114 		    sc->ale_cdata.ale_rx_page[i].cmb_addr,
1115 		    ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1116 		if (error != 0 || ctx.ale_busaddr == 0) {
1117 			device_printf(sc->ale_dev, "could not load DMA'able "
1118 			    "memory for Rx page %d CMB.\n", i);
1119 			goto fail;
1120 		}
1121 		sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1122 	}
1123 
1124 	/*
1125 	 * Tx descriptors/RXF0/CMB DMA blocks share the same
1126 	 * high address region of 64bit DMA address space.
1127 	 */
1128 	if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1129 	    (error = ale_check_boundary(sc)) != 0) {
1130 		device_printf(sc->ale_dev, "4GB boundary crossed, "
1131 		    "switching to 32bit DMA addressing mode.\n");
1132 		ale_dma_free(sc);
1133 		/*
1134 		 * Limit max allowable DMA address space to 32bit
1135 		 * and try again.
1136 		 */
1137 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1138 		goto again;
1139 	}
1140 
1141 	/*
1142 	 * Create Tx buffer parent tag.
1143 	 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1144 	 * needs separate parent DMA tag as parent DMA address space
1145 	 * could be restricted to be within 32bit address space by
1146 	 * 4GB boundary crossing.
1147 	 */
1148 	error = bus_dma_tag_create(
1149 	    NULL,			/* parent */
1150 	    1, 0,			/* alignment, boundary */
1151 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1152 	    BUS_SPACE_MAXADDR,		/* highaddr */
1153 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1154 	    0,				/* nsegments */
1155 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1156 	    0,				/* flags */
1157 	    &sc->ale_cdata.ale_buffer_tag);
1158 	if (error != 0) {
1159 		device_printf(sc->ale_dev,
1160 		    "could not create parent buffer DMA tag.\n");
1161 		goto fail;
1162 	}
1163 
1164 	/* Create DMA tag for Tx buffers. */
1165 	error = bus_dma_tag_create(
1166 	    sc->ale_cdata.ale_buffer_tag, /* parent */
1167 	    1, 0,			/* alignment, boundary */
1168 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1169 	    BUS_SPACE_MAXADDR,		/* highaddr */
1170 	    ALE_TSO_MAXSIZE,		/* maxsize */
1171 	    ALE_MAXTXSEGS,		/* nsegments */
1172 	    ALE_TSO_MAXSEGSIZE,		/* maxsegsize */
1173 	    0,				/* flags */
1174 	    &sc->ale_cdata.ale_tx_tag);
1175 	if (error != 0) {
1176 		device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1177 		goto fail;
1178 	}
1179 
1180 	/* Create DMA maps for Tx buffers. */
1181 	for (i = 0; i < ALE_TX_RING_CNT; i++) {
1182 		txd = &sc->ale_cdata.ale_txdesc[i];
1183 		txd->tx_m = NULL;
1184 		txd->tx_dmamap = NULL;
1185 		error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1186 		    &txd->tx_dmamap);
1187 		if (error != 0) {
1188 			device_printf(sc->ale_dev,
1189 			    "could not create Tx dmamap.\n");
1190 			goto fail;
1191 		}
1192 	}
1193 fail:
1194 	return (error);
1195 }
1196 
1197 static void
ale_dma_free(struct ale_softc * sc)1198 ale_dma_free(struct ale_softc *sc)
1199 {
1200 	struct ale_txdesc *txd;
1201 	int i;
1202 
1203 	/* Tx buffers. */
1204 	if (sc->ale_cdata.ale_tx_tag != NULL) {
1205 		for (i = 0; i < ALE_TX_RING_CNT; i++) {
1206 			txd = &sc->ale_cdata.ale_txdesc[i];
1207 			if (txd->tx_dmamap != NULL) {
1208 				bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1209 				    txd->tx_dmamap);
1210 				txd->tx_dmamap = NULL;
1211 			}
1212 		}
1213 		bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1214 		sc->ale_cdata.ale_tx_tag = NULL;
1215 	}
1216 	/* Tx descriptor ring. */
1217 	if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1218 		if (sc->ale_cdata.ale_tx_ring_map != NULL)
1219 			bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1220 			    sc->ale_cdata.ale_tx_ring_map);
1221 		if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1222 		    sc->ale_cdata.ale_tx_ring != NULL)
1223 			bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1224 			    sc->ale_cdata.ale_tx_ring,
1225 			    sc->ale_cdata.ale_tx_ring_map);
1226 		sc->ale_cdata.ale_tx_ring = NULL;
1227 		sc->ale_cdata.ale_tx_ring_map = NULL;
1228 		bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1229 		sc->ale_cdata.ale_tx_ring_tag = NULL;
1230 	}
1231 	/* Rx page block. */
1232 	for (i = 0; i < ALE_RX_PAGES; i++) {
1233 		if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1234 			if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1235 				bus_dmamap_unload(
1236 				    sc->ale_cdata.ale_rx_page[i].page_tag,
1237 				    sc->ale_cdata.ale_rx_page[i].page_map);
1238 			if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1239 			    sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1240 				bus_dmamem_free(
1241 				    sc->ale_cdata.ale_rx_page[i].page_tag,
1242 				    sc->ale_cdata.ale_rx_page[i].page_addr,
1243 				    sc->ale_cdata.ale_rx_page[i].page_map);
1244 			sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1245 			sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1246 			bus_dma_tag_destroy(
1247 			    sc->ale_cdata.ale_rx_page[i].page_tag);
1248 			sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1249 		}
1250 	}
1251 	/* Rx CMB. */
1252 	for (i = 0; i < ALE_RX_PAGES; i++) {
1253 		if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1254 			if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1255 				bus_dmamap_unload(
1256 				    sc->ale_cdata.ale_rx_page[i].cmb_tag,
1257 				    sc->ale_cdata.ale_rx_page[i].cmb_map);
1258 			if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1259 			    sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1260 				bus_dmamem_free(
1261 				    sc->ale_cdata.ale_rx_page[i].cmb_tag,
1262 				    sc->ale_cdata.ale_rx_page[i].cmb_addr,
1263 				    sc->ale_cdata.ale_rx_page[i].cmb_map);
1264 			sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1265 			sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1266 			bus_dma_tag_destroy(
1267 			    sc->ale_cdata.ale_rx_page[i].cmb_tag);
1268 			sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1269 		}
1270 	}
1271 	/* Tx CMB. */
1272 	if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1273 		if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1274 			bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1275 			    sc->ale_cdata.ale_tx_cmb_map);
1276 		if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1277 		    sc->ale_cdata.ale_tx_cmb != NULL)
1278 			bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1279 			    sc->ale_cdata.ale_tx_cmb,
1280 			    sc->ale_cdata.ale_tx_cmb_map);
1281 		sc->ale_cdata.ale_tx_cmb = NULL;
1282 		sc->ale_cdata.ale_tx_cmb_map = NULL;
1283 		bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1284 		sc->ale_cdata.ale_tx_cmb_tag = NULL;
1285 	}
1286 	if (sc->ale_cdata.ale_buffer_tag != NULL) {
1287 		bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1288 		sc->ale_cdata.ale_buffer_tag = NULL;
1289 	}
1290 	if (sc->ale_cdata.ale_parent_tag != NULL) {
1291 		bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1292 		sc->ale_cdata.ale_parent_tag = NULL;
1293 	}
1294 }
1295 
1296 static int
ale_shutdown(device_t dev)1297 ale_shutdown(device_t dev)
1298 {
1299 	return (ale_suspend(dev));
1300 }
1301 
1302 #ifdef notyet
1303 
1304 /*
1305  * Note, this driver resets the link speed to 10/100Mbps by
1306  * restarting auto-negotiation in suspend/shutdown phase but we
1307  * don't know whether that auto-negotiation would succeed or not
1308  * as driver has no control after powering off/suspend operation.
1309  * If the renegotiation fail WOL may not work. Running at 1Gbps
1310  * will draw more power than 375mA at 3.3V which is specified in
1311  * PCI specification and that would result in complete
1312  * shutdowning power to ethernet controller.
1313  *
1314  * TODO
1315  * Save current negotiated media speed/duplex/flow-control to
1316  * softc and restore the same link again after resuming. PHY
1317  * handling such as power down/resetting to 100Mbps may be better
1318  * handled in suspend method in phy driver.
1319  */
1320 static void
ale_setlinkspeed(struct ale_softc * sc)1321 ale_setlinkspeed(struct ale_softc *sc)
1322 {
1323 	struct mii_data *mii;
1324 	int aneg, i;
1325 
1326 	mii = device_get_softc(sc->ale_miibus);
1327 	mii_pollstat(mii);
1328 	aneg = 0;
1329 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1330 	    (IFM_ACTIVE | IFM_AVALID)) {
1331 		switch IFM_SUBTYPE(mii->mii_media_active) {
1332 		case IFM_10_T:
1333 		case IFM_100_TX:
1334 			return;
1335 		case IFM_1000_T:
1336 			aneg++;
1337 			break;
1338 		default:
1339 			break;
1340 		}
1341 	}
1342 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1343 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1344 	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1345 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1346 	    MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1347 	DELAY(1000);
1348 	if (aneg != 0) {
1349 		/*
1350 		 * Poll link state until ale(4) get a 10/100Mbps link.
1351 		 */
1352 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1353 			mii_pollstat(mii);
1354 			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1355 			    == (IFM_ACTIVE | IFM_AVALID)) {
1356 				switch (IFM_SUBTYPE(
1357 				    mii->mii_media_active)) {
1358 				case IFM_10_T:
1359 				case IFM_100_TX:
1360 					ale_mac_config(sc);
1361 					return;
1362 				default:
1363 					break;
1364 				}
1365 			}
1366 			ALE_UNLOCK(sc);
1367 			pause("alelnk", hz);
1368 			ALE_LOCK(sc);
1369 		}
1370 		if (i == MII_ANEGTICKS_GIGE)
1371 			device_printf(sc->ale_dev,
1372 			    "establishing a link failed, WOL may not work!");
1373 	}
1374 	/*
1375 	 * No link, force MAC to have 100Mbps, full-duplex link.
1376 	 * This is the last resort and may/may not work.
1377 	 */
1378 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1379 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1380 	ale_mac_config(sc);
1381 }
1382 
1383 static void
ale_setwol(struct ale_softc * sc)1384 ale_setwol(struct ale_softc *sc)
1385 {
1386 	struct ifnet *ifp;
1387 	uint32_t reg, pmcs;
1388 	uint16_t pmstat;
1389 	int pmc;
1390 
1391 	ALE_LOCK_ASSERT(sc);
1392 
1393 	if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1394 		/* Disable WOL. */
1395 		CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1396 		reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1397 		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1398 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1399 		/* Force PHY power down. */
1400 		CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1401 		    GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1402 		    GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1403 		    GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1404 		    GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1405 		return;
1406 	}
1407 
1408 	ifp = sc->ale_ifp;
1409 	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1410 		if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1411 			ale_setlinkspeed(sc);
1412 	}
1413 
1414 	pmcs = 0;
1415 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1416 		pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1417 	CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1418 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1419 	reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1420 	    MAC_CFG_BCAST);
1421 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1422 		reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1423 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1424 		reg |= MAC_CFG_RX_ENB;
1425 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1426 
1427 	if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1428 		/* WOL disabled, PHY power down. */
1429 		reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1430 		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1431 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1432 		CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1433 		    GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1434 		    GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1435 		    GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1436 		    GPHY_CTRL_PWDOWN_HW);
1437 	}
1438 	/* Request PME. */
1439 	pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1440 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1441 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1442 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1443 	pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1444 }
1445 
1446 #endif	/* notyet */
1447 
1448 static int
ale_suspend(device_t dev)1449 ale_suspend(device_t dev)
1450 {
1451 	struct ale_softc *sc = device_get_softc(dev);
1452 	struct ifnet *ifp = &sc->arpcom.ac_if;
1453 
1454 	lwkt_serialize_enter(ifp->if_serializer);
1455 	ale_stop(sc);
1456 #ifdef notyet
1457 	ale_setwol(sc);
1458 #endif
1459 	lwkt_serialize_exit(ifp->if_serializer);
1460 	return (0);
1461 }
1462 
1463 static int
ale_resume(device_t dev)1464 ale_resume(device_t dev)
1465 {
1466 	struct ale_softc *sc = device_get_softc(dev);
1467 	struct ifnet *ifp = &sc->arpcom.ac_if;
1468 	uint16_t cmd;
1469 
1470 	lwkt_serialize_enter(ifp->if_serializer);
1471 
1472 	/*
1473 	 * Clear INTx emulation disable for hardwares that
1474 	 * is set in resume event. From Linux.
1475 	 */
1476 	cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2);
1477 	if ((cmd & 0x0400) != 0) {
1478 		cmd &= ~0x0400;
1479 		pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2);
1480 	}
1481 
1482 #ifdef notyet
1483 	if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1484 		uint16_t pmstat;
1485 		int pmc;
1486 
1487 		/* Disable PME and clear PME status. */
1488 		pmstat = pci_read_config(sc->ale_dev,
1489 		    pmc + PCIR_POWER_STATUS, 2);
1490 		if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1491 			pmstat &= ~PCIM_PSTAT_PMEENABLE;
1492 			pci_write_config(sc->ale_dev,
1493 			    pmc + PCIR_POWER_STATUS, pmstat, 2);
1494 		}
1495 	}
1496 #endif
1497 
1498 	/* Reset PHY. */
1499 	ale_phy_reset(sc);
1500 	if ((ifp->if_flags & IFF_UP) != 0)
1501 		ale_init(sc);
1502 
1503 	lwkt_serialize_exit(ifp->if_serializer);
1504 	return (0);
1505 }
1506 
1507 static int
ale_encap(struct ale_softc * sc,struct mbuf ** m_head)1508 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1509 {
1510 	struct ale_txdesc *txd, *txd_last;
1511 	struct tx_desc *desc;
1512 	struct mbuf *m;
1513 	bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1514 	struct ale_dmamap_ctx ctx;
1515 	bus_dmamap_t map;
1516 	uint32_t cflags, poff, vtag;
1517 	int error, i, nsegs, prod;
1518 
1519 	M_ASSERTPKTHDR((*m_head));
1520 
1521 	m = *m_head;
1522 	cflags = vtag = 0;
1523 	poff = 0;
1524 
1525 	prod = sc->ale_cdata.ale_tx_prod;
1526 	txd = &sc->ale_cdata.ale_txdesc[prod];
1527 	txd_last = txd;
1528 	map = txd->tx_dmamap;
1529 
1530 	ctx.nsegs = ALE_MAXTXSEGS;
1531 	ctx.segs = txsegs;
1532 	error =  bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1533 				      *m_head, ale_dmamap_buf_cb, &ctx,
1534 				      BUS_DMA_NOWAIT);
1535 	if (error == EFBIG) {
1536 		m = m_defrag(*m_head, M_NOWAIT);
1537 		if (m == NULL) {
1538 			m_freem(*m_head);
1539 			*m_head = NULL;
1540 			return (ENOMEM);
1541 		}
1542 		*m_head = m;
1543 
1544 		ctx.nsegs = ALE_MAXTXSEGS;
1545 		ctx.segs = txsegs;
1546 		error =  bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1547 					      *m_head, ale_dmamap_buf_cb, &ctx,
1548 					      BUS_DMA_NOWAIT);
1549 		if (error != 0) {
1550 			m_freem(*m_head);
1551 			*m_head = NULL;
1552 			return (error);
1553 		}
1554 	} else if (error != 0) {
1555 		return (error);
1556 	}
1557 	nsegs = ctx.nsegs;
1558 
1559 	if (nsegs == 0) {
1560 		m_freem(*m_head);
1561 		*m_head = NULL;
1562 		return (EIO);
1563 	}
1564 
1565 	/* Check descriptor overrun. */
1566 	if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) {
1567 		bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1568 		return (ENOBUFS);
1569 	}
1570 	bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1571 
1572 	m = *m_head;
1573 	/* Configure Tx checksum offload. */
1574 	if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1575 		/*
1576 		 * AR81xx supports Tx custom checksum offload feature
1577 		 * that offloads single 16bit checksum computation.
1578 		 * So you can choose one among IP, TCP and UDP.
1579 		 * Normally driver sets checksum start/insertion
1580 		 * position from the information of TCP/UDP frame as
1581 		 * TCP/UDP checksum takes more time than that of IP.
1582 		 * However it seems that custom checksum offload
1583 		 * requires 4 bytes aligned Tx buffers due to hardware
1584 		 * bug.
1585 		 * AR81xx also supports explicit Tx checksum computation
1586 		 * if it is told that the size of IP header and TCP
1587 		 * header(for UDP, the header size does not matter
1588 		 * because it's fixed length). However with this scheme
1589 		 * TSO does not work so you have to choose one either
1590 		 * TSO or explicit Tx checksum offload. I chosen TSO
1591 		 * plus custom checksum offload with work-around which
1592 		 * will cover most common usage for this consumer
1593 		 * ethernet controller. The work-around takes a lot of
1594 		 * CPU cycles if Tx buffer is not aligned on 4 bytes
1595 		 * boundary, though.
1596 		 */
1597 		cflags |= ALE_TD_CXSUM;
1598 		/* Set checksum start offset. */
1599 		cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1600 		/* Set checksum insertion position of TCP/UDP. */
1601 		cflags |= ((poff + m->m_pkthdr.csum_data) <<
1602 		    ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1603 	}
1604 
1605 	/* Configure VLAN hardware tag insertion. */
1606 	if ((m->m_flags & M_VLANTAG) != 0) {
1607 		vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag);
1608 		vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1609 		cflags |= ALE_TD_INSERT_VLAN_TAG;
1610 	}
1611 
1612 	desc = NULL;
1613 	for (i = 0; i < nsegs; i++) {
1614 		desc = &sc->ale_cdata.ale_tx_ring[prod];
1615 		desc->addr = htole64(txsegs[i].ds_addr);
1616 		desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1617 		desc->flags = htole32(cflags);
1618 		sc->ale_cdata.ale_tx_cnt++;
1619 		ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1620 	}
1621 	/* Update producer index. */
1622 	sc->ale_cdata.ale_tx_prod = prod;
1623 
1624 	/* Finally set EOP on the last descriptor. */
1625 	prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1626 	desc = &sc->ale_cdata.ale_tx_ring[prod];
1627 	desc->flags |= htole32(ALE_TD_EOP);
1628 
1629 	/* Swap dmamap of the first and the last. */
1630 	txd = &sc->ale_cdata.ale_txdesc[prod];
1631 	map = txd_last->tx_dmamap;
1632 	txd_last->tx_dmamap = txd->tx_dmamap;
1633 	txd->tx_dmamap = map;
1634 	txd->tx_m = m;
1635 
1636 	/* Sync descriptors. */
1637 	bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1638 	    sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREWRITE);
1639 
1640 	return (0);
1641 }
1642 
1643 static void
ale_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1644 ale_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1645 {
1646         struct ale_softc *sc = ifp->if_softc;
1647 	struct mbuf *m_head;
1648 	int enq;
1649 
1650 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1651 	ASSERT_SERIALIZED(ifp->if_serializer);
1652 
1653 	if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1654 		ifq_purge(&ifp->if_snd);
1655 		return;
1656 	}
1657 
1658 	if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1659 		return;
1660 
1661 	/* Reclaim transmitted frames. */
1662 	if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1663 		ale_txeof(sc);
1664 
1665 	enq = 0;
1666 	while (!ifq_is_empty(&ifp->if_snd)) {
1667 		m_head = ifq_dequeue(&ifp->if_snd);
1668 		if (m_head == NULL)
1669 			break;
1670 
1671 		/*
1672 		 * Pack the data into the transmit ring. If we
1673 		 * don't have room, set the OACTIVE flag and wait
1674 		 * for the NIC to drain the ring.
1675 		 */
1676 		if (ale_encap(sc, &m_head)) {
1677 			if (m_head == NULL)
1678 				break;
1679 			ifq_prepend(&ifp->if_snd, m_head);
1680 			ifq_set_oactive(&ifp->if_snd);
1681 			break;
1682 		}
1683 		enq = 1;
1684 
1685 		/*
1686 		 * If there's a BPF listener, bounce a copy of this frame
1687 		 * to him.
1688 		 */
1689 		ETHER_BPF_MTAP(ifp, m_head);
1690 	}
1691 
1692 	if (enq) {
1693 		/* Kick. */
1694 		CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1695 		    sc->ale_cdata.ale_tx_prod);
1696 
1697 		/* Set a timeout in case the chip goes out to lunch. */
1698 		ifp->if_timer = ALE_TX_TIMEOUT;
1699 	}
1700 }
1701 
1702 static void
ale_watchdog(struct ifnet * ifp)1703 ale_watchdog(struct ifnet *ifp)
1704 {
1705 	struct ale_softc *sc = ifp->if_softc;
1706 
1707 	ASSERT_SERIALIZED(ifp->if_serializer);
1708 
1709 	if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1710 		if_printf(ifp, "watchdog timeout (lost link)\n");
1711 		IFNET_STAT_INC(ifp, oerrors, 1);
1712 		ale_init(sc);
1713 		return;
1714 	}
1715 
1716 	if_printf(ifp, "watchdog timeout -- resetting\n");
1717 	IFNET_STAT_INC(ifp, oerrors, 1);
1718 	ale_init(sc);
1719 
1720 	if (!ifq_is_empty(&ifp->if_snd))
1721 		if_devstart(ifp);
1722 }
1723 
1724 static int
ale_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data,struct ucred * cr)1725 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1726 {
1727 	struct ale_softc *sc;
1728 	struct ifreq *ifr;
1729 	struct mii_data *mii;
1730 	int error, mask;
1731 
1732 	ASSERT_SERIALIZED(ifp->if_serializer);
1733 
1734 	sc = ifp->if_softc;
1735 	ifr = (struct ifreq *)data;
1736 	error = 0;
1737 
1738 	switch (cmd) {
1739 	case SIOCSIFMTU:
1740 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1741 		    ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1742 		    ifr->ifr_mtu > ETHERMTU))
1743 			error = EINVAL;
1744 		else if (ifp->if_mtu != ifr->ifr_mtu) {
1745 			ifp->if_mtu = ifr->ifr_mtu;
1746 			if ((ifp->if_flags & IFF_RUNNING) != 0)
1747 				ale_init(sc);
1748 		}
1749 		break;
1750 
1751 	case SIOCSIFFLAGS:
1752 		if ((ifp->if_flags & IFF_UP) != 0) {
1753 			if ((ifp->if_flags & IFF_RUNNING) != 0) {
1754 				if (((ifp->if_flags ^ sc->ale_if_flags)
1755 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1756 					ale_rxfilter(sc);
1757 			} else {
1758 				if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1759 					ale_init(sc);
1760 			}
1761 		} else {
1762 			if ((ifp->if_flags & IFF_RUNNING) != 0)
1763 				ale_stop(sc);
1764 		}
1765 		sc->ale_if_flags = ifp->if_flags;
1766 		break;
1767 
1768 	case SIOCADDMULTI:
1769 	case SIOCDELMULTI:
1770 		if ((ifp->if_flags & IFF_RUNNING) != 0)
1771 			ale_rxfilter(sc);
1772 		break;
1773 
1774 	case SIOCSIFMEDIA:
1775 	case SIOCGIFMEDIA:
1776 		mii = device_get_softc(sc->ale_miibus);
1777 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1778 		break;
1779 
1780 	case SIOCSIFCAP:
1781 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1782 		if ((mask & IFCAP_TXCSUM) != 0 &&
1783 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1784 			ifp->if_capenable ^= IFCAP_TXCSUM;
1785 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1786 				ifp->if_hwassist |= ALE_CSUM_FEATURES;
1787 			else
1788 				ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
1789 		}
1790 		if ((mask & IFCAP_RXCSUM) != 0 &&
1791 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1792 			ifp->if_capenable ^= IFCAP_RXCSUM;
1793 
1794 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1795 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1796 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1797 			ale_rxvlan(sc);
1798 		}
1799 		break;
1800 
1801 	default:
1802 		error = ether_ioctl(ifp, cmd, data);
1803 		break;
1804 	}
1805 	return (error);
1806 }
1807 
1808 static void
ale_mac_config(struct ale_softc * sc)1809 ale_mac_config(struct ale_softc *sc)
1810 {
1811 	struct mii_data *mii;
1812 	uint32_t reg;
1813 
1814 	mii = device_get_softc(sc->ale_miibus);
1815 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1816 	reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
1817 	    MAC_CFG_SPEED_MASK);
1818 	/* Reprogram MAC with resolved speed/duplex. */
1819 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1820 	case IFM_10_T:
1821 	case IFM_100_TX:
1822 		reg |= MAC_CFG_SPEED_10_100;
1823 		break;
1824 	case IFM_1000_T:
1825 		reg |= MAC_CFG_SPEED_1000;
1826 		break;
1827 	}
1828 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1829 		reg |= MAC_CFG_FULL_DUPLEX;
1830 #ifdef notyet
1831 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1832 			reg |= MAC_CFG_TX_FC;
1833 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1834 			reg |= MAC_CFG_RX_FC;
1835 #endif
1836 	}
1837 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1838 }
1839 
1840 static void
ale_stats_clear(struct ale_softc * sc)1841 ale_stats_clear(struct ale_softc *sc)
1842 {
1843 	struct smb sb;
1844 	uint32_t *reg;
1845 	int i;
1846 
1847 	for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1848 		CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1849 		i += sizeof(uint32_t);
1850 	}
1851 	/* Read Tx statistics. */
1852 	for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1853 		CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1854 		i += sizeof(uint32_t);
1855 	}
1856 }
1857 
1858 static void
ale_stats_update(struct ale_softc * sc)1859 ale_stats_update(struct ale_softc *sc)
1860 {
1861 	struct ale_hw_stats *stat;
1862 	struct smb sb, *smb;
1863 	struct ifnet *ifp;
1864 	uint32_t *reg;
1865 	int i;
1866 
1867 	ifp = &sc->arpcom.ac_if;
1868 	stat = &sc->ale_stats;
1869 	smb = &sb;
1870 
1871 	/* Read Rx statistics. */
1872 	for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1873 		*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1874 		i += sizeof(uint32_t);
1875 	}
1876 	/* Read Tx statistics. */
1877 	for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1878 		*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1879 		i += sizeof(uint32_t);
1880 	}
1881 
1882 	/* Rx stats. */
1883 	stat->rx_frames += smb->rx_frames;
1884 	stat->rx_bcast_frames += smb->rx_bcast_frames;
1885 	stat->rx_mcast_frames += smb->rx_mcast_frames;
1886 	stat->rx_pause_frames += smb->rx_pause_frames;
1887 	stat->rx_control_frames += smb->rx_control_frames;
1888 	stat->rx_crcerrs += smb->rx_crcerrs;
1889 	stat->rx_lenerrs += smb->rx_lenerrs;
1890 	stat->rx_bytes += smb->rx_bytes;
1891 	stat->rx_runts += smb->rx_runts;
1892 	stat->rx_fragments += smb->rx_fragments;
1893 	stat->rx_pkts_64 += smb->rx_pkts_64;
1894 	stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
1895 	stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
1896 	stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
1897 	stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
1898 	stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
1899 	stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
1900 	stat->rx_pkts_truncated += smb->rx_pkts_truncated;
1901 	stat->rx_fifo_oflows += smb->rx_fifo_oflows;
1902 	stat->rx_rrs_errs += smb->rx_rrs_errs;
1903 	stat->rx_alignerrs += smb->rx_alignerrs;
1904 	stat->rx_bcast_bytes += smb->rx_bcast_bytes;
1905 	stat->rx_mcast_bytes += smb->rx_mcast_bytes;
1906 	stat->rx_pkts_filtered += smb->rx_pkts_filtered;
1907 
1908 	/* Tx stats. */
1909 	stat->tx_frames += smb->tx_frames;
1910 	stat->tx_bcast_frames += smb->tx_bcast_frames;
1911 	stat->tx_mcast_frames += smb->tx_mcast_frames;
1912 	stat->tx_pause_frames += smb->tx_pause_frames;
1913 	stat->tx_excess_defer += smb->tx_excess_defer;
1914 	stat->tx_control_frames += smb->tx_control_frames;
1915 	stat->tx_deferred += smb->tx_deferred;
1916 	stat->tx_bytes += smb->tx_bytes;
1917 	stat->tx_pkts_64 += smb->tx_pkts_64;
1918 	stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
1919 	stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
1920 	stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
1921 	stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
1922 	stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
1923 	stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
1924 	stat->tx_single_colls += smb->tx_single_colls;
1925 	stat->tx_multi_colls += smb->tx_multi_colls;
1926 	stat->tx_late_colls += smb->tx_late_colls;
1927 	stat->tx_excess_colls += smb->tx_excess_colls;
1928 	stat->tx_abort += smb->tx_abort;
1929 	stat->tx_underrun += smb->tx_underrun;
1930 	stat->tx_desc_underrun += smb->tx_desc_underrun;
1931 	stat->tx_lenerrs += smb->tx_lenerrs;
1932 	stat->tx_pkts_truncated += smb->tx_pkts_truncated;
1933 	stat->tx_bcast_bytes += smb->tx_bcast_bytes;
1934 	stat->tx_mcast_bytes += smb->tx_mcast_bytes;
1935 
1936 	/* Update counters in ifnet. */
1937 	IFNET_STAT_INC(ifp, opackets, smb->tx_frames);
1938 
1939 	IFNET_STAT_INC(ifp, collisions, smb->tx_single_colls +
1940 	    smb->tx_multi_colls * 2 + smb->tx_late_colls +
1941 	    smb->tx_abort * HDPX_CFG_RETRY_DEFAULT);
1942 
1943 	/*
1944 	 * XXX
1945 	 * tx_pkts_truncated counter looks suspicious. It constantly
1946 	 * increments with no sign of Tx errors. This may indicate
1947 	 * the counter name is not correct one so I've removed the
1948 	 * counter in output errors.
1949 	 */
1950 	IFNET_STAT_INC(ifp, oerrors, smb->tx_abort + smb->tx_late_colls +
1951 	    smb->tx_underrun);
1952 
1953 	IFNET_STAT_INC(ifp, ipackets, smb->rx_frames);
1954 
1955 	IFNET_STAT_INC(ifp, ierrors, smb->rx_crcerrs + smb->rx_lenerrs +
1956 	    smb->rx_runts + smb->rx_pkts_truncated +
1957 	    smb->rx_fifo_oflows + smb->rx_rrs_errs +
1958 	    smb->rx_alignerrs);
1959 }
1960 
1961 static void
ale_intr(void * xsc)1962 ale_intr(void *xsc)
1963 {
1964 	struct ale_softc *sc = xsc;
1965 	struct ifnet *ifp = &sc->arpcom.ac_if;
1966 	uint32_t status;
1967 
1968 	ASSERT_SERIALIZED(ifp->if_serializer);
1969 
1970 	status = CSR_READ_4(sc, ALE_INTR_STATUS);
1971 	if ((status & ALE_INTRS) == 0)
1972 		return;
1973 
1974 	/* Acknowledge and disable interrupts. */
1975 	CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1976 
1977 	if ((ifp->if_flags & IFF_RUNNING) != 0) {
1978 		int error;
1979 
1980 		error = ale_rxeof(sc);
1981 		if (error) {
1982 			sc->ale_stats.reset_brk_seq++;
1983 			ale_init(sc);
1984 			return;
1985 		}
1986 
1987 		if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
1988 			if ((status & INTR_DMA_RD_TO_RST) != 0)
1989 				device_printf(sc->ale_dev,
1990 				    "DMA read error! -- resetting\n");
1991 			if ((status & INTR_DMA_WR_TO_RST) != 0)
1992 				device_printf(sc->ale_dev,
1993 				    "DMA write error! -- resetting\n");
1994 			ale_init(sc);
1995 			return;
1996 		}
1997 
1998 		ale_txeof(sc);
1999 		if (!ifq_is_empty(&ifp->if_snd))
2000 			if_devstart(ifp);
2001 	}
2002 
2003 	/* Re-enable interrupts. */
2004 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2005 }
2006 
2007 static void
ale_txeof(struct ale_softc * sc)2008 ale_txeof(struct ale_softc *sc)
2009 {
2010 	struct ifnet *ifp = &sc->arpcom.ac_if;
2011 	struct ale_txdesc *txd;
2012 	uint32_t cons, prod;
2013 	int prog;
2014 
2015 	if (sc->ale_cdata.ale_tx_cnt == 0)
2016 		return;
2017 
2018 	bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2019 	    sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD);
2020 	if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2021 		bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2022 		    sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD);
2023 		prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2024 	} else
2025 		prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2026 	cons = sc->ale_cdata.ale_tx_cons;
2027 	/*
2028 	 * Go through our Tx list and free mbufs for those
2029 	 * frames which have been transmitted.
2030 	 */
2031 	for (prog = 0; cons != prod; prog++,
2032 	     ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2033 		if (sc->ale_cdata.ale_tx_cnt <= 0)
2034 			break;
2035 		prog++;
2036 		ifq_clr_oactive(&ifp->if_snd);
2037 		sc->ale_cdata.ale_tx_cnt--;
2038 		txd = &sc->ale_cdata.ale_txdesc[cons];
2039 		if (txd->tx_m != NULL) {
2040 			/* Reclaim transmitted mbufs. */
2041 			bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2042 			    txd->tx_dmamap);
2043 			m_freem(txd->tx_m);
2044 			txd->tx_m = NULL;
2045 		}
2046 	}
2047 
2048 	if (prog > 0) {
2049 		sc->ale_cdata.ale_tx_cons = cons;
2050 		/*
2051 		 * Unarm watchdog timer only when there is no pending
2052 		 * Tx descriptors in queue.
2053 		 */
2054 		if (sc->ale_cdata.ale_tx_cnt == 0)
2055 			ifp->if_timer = 0;
2056 	}
2057 }
2058 
2059 static void
ale_rx_update_page(struct ale_softc * sc,struct ale_rx_page ** page,uint32_t length,uint32_t * prod)2060 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2061     uint32_t length, uint32_t *prod)
2062 {
2063 	struct ale_rx_page *rx_page;
2064 
2065 	rx_page = *page;
2066 	/* Update consumer position. */
2067 	rx_page->cons += roundup(length + sizeof(struct rx_rs),
2068 	    ALE_RX_PAGE_ALIGN);
2069 	if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2070 		/*
2071 		 * End of Rx page reached, let hardware reuse
2072 		 * this page.
2073 		 */
2074 		rx_page->cons = 0;
2075 		*rx_page->cmb_addr = 0;
2076 		bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2077 				BUS_DMASYNC_PREWRITE);
2078 		CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2079 		    RXF_VALID);
2080 		/* Switch to alternate Rx page. */
2081 		sc->ale_cdata.ale_rx_curp ^= 1;
2082 		rx_page = *page =
2083 		    &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2084 		/* Page flipped, sync CMB and Rx page. */
2085 		bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2086 		    BUS_DMASYNC_POSTREAD);
2087 		bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2088 		    BUS_DMASYNC_POSTREAD);
2089 		/* Sync completed, cache updated producer index. */
2090 		*prod = *rx_page->cmb_addr;
2091 	}
2092 }
2093 
2094 
2095 /*
2096  * It seems that AR81xx controller can compute partial checksum.
2097  * The partial checksum value can be used to accelerate checksum
2098  * computation for fragmented TCP/UDP packets. Upper network stack
2099  * already takes advantage of the partial checksum value in IP
2100  * reassembly stage. But I'm not sure the correctness of the
2101  * partial hardware checksum assistance due to lack of data sheet.
2102  * In addition, the Rx feature of controller that requires copying
2103  * for every frames effectively nullifies one of most nice offload
2104  * capability of controller.
2105  */
2106 static void
ale_rxcsum(struct ale_softc * sc,struct mbuf * m,uint32_t status)2107 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2108 {
2109 	struct ifnet *ifp = &sc->arpcom.ac_if;
2110 	struct ip *ip;
2111 	char *p;
2112 
2113 	m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2114 	if ((status & ALE_RD_IPCSUM_NOK) == 0)
2115 		m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2116 
2117 	if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2118 		if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2119 		    ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2120 		    ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2121 			m->m_pkthdr.csum_flags |=
2122 			    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2123 			m->m_pkthdr.csum_data = 0xffff;
2124 		}
2125 	} else {
2126 		if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2127 		    (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2128 			p = mtod(m, char *);
2129 			p += ETHER_HDR_LEN;
2130 			if ((status & ALE_RD_802_3) != 0)
2131 				p += LLC_SNAPFRAMELEN;
2132 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2133 			    (status & ALE_RD_VLAN) != 0)
2134 				p += EVL_ENCAPLEN;
2135 			ip = (struct ip *)p;
2136 			if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2137 				return;
2138 			m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2139 			    CSUM_PSEUDO_HDR;
2140 			m->m_pkthdr.csum_data = 0xffff;
2141 		}
2142 	}
2143 	/*
2144 	 * Don't mark bad checksum for TCP/UDP frames
2145 	 * as fragmented frames may always have set
2146 	 * bad checksummed bit of frame status.
2147 	 */
2148 }
2149 
2150 /* Process received frames. */
2151 static int
ale_rxeof(struct ale_softc * sc)2152 ale_rxeof(struct ale_softc *sc)
2153 {
2154 	struct ifnet *ifp = &sc->arpcom.ac_if;
2155 	struct ale_rx_page *rx_page;
2156 	struct rx_rs *rs;
2157 	struct mbuf *m;
2158 	uint32_t length, prod, seqno, status, vtags;
2159 	int prog;
2160 
2161 	rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2162 	bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2163 			BUS_DMASYNC_POSTREAD);
2164 	bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2165 			BUS_DMASYNC_POSTREAD);
2166 	/*
2167 	 * Don't directly access producer index as hardware may
2168 	 * update it while Rx handler is in progress. It would
2169 	 * be even better if there is a way to let hardware
2170 	 * know how far driver processed its received frames.
2171 	 * Alternatively, hardware could provide a way to disable
2172 	 * CMB updates until driver acknowledges the end of CMB
2173 	 * access.
2174 	 */
2175 	prod = *rx_page->cmb_addr;
2176 	for (prog = 0; ; prog++) {
2177 		if (rx_page->cons >= prod)
2178 			break;
2179 		rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2180 		seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2181 		if (sc->ale_cdata.ale_rx_seqno != seqno) {
2182 			/*
2183 			 * Normally I believe this should not happen unless
2184 			 * severe driver bug or corrupted memory. However
2185 			 * it seems to happen under certain conditions which
2186 			 * is triggered by abrupt Rx events such as initiation
2187 			 * of bulk transfer of remote host. It's not easy to
2188 			 * reproduce this and I doubt it could be related
2189 			 * with FIFO overflow of hardware or activity of Tx
2190 			 * CMB updates. I also remember similar behaviour
2191 			 * seen on RealTek 8139 which uses resembling Rx
2192 			 * scheme.
2193 			 */
2194 			if (bootverbose)
2195 				device_printf(sc->ale_dev,
2196 				    "garbled seq: %u, expected: %u -- "
2197 				    "resetting!\n", seqno,
2198 				    sc->ale_cdata.ale_rx_seqno);
2199 			return (EIO);
2200 		}
2201 		/* Frame received. */
2202 		sc->ale_cdata.ale_rx_seqno++;
2203 		length = ALE_RX_BYTES(le32toh(rs->length));
2204 		status = le32toh(rs->flags);
2205 		if ((status & ALE_RD_ERROR) != 0) {
2206 			/*
2207 			 * We want to pass the following frames to upper
2208 			 * layer regardless of error status of Rx return
2209 			 * status.
2210 			 *
2211 			 *  o IP/TCP/UDP checksum is bad.
2212 			 *  o frame length and protocol specific length
2213 			 *     does not match.
2214 			 */
2215 			if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2216 			    ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2217 			    ALE_RD_TRUNC)) != 0) {
2218 				ale_rx_update_page(sc, &rx_page, length, &prod);
2219 				continue;
2220 			}
2221 		}
2222 		/*
2223 		 * m_devget(9) is major bottle-neck of ale(4) (It comes
2224 		 * from hardware limitation). For jumbo frames we could
2225 		 * get a slightly better performance if driver use
2226 		 * m_getjcl(9) with proper buffer size argument. However
2227 		 * that would make code more complicated and I don't
2228 		 * think users would expect good Rx performance numbers
2229 		 * on these low-end consumer ethernet controller.
2230 		 */
2231 		m = m_devget(rs + 1, length - ETHER_CRC_LEN, 0, ifp);
2232 		if (m == NULL) {
2233 			IFNET_STAT_INC(ifp, iqdrops, 1);
2234 			ale_rx_update_page(sc, &rx_page, length, &prod);
2235 			continue;
2236 		}
2237 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2238 		    (status & ALE_RD_IPV4) != 0)
2239 			ale_rxcsum(sc, m, status);
2240 		if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2241 		    (status & ALE_RD_VLAN) != 0) {
2242 			vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2243 			m->m_pkthdr.ether_vlantag = ALE_RX_VLAN_TAG(vtags);
2244 			m->m_flags |= M_VLANTAG;
2245 		}
2246 
2247 		/* Pass it to upper layer. */
2248 		ifp->if_input(ifp, m, NULL, -1);
2249 
2250 		ale_rx_update_page(sc, &rx_page, length, &prod);
2251 	}
2252 	return 0;
2253 }
2254 
2255 static void
ale_tick(void * xsc)2256 ale_tick(void *xsc)
2257 {
2258 	struct ale_softc *sc = xsc;
2259 	struct ifnet *ifp = &sc->arpcom.ac_if;
2260 	struct mii_data *mii;
2261 
2262 	lwkt_serialize_enter(ifp->if_serializer);
2263 
2264 	mii = device_get_softc(sc->ale_miibus);
2265 	mii_tick(mii);
2266 	ale_stats_update(sc);
2267 
2268 	callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2269 
2270 	lwkt_serialize_exit(ifp->if_serializer);
2271 }
2272 
2273 static void
ale_reset(struct ale_softc * sc)2274 ale_reset(struct ale_softc *sc)
2275 {
2276 	uint32_t reg;
2277 	int i;
2278 
2279 	/* Initialize PCIe module. From Linux. */
2280 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2281 
2282 	CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2283 	for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2284 		DELAY(10);
2285 		if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2286 			break;
2287 	}
2288 	if (i == 0)
2289 		device_printf(sc->ale_dev, "master reset timeout!\n");
2290 
2291 	for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2292 		if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2293 			break;
2294 		DELAY(10);
2295 	}
2296 
2297 	if (i == 0)
2298 		device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2299 }
2300 
2301 static void
ale_init(void * xsc)2302 ale_init(void *xsc)
2303 {
2304 	struct ale_softc *sc = xsc;
2305 	struct ifnet *ifp = &sc->arpcom.ac_if;
2306 	struct mii_data *mii;
2307 	uint8_t eaddr[ETHER_ADDR_LEN];
2308 	bus_addr_t paddr;
2309 	uint32_t reg, rxf_hi, rxf_lo;
2310 
2311 	ASSERT_SERIALIZED(ifp->if_serializer);
2312 
2313 	mii = device_get_softc(sc->ale_miibus);
2314 
2315 	/*
2316 	 * Cancel any pending I/O.
2317 	 */
2318 	ale_stop(sc);
2319 
2320 	/*
2321 	 * Reset the chip to a known state.
2322 	 */
2323 	ale_reset(sc);
2324 
2325 	/* Initialize Tx descriptors, DMA memory blocks. */
2326 	ale_init_rx_pages(sc);
2327 	ale_init_tx_ring(sc);
2328 
2329 	/* Reprogram the station address. */
2330 	bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2331 	CSR_WRITE_4(sc, ALE_PAR0,
2332 	    eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2333 	CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2334 
2335 	/*
2336 	 * Clear WOL status and disable all WOL feature as WOL
2337 	 * would interfere Rx operation under normal environments.
2338 	 */
2339 	CSR_READ_4(sc, ALE_WOL_CFG);
2340 	CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2341 
2342 	/*
2343 	 * Set Tx descriptor/RXF0/CMB base addresses. They share
2344 	 * the same high address part of DMAable region.
2345 	 */
2346 	paddr = sc->ale_cdata.ale_tx_ring_paddr;
2347 	CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2348 	CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2349 	CSR_WRITE_4(sc, ALE_TPD_CNT,
2350 	    (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2351 
2352 	/* Set Rx page base address, note we use single queue. */
2353 	paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2354 	CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2355 	paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2356 	CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2357 
2358 	/* Set Tx/Rx CMB addresses. */
2359 	paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2360 	CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2361 	paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2362 	CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2363 	paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2364 	CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2365 
2366 	/* Mark RXF0 is valid. */
2367 	CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2368 	CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2369 	/*
2370 	 * No need to initialize RFX1/RXF2/RXF3. We don't use
2371 	 * multi-queue yet.
2372 	 */
2373 
2374 	/* Set Rx page size, excluding guard frame size. */
2375 	CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2376 
2377 	/* Tell hardware that we're ready to load DMA blocks. */
2378 	CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2379 
2380 	/* Set Rx/Tx interrupt trigger threshold. */
2381 	CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2382 	    (4 << INT_TRIG_TX_THRESH_SHIFT));
2383 	/*
2384 	 * XXX
2385 	 * Set interrupt trigger timer, its purpose and relation
2386 	 * with interrupt moderation mechanism is not clear yet.
2387 	 */
2388 	CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2389 	    ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2390 	    (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2391 
2392 	/* Configure interrupt moderation timer. */
2393 	reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2394 	reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2395 	CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2396 	reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2397 	reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2398 	reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2399 	if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2400 		reg |= MASTER_IM_RX_TIMER_ENB;
2401 	if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2402 		reg |= MASTER_IM_TX_TIMER_ENB;
2403 	CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2404 	CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2405 
2406 	/* Set Maximum frame size of controller. */
2407 	if (ifp->if_mtu < ETHERMTU)
2408 		sc->ale_max_frame_size = ETHERMTU;
2409 	else
2410 		sc->ale_max_frame_size = ifp->if_mtu;
2411 	sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN;
2412 	CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2413 
2414 	/* Configure IPG/IFG parameters. */
2415 	CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2416 	    ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2417 	    ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2418 	    ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2419 	    ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2420 
2421 	/* Set parameters for half-duplex media. */
2422 	CSR_WRITE_4(sc, ALE_HDPX_CFG,
2423 	    ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2424 	    HDPX_CFG_LCOL_MASK) |
2425 	    ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2426 	    HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2427 	    ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2428 	    HDPX_CFG_ABEBT_MASK) |
2429 	    ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2430 	    HDPX_CFG_JAMIPG_MASK));
2431 
2432 	/* Configure Tx jumbo frame parameters. */
2433 	if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2434 		if (ifp->if_mtu < ETHERMTU)
2435 			reg = sc->ale_max_frame_size;
2436 		else if (ifp->if_mtu < 6 * 1024)
2437 			reg = (sc->ale_max_frame_size * 2) / 3;
2438 		else
2439 			reg = sc->ale_max_frame_size / 2;
2440 		CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2441 		    roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2442 		    TX_JUMBO_THRESH_UNIT_SHIFT);
2443 	}
2444 
2445 	/* Configure TxQ. */
2446 	reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2447 	    << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2448 	reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2449 	    TXQ_CFG_TPD_BURST_MASK;
2450 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2451 
2452 	/* Configure Rx jumbo frame & flow control parameters. */
2453 	if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2454 		reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2455 		CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2456 		    (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2457 		    RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2458 		    ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2459 		    RX_JUMBO_LKAH_MASK));
2460 		reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2461 		rxf_hi = (reg * 7) / 10;
2462 		rxf_lo = (reg * 3)/ 10;
2463 		CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2464 		    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2465 		    RX_FIFO_PAUSE_THRESH_LO_MASK) |
2466 		    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2467 		     RX_FIFO_PAUSE_THRESH_HI_MASK));
2468 	}
2469 
2470 	/* Disable RSS. */
2471 	CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2472 	CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2473 
2474 	/* Configure RxQ. */
2475 	CSR_WRITE_4(sc, ALE_RXQ_CFG,
2476 	    RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2477 
2478 	/* Configure DMA parameters. */
2479 	reg = 0;
2480 	if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2481 		reg |= DMA_CFG_TXCMB_ENB;
2482 	CSR_WRITE_4(sc, ALE_DMA_CFG,
2483 	    DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2484 	    sc->ale_dma_rd_burst | reg |
2485 	    sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2486 	    ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2487 	    DMA_CFG_RD_DELAY_CNT_MASK) |
2488 	    ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2489 	    DMA_CFG_WR_DELAY_CNT_MASK));
2490 
2491 	/*
2492 	 * Hardware can be configured to issue SMB interrupt based
2493 	 * on programmed interval. Since there is a callout that is
2494 	 * invoked for every hz in driver we use that instead of
2495 	 * relying on periodic SMB interrupt.
2496 	 */
2497 	CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2498 
2499 	/* Clear MAC statistics. */
2500 	ale_stats_clear(sc);
2501 
2502 	/*
2503 	 * Configure Tx/Rx MACs.
2504 	 *  - Auto-padding for short frames.
2505 	 *  - Enable CRC generation.
2506 	 *  Actual reconfiguration of MAC for resolved speed/duplex
2507 	 *  is followed after detection of link establishment.
2508 	 *  AR81xx always does checksum computation regardless of
2509 	 *  MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2510 	 *  cause Rx handling issue for fragmented IP datagrams due
2511 	 *  to silicon bug.
2512 	 */
2513 	reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2514 	    ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2515 	    MAC_CFG_PREAMBLE_MASK);
2516 	if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2517 		reg |= MAC_CFG_SPEED_10_100;
2518 	else
2519 		reg |= MAC_CFG_SPEED_1000;
2520 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2521 
2522 	/* Set up the receive filter. */
2523 	ale_rxfilter(sc);
2524 	ale_rxvlan(sc);
2525 
2526 	/* Acknowledge all pending interrupts and clear it. */
2527 	CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2528 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2529 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2530 
2531 	sc->ale_flags &= ~ALE_FLAG_LINK;
2532 
2533 	/* Switch to the current media. */
2534 	mii_mediachg(mii);
2535 
2536 	callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2537 
2538 	ifp->if_flags |= IFF_RUNNING;
2539 	ifq_clr_oactive(&ifp->if_snd);
2540 }
2541 
2542 static void
ale_stop(struct ale_softc * sc)2543 ale_stop(struct ale_softc *sc)
2544 {
2545 	struct ifnet *ifp = &sc->arpcom.ac_if;
2546 	struct ale_txdesc *txd;
2547 	uint32_t reg;
2548 	int i;
2549 
2550 	ASSERT_SERIALIZED(ifp->if_serializer);
2551 
2552 	/*
2553 	 * Mark the interface down and cancel the watchdog timer.
2554 	 */
2555 	ifp->if_flags &= ~IFF_RUNNING;
2556 	ifq_clr_oactive(&ifp->if_snd);
2557 	ifp->if_timer = 0;
2558 
2559 	callout_stop(&sc->ale_tick_ch);
2560 	sc->ale_flags &= ~ALE_FLAG_LINK;
2561 
2562 	ale_stats_update(sc);
2563 
2564 	/* Disable interrupts. */
2565 	CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2566 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2567 
2568 	/* Disable queue processing and DMA. */
2569 	reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2570 	reg &= ~TXQ_CFG_ENB;
2571 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2572 	reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2573 	reg &= ~RXQ_CFG_ENB;
2574 	CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2575 	reg = CSR_READ_4(sc, ALE_DMA_CFG);
2576 	reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2577 	CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2578 	DELAY(1000);
2579 
2580 	/* Stop Rx/Tx MACs. */
2581 	ale_stop_mac(sc);
2582 
2583 	/* Disable interrupts again? XXX */
2584 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2585 
2586 	/*
2587 	 * Free TX mbufs still in the queues.
2588 	 */
2589 	for (i = 0; i < ALE_TX_RING_CNT; i++) {
2590 		txd = &sc->ale_cdata.ale_txdesc[i];
2591 		if (txd->tx_m != NULL) {
2592 			bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2593 			    txd->tx_dmamap);
2594 			m_freem(txd->tx_m);
2595 			txd->tx_m = NULL;
2596 		}
2597         }
2598 }
2599 
2600 static void
ale_stop_mac(struct ale_softc * sc)2601 ale_stop_mac(struct ale_softc *sc)
2602 {
2603 	uint32_t reg;
2604 	int i;
2605 
2606 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2607 	if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2608 		reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2609 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2610 	}
2611 
2612 	for (i = ALE_TIMEOUT; i > 0; i--) {
2613 		reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2614 		if (reg == 0)
2615 			break;
2616 		DELAY(10);
2617 	}
2618 	if (i == 0)
2619 		device_printf(sc->ale_dev,
2620 		    "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2621 }
2622 
2623 static void
ale_init_tx_ring(struct ale_softc * sc)2624 ale_init_tx_ring(struct ale_softc *sc)
2625 {
2626 	struct ale_txdesc *txd;
2627 	int i;
2628 
2629 	sc->ale_cdata.ale_tx_prod = 0;
2630 	sc->ale_cdata.ale_tx_cons = 0;
2631 	sc->ale_cdata.ale_tx_cnt = 0;
2632 
2633 	bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2634 	bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2635 	for (i = 0; i < ALE_TX_RING_CNT; i++) {
2636 		txd = &sc->ale_cdata.ale_txdesc[i];
2637 		txd->tx_m = NULL;
2638 	}
2639 	*sc->ale_cdata.ale_tx_cmb = 0;
2640 	bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2641 	    sc->ale_cdata.ale_tx_cmb_map,
2642 	    BUS_DMASYNC_PREWRITE);
2643 	bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2644 	    sc->ale_cdata.ale_tx_ring_map,
2645 	    BUS_DMASYNC_PREWRITE);
2646 }
2647 
2648 static void
ale_init_rx_pages(struct ale_softc * sc)2649 ale_init_rx_pages(struct ale_softc *sc)
2650 {
2651 	struct ale_rx_page *rx_page;
2652 	int i;
2653 
2654 	sc->ale_cdata.ale_rx_seqno = 0;
2655 	sc->ale_cdata.ale_rx_curp = 0;
2656 
2657 	for (i = 0; i < ALE_RX_PAGES; i++) {
2658 		rx_page = &sc->ale_cdata.ale_rx_page[i];
2659 		bzero(rx_page->page_addr, sc->ale_pagesize);
2660 		bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2661 		rx_page->cons = 0;
2662 		*rx_page->cmb_addr = 0;
2663 		bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2664 				BUS_DMASYNC_PREWRITE);
2665 		bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2666 				BUS_DMASYNC_PREWRITE);
2667 	}
2668 }
2669 
2670 static void
ale_rxvlan(struct ale_softc * sc)2671 ale_rxvlan(struct ale_softc *sc)
2672 {
2673 	struct ifnet *ifp;
2674 	uint32_t reg;
2675 
2676 	ifp = &sc->arpcom.ac_if;
2677 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2678 	reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2679 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2680 		reg |= MAC_CFG_VLAN_TAG_STRIP;
2681 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2682 }
2683 
2684 static void
ale_rxfilter(struct ale_softc * sc)2685 ale_rxfilter(struct ale_softc *sc)
2686 {
2687 	struct ifnet *ifp;
2688 	struct ifmultiaddr *ifma;
2689 	uint32_t crc;
2690 	uint32_t mchash[2];
2691 	uint32_t rxcfg;
2692 
2693 	ifp = &sc->arpcom.ac_if;
2694 
2695 	rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
2696 	rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
2697 	if ((ifp->if_flags & IFF_BROADCAST) != 0)
2698 		rxcfg |= MAC_CFG_BCAST;
2699 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2700 		if ((ifp->if_flags & IFF_PROMISC) != 0)
2701 			rxcfg |= MAC_CFG_PROMISC;
2702 		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2703 			rxcfg |= MAC_CFG_ALLMULTI;
2704 		CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
2705 		CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
2706 		CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2707 		return;
2708 	}
2709 
2710 	/* Program new filter. */
2711 	bzero(mchash, sizeof(mchash));
2712 
2713 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2714 		if (ifma->ifma_addr->sa_family != AF_LINK)
2715 			continue;
2716 		crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2717 		    ifma->ifma_addr), ETHER_ADDR_LEN);
2718 		mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2719 	}
2720 
2721 	CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
2722 	CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
2723 	CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2724 }
2725 
2726 static int
sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)2727 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
2728 {
2729 	return (sysctl_int_range(oidp, arg1, arg2, req,
2730 	    ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
2731 }
2732 
2733 static void
ale_dmamap_buf_cb(void * xctx,bus_dma_segment_t * segs,int nsegs,bus_size_t mapsz __unused,int error)2734 ale_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
2735 		  bus_size_t mapsz __unused, int error)
2736 {
2737 	struct ale_dmamap_ctx *ctx = xctx;
2738 	int i;
2739 
2740 	if (error)
2741 		return;
2742 
2743 	if (nsegs > ctx->nsegs) {
2744 		ctx->nsegs = 0;
2745 		return;
2746 	}
2747 
2748 	ctx->nsegs = nsegs;
2749 	for (i = 0; i < nsegs; ++i)
2750 		ctx->segs[i] = segs[i];
2751 }
2752