xref: /dragonfly/sys/dev/netif/ig_hal/e1000_mac.c (revision 01a55482)
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3   Copyright (c) 2001-2019, Intel Corporation
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #include "e1000_api.h"
36 
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
40 
41 /**
42  *  e1000_init_mac_ops_generic - Initialize MAC function pointers
43  *  @hw: pointer to the HW structure
44  *
45  *  Setups up the function pointers to no-op functions
46  **/
e1000_init_mac_ops_generic(struct e1000_hw * hw)47 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
48 {
49 	struct e1000_mac_info *mac = &hw->mac;
50 	DEBUGFUNC("e1000_init_mac_ops_generic");
51 
52 	/* General Setup */
53 	mac->ops.init_params = e1000_null_ops_generic;
54 	mac->ops.init_hw = e1000_null_ops_generic;
55 	mac->ops.reset_hw = e1000_null_ops_generic;
56 	mac->ops.setup_physical_interface = e1000_null_ops_generic;
57 	mac->ops.get_bus_info = e1000_null_ops_generic;
58 	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
59 	mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
60 	mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
61 	mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
62 	/* LED */
63 	mac->ops.cleanup_led = e1000_null_ops_generic;
64 	mac->ops.setup_led = e1000_null_ops_generic;
65 	mac->ops.blink_led = e1000_null_ops_generic;
66 	mac->ops.led_on = e1000_null_ops_generic;
67 	mac->ops.led_off = e1000_null_ops_generic;
68 	/* LINK */
69 	mac->ops.setup_link = e1000_null_ops_generic;
70 	mac->ops.get_link_up_info = e1000_null_link_info;
71 	mac->ops.check_for_link = e1000_null_ops_generic;
72 	mac->ops.set_obff_timer = e1000_null_set_obff_timer;
73 	/* Management */
74 	mac->ops.check_mng_mode = e1000_null_mng_mode;
75 	/* VLAN, MC, etc. */
76 	mac->ops.update_mc_addr_list = e1000_null_update_mc;
77 	mac->ops.clear_vfta = e1000_null_mac_generic;
78 	mac->ops.write_vfta = e1000_null_write_vfta;
79 	mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
80 	mac->ops.rar_set = e1000_rar_set_generic;
81 }
82 
83 /**
84  *  e1000_null_ops_generic - No-op function, returns 0
85  *  @hw: pointer to the HW structure
86  **/
e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG * hw)87 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
88 {
89 	DEBUGFUNC("e1000_null_ops_generic");
90 	return E1000_SUCCESS;
91 }
92 
93 /**
94  *  e1000_null_mac_generic - No-op function, return void
95  *  @hw: pointer to the HW structure
96  **/
e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG * hw)97 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
98 {
99 	DEBUGFUNC("e1000_null_mac_generic");
100 	return;
101 }
102 
103 /**
104  *  e1000_null_link_info - No-op function, return 0
105  *  @hw: pointer to the HW structure
106  *  @s: dummy variable
107  *  @d: dummy variable
108  **/
e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG * hw,u16 E1000_UNUSEDARG * s,u16 E1000_UNUSEDARG * d)109 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
110 			 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
111 {
112 	DEBUGFUNC("e1000_null_link_info");
113 	return E1000_SUCCESS;
114 }
115 
116 /**
117  *  e1000_null_mng_mode - No-op function, return FALSE
118  *  @hw: pointer to the HW structure
119  **/
e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG * hw)120 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
121 {
122 	DEBUGFUNC("e1000_null_mng_mode");
123 	return FALSE;
124 }
125 
126 /**
127  *  e1000_null_update_mc - No-op function, return void
128  *  @hw: pointer to the HW structure
129  *  @h: dummy variable
130  *  @a: dummy variable
131  **/
e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG * h,u32 E1000_UNUSEDARG a)132 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
133 			  u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
134 {
135 	DEBUGFUNC("e1000_null_update_mc");
136 	return;
137 }
138 
139 /**
140  *  e1000_null_write_vfta - No-op function, return void
141  *  @hw: pointer to the HW structure
142  *  @a: dummy variable
143  *  @b: dummy variable
144  **/
e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG a,u32 E1000_UNUSEDARG b)145 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
146 			   u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
147 {
148 	DEBUGFUNC("e1000_null_write_vfta");
149 	return;
150 }
151 
152 /**
153  *  e1000_null_rar_set - No-op function, return 0
154  *  @hw: pointer to the HW structure
155  *  @h: dummy variable
156  *  @a: dummy variable
157  **/
e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG * h,u32 E1000_UNUSEDARG a)158 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
159 			u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
160 {
161 	DEBUGFUNC("e1000_null_rar_set");
162 	return E1000_SUCCESS;
163 }
164 
165 /**
166  *  e1000_null_set_obff_timer - No-op function, return 0
167  *  @hw: pointer to the HW structure
168  **/
e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG a)169 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
170 			      u32 E1000_UNUSEDARG a)
171 {
172 	DEBUGFUNC("e1000_null_set_obff_timer");
173 	return E1000_SUCCESS;
174 }
175 
176 /**
177  *  e1000_get_bus_info_pci_generic - Get PCI(x) bus information
178  *  @hw: pointer to the HW structure
179  *
180  *  Determines and stores the system bus information for a particular
181  *  network interface.  The following bus information is determined and stored:
182  *  bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
183  **/
e1000_get_bus_info_pci_generic(struct e1000_hw * hw)184 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
185 {
186 	struct e1000_mac_info *mac = &hw->mac;
187 	struct e1000_bus_info *bus = &hw->bus;
188 	u32 status = E1000_READ_REG(hw, E1000_STATUS);
189 	s32 ret_val = E1000_SUCCESS;
190 
191 	DEBUGFUNC("e1000_get_bus_info_pci_generic");
192 
193 	/* PCI or PCI-X? */
194 	bus->type = (status & E1000_STATUS_PCIX_MODE)
195 			? e1000_bus_type_pcix
196 			: e1000_bus_type_pci;
197 
198 	/* Bus speed */
199 	if (bus->type == e1000_bus_type_pci) {
200 		bus->speed = (status & E1000_STATUS_PCI66)
201 			     ? e1000_bus_speed_66
202 			     : e1000_bus_speed_33;
203 	} else {
204 		switch (status & E1000_STATUS_PCIX_SPEED) {
205 		case E1000_STATUS_PCIX_SPEED_66:
206 			bus->speed = e1000_bus_speed_66;
207 			break;
208 		case E1000_STATUS_PCIX_SPEED_100:
209 			bus->speed = e1000_bus_speed_100;
210 			break;
211 		case E1000_STATUS_PCIX_SPEED_133:
212 			bus->speed = e1000_bus_speed_133;
213 			break;
214 		default:
215 			bus->speed = e1000_bus_speed_reserved;
216 			break;
217 		}
218 	}
219 
220 	/* Bus width */
221 	bus->width = (status & E1000_STATUS_BUS64)
222 		     ? e1000_bus_width_64
223 		     : e1000_bus_width_32;
224 
225 	/* Which PCI(-X) function? */
226 	mac->ops.set_lan_id(hw);
227 
228 	return ret_val;
229 }
230 
231 /**
232  *  e1000_get_bus_info_pcie_generic - Get PCIe bus information
233  *  @hw: pointer to the HW structure
234  *
235  *  Determines and stores the system bus information for a particular
236  *  network interface.  The following bus information is determined and stored:
237  *  bus speed, bus width, type (PCIe), and PCIe function.
238  **/
e1000_get_bus_info_pcie_generic(struct e1000_hw * hw)239 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
240 {
241 	struct e1000_mac_info *mac = &hw->mac;
242 	struct e1000_bus_info *bus = &hw->bus;
243 	s32 ret_val;
244 	u16 pcie_link_status;
245 
246 	DEBUGFUNC("e1000_get_bus_info_pcie_generic");
247 
248 	bus->type = e1000_bus_type_pci_express;
249 
250 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
251 					  &pcie_link_status);
252 	if (ret_val) {
253 		bus->width = e1000_bus_width_unknown;
254 		bus->speed = e1000_bus_speed_unknown;
255 	} else {
256 		switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
257 		case PCIE_LINK_SPEED_2500:
258 			bus->speed = e1000_bus_speed_2500;
259 			break;
260 		case PCIE_LINK_SPEED_5000:
261 			bus->speed = e1000_bus_speed_5000;
262 			break;
263 		default:
264 			bus->speed = e1000_bus_speed_unknown;
265 			break;
266 		}
267 
268 		bus->width = (enum e1000_bus_width)((pcie_link_status &
269 			      PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
270 	}
271 
272 	mac->ops.set_lan_id(hw);
273 
274 	return E1000_SUCCESS;
275 }
276 
277 /**
278  *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
279  *
280  *  @hw: pointer to the HW structure
281  *
282  *  Determines the LAN function id by reading memory-mapped registers
283  *  and swaps the port value if requested.
284  **/
e1000_set_lan_id_multi_port_pcie(struct e1000_hw * hw)285 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
286 {
287 	struct e1000_bus_info *bus = &hw->bus;
288 	u32 reg;
289 
290 	/* The status register reports the correct function number
291 	 * for the device regardless of function swap state.
292 	 */
293 	reg = E1000_READ_REG(hw, E1000_STATUS);
294 	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
295 }
296 
297 /**
298  *  e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
299  *  @hw: pointer to the HW structure
300  *
301  *  Determines the LAN function id by reading PCI config space.
302  **/
e1000_set_lan_id_multi_port_pci(struct e1000_hw * hw)303 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
304 {
305 	struct e1000_bus_info *bus = &hw->bus;
306 	u16 pci_header_type;
307 	u32 status;
308 
309 	e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
310 	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
311 		status = E1000_READ_REG(hw, E1000_STATUS);
312 		bus->func = (status & E1000_STATUS_FUNC_MASK)
313 			    >> E1000_STATUS_FUNC_SHIFT;
314 	} else {
315 		bus->func = 0;
316 	}
317 }
318 
319 /**
320  *  e1000_set_lan_id_single_port - Set LAN id for a single port device
321  *  @hw: pointer to the HW structure
322  *
323  *  Sets the LAN function id to zero for a single port device.
324  **/
e1000_set_lan_id_single_port(struct e1000_hw * hw)325 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
326 {
327 	struct e1000_bus_info *bus = &hw->bus;
328 
329 	bus->func = 0;
330 }
331 
332 /**
333  *  e1000_clear_vfta_generic - Clear VLAN filter table
334  *  @hw: pointer to the HW structure
335  *
336  *  Clears the register array which contains the VLAN filter table by
337  *  setting all the values to 0.
338  **/
e1000_clear_vfta_generic(struct e1000_hw * hw)339 void e1000_clear_vfta_generic(struct e1000_hw *hw)
340 {
341 	u32 offset;
342 
343 	DEBUGFUNC("e1000_clear_vfta_generic");
344 
345 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
346 		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
347 		E1000_WRITE_FLUSH(hw);
348 	}
349 }
350 
351 /**
352  *  e1000_write_vfta_generic - Write value to VLAN filter table
353  *  @hw: pointer to the HW structure
354  *  @offset: register offset in VLAN filter table
355  *  @value: register value written to VLAN filter table
356  *
357  *  Writes value at the given offset in the register array which stores
358  *  the VLAN filter table.
359  **/
e1000_write_vfta_generic(struct e1000_hw * hw,u32 offset,u32 value)360 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
361 {
362 	DEBUGFUNC("e1000_write_vfta_generic");
363 
364 	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
365 	E1000_WRITE_FLUSH(hw);
366 }
367 
368 /**
369  *  e1000_init_rx_addrs_generic - Initialize receive address's
370  *  @hw: pointer to the HW structure
371  *  @rar_count: receive address registers
372  *
373  *  Setup the receive address registers by setting the base receive address
374  *  register to the devices MAC address and clearing all the other receive
375  *  address registers to 0.
376  **/
e1000_init_rx_addrs_generic(struct e1000_hw * hw,u16 rar_count)377 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
378 {
379 	u32 i;
380 	u8 mac_addr[ETH_ADDR_LEN] = {0};
381 
382 	DEBUGFUNC("e1000_init_rx_addrs_generic");
383 
384 	/* Setup the receive address */
385 	DEBUGOUT("Programming MAC Address into RAR[0]\n");
386 
387 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
388 
389 	/* Zero out the other (rar_entry_count - 1) receive addresses */
390 	DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
391 	for (i = 1; i < rar_count; i++)
392 		hw->mac.ops.rar_set(hw, mac_addr, i);
393 }
394 
395 /**
396  *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
397  *  @hw: pointer to the HW structure
398  *
399  *  Checks the nvm for an alternate MAC address.  An alternate MAC address
400  *  can be setup by pre-boot software and must be treated like a permanent
401  *  address and must override the actual permanent MAC address. If an
402  *  alternate MAC address is found it is programmed into RAR0, replacing
403  *  the permanent address that was installed into RAR0 by the Si on reset.
404  *  This function will return SUCCESS unless it encounters an error while
405  *  reading the EEPROM.
406  **/
e1000_check_alt_mac_addr_generic(struct e1000_hw * hw)407 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
408 {
409 	u32 i;
410 	s32 ret_val;
411 	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
412 	u8 alt_mac_addr[ETH_ADDR_LEN];
413 
414 	DEBUGFUNC("e1000_check_alt_mac_addr_generic");
415 
416 	ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
417 	if (ret_val)
418 		return ret_val;
419 
420 	/* not supported on older hardware or 82573.
421 	 *
422 	 * Alternate MAC address is handled by the option ROM for 82580
423 	 * and newer. SW support not required.
424 	 */
425 	if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573) ||
426 	    hw->mac.type >= e1000_82580)
427 		return E1000_SUCCESS;
428 
429 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
430 				   &nvm_alt_mac_addr_offset);
431 	if (ret_val) {
432 		DEBUGOUT("NVM Read Error\n");
433 		return ret_val;
434 	}
435 
436 	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
437 	    (nvm_alt_mac_addr_offset == 0x0000))
438 		/* There is no Alternate MAC Address */
439 		return E1000_SUCCESS;
440 
441 	if (hw->bus.func == E1000_FUNC_1)
442 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
443 	if (hw->bus.func == E1000_FUNC_2)
444 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
445 
446 	if (hw->bus.func == E1000_FUNC_3)
447 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
448 	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
449 		offset = nvm_alt_mac_addr_offset + (i >> 1);
450 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
451 		if (ret_val) {
452 			DEBUGOUT("NVM Read Error\n");
453 			return ret_val;
454 		}
455 
456 		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
457 		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
458 	}
459 
460 	/* if multicast bit is set, the alternate address will not be used */
461 	if (alt_mac_addr[0] & 0x01) {
462 		DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
463 		return E1000_SUCCESS;
464 	}
465 
466 	/* We have a valid alternate MAC address, and we want to treat it the
467 	 * same as the normal permanent MAC address stored by the HW into the
468 	 * RAR. Do this by mapping this address into RAR0.
469 	 */
470 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
471 
472 	return E1000_SUCCESS;
473 }
474 
475 /**
476  *  e1000_rar_set_generic - Set receive address register
477  *  @hw: pointer to the HW structure
478  *  @addr: pointer to the receive address
479  *  @index: receive address array register
480  *
481  *  Sets the receive address array register at index to the address passed
482  *  in by addr.
483  **/
e1000_rar_set_generic(struct e1000_hw * hw,u8 * addr,u32 index)484 int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
485 {
486 	u32 rar_low, rar_high;
487 
488 	DEBUGFUNC("e1000_rar_set_generic");
489 
490 	/* HW expects these in little endian so we reverse the byte order
491 	 * from network order (big endian) to little endian
492 	 */
493 	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
494 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
495 
496 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
497 
498 	/* If MAC address zero, no need to set the AV bit */
499 	if (rar_low || rar_high)
500 		rar_high |= E1000_RAH_AV;
501 
502 	/* Some bridges will combine consecutive 32-bit writes into
503 	 * a single burst write, which will malfunction on some parts.
504 	 * The flushes avoid this.
505 	 */
506 	E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
507 	E1000_WRITE_FLUSH(hw);
508 	E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
509 	E1000_WRITE_FLUSH(hw);
510 
511 	return E1000_SUCCESS;
512 }
513 
514 /**
515  *  e1000_hash_mc_addr_generic - Generate a multicast hash value
516  *  @hw: pointer to the HW structure
517  *  @mc_addr: pointer to a multicast address
518  *
519  *  Generates a multicast address hash value which is used to determine
520  *  the multicast filter table array address and new table value.
521  **/
e1000_hash_mc_addr_generic(struct e1000_hw * hw,u8 * mc_addr)522 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
523 {
524 	u32 hash_value, hash_mask;
525 	u8 bit_shift = 0;
526 
527 	DEBUGFUNC("e1000_hash_mc_addr_generic");
528 
529 	/* Register count multiplied by bits per register */
530 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
531 
532 	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts
533 	 * where 0xFF would still fall within the hash mask.
534 	 */
535 	while (hash_mask >> bit_shift != 0xFF)
536 		bit_shift++;
537 
538 	/* The portion of the address that is used for the hash table
539 	 * is determined by the mc_filter_type setting.
540 	 * The algorithm is such that there is a total of 8 bits of shifting.
541 	 * The bit_shift for a mc_filter_type of 0 represents the number of
542 	 * left-shifts where the MSB of mc_addr[5] would still fall within
543 	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
544 	 * of 8 bits of shifting, then mc_addr[4] will shift right the
545 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
546 	 * cases are a variation of this algorithm...essentially raising the
547 	 * number of bits to shift mc_addr[5] left, while still keeping the
548 	 * 8-bit shifting total.
549 	 *
550 	 * For example, given the following Destination MAC Address and an
551 	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
552 	 * we can see that the bit_shift for case 0 is 4.  These are the hash
553 	 * values resulting from each mc_filter_type...
554 	 * [0] [1] [2] [3] [4] [5]
555 	 * 01  AA  00  12  34  56
556 	 * LSB		 MSB
557 	 *
558 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
559 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
560 	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
561 	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
562 	 */
563 	switch (hw->mac.mc_filter_type) {
564 	default:
565 	case 0:
566 		break;
567 	case 1:
568 		bit_shift += 1;
569 		break;
570 	case 2:
571 		bit_shift += 2;
572 		break;
573 	case 3:
574 		bit_shift += 4;
575 		break;
576 	}
577 
578 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
579 				  (((u16) mc_addr[5]) << bit_shift)));
580 
581 	return hash_value;
582 }
583 
584 /**
585  *  e1000_update_mc_addr_list_generic - Update Multicast addresses
586  *  @hw: pointer to the HW structure
587  *  @mc_addr_list: array of multicast addresses to program
588  *  @mc_addr_count: number of multicast addresses to program
589  *
590  *  Updates entire Multicast Table Array.
591  *  The caller must have a packed mc_addr_list of multicast addresses.
592  **/
e1000_update_mc_addr_list_generic(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)593 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
594 				       u8 *mc_addr_list, u32 mc_addr_count)
595 {
596 	u32 hash_value, hash_bit, hash_reg;
597 	int i;
598 
599 	DEBUGFUNC("e1000_update_mc_addr_list_generic");
600 
601 	/* clear mta_shadow */
602 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
603 
604 	/* update mta_shadow from mc_addr_list */
605 	for (i = 0; (u32) i < mc_addr_count; i++) {
606 		hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
607 
608 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
609 		hash_bit = hash_value & 0x1F;
610 
611 		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
612 		mc_addr_list += (ETH_ADDR_LEN);
613 	}
614 
615 	/* replace the entire MTA table */
616 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
617 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
618 	E1000_WRITE_FLUSH(hw);
619 }
620 
621 /**
622  *  e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
623  *  @hw: pointer to the HW structure
624  *
625  *  In certain situations, a system BIOS may report that the PCIx maximum
626  *  memory read byte count (MMRBC) value is higher than than the actual
627  *  value. We check the PCIx command register with the current PCIx status
628  *  register.
629  **/
e1000_pcix_mmrbc_workaround_generic(struct e1000_hw * hw)630 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
631 {
632 	u16 cmd_mmrbc;
633 	u16 pcix_cmd;
634 	u16 pcix_stat_hi_word;
635 	u16 stat_mmrbc;
636 
637 	DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
638 
639 	/* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
640 	if (hw->bus.type != e1000_bus_type_pcix)
641 		return;
642 
643 	e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
644 	e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
645 	cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
646 		     PCIX_COMMAND_MMRBC_SHIFT;
647 	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
648 		      PCIX_STATUS_HI_MMRBC_SHIFT;
649 	if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
650 		stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
651 	if (cmd_mmrbc > stat_mmrbc) {
652 		pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
653 		pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
654 		e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
655 	}
656 }
657 
658 /**
659  *  e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
660  *  @hw: pointer to the HW structure
661  *
662  *  Clears the base hardware counters by reading the counter registers.
663  **/
e1000_clear_hw_cntrs_base_generic(struct e1000_hw * hw)664 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
665 {
666 	DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
667 
668 	E1000_READ_REG(hw, E1000_CRCERRS);
669 	E1000_READ_REG(hw, E1000_SYMERRS);
670 	E1000_READ_REG(hw, E1000_MPC);
671 	E1000_READ_REG(hw, E1000_SCC);
672 	E1000_READ_REG(hw, E1000_ECOL);
673 	E1000_READ_REG(hw, E1000_MCC);
674 	E1000_READ_REG(hw, E1000_LATECOL);
675 	E1000_READ_REG(hw, E1000_COLC);
676 	E1000_READ_REG(hw, E1000_DC);
677 	E1000_READ_REG(hw, E1000_SEC);
678 	E1000_READ_REG(hw, E1000_RLEC);
679 	E1000_READ_REG(hw, E1000_XONRXC);
680 	E1000_READ_REG(hw, E1000_XONTXC);
681 	E1000_READ_REG(hw, E1000_XOFFRXC);
682 	E1000_READ_REG(hw, E1000_XOFFTXC);
683 	E1000_READ_REG(hw, E1000_FCRUC);
684 	E1000_READ_REG(hw, E1000_GPRC);
685 	E1000_READ_REG(hw, E1000_BPRC);
686 	E1000_READ_REG(hw, E1000_MPRC);
687 	E1000_READ_REG(hw, E1000_GPTC);
688 	E1000_READ_REG(hw, E1000_GORCL);
689 	E1000_READ_REG(hw, E1000_GORCH);
690 	E1000_READ_REG(hw, E1000_GOTCL);
691 	E1000_READ_REG(hw, E1000_GOTCH);
692 	E1000_READ_REG(hw, E1000_RNBC);
693 	E1000_READ_REG(hw, E1000_RUC);
694 	E1000_READ_REG(hw, E1000_RFC);
695 	E1000_READ_REG(hw, E1000_ROC);
696 	E1000_READ_REG(hw, E1000_RJC);
697 	E1000_READ_REG(hw, E1000_TORL);
698 	E1000_READ_REG(hw, E1000_TORH);
699 	E1000_READ_REG(hw, E1000_TOTL);
700 	E1000_READ_REG(hw, E1000_TOTH);
701 	E1000_READ_REG(hw, E1000_TPR);
702 	E1000_READ_REG(hw, E1000_TPT);
703 	E1000_READ_REG(hw, E1000_MPTC);
704 	E1000_READ_REG(hw, E1000_BPTC);
705 }
706 
707 /**
708  *  e1000_check_for_copper_link_generic - Check for link (Copper)
709  *  @hw: pointer to the HW structure
710  *
711  *  Checks to see of the link status of the hardware has changed.  If a
712  *  change in link status has been detected, then we read the PHY registers
713  *  to get the current speed/duplex if link exists.
714  **/
e1000_check_for_copper_link_generic(struct e1000_hw * hw)715 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
716 {
717 	struct e1000_mac_info *mac = &hw->mac;
718 	s32 ret_val;
719 	bool link;
720 
721 	DEBUGFUNC("e1000_check_for_copper_link");
722 
723 	/* We only want to go out to the PHY registers to see if Auto-Neg
724 	 * has completed and/or if our link status has changed.  The
725 	 * get_link_status flag is set upon receiving a Link Status
726 	 * Change or Rx Sequence Error interrupt.
727 	 */
728 	if (!mac->get_link_status)
729 		return E1000_SUCCESS;
730 
731 	/* First we want to see if the MII Status Register reports
732 	 * link.  If so, then we want to get the current speed/duplex
733 	 * of the PHY.
734 	 */
735 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
736 	if (ret_val)
737 		return ret_val;
738 
739 	if (!link)
740 		return E1000_SUCCESS; /* No link detected */
741 
742 	mac->get_link_status = FALSE;
743 
744 	/* Check if there was DownShift, must be checked
745 	 * immediately after link-up
746 	 */
747 	e1000_check_downshift_generic(hw);
748 
749 	/* If we are forcing speed/duplex, then we simply return since
750 	 * we have already determined whether we have link or not.
751 	 */
752 	if (!mac->autoneg)
753 		return -E1000_ERR_CONFIG;
754 
755 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
756 	 * of MAC speed/duplex configuration.  So we only need to
757 	 * configure Collision Distance in the MAC.
758 	 */
759 	mac->ops.config_collision_dist(hw);
760 
761 	/* Configure Flow Control now that Auto-Neg has completed.
762 	 * First, we need to restore the desired flow control
763 	 * settings because we may have had to re-autoneg with a
764 	 * different link partner.
765 	 */
766 	ret_val = e1000_config_fc_after_link_up_generic(hw);
767 	if (ret_val)
768 		DEBUGOUT("Error configuring flow control\n");
769 
770 	return ret_val;
771 }
772 
773 /**
774  *  e1000_check_for_fiber_link_generic - Check for link (Fiber)
775  *  @hw: pointer to the HW structure
776  *
777  *  Checks for link up on the hardware.  If link is not up and we have
778  *  a signal, then we need to force link up.
779  **/
e1000_check_for_fiber_link_generic(struct e1000_hw * hw)780 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
781 {
782 	struct e1000_mac_info *mac = &hw->mac;
783 	u32 rxcw;
784 	u32 ctrl;
785 	u32 status;
786 	s32 ret_val;
787 
788 	DEBUGFUNC("e1000_check_for_fiber_link_generic");
789 
790 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
791 	status = E1000_READ_REG(hw, E1000_STATUS);
792 	rxcw = E1000_READ_REG(hw, E1000_RXCW);
793 
794 	/* If we don't have link (auto-negotiation failed or link partner
795 	 * cannot auto-negotiate), the cable is plugged in (we have signal),
796 	 * and our link partner is not trying to auto-negotiate with us (we
797 	 * are receiving idles or data), we need to force link up. We also
798 	 * need to give auto-negotiation time to complete, in case the cable
799 	 * was just plugged in. The autoneg_failed flag does this.
800 	 */
801 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
802 	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
803 	    !(rxcw & E1000_RXCW_C)) {
804 		if (!mac->autoneg_failed) {
805 			mac->autoneg_failed = TRUE;
806 			return E1000_SUCCESS;
807 		}
808 		DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
809 
810 		/* Disable auto-negotiation in the TXCW register */
811 		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
812 
813 		/* Force link-up and also force full-duplex. */
814 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
815 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
816 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
817 
818 		/* Configure Flow Control after forcing link up. */
819 		ret_val = e1000_config_fc_after_link_up_generic(hw);
820 		if (ret_val) {
821 			DEBUGOUT("Error configuring flow control\n");
822 			return ret_val;
823 		}
824 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
825 		/* If we are forcing link and we are receiving /C/ ordered
826 		 * sets, re-enable auto-negotiation in the TXCW register
827 		 * and disable forced link in the Device Control register
828 		 * in an attempt to auto-negotiate with our link partner.
829 		 */
830 		DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
831 		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
832 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
833 
834 		mac->serdes_has_link = TRUE;
835 	}
836 
837 	return E1000_SUCCESS;
838 }
839 
840 /**
841  *  e1000_check_for_serdes_link_generic - Check for link (Serdes)
842  *  @hw: pointer to the HW structure
843  *
844  *  Checks for link up on the hardware.  If link is not up and we have
845  *  a signal, then we need to force link up.
846  **/
e1000_check_for_serdes_link_generic(struct e1000_hw * hw)847 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
848 {
849 	struct e1000_mac_info *mac = &hw->mac;
850 	u32 rxcw;
851 	u32 ctrl;
852 	u32 status;
853 	s32 ret_val;
854 
855 	DEBUGFUNC("e1000_check_for_serdes_link_generic");
856 
857 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
858 	status = E1000_READ_REG(hw, E1000_STATUS);
859 	rxcw = E1000_READ_REG(hw, E1000_RXCW);
860 
861 	/* If we don't have link (auto-negotiation failed or link partner
862 	 * cannot auto-negotiate), and our link partner is not trying to
863 	 * auto-negotiate with us (we are receiving idles or data),
864 	 * we need to force link up. We also need to give auto-negotiation
865 	 * time to complete.
866 	 */
867 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
868 	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
869 		if (!mac->autoneg_failed) {
870 			mac->autoneg_failed = TRUE;
871 			return E1000_SUCCESS;
872 		}
873 		DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
874 
875 		/* Disable auto-negotiation in the TXCW register */
876 		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
877 
878 		/* Force link-up and also force full-duplex. */
879 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
880 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
881 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
882 
883 		/* Configure Flow Control after forcing link up. */
884 		ret_val = e1000_config_fc_after_link_up_generic(hw);
885 		if (ret_val) {
886 			DEBUGOUT("Error configuring flow control\n");
887 			return ret_val;
888 		}
889 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
890 		/* If we are forcing link and we are receiving /C/ ordered
891 		 * sets, re-enable auto-negotiation in the TXCW register
892 		 * and disable forced link in the Device Control register
893 		 * in an attempt to auto-negotiate with our link partner.
894 		 */
895 		DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
896 		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
897 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
898 
899 		mac->serdes_has_link = TRUE;
900 	} else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
901 		/* If we force link for non-auto-negotiation switch, check
902 		 * link status based on MAC synchronization for internal
903 		 * serdes media type.
904 		 */
905 		/* SYNCH bit and IV bit are sticky. */
906 		usec_delay(10);
907 		rxcw = E1000_READ_REG(hw, E1000_RXCW);
908 		if (rxcw & E1000_RXCW_SYNCH) {
909 			if (!(rxcw & E1000_RXCW_IV)) {
910 				mac->serdes_has_link = TRUE;
911 				DEBUGOUT("SERDES: Link up - forced.\n");
912 			}
913 		} else {
914 			mac->serdes_has_link = FALSE;
915 			DEBUGOUT("SERDES: Link down - force failed.\n");
916 		}
917 	}
918 
919 	if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
920 		status = E1000_READ_REG(hw, E1000_STATUS);
921 		if (status & E1000_STATUS_LU) {
922 			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
923 			usec_delay(10);
924 			rxcw = E1000_READ_REG(hw, E1000_RXCW);
925 			if (rxcw & E1000_RXCW_SYNCH) {
926 				if (!(rxcw & E1000_RXCW_IV)) {
927 					mac->serdes_has_link = TRUE;
928 					DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
929 				} else {
930 					mac->serdes_has_link = FALSE;
931 					DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
932 				}
933 			} else {
934 				mac->serdes_has_link = FALSE;
935 				DEBUGOUT("SERDES: Link down - no sync.\n");
936 			}
937 		} else {
938 			mac->serdes_has_link = FALSE;
939 			DEBUGOUT("SERDES: Link down - autoneg failed\n");
940 		}
941 	}
942 
943 	return E1000_SUCCESS;
944 }
945 
946 /**
947  *  e1000_set_default_fc_generic - Set flow control default values
948  *  @hw: pointer to the HW structure
949  *
950  *  Read the EEPROM for the default values for flow control and store the
951  *  values.
952  **/
e1000_set_default_fc_generic(struct e1000_hw * hw)953 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
954 {
955 	s32 ret_val;
956 	u16 nvm_data;
957 	u16 nvm_offset = 0;
958 
959 	DEBUGFUNC("e1000_set_default_fc_generic");
960 
961 	/* Read and store word 0x0F of the EEPROM. This word contains bits
962 	 * that determine the hardware's default PAUSE (flow control) mode,
963 	 * a bit that determines whether the HW defaults to enabling or
964 	 * disabling auto-negotiation, and the direction of the
965 	 * SW defined pins. If there is no SW over-ride of the flow
966 	 * control setting, then the variable hw->fc will
967 	 * be initialized based on a value in the EEPROM.
968 	 */
969 	if (hw->mac.type == e1000_i350) {
970 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
971 		ret_val = hw->nvm.ops.read(hw,
972 					   NVM_INIT_CONTROL2_REG +
973 					   nvm_offset,
974 					   1, &nvm_data);
975 	} else {
976 		ret_val = hw->nvm.ops.read(hw,
977 					   NVM_INIT_CONTROL2_REG,
978 					   1, &nvm_data);
979 	}
980 
981 
982 	if (ret_val) {
983 		DEBUGOUT("NVM Read Error\n");
984 		return ret_val;
985 	}
986 
987 	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
988 		hw->fc.requested_mode = e1000_fc_none;
989 	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
990 		 NVM_WORD0F_ASM_DIR)
991 		hw->fc.requested_mode = e1000_fc_tx_pause;
992 	else
993 		hw->fc.requested_mode = e1000_fc_full;
994 
995 	return E1000_SUCCESS;
996 }
997 
998 /**
999  *  e1000_setup_link_generic - Setup flow control and link settings
1000  *  @hw: pointer to the HW structure
1001  *
1002  *  Determines which flow control settings to use, then configures flow
1003  *  control.  Calls the appropriate media-specific link configuration
1004  *  function.  Assuming the adapter has a valid link partner, a valid link
1005  *  should be established.  Assumes the hardware has previously been reset
1006  *  and the transmitter and receiver are not enabled.
1007  **/
e1000_setup_link_generic(struct e1000_hw * hw)1008 s32 e1000_setup_link_generic(struct e1000_hw *hw)
1009 {
1010 	s32 ret_val;
1011 
1012 	DEBUGFUNC("e1000_setup_link_generic");
1013 
1014 	/* In the case of the phy reset being blocked, we already have a link.
1015 	 * We do not need to set it up again.
1016 	 */
1017 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1018 		return E1000_SUCCESS;
1019 
1020 	/* If requested flow control is set to default, set flow control
1021 	 * based on the EEPROM flow control settings.
1022 	 */
1023 	if (hw->fc.requested_mode == e1000_fc_default) {
1024 		ret_val = e1000_set_default_fc_generic(hw);
1025 		if (ret_val)
1026 			return ret_val;
1027 	}
1028 
1029 	/* Save off the requested flow control mode for use later.  Depending
1030 	 * on the link partner's capabilities, we may or may not use this mode.
1031 	 */
1032 	hw->fc.current_mode = hw->fc.requested_mode;
1033 
1034 	DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1035 		hw->fc.current_mode);
1036 
1037 	/* Call the necessary media_type subroutine to configure the link. */
1038 	ret_val = hw->mac.ops.setup_physical_interface(hw);
1039 	if (ret_val)
1040 		return ret_val;
1041 
1042 	/* Initialize the flow control address, type, and PAUSE timer
1043 	 * registers to their default values.  This is done even if flow
1044 	 * control is disabled, because it does not hurt anything to
1045 	 * initialize these registers.
1046 	 */
1047 	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1048 	E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1049 	E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1050 	E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1051 
1052 	E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1053 
1054 	return e1000_set_fc_watermarks_generic(hw);
1055 }
1056 
1057 /**
1058  *  e1000_commit_fc_settings_generic - Configure flow control
1059  *  @hw: pointer to the HW structure
1060  *
1061  *  Write the flow control settings to the Transmit Config Word Register (TXCW)
1062  *  base on the flow control settings in e1000_mac_info.
1063  **/
e1000_commit_fc_settings_generic(struct e1000_hw * hw)1064 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1065 {
1066 	struct e1000_mac_info *mac = &hw->mac;
1067 	u32 txcw;
1068 
1069 	DEBUGFUNC("e1000_commit_fc_settings_generic");
1070 
1071 	/* Check for a software override of the flow control settings, and
1072 	 * setup the device accordingly.  If auto-negotiation is enabled, then
1073 	 * software will have to set the "PAUSE" bits to the correct value in
1074 	 * the Transmit Config Word Register (TXCW) and re-start auto-
1075 	 * negotiation.  However, if auto-negotiation is disabled, then
1076 	 * software will have to manually configure the two flow control enable
1077 	 * bits in the CTRL register.
1078 	 *
1079 	 * The possible values of the "fc" parameter are:
1080 	 *      0:  Flow control is completely disabled
1081 	 *      1:  Rx flow control is enabled (we can receive pause frames,
1082 	 *          but not send pause frames).
1083 	 *      2:  Tx flow control is enabled (we can send pause frames but we
1084 	 *          do not support receiving pause frames).
1085 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
1086 	 */
1087 	switch (hw->fc.current_mode) {
1088 	case e1000_fc_none:
1089 		/* Flow control completely disabled by a software over-ride. */
1090 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1091 		break;
1092 	case e1000_fc_rx_pause:
1093 		/* Rx Flow control is enabled and Tx Flow control is disabled
1094 		 * by a software over-ride. Since there really isn't a way to
1095 		 * advertise that we are capable of Rx Pause ONLY, we will
1096 		 * advertise that we support both symmetric and asymmetric Rx
1097 		 * PAUSE.  Later, we will disable the adapter's ability to send
1098 		 * PAUSE frames.
1099 		 */
1100 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1101 		break;
1102 	case e1000_fc_tx_pause:
1103 		/* Tx Flow control is enabled, and Rx Flow control is disabled,
1104 		 * by a software over-ride.
1105 		 */
1106 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1107 		break;
1108 	case e1000_fc_full:
1109 		/* Flow control (both Rx and Tx) is enabled by a software
1110 		 * over-ride.
1111 		 */
1112 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1113 		break;
1114 	default:
1115 		DEBUGOUT("Flow control param set incorrectly\n");
1116 		return -E1000_ERR_CONFIG;
1117 		break;
1118 	}
1119 
1120 	E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1121 	mac->txcw = txcw;
1122 
1123 	return E1000_SUCCESS;
1124 }
1125 
1126 /**
1127  *  e1000_poll_fiber_serdes_link_generic - Poll for link up
1128  *  @hw: pointer to the HW structure
1129  *
1130  *  Polls for link up by reading the status register, if link fails to come
1131  *  up with auto-negotiation, then the link is forced if a signal is detected.
1132  **/
e1000_poll_fiber_serdes_link_generic(struct e1000_hw * hw)1133 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1134 {
1135 	struct e1000_mac_info *mac = &hw->mac;
1136 	u32 i, status;
1137 	s32 ret_val;
1138 
1139 	DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1140 
1141 	/* If we have a signal (the cable is plugged in, or assumed TRUE for
1142 	 * serdes media) then poll for a "Link-Up" indication in the Device
1143 	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
1144 	 * seconds (Auto-negotiation should complete in less than 500
1145 	 * milliseconds even if the other end is doing it in SW).
1146 	 */
1147 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1148 		msec_delay(10);
1149 		status = E1000_READ_REG(hw, E1000_STATUS);
1150 		if (status & E1000_STATUS_LU)
1151 			break;
1152 	}
1153 	if (i == FIBER_LINK_UP_LIMIT) {
1154 		DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1155 		mac->autoneg_failed = TRUE;
1156 		/* AutoNeg failed to achieve a link, so we'll call
1157 		 * mac->check_for_link. This routine will force the
1158 		 * link up if we detect a signal. This will allow us to
1159 		 * communicate with non-autonegotiating link partners.
1160 		 */
1161 		ret_val = mac->ops.check_for_link(hw);
1162 		if (ret_val) {
1163 			DEBUGOUT("Error while checking for link\n");
1164 			return ret_val;
1165 		}
1166 		mac->autoneg_failed = FALSE;
1167 	} else {
1168 		mac->autoneg_failed = FALSE;
1169 		DEBUGOUT("Valid Link Found\n");
1170 	}
1171 
1172 	return E1000_SUCCESS;
1173 }
1174 
1175 /**
1176  *  e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1177  *  @hw: pointer to the HW structure
1178  *
1179  *  Configures collision distance and flow control for fiber and serdes
1180  *  links.  Upon successful setup, poll for link.
1181  **/
e1000_setup_fiber_serdes_link_generic(struct e1000_hw * hw)1182 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1183 {
1184 	u32 ctrl;
1185 	s32 ret_val;
1186 
1187 	DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1188 
1189 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1190 
1191 	/* Take the link out of reset */
1192 	ctrl &= ~E1000_CTRL_LRST;
1193 
1194 	hw->mac.ops.config_collision_dist(hw);
1195 
1196 	ret_val = e1000_commit_fc_settings_generic(hw);
1197 	if (ret_val)
1198 		return ret_val;
1199 
1200 	/* Since auto-negotiation is enabled, take the link out of reset (the
1201 	 * link will be in reset, because we previously reset the chip). This
1202 	 * will restart auto-negotiation.  If auto-negotiation is successful
1203 	 * then the link-up status bit will be set and the flow control enable
1204 	 * bits (RFCE and TFCE) will be set according to their negotiated value.
1205 	 */
1206 	DEBUGOUT("Auto-negotiation enabled\n");
1207 
1208 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1209 	E1000_WRITE_FLUSH(hw);
1210 	msec_delay(1);
1211 
1212 	/* For these adapters, the SW definable pin 1 is set when the optics
1213 	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
1214 	 * indication.
1215 	 */
1216 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1217 	    (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1218 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1219 	} else {
1220 		DEBUGOUT("No signal detected\n");
1221 	}
1222 
1223 	return ret_val;
1224 }
1225 
1226 /**
1227  *  e1000_config_collision_dist_generic - Configure collision distance
1228  *  @hw: pointer to the HW structure
1229  *
1230  *  Configures the collision distance to the default value and is used
1231  *  during link setup.
1232  **/
e1000_config_collision_dist_generic(struct e1000_hw * hw)1233 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1234 {
1235 	u32 tctl;
1236 
1237 	DEBUGFUNC("e1000_config_collision_dist_generic");
1238 
1239 	tctl = E1000_READ_REG(hw, E1000_TCTL);
1240 
1241 	tctl &= ~E1000_TCTL_COLD;
1242 	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1243 
1244 	E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1245 	E1000_WRITE_FLUSH(hw);
1246 }
1247 
1248 /**
1249  *  e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1250  *  @hw: pointer to the HW structure
1251  *
1252  *  Sets the flow control high/low threshold (watermark) registers.  If
1253  *  flow control XON frame transmission is enabled, then set XON frame
1254  *  transmission as well.
1255  **/
e1000_set_fc_watermarks_generic(struct e1000_hw * hw)1256 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1257 {
1258 	u32 fcrtl = 0, fcrth = 0;
1259 
1260 	DEBUGFUNC("e1000_set_fc_watermarks_generic");
1261 
1262 	/* Set the flow control receive threshold registers.  Normally,
1263 	 * these registers will be set to a default threshold that may be
1264 	 * adjusted later by the driver's runtime code.  However, if the
1265 	 * ability to transmit pause frames is not enabled, then these
1266 	 * registers will be set to 0.
1267 	 */
1268 	if (hw->fc.current_mode & e1000_fc_tx_pause) {
1269 		/* We need to set up the Receive Threshold high and low water
1270 		 * marks as well as (optionally) enabling the transmission of
1271 		 * XON frames.
1272 		 */
1273 		fcrtl = hw->fc.low_water;
1274 		if (hw->fc.send_xon)
1275 			fcrtl |= E1000_FCRTL_XONE;
1276 
1277 		fcrth = hw->fc.high_water;
1278 	}
1279 	E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1280 	E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1281 
1282 	return E1000_SUCCESS;
1283 }
1284 
1285 /**
1286  *  e1000_force_mac_fc_generic - Force the MAC's flow control settings
1287  *  @hw: pointer to the HW structure
1288  *
1289  *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
1290  *  device control register to reflect the adapter settings.  TFCE and RFCE
1291  *  need to be explicitly set by software when a copper PHY is used because
1292  *  autonegotiation is managed by the PHY rather than the MAC.  Software must
1293  *  also configure these bits when link is forced on a fiber connection.
1294  **/
e1000_force_mac_fc_generic(struct e1000_hw * hw)1295 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1296 {
1297 	u32 ctrl;
1298 
1299 	DEBUGFUNC("e1000_force_mac_fc_generic");
1300 
1301 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1302 
1303 	/* Because we didn't get link via the internal auto-negotiation
1304 	 * mechanism (we either forced link or we got link via PHY
1305 	 * auto-neg), we have to manually enable/disable transmit an
1306 	 * receive flow control.
1307 	 *
1308 	 * The "Case" statement below enables/disable flow control
1309 	 * according to the "hw->fc.current_mode" parameter.
1310 	 *
1311 	 * The possible values of the "fc" parameter are:
1312 	 *      0:  Flow control is completely disabled
1313 	 *      1:  Rx flow control is enabled (we can receive pause
1314 	 *          frames but not send pause frames).
1315 	 *      2:  Tx flow control is enabled (we can send pause frames
1316 	 *          frames but we do not receive pause frames).
1317 	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
1318 	 *  other:  No other values should be possible at this point.
1319 	 */
1320 	DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1321 
1322 	switch (hw->fc.current_mode) {
1323 	case e1000_fc_none:
1324 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1325 		break;
1326 	case e1000_fc_rx_pause:
1327 		ctrl &= (~E1000_CTRL_TFCE);
1328 		ctrl |= E1000_CTRL_RFCE;
1329 		break;
1330 	case e1000_fc_tx_pause:
1331 		ctrl &= (~E1000_CTRL_RFCE);
1332 		ctrl |= E1000_CTRL_TFCE;
1333 		break;
1334 	case e1000_fc_full:
1335 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1336 		break;
1337 	default:
1338 		DEBUGOUT("Flow control param set incorrectly\n");
1339 		return -E1000_ERR_CONFIG;
1340 	}
1341 
1342 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1343 
1344 	return E1000_SUCCESS;
1345 }
1346 
1347 /**
1348  *  e1000_config_fc_after_link_up_generic - Configures flow control after link
1349  *  @hw: pointer to the HW structure
1350  *
1351  *  Checks the status of auto-negotiation after link up to ensure that the
1352  *  speed and duplex were not forced.  If the link needed to be forced, then
1353  *  flow control needs to be forced also.  If auto-negotiation is enabled
1354  *  and did not fail, then we configure flow control based on our link
1355  *  partner.
1356  **/
e1000_config_fc_after_link_up_generic(struct e1000_hw * hw)1357 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1358 {
1359 	struct e1000_mac_info *mac = &hw->mac;
1360 	s32 ret_val = E1000_SUCCESS;
1361 	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1362 	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1363 	u16 speed, duplex;
1364 
1365 	DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1366 
1367 	/* Check for the case where we have fiber media and auto-neg failed
1368 	 * so we had to force link.  In this case, we need to force the
1369 	 * configuration of the MAC to match the "fc" parameter.
1370 	 */
1371 	if (mac->autoneg_failed) {
1372 		if (hw->phy.media_type == e1000_media_type_fiber ||
1373 		    hw->phy.media_type == e1000_media_type_internal_serdes)
1374 			ret_val = e1000_force_mac_fc_generic(hw);
1375 	} else {
1376 		if (hw->phy.media_type == e1000_media_type_copper)
1377 			ret_val = e1000_force_mac_fc_generic(hw);
1378 	}
1379 
1380 	if (ret_val) {
1381 		DEBUGOUT("Error forcing flow control settings\n");
1382 		return ret_val;
1383 	}
1384 
1385 	/* Check for the case where we have copper media and auto-neg is
1386 	 * enabled.  In this case, we need to check and see if Auto-Neg
1387 	 * has completed, and if so, how the PHY and link partner has
1388 	 * flow control configured.
1389 	 */
1390 	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1391 		/* Read the MII Status Register and check to see if AutoNeg
1392 		 * has completed.  We read this twice because this reg has
1393 		 * some "sticky" (latched) bits.
1394 		 */
1395 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1396 		if (ret_val)
1397 			return ret_val;
1398 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1399 		if (ret_val)
1400 			return ret_val;
1401 
1402 		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1403 			DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1404 			return ret_val;
1405 		}
1406 
1407 		/* The AutoNeg process has completed, so we now need to
1408 		 * read both the Auto Negotiation Advertisement
1409 		 * Register (Address 4) and the Auto_Negotiation Base
1410 		 * Page Ability Register (Address 5) to determine how
1411 		 * flow control was negotiated.
1412 		 */
1413 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1414 					       &mii_nway_adv_reg);
1415 		if (ret_val)
1416 			return ret_val;
1417 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1418 					       &mii_nway_lp_ability_reg);
1419 		if (ret_val)
1420 			return ret_val;
1421 
1422 		/* Two bits in the Auto Negotiation Advertisement Register
1423 		 * (Address 4) and two bits in the Auto Negotiation Base
1424 		 * Page Ability Register (Address 5) determine flow control
1425 		 * for both the PHY and the link partner.  The following
1426 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1427 		 * 1999, describes these PAUSE resolution bits and how flow
1428 		 * control is determined based upon these settings.
1429 		 * NOTE:  DC = Don't Care
1430 		 *
1431 		 *   LOCAL DEVICE  |   LINK PARTNER
1432 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1433 		 *-------|---------|-------|---------|--------------------
1434 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1435 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1436 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1437 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1438 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1439 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1440 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1441 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1442 		 *
1443 		 * Are both PAUSE bits set to 1?  If so, this implies
1444 		 * Symmetric Flow Control is enabled at both ends.  The
1445 		 * ASM_DIR bits are irrelevant per the spec.
1446 		 *
1447 		 * For Symmetric Flow Control:
1448 		 *
1449 		 *   LOCAL DEVICE  |   LINK PARTNER
1450 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1451 		 *-------|---------|-------|---------|--------------------
1452 		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
1453 		 *
1454 		 */
1455 		if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1456 		    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1457 			/* Now we need to check if the user selected Rx ONLY
1458 			 * of pause frames.  In this case, we had to advertise
1459 			 * FULL flow control because we could not advertise Rx
1460 			 * ONLY. Hence, we must now check to see if we need to
1461 			 * turn OFF the TRANSMISSION of PAUSE frames.
1462 			 */
1463 			if (hw->fc.requested_mode == e1000_fc_full) {
1464 				hw->fc.current_mode = e1000_fc_full;
1465 				DEBUGOUT("Flow Control = FULL.\n");
1466 			} else {
1467 				hw->fc.current_mode = e1000_fc_rx_pause;
1468 				DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1469 			}
1470 		}
1471 		/* For receiving PAUSE frames ONLY.
1472 		 *
1473 		 *   LOCAL DEVICE  |   LINK PARTNER
1474 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1475 		 *-------|---------|-------|---------|--------------------
1476 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1477 		 */
1478 		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1479 			  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1480 			  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1481 			  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1482 			hw->fc.current_mode = e1000_fc_tx_pause;
1483 			DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1484 		}
1485 		/* For transmitting PAUSE frames ONLY.
1486 		 *
1487 		 *   LOCAL DEVICE  |   LINK PARTNER
1488 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1489 		 *-------|---------|-------|---------|--------------------
1490 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1491 		 */
1492 		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1493 			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1494 			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1495 			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1496 			hw->fc.current_mode = e1000_fc_rx_pause;
1497 			DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1498 		} else {
1499 			/* Per the IEEE spec, at this point flow control
1500 			 * should be disabled.
1501 			 */
1502 			hw->fc.current_mode = e1000_fc_none;
1503 			DEBUGOUT("Flow Control = NONE.\n");
1504 		}
1505 
1506 		/* Now we need to do one last check...  If we auto-
1507 		 * negotiated to HALF DUPLEX, flow control should not be
1508 		 * enabled per IEEE 802.3 spec.
1509 		 */
1510 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1511 		if (ret_val) {
1512 			DEBUGOUT("Error getting link speed and duplex\n");
1513 			return ret_val;
1514 		}
1515 
1516 		if (duplex == HALF_DUPLEX)
1517 			hw->fc.current_mode = e1000_fc_none;
1518 
1519 		/* Now we call a subroutine to actually force the MAC
1520 		 * controller to use the correct flow control settings.
1521 		 */
1522 		ret_val = e1000_force_mac_fc_generic(hw);
1523 		if (ret_val) {
1524 			DEBUGOUT("Error forcing flow control settings\n");
1525 			return ret_val;
1526 		}
1527 	}
1528 
1529 	/* Check for the case where we have SerDes media and auto-neg is
1530 	 * enabled.  In this case, we need to check and see if Auto-Neg
1531 	 * has completed, and if so, how the PHY and link partner has
1532 	 * flow control configured.
1533 	 */
1534 	if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1535 	    mac->autoneg) {
1536 		/* Read the PCS_LSTS and check to see if AutoNeg
1537 		 * has completed.
1538 		 */
1539 		pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1540 
1541 		if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1542 			DEBUGOUT("PCS Auto Neg has not completed.\n");
1543 			return ret_val;
1544 		}
1545 
1546 		/* The AutoNeg process has completed, so we now need to
1547 		 * read both the Auto Negotiation Advertisement
1548 		 * Register (PCS_ANADV) and the Auto_Negotiation Base
1549 		 * Page Ability Register (PCS_LPAB) to determine how
1550 		 * flow control was negotiated.
1551 		 */
1552 		pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1553 		pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1554 
1555 		/* Two bits in the Auto Negotiation Advertisement Register
1556 		 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1557 		 * Page Ability Register (PCS_LPAB) determine flow control
1558 		 * for both the PHY and the link partner.  The following
1559 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1560 		 * 1999, describes these PAUSE resolution bits and how flow
1561 		 * control is determined based upon these settings.
1562 		 * NOTE:  DC = Don't Care
1563 		 *
1564 		 *   LOCAL DEVICE  |   LINK PARTNER
1565 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1566 		 *-------|---------|-------|---------|--------------------
1567 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1568 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1569 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1570 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1571 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1572 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1573 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1574 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1575 		 *
1576 		 * Are both PAUSE bits set to 1?  If so, this implies
1577 		 * Symmetric Flow Control is enabled at both ends.  The
1578 		 * ASM_DIR bits are irrelevant per the spec.
1579 		 *
1580 		 * For Symmetric Flow Control:
1581 		 *
1582 		 *   LOCAL DEVICE  |   LINK PARTNER
1583 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1584 		 *-------|---------|-------|---------|--------------------
1585 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1586 		 *
1587 		 */
1588 		if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1589 		    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1590 			/* Now we need to check if the user selected Rx ONLY
1591 			 * of pause frames.  In this case, we had to advertise
1592 			 * FULL flow control because we could not advertise Rx
1593 			 * ONLY. Hence, we must now check to see if we need to
1594 			 * turn OFF the TRANSMISSION of PAUSE frames.
1595 			 */
1596 			if (hw->fc.requested_mode == e1000_fc_full) {
1597 				hw->fc.current_mode = e1000_fc_full;
1598 				DEBUGOUT("Flow Control = FULL.\n");
1599 			} else {
1600 				hw->fc.current_mode = e1000_fc_rx_pause;
1601 				DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1602 			}
1603 		}
1604 		/* For receiving PAUSE frames ONLY.
1605 		 *
1606 		 *   LOCAL DEVICE  |   LINK PARTNER
1607 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1608 		 *-------|---------|-------|---------|--------------------
1609 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1610 		 */
1611 		else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1612 			  (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1613 			  (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1614 			  (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1615 			hw->fc.current_mode = e1000_fc_tx_pause;
1616 			DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1617 		}
1618 		/* For transmitting PAUSE frames ONLY.
1619 		 *
1620 		 *   LOCAL DEVICE  |   LINK PARTNER
1621 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1622 		 *-------|---------|-------|---------|--------------------
1623 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1624 		 */
1625 		else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1626 			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1627 			 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1628 			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1629 			hw->fc.current_mode = e1000_fc_rx_pause;
1630 			DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1631 		} else {
1632 			/* Per the IEEE spec, at this point flow control
1633 			 * should be disabled.
1634 			 */
1635 			hw->fc.current_mode = e1000_fc_none;
1636 			DEBUGOUT("Flow Control = NONE.\n");
1637 		}
1638 
1639 		/* Now we call a subroutine to actually force the MAC
1640 		 * controller to use the correct flow control settings.
1641 		 */
1642 		pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1643 		pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1644 		E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1645 
1646 		ret_val = e1000_force_mac_fc_generic(hw);
1647 		if (ret_val) {
1648 			DEBUGOUT("Error forcing flow control settings\n");
1649 			return ret_val;
1650 		}
1651 	}
1652 
1653 	return E1000_SUCCESS;
1654 }
1655 
1656 /**
1657  *  e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1658  *  @hw: pointer to the HW structure
1659  *  @speed: stores the current speed
1660  *  @duplex: stores the current duplex
1661  *
1662  *  Read the status register for the current speed/duplex and store the current
1663  *  speed and duplex for copper connections.
1664  **/
e1000_get_speed_and_duplex_copper_generic(struct e1000_hw * hw,u16 * speed,u16 * duplex)1665 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1666 					      u16 *duplex)
1667 {
1668 	u32 status;
1669 
1670 	DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1671 
1672 	status = E1000_READ_REG(hw, E1000_STATUS);
1673 	if (status & E1000_STATUS_SPEED_1000) {
1674 		*speed = SPEED_1000;
1675 		DEBUGOUT("1000 Mbs, ");
1676 	} else if (status & E1000_STATUS_SPEED_100) {
1677 		*speed = SPEED_100;
1678 		DEBUGOUT("100 Mbs, ");
1679 	} else {
1680 		*speed = SPEED_10;
1681 		DEBUGOUT("10 Mbs, ");
1682 	}
1683 
1684 	if (status & E1000_STATUS_FD) {
1685 		*duplex = FULL_DUPLEX;
1686 		DEBUGOUT("Full Duplex\n");
1687 	} else {
1688 		*duplex = HALF_DUPLEX;
1689 		DEBUGOUT("Half Duplex\n");
1690 	}
1691 
1692 	return E1000_SUCCESS;
1693 }
1694 
1695 /**
1696  *  e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1697  *  @hw: pointer to the HW structure
1698  *  @speed: stores the current speed
1699  *  @duplex: stores the current duplex
1700  *
1701  *  Sets the speed and duplex to gigabit full duplex (the only possible option)
1702  *  for fiber/serdes links.
1703  **/
e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG * hw,u16 * speed,u16 * duplex)1704 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1705 						    u16 *speed, u16 *duplex)
1706 {
1707 	DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1708 
1709 	*speed = SPEED_1000;
1710 	*duplex = FULL_DUPLEX;
1711 
1712 	return E1000_SUCCESS;
1713 }
1714 
1715 /**
1716  *  e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1717  *  @hw: pointer to the HW structure
1718  *
1719  *  Acquire the HW semaphore to access the PHY or NVM
1720  **/
e1000_get_hw_semaphore_generic(struct e1000_hw * hw)1721 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1722 {
1723 	u32 swsm;
1724 	s32 timeout = hw->nvm.word_size + 1;
1725 	s32 i = 0;
1726 
1727 	DEBUGFUNC("e1000_get_hw_semaphore_generic");
1728 
1729 	/* Get the SW semaphore */
1730 	while (i < timeout) {
1731 		swsm = E1000_READ_REG(hw, E1000_SWSM);
1732 		if (!(swsm & E1000_SWSM_SMBI))
1733 			break;
1734 
1735 		usec_delay(50);
1736 		i++;
1737 	}
1738 
1739 	if (i == timeout) {
1740 		DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1741 		return -E1000_ERR_NVM;
1742 	}
1743 
1744 	/* Get the FW semaphore. */
1745 	for (i = 0; i < timeout; i++) {
1746 		swsm = E1000_READ_REG(hw, E1000_SWSM);
1747 		E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1748 
1749 		/* Semaphore acquired if bit latched */
1750 		if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1751 			break;
1752 
1753 		usec_delay(50);
1754 	}
1755 
1756 	if (i == timeout) {
1757 		/* Release semaphores */
1758 		e1000_put_hw_semaphore_generic(hw);
1759 		DEBUGOUT("Driver can't access the NVM\n");
1760 		return -E1000_ERR_NVM;
1761 	}
1762 
1763 	return E1000_SUCCESS;
1764 }
1765 
1766 /**
1767  *  e1000_put_hw_semaphore_generic - Release hardware semaphore
1768  *  @hw: pointer to the HW structure
1769  *
1770  *  Release hardware semaphore used to access the PHY or NVM
1771  **/
e1000_put_hw_semaphore_generic(struct e1000_hw * hw)1772 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1773 {
1774 	u32 swsm;
1775 
1776 	DEBUGFUNC("e1000_put_hw_semaphore_generic");
1777 
1778 	swsm = E1000_READ_REG(hw, E1000_SWSM);
1779 
1780 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1781 
1782 	E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1783 }
1784 
1785 /**
1786  *  e1000_get_auto_rd_done_generic - Check for auto read completion
1787  *  @hw: pointer to the HW structure
1788  *
1789  *  Check EEPROM for Auto Read done bit.
1790  **/
e1000_get_auto_rd_done_generic(struct e1000_hw * hw)1791 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1792 {
1793 	s32 i = 0;
1794 
1795 	DEBUGFUNC("e1000_get_auto_rd_done_generic");
1796 
1797 	while (i < AUTO_READ_DONE_TIMEOUT) {
1798 		if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1799 			break;
1800 		msec_delay(1);
1801 		i++;
1802 	}
1803 
1804 	if (i == AUTO_READ_DONE_TIMEOUT) {
1805 		DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1806 		return -E1000_ERR_RESET;
1807 	}
1808 
1809 	return E1000_SUCCESS;
1810 }
1811 
1812 /**
1813  *  e1000_valid_led_default_generic - Verify a valid default LED config
1814  *  @hw: pointer to the HW structure
1815  *  @data: pointer to the NVM (EEPROM)
1816  *
1817  *  Read the EEPROM for the current default LED configuration.  If the
1818  *  LED configuration is not valid, set to a valid LED configuration.
1819  **/
e1000_valid_led_default_generic(struct e1000_hw * hw,u16 * data)1820 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1821 {
1822 	s32 ret_val;
1823 
1824 	DEBUGFUNC("e1000_valid_led_default_generic");
1825 
1826 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1827 	if (ret_val) {
1828 		DEBUGOUT("NVM Read Error\n");
1829 		return ret_val;
1830 	}
1831 
1832 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1833 		*data = ID_LED_DEFAULT;
1834 
1835 	return E1000_SUCCESS;
1836 }
1837 
1838 /**
1839  *  e1000_id_led_init_generic -
1840  *  @hw: pointer to the HW structure
1841  *
1842  **/
e1000_id_led_init_generic(struct e1000_hw * hw)1843 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1844 {
1845 	struct e1000_mac_info *mac = &hw->mac;
1846 	s32 ret_val;
1847 	const u32 ledctl_mask = 0x000000FF;
1848 	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1849 	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1850 	u16 data, i, temp;
1851 	const u16 led_mask = 0x0F;
1852 
1853 	DEBUGFUNC("e1000_id_led_init_generic");
1854 
1855 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1856 	if (ret_val)
1857 		return ret_val;
1858 
1859 	mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1860 	mac->ledctl_mode1 = mac->ledctl_default;
1861 	mac->ledctl_mode2 = mac->ledctl_default;
1862 
1863 	for (i = 0; i < 4; i++) {
1864 		temp = (data >> (i << 2)) & led_mask;
1865 		switch (temp) {
1866 		case ID_LED_ON1_DEF2:
1867 		case ID_LED_ON1_ON2:
1868 		case ID_LED_ON1_OFF2:
1869 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1870 			mac->ledctl_mode1 |= ledctl_on << (i << 3);
1871 			break;
1872 		case ID_LED_OFF1_DEF2:
1873 		case ID_LED_OFF1_ON2:
1874 		case ID_LED_OFF1_OFF2:
1875 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1876 			mac->ledctl_mode1 |= ledctl_off << (i << 3);
1877 			break;
1878 		default:
1879 			/* Do nothing */
1880 			break;
1881 		}
1882 		switch (temp) {
1883 		case ID_LED_DEF1_ON2:
1884 		case ID_LED_ON1_ON2:
1885 		case ID_LED_OFF1_ON2:
1886 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1887 			mac->ledctl_mode2 |= ledctl_on << (i << 3);
1888 			break;
1889 		case ID_LED_DEF1_OFF2:
1890 		case ID_LED_ON1_OFF2:
1891 		case ID_LED_OFF1_OFF2:
1892 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1893 			mac->ledctl_mode2 |= ledctl_off << (i << 3);
1894 			break;
1895 		default:
1896 			/* Do nothing */
1897 			break;
1898 		}
1899 	}
1900 
1901 	return E1000_SUCCESS;
1902 }
1903 
1904 /**
1905  *  e1000_setup_led_generic - Configures SW controllable LED
1906  *  @hw: pointer to the HW structure
1907  *
1908  *  This prepares the SW controllable LED for use and saves the current state
1909  *  of the LED so it can be later restored.
1910  **/
e1000_setup_led_generic(struct e1000_hw * hw)1911 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1912 {
1913 	u32 ledctl;
1914 
1915 	DEBUGFUNC("e1000_setup_led_generic");
1916 
1917 	if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1918 		return -E1000_ERR_CONFIG;
1919 
1920 	if (hw->phy.media_type == e1000_media_type_fiber) {
1921 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1922 		hw->mac.ledctl_default = ledctl;
1923 		/* Turn off LED0 */
1924 		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1925 			    E1000_LEDCTL_LED0_MODE_MASK);
1926 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1927 			   E1000_LEDCTL_LED0_MODE_SHIFT);
1928 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1929 	} else if (hw->phy.media_type == e1000_media_type_copper) {
1930 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1931 	}
1932 
1933 	return E1000_SUCCESS;
1934 }
1935 
1936 /**
1937  *  e1000_cleanup_led_generic - Set LED config to default operation
1938  *  @hw: pointer to the HW structure
1939  *
1940  *  Remove the current LED configuration and set the LED configuration
1941  *  to the default value, saved from the EEPROM.
1942  **/
e1000_cleanup_led_generic(struct e1000_hw * hw)1943 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1944 {
1945 	DEBUGFUNC("e1000_cleanup_led_generic");
1946 
1947 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1948 	return E1000_SUCCESS;
1949 }
1950 
1951 /**
1952  *  e1000_blink_led_generic - Blink LED
1953  *  @hw: pointer to the HW structure
1954  *
1955  *  Blink the LEDs which are set to be on.
1956  **/
e1000_blink_led_generic(struct e1000_hw * hw)1957 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1958 {
1959 	u32 ledctl_blink = 0;
1960 	u32 i;
1961 
1962 	DEBUGFUNC("e1000_blink_led_generic");
1963 
1964 	if (hw->phy.media_type == e1000_media_type_fiber) {
1965 		/* always blink LED0 for PCI-E fiber */
1966 		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1967 		     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1968 	} else {
1969 		/* Set the blink bit for each LED that's "on" (0x0E)
1970 		 * (or "off" if inverted) in ledctl_mode2.  The blink
1971 		 * logic in hardware only works when mode is set to "on"
1972 		 * so it must be changed accordingly when the mode is
1973 		 * "off" and inverted.
1974 		 */
1975 		ledctl_blink = hw->mac.ledctl_mode2;
1976 		for (i = 0; i < 32; i += 8) {
1977 			u32 mode = (hw->mac.ledctl_mode2 >> i) &
1978 			    E1000_LEDCTL_LED0_MODE_MASK;
1979 			u32 led_default = hw->mac.ledctl_default >> i;
1980 
1981 			if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1982 			     (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1983 			    ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1984 			     (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1985 				ledctl_blink &=
1986 				    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1987 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1988 						 E1000_LEDCTL_MODE_LED_ON) << i;
1989 			}
1990 		}
1991 	}
1992 
1993 	E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1994 
1995 	return E1000_SUCCESS;
1996 }
1997 
1998 /**
1999  *  e1000_led_on_generic - Turn LED on
2000  *  @hw: pointer to the HW structure
2001  *
2002  *  Turn LED on.
2003  **/
e1000_led_on_generic(struct e1000_hw * hw)2004 s32 e1000_led_on_generic(struct e1000_hw *hw)
2005 {
2006 	u32 ctrl;
2007 
2008 	DEBUGFUNC("e1000_led_on_generic");
2009 
2010 	switch (hw->phy.media_type) {
2011 	case e1000_media_type_fiber:
2012 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
2013 		ctrl &= ~E1000_CTRL_SWDPIN0;
2014 		ctrl |= E1000_CTRL_SWDPIO0;
2015 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2016 		break;
2017 	case e1000_media_type_copper:
2018 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2019 		break;
2020 	default:
2021 		break;
2022 	}
2023 
2024 	return E1000_SUCCESS;
2025 }
2026 
2027 /**
2028  *  e1000_led_off_generic - Turn LED off
2029  *  @hw: pointer to the HW structure
2030  *
2031  *  Turn LED off.
2032  **/
e1000_led_off_generic(struct e1000_hw * hw)2033 s32 e1000_led_off_generic(struct e1000_hw *hw)
2034 {
2035 	u32 ctrl;
2036 
2037 	DEBUGFUNC("e1000_led_off_generic");
2038 
2039 	switch (hw->phy.media_type) {
2040 	case e1000_media_type_fiber:
2041 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
2042 		ctrl |= E1000_CTRL_SWDPIN0;
2043 		ctrl |= E1000_CTRL_SWDPIO0;
2044 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2045 		break;
2046 	case e1000_media_type_copper:
2047 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2048 		break;
2049 	default:
2050 		break;
2051 	}
2052 
2053 	return E1000_SUCCESS;
2054 }
2055 
2056 /**
2057  *  e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2058  *  @hw: pointer to the HW structure
2059  *  @no_snoop: bitmap of snoop events
2060  *
2061  *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2062  **/
e1000_set_pcie_no_snoop_generic(struct e1000_hw * hw,u32 no_snoop)2063 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2064 {
2065 	u32 gcr;
2066 
2067 	DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2068 
2069 	if (hw->bus.type != e1000_bus_type_pci_express)
2070 		return;
2071 
2072 	if (no_snoop) {
2073 		gcr = E1000_READ_REG(hw, E1000_GCR);
2074 		gcr &= ~(PCIE_NO_SNOOP_ALL);
2075 		gcr |= no_snoop;
2076 		E1000_WRITE_REG(hw, E1000_GCR, gcr);
2077 	}
2078 }
2079 
2080 /**
2081  *  e1000_disable_pcie_master_generic - Disables PCI-express master access
2082  *  @hw: pointer to the HW structure
2083  *
2084  *  Returns E1000_SUCCESS if successful, else returns -10
2085  *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2086  *  the master requests to be disabled.
2087  *
2088  *  Disables PCI-Express master access and verifies there are no pending
2089  *  requests.
2090  **/
e1000_disable_pcie_master_generic(struct e1000_hw * hw)2091 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2092 {
2093 	u32 ctrl;
2094 	s32 timeout = MASTER_DISABLE_TIMEOUT;
2095 
2096 	DEBUGFUNC("e1000_disable_pcie_master_generic");
2097 
2098 	if (hw->bus.type != e1000_bus_type_pci_express)
2099 		return E1000_SUCCESS;
2100 
2101 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
2102 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2103 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2104 
2105 	while (timeout) {
2106 		if (!(E1000_READ_REG(hw, E1000_STATUS) &
2107 		      E1000_STATUS_GIO_MASTER_ENABLE) ||
2108 				E1000_REMOVED(hw->hw_addr))
2109 			break;
2110 		usec_delay(100);
2111 		timeout--;
2112 	}
2113 
2114 	if (!timeout) {
2115 		DEBUGOUT("Master requests are pending.\n");
2116 		return -E1000_ERR_MASTER_REQUESTS_PENDING;
2117 	}
2118 
2119 	return E1000_SUCCESS;
2120 }
2121 
2122 /**
2123  *  e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2124  *  @hw: pointer to the HW structure
2125  *
2126  *  Reset the Adaptive Interframe Spacing throttle to default values.
2127  **/
e1000_reset_adaptive_generic(struct e1000_hw * hw)2128 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2129 {
2130 	struct e1000_mac_info *mac = &hw->mac;
2131 
2132 	DEBUGFUNC("e1000_reset_adaptive_generic");
2133 
2134 	if (!mac->adaptive_ifs) {
2135 		DEBUGOUT("Not in Adaptive IFS mode!\n");
2136 		return;
2137 	}
2138 
2139 	mac->current_ifs_val = 0;
2140 	mac->ifs_min_val = IFS_MIN;
2141 	mac->ifs_max_val = IFS_MAX;
2142 	mac->ifs_step_size = IFS_STEP;
2143 	mac->ifs_ratio = IFS_RATIO;
2144 
2145 	mac->in_ifs_mode = FALSE;
2146 	E1000_WRITE_REG(hw, E1000_AIT, 0);
2147 }
2148 
2149 /**
2150  *  e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2151  *  @hw: pointer to the HW structure
2152  *
2153  *  Update the Adaptive Interframe Spacing Throttle value based on the
2154  *  time between transmitted packets and time between collisions.
2155  **/
e1000_update_adaptive_generic(struct e1000_hw * hw)2156 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2157 {
2158 	struct e1000_mac_info *mac = &hw->mac;
2159 
2160 	DEBUGFUNC("e1000_update_adaptive_generic");
2161 
2162 	if (!mac->adaptive_ifs) {
2163 		DEBUGOUT("Not in Adaptive IFS mode!\n");
2164 		return;
2165 	}
2166 
2167 	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2168 		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2169 			mac->in_ifs_mode = TRUE;
2170 			if (mac->current_ifs_val < mac->ifs_max_val) {
2171 				if (!mac->current_ifs_val)
2172 					mac->current_ifs_val = mac->ifs_min_val;
2173 				else
2174 					mac->current_ifs_val +=
2175 						mac->ifs_step_size;
2176 				E1000_WRITE_REG(hw, E1000_AIT,
2177 						mac->current_ifs_val);
2178 			}
2179 		}
2180 	} else {
2181 		if (mac->in_ifs_mode &&
2182 		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2183 			mac->current_ifs_val = 0;
2184 			mac->in_ifs_mode = FALSE;
2185 			E1000_WRITE_REG(hw, E1000_AIT, 0);
2186 		}
2187 	}
2188 }
2189 
2190 /**
2191  *  e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2192  *  @hw: pointer to the HW structure
2193  *
2194  *  Verify that when not using auto-negotiation that MDI/MDIx is correctly
2195  *  set, which is forced to MDI mode only.
2196  **/
e1000_validate_mdi_setting_generic(struct e1000_hw * hw)2197 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2198 {
2199 	DEBUGFUNC("e1000_validate_mdi_setting_generic");
2200 
2201 	if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2202 		DEBUGOUT("Invalid MDI setting detected\n");
2203 		hw->phy.mdix = 1;
2204 		return -E1000_ERR_CONFIG;
2205 	}
2206 
2207 	return E1000_SUCCESS;
2208 }
2209 
2210 /**
2211  *  e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2212  *  @hw: pointer to the HW structure
2213  *
2214  *  Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2215  *  operation.
2216  **/
e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG * hw)2217 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2218 {
2219 	DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2220 
2221 	return E1000_SUCCESS;
2222 }
2223 
2224 /**
2225  *  e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2226  *  @hw: pointer to the HW structure
2227  *  @reg: 32bit register offset such as E1000_SCTL
2228  *  @offset: register offset to write to
2229  *  @data: data to write at register offset
2230  *
2231  *  Writes an address/data control type register.  There are several of these
2232  *  and they all have the format address << 8 | data and bit 31 is polled for
2233  *  completion.
2234  **/
e1000_write_8bit_ctrl_reg_generic(struct e1000_hw * hw,u32 reg,u32 offset,u8 data)2235 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2236 				      u32 offset, u8 data)
2237 {
2238 	u32 i, regvalue = 0;
2239 
2240 	DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2241 
2242 	/* Set up the address and data */
2243 	regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2244 	E1000_WRITE_REG(hw, reg, regvalue);
2245 
2246 	/* Poll the ready bit to see if the MDI read completed */
2247 	for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2248 		usec_delay(5);
2249 		regvalue = E1000_READ_REG(hw, reg);
2250 		if (regvalue & E1000_GEN_CTL_READY)
2251 			break;
2252 	}
2253 	if (!(regvalue & E1000_GEN_CTL_READY)) {
2254 		DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2255 		return -E1000_ERR_PHY;
2256 	}
2257 
2258 	return E1000_SUCCESS;
2259 }
2260