xref: /dragonfly/contrib/gdb-7/gdb/amd64-tdep.c (revision ef5ccd6c)
1 /* Target-dependent code for AMD64.
2 
3    Copyright (C) 2001-2013 Free Software Foundation, Inc.
4 
5    Contributed by Jiri Smid, SuSE Labs.
6 
7    This file is part of GDB.
8 
9    This program is free software; you can redistribute it and/or modify
10    it under the terms of the GNU General Public License as published by
11    the Free Software Foundation; either version 3 of the License, or
12    (at your option) any later version.
13 
14    This program is distributed in the hope that it will be useful,
15    but WITHOUT ANY WARRANTY; without even the implied warranty of
16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17    GNU General Public License for more details.
18 
19    You should have received a copy of the GNU General Public License
20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21 
22 #include "defs.h"
23 #include "opcode/i386.h"
24 #include "dis-asm.h"
25 #include "arch-utils.h"
26 #include "block.h"
27 #include "dummy-frame.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "inferior.h"
32 #include "gdbcmd.h"
33 #include "gdbcore.h"
34 #include "objfiles.h"
35 #include "regcache.h"
36 #include "regset.h"
37 #include "symfile.h"
38 #include "disasm.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
43 
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
48 
49 #include "ax.h"
50 #include "ax-gdb.h"
51 
52 /* Note that the AMD64 architecture was previously known as x86-64.
53    The latter is (forever) engraved into the canonical system name as
54    returned by config.guess, and used as the name for the AMD64 port
55    of GNU/Linux.  The BSD's have renamed their ports to amd64; they
56    don't like to shout.  For GDB we prefer the amd64_-prefix over the
57    x86_64_-prefix since it's so much easier to type.  */
58 
59 /* Register information.  */
60 
61 static const char *amd64_register_names[] =
62 {
63   "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
64 
65   /* %r8 is indeed register number 8.  */
66   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67   "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
68 
69   /* %st0 is register number 24.  */
70   "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71   "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
72 
73   /* %xmm0 is register number 40.  */
74   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
76   "mxcsr",
77 };
78 
79 static const char *amd64_ymm_names[] =
80 {
81   "ymm0", "ymm1", "ymm2", "ymm3",
82   "ymm4", "ymm5", "ymm6", "ymm7",
83   "ymm8", "ymm9", "ymm10", "ymm11",
84   "ymm12", "ymm13", "ymm14", "ymm15"
85 };
86 
87 static const char *amd64_ymmh_names[] =
88 {
89   "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90   "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91   "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92   "ymm12h", "ymm13h", "ymm14h", "ymm15h"
93 };
94 
95 /* The registers used to pass integer arguments during a function call.  */
96 static int amd64_dummy_call_integer_regs[] =
97 {
98   AMD64_RDI_REGNUM,		/* %rdi */
99   AMD64_RSI_REGNUM,		/* %rsi */
100   AMD64_RDX_REGNUM,		/* %rdx */
101   AMD64_RCX_REGNUM,		/* %rcx */
102   8,				/* %r8 */
103   9				/* %r9 */
104 };
105 
106 /* DWARF Register Number Mapping as defined in the System V psABI,
107    section 3.6.  */
108 
109 static int amd64_dwarf_regmap[] =
110 {
111   /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI.  */
112   AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
113   AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
114   AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
115 
116   /* Frame Pointer Register RBP.  */
117   AMD64_RBP_REGNUM,
118 
119   /* Stack Pointer Register RSP.  */
120   AMD64_RSP_REGNUM,
121 
122   /* Extended Integer Registers 8 - 15.  */
123   8, 9, 10, 11, 12, 13, 14, 15,
124 
125   /* Return Address RA.  Mapped to RIP.  */
126   AMD64_RIP_REGNUM,
127 
128   /* SSE Registers 0 - 7.  */
129   AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
130   AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
131   AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
132   AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
133 
134   /* Extended SSE Registers 8 - 15.  */
135   AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
136   AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
137   AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
138   AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
139 
140   /* Floating Point Registers 0-7.  */
141   AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
142   AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
143   AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
144   AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
145 
146   /* Control and Status Flags Register.  */
147   AMD64_EFLAGS_REGNUM,
148 
149   /* Selector Registers.  */
150   AMD64_ES_REGNUM,
151   AMD64_CS_REGNUM,
152   AMD64_SS_REGNUM,
153   AMD64_DS_REGNUM,
154   AMD64_FS_REGNUM,
155   AMD64_GS_REGNUM,
156   -1,
157   -1,
158 
159   /* Segment Base Address Registers.  */
160   -1,
161   -1,
162   -1,
163   -1,
164 
165   /* Special Selector Registers.  */
166   -1,
167   -1,
168 
169   /* Floating Point Control Registers.  */
170   AMD64_MXCSR_REGNUM,
171   AMD64_FCTRL_REGNUM,
172   AMD64_FSTAT_REGNUM
173 };
174 
175 static const int amd64_dwarf_regmap_len =
176   (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
177 
178 /* Convert DWARF register number REG to the appropriate register
179    number used by GDB.  */
180 
181 static int
amd64_dwarf_reg_to_regnum(struct gdbarch * gdbarch,int reg)182 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
183 {
184   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
185   int ymm0_regnum = tdep->ymm0_regnum;
186   int regnum = -1;
187 
188   if (reg >= 0 && reg < amd64_dwarf_regmap_len)
189     regnum = amd64_dwarf_regmap[reg];
190 
191   if (regnum == -1)
192     warning (_("Unmapped DWARF Register #%d encountered."), reg);
193   else if (ymm0_regnum >= 0
194 	   && i386_xmm_regnum_p (gdbarch, regnum))
195     regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
196 
197   return regnum;
198 }
199 
200 /* Map architectural register numbers to gdb register numbers.  */
201 
202 static const int amd64_arch_regmap[16] =
203 {
204   AMD64_RAX_REGNUM,	/* %rax */
205   AMD64_RCX_REGNUM,	/* %rcx */
206   AMD64_RDX_REGNUM,	/* %rdx */
207   AMD64_RBX_REGNUM,	/* %rbx */
208   AMD64_RSP_REGNUM,	/* %rsp */
209   AMD64_RBP_REGNUM,	/* %rbp */
210   AMD64_RSI_REGNUM,	/* %rsi */
211   AMD64_RDI_REGNUM,	/* %rdi */
212   AMD64_R8_REGNUM,	/* %r8 */
213   AMD64_R9_REGNUM,	/* %r9 */
214   AMD64_R10_REGNUM,	/* %r10 */
215   AMD64_R11_REGNUM,	/* %r11 */
216   AMD64_R12_REGNUM,	/* %r12 */
217   AMD64_R13_REGNUM,	/* %r13 */
218   AMD64_R14_REGNUM,	/* %r14 */
219   AMD64_R15_REGNUM	/* %r15 */
220 };
221 
222 static const int amd64_arch_regmap_len =
223   (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
224 
225 /* Convert architectural register number REG to the appropriate register
226    number used by GDB.  */
227 
228 static int
amd64_arch_reg_to_regnum(int reg)229 amd64_arch_reg_to_regnum (int reg)
230 {
231   gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
232 
233   return amd64_arch_regmap[reg];
234 }
235 
236 /* Register names for byte pseudo-registers.  */
237 
238 static const char *amd64_byte_names[] =
239 {
240   "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
241   "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
242   "ah", "bh", "ch", "dh"
243 };
244 
245 /* Number of lower byte registers.  */
246 #define AMD64_NUM_LOWER_BYTE_REGS 16
247 
248 /* Register names for word pseudo-registers.  */
249 
250 static const char *amd64_word_names[] =
251 {
252   "ax", "bx", "cx", "dx", "si", "di", "bp", "",
253   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
254 };
255 
256 /* Register names for dword pseudo-registers.  */
257 
258 static const char *amd64_dword_names[] =
259 {
260   "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
261   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
262   "eip"
263 };
264 
265 /* Return the name of register REGNUM.  */
266 
267 static const char *
amd64_pseudo_register_name(struct gdbarch * gdbarch,int regnum)268 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
269 {
270   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
271   if (i386_byte_regnum_p (gdbarch, regnum))
272     return amd64_byte_names[regnum - tdep->al_regnum];
273   else if (i386_ymm_regnum_p (gdbarch, regnum))
274     return amd64_ymm_names[regnum - tdep->ymm0_regnum];
275   else if (i386_word_regnum_p (gdbarch, regnum))
276     return amd64_word_names[regnum - tdep->ax_regnum];
277   else if (i386_dword_regnum_p (gdbarch, regnum))
278     return amd64_dword_names[regnum - tdep->eax_regnum];
279   else
280     return i386_pseudo_register_name (gdbarch, regnum);
281 }
282 
283 static struct value *
amd64_pseudo_register_read_value(struct gdbarch * gdbarch,struct regcache * regcache,int regnum)284 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
285 				  struct regcache *regcache,
286 				  int regnum)
287 {
288   gdb_byte raw_buf[MAX_REGISTER_SIZE];
289   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
290   enum register_status status;
291   struct value *result_value;
292   gdb_byte *buf;
293 
294   result_value = allocate_value (register_type (gdbarch, regnum));
295   VALUE_LVAL (result_value) = lval_register;
296   VALUE_REGNUM (result_value) = regnum;
297   buf = value_contents_raw (result_value);
298 
299   if (i386_byte_regnum_p (gdbarch, regnum))
300     {
301       int gpnum = regnum - tdep->al_regnum;
302 
303       /* Extract (always little endian).  */
304       if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
305 	{
306 	  /* Special handling for AH, BH, CH, DH.  */
307 	  status = regcache_raw_read (regcache,
308 				      gpnum - AMD64_NUM_LOWER_BYTE_REGS,
309 				      raw_buf);
310 	  if (status == REG_VALID)
311 	    memcpy (buf, raw_buf + 1, 1);
312 	  else
313 	    mark_value_bytes_unavailable (result_value, 0,
314 					  TYPE_LENGTH (value_type (result_value)));
315 	}
316       else
317 	{
318 	  status = regcache_raw_read (regcache, gpnum, raw_buf);
319 	  if (status == REG_VALID)
320 	    memcpy (buf, raw_buf, 1);
321 	  else
322 	    mark_value_bytes_unavailable (result_value, 0,
323 					  TYPE_LENGTH (value_type (result_value)));
324 	}
325     }
326   else if (i386_dword_regnum_p (gdbarch, regnum))
327     {
328       int gpnum = regnum - tdep->eax_regnum;
329       /* Extract (always little endian).  */
330       status = regcache_raw_read (regcache, gpnum, raw_buf);
331       if (status == REG_VALID)
332 	memcpy (buf, raw_buf, 4);
333       else
334 	mark_value_bytes_unavailable (result_value, 0,
335 				      TYPE_LENGTH (value_type (result_value)));
336     }
337   else
338     i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
339 					  result_value);
340 
341   return result_value;
342 }
343 
344 static void
amd64_pseudo_register_write(struct gdbarch * gdbarch,struct regcache * regcache,int regnum,const gdb_byte * buf)345 amd64_pseudo_register_write (struct gdbarch *gdbarch,
346 			     struct regcache *regcache,
347 			     int regnum, const gdb_byte *buf)
348 {
349   gdb_byte raw_buf[MAX_REGISTER_SIZE];
350   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
351 
352   if (i386_byte_regnum_p (gdbarch, regnum))
353     {
354       int gpnum = regnum - tdep->al_regnum;
355 
356       if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
357 	{
358 	  /* Read ... AH, BH, CH, DH.  */
359 	  regcache_raw_read (regcache,
360 			     gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
361 	  /* ... Modify ... (always little endian).  */
362 	  memcpy (raw_buf + 1, buf, 1);
363 	  /* ... Write.  */
364 	  regcache_raw_write (regcache,
365 			      gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
366 	}
367       else
368 	{
369 	  /* Read ...  */
370 	  regcache_raw_read (regcache, gpnum, raw_buf);
371 	  /* ... Modify ... (always little endian).  */
372 	  memcpy (raw_buf, buf, 1);
373 	  /* ... Write.  */
374 	  regcache_raw_write (regcache, gpnum, raw_buf);
375 	}
376     }
377   else if (i386_dword_regnum_p (gdbarch, regnum))
378     {
379       int gpnum = regnum - tdep->eax_regnum;
380 
381       /* Read ...  */
382       regcache_raw_read (regcache, gpnum, raw_buf);
383       /* ... Modify ... (always little endian).  */
384       memcpy (raw_buf, buf, 4);
385       /* ... Write.  */
386       regcache_raw_write (regcache, gpnum, raw_buf);
387     }
388   else
389     i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
390 }
391 
392 
393 
394 /* Return the union class of CLASS1 and CLASS2.  See the psABI for
395    details.  */
396 
397 static enum amd64_reg_class
amd64_merge_classes(enum amd64_reg_class class1,enum amd64_reg_class class2)398 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
399 {
400   /* Rule (a): If both classes are equal, this is the resulting class.  */
401   if (class1 == class2)
402     return class1;
403 
404   /* Rule (b): If one of the classes is NO_CLASS, the resulting class
405      is the other class.  */
406   if (class1 == AMD64_NO_CLASS)
407     return class2;
408   if (class2 == AMD64_NO_CLASS)
409     return class1;
410 
411   /* Rule (c): If one of the classes is MEMORY, the result is MEMORY.  */
412   if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
413     return AMD64_MEMORY;
414 
415   /* Rule (d): If one of the classes is INTEGER, the result is INTEGER.  */
416   if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
417     return AMD64_INTEGER;
418 
419   /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
420      MEMORY is used as class.  */
421   if (class1 == AMD64_X87 || class1 == AMD64_X87UP
422       || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
423       || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
424     return AMD64_MEMORY;
425 
426   /* Rule (f): Otherwise class SSE is used.  */
427   return AMD64_SSE;
428 }
429 
430 /* Return non-zero if TYPE is a non-POD structure or union type.  */
431 
432 static int
amd64_non_pod_p(struct type * type)433 amd64_non_pod_p (struct type *type)
434 {
435   /* ??? A class with a base class certainly isn't POD, but does this
436      catch all non-POD structure types?  */
437   if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
438     return 1;
439 
440   return 0;
441 }
442 
443 /* Classify TYPE according to the rules for aggregate (structures and
444    arrays) and union types, and store the result in CLASS.  */
445 
446 static void
amd64_classify_aggregate(struct type * type,enum amd64_reg_class class[2])447 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
448 {
449   /* 1. If the size of an object is larger than two eightbytes, or in
450         C++, is a non-POD structure or union type, or contains
451         unaligned fields, it has class memory.  */
452   if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
453     {
454       class[0] = class[1] = AMD64_MEMORY;
455       return;
456     }
457 
458   /* 2. Both eightbytes get initialized to class NO_CLASS.  */
459   class[0] = class[1] = AMD64_NO_CLASS;
460 
461   /* 3. Each field of an object is classified recursively so that
462         always two fields are considered. The resulting class is
463         calculated according to the classes of the fields in the
464         eightbyte: */
465 
466   if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
467     {
468       struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
469 
470       /* All fields in an array have the same type.  */
471       amd64_classify (subtype, class);
472       if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS)
473 	class[1] = class[0];
474     }
475   else
476     {
477       int i;
478 
479       /* Structure or union.  */
480       gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
481 		  || TYPE_CODE (type) == TYPE_CODE_UNION);
482 
483       for (i = 0; i < TYPE_NFIELDS (type); i++)
484 	{
485 	  struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
486 	  int pos = TYPE_FIELD_BITPOS (type, i) / 64;
487 	  enum amd64_reg_class subclass[2];
488 	  int bitsize = TYPE_FIELD_BITSIZE (type, i);
489 	  int endpos;
490 
491 	  if (bitsize == 0)
492 	    bitsize = TYPE_LENGTH (subtype) * 8;
493 	  endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
494 
495 	  /* Ignore static fields.  */
496 	  if (field_is_static (&TYPE_FIELD (type, i)))
497 	    continue;
498 
499 	  gdb_assert (pos == 0 || pos == 1);
500 
501 	  amd64_classify (subtype, subclass);
502 	  class[pos] = amd64_merge_classes (class[pos], subclass[0]);
503 	  if (bitsize <= 64 && pos == 0 && endpos == 1)
504 	    /* This is a bit of an odd case:  We have a field that would
505 	       normally fit in one of the two eightbytes, except that
506 	       it is placed in a way that this field straddles them.
507 	       This has been seen with a structure containing an array.
508 
509 	       The ABI is a bit unclear in this case, but we assume that
510 	       this field's class (stored in subclass[0]) must also be merged
511 	       into class[1].  In other words, our field has a piece stored
512 	       in the second eight-byte, and thus its class applies to
513 	       the second eight-byte as well.
514 
515 	       In the case where the field length exceeds 8 bytes,
516 	       it should not be necessary to merge the field class
517 	       into class[1].  As LEN > 8, subclass[1] is necessarily
518 	       different from AMD64_NO_CLASS.  If subclass[1] is equal
519 	       to subclass[0], then the normal class[1]/subclass[1]
520 	       merging will take care of everything.  For subclass[1]
521 	       to be different from subclass[0], I can only see the case
522 	       where we have a SSE/SSEUP or X87/X87UP pair, which both
523 	       use up all 16 bytes of the aggregate, and are already
524 	       handled just fine (because each portion sits on its own
525 	       8-byte).  */
526 	    class[1] = amd64_merge_classes (class[1], subclass[0]);
527 	  if (pos == 0)
528 	    class[1] = amd64_merge_classes (class[1], subclass[1]);
529 	}
530     }
531 
532   /* 4. Then a post merger cleanup is done:  */
533 
534   /* Rule (a): If one of the classes is MEMORY, the whole argument is
535      passed in memory.  */
536   if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
537     class[0] = class[1] = AMD64_MEMORY;
538 
539   /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
540      SSE.  */
541   if (class[0] == AMD64_SSEUP)
542     class[0] = AMD64_SSE;
543   if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
544     class[1] = AMD64_SSE;
545 }
546 
547 /* Classify TYPE, and store the result in CLASS.  */
548 
549 void
amd64_classify(struct type * type,enum amd64_reg_class class[2])550 amd64_classify (struct type *type, enum amd64_reg_class class[2])
551 {
552   enum type_code code = TYPE_CODE (type);
553   int len = TYPE_LENGTH (type);
554 
555   class[0] = class[1] = AMD64_NO_CLASS;
556 
557   /* Arguments of types (signed and unsigned) _Bool, char, short, int,
558      long, long long, and pointers are in the INTEGER class.  Similarly,
559      range types, used by languages such as Ada, are also in the INTEGER
560      class.  */
561   if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
562        || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
563        || code == TYPE_CODE_CHAR
564        || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
565       && (len == 1 || len == 2 || len == 4 || len == 8))
566     class[0] = AMD64_INTEGER;
567 
568   /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
569      are in class SSE.  */
570   else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
571 	   && (len == 4 || len == 8))
572     /* FIXME: __m64 .  */
573     class[0] = AMD64_SSE;
574 
575   /* Arguments of types __float128, _Decimal128 and __m128 are split into
576      two halves.  The least significant ones belong to class SSE, the most
577      significant one to class SSEUP.  */
578   else if (code == TYPE_CODE_DECFLOAT && len == 16)
579     /* FIXME: __float128, __m128.  */
580     class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
581 
582   /* The 64-bit mantissa of arguments of type long double belongs to
583      class X87, the 16-bit exponent plus 6 bytes of padding belongs to
584      class X87UP.  */
585   else if (code == TYPE_CODE_FLT && len == 16)
586     /* Class X87 and X87UP.  */
587     class[0] = AMD64_X87, class[1] = AMD64_X87UP;
588 
589   /* Arguments of complex T where T is one of the types float or
590      double get treated as if they are implemented as:
591 
592      struct complexT {
593        T real;
594        T imag;
595      };  */
596   else if (code == TYPE_CODE_COMPLEX && len == 8)
597     class[0] = AMD64_SSE;
598   else if (code == TYPE_CODE_COMPLEX && len == 16)
599     class[0] = class[1] = AMD64_SSE;
600 
601   /* A variable of type complex long double is classified as type
602      COMPLEX_X87.  */
603   else if (code == TYPE_CODE_COMPLEX && len == 32)
604     class[0] = AMD64_COMPLEX_X87;
605 
606   /* Aggregates.  */
607   else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
608 	   || code == TYPE_CODE_UNION)
609     amd64_classify_aggregate (type, class);
610 }
611 
612 static enum return_value_convention
amd64_return_value(struct gdbarch * gdbarch,struct value * function,struct type * type,struct regcache * regcache,gdb_byte * readbuf,const gdb_byte * writebuf)613 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
614 		    struct type *type, struct regcache *regcache,
615 		    gdb_byte *readbuf, const gdb_byte *writebuf)
616 {
617   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
618   enum amd64_reg_class class[2];
619   int len = TYPE_LENGTH (type);
620   static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
621   static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
622   int integer_reg = 0;
623   int sse_reg = 0;
624   int i;
625 
626   gdb_assert (!(readbuf && writebuf));
627   gdb_assert (tdep->classify);
628 
629   /* 1. Classify the return type with the classification algorithm.  */
630   tdep->classify (type, class);
631 
632   /* 2. If the type has class MEMORY, then the caller provides space
633      for the return value and passes the address of this storage in
634      %rdi as if it were the first argument to the function.  In effect,
635      this address becomes a hidden first argument.
636 
637      On return %rax will contain the address that has been passed in
638      by the caller in %rdi.  */
639   if (class[0] == AMD64_MEMORY)
640     {
641       /* As indicated by the comment above, the ABI guarantees that we
642          can always find the return value just after the function has
643          returned.  */
644 
645       if (readbuf)
646 	{
647 	  ULONGEST addr;
648 
649 	  regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
650 	  read_memory (addr, readbuf, TYPE_LENGTH (type));
651 	}
652 
653       return RETURN_VALUE_ABI_RETURNS_ADDRESS;
654     }
655 
656   /* 8. If the class is COMPLEX_X87, the real part of the value is
657         returned in %st0 and the imaginary part in %st1.  */
658   if (class[0] == AMD64_COMPLEX_X87)
659     {
660       if (readbuf)
661 	{
662 	  regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
663 	  regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
664 	}
665 
666       if (writebuf)
667 	{
668 	  i387_return_value (gdbarch, regcache);
669 	  regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
670 	  regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
671 
672 	  /* Fix up the tag word such that both %st(0) and %st(1) are
673 	     marked as valid.  */
674 	  regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
675 	}
676 
677       return RETURN_VALUE_REGISTER_CONVENTION;
678     }
679 
680   gdb_assert (class[1] != AMD64_MEMORY);
681   gdb_assert (len <= 16);
682 
683   for (i = 0; len > 0; i++, len -= 8)
684     {
685       int regnum = -1;
686       int offset = 0;
687 
688       switch (class[i])
689 	{
690 	case AMD64_INTEGER:
691 	  /* 3. If the class is INTEGER, the next available register
692 	     of the sequence %rax, %rdx is used.  */
693 	  regnum = integer_regnum[integer_reg++];
694 	  break;
695 
696 	case AMD64_SSE:
697 	  /* 4. If the class is SSE, the next available SSE register
698              of the sequence %xmm0, %xmm1 is used.  */
699 	  regnum = sse_regnum[sse_reg++];
700 	  break;
701 
702 	case AMD64_SSEUP:
703 	  /* 5. If the class is SSEUP, the eightbyte is passed in the
704 	     upper half of the last used SSE register.  */
705 	  gdb_assert (sse_reg > 0);
706 	  regnum = sse_regnum[sse_reg - 1];
707 	  offset = 8;
708 	  break;
709 
710 	case AMD64_X87:
711 	  /* 6. If the class is X87, the value is returned on the X87
712              stack in %st0 as 80-bit x87 number.  */
713 	  regnum = AMD64_ST0_REGNUM;
714 	  if (writebuf)
715 	    i387_return_value (gdbarch, regcache);
716 	  break;
717 
718 	case AMD64_X87UP:
719 	  /* 7. If the class is X87UP, the value is returned together
720              with the previous X87 value in %st0.  */
721 	  gdb_assert (i > 0 && class[0] == AMD64_X87);
722 	  regnum = AMD64_ST0_REGNUM;
723 	  offset = 8;
724 	  len = 2;
725 	  break;
726 
727 	case AMD64_NO_CLASS:
728 	  continue;
729 
730 	default:
731 	  gdb_assert (!"Unexpected register class.");
732 	}
733 
734       gdb_assert (regnum != -1);
735 
736       if (readbuf)
737 	regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
738 				readbuf + i * 8);
739       if (writebuf)
740 	regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
741 				 writebuf + i * 8);
742     }
743 
744   return RETURN_VALUE_REGISTER_CONVENTION;
745 }
746 
747 
748 static CORE_ADDR
amd64_push_arguments(struct regcache * regcache,int nargs,struct value ** args,CORE_ADDR sp,int struct_return)749 amd64_push_arguments (struct regcache *regcache, int nargs,
750 		      struct value **args, CORE_ADDR sp, int struct_return)
751 {
752   struct gdbarch *gdbarch = get_regcache_arch (regcache);
753   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
754   int *integer_regs = tdep->call_dummy_integer_regs;
755   int num_integer_regs = tdep->call_dummy_num_integer_regs;
756 
757   static int sse_regnum[] =
758   {
759     /* %xmm0 ... %xmm7 */
760     AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
761     AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
762     AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
763     AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
764   };
765   struct value **stack_args = alloca (nargs * sizeof (struct value *));
766   /* An array that mirrors the stack_args array.  For all arguments
767      that are passed by MEMORY, if that argument's address also needs
768      to be stored in a register, the ARG_ADDR_REGNO array will contain
769      that register number (or a negative value otherwise).  */
770   int *arg_addr_regno = alloca (nargs * sizeof (int));
771   int num_stack_args = 0;
772   int num_elements = 0;
773   int element = 0;
774   int integer_reg = 0;
775   int sse_reg = 0;
776   int i;
777 
778   gdb_assert (tdep->classify);
779 
780   /* Reserve a register for the "hidden" argument.  */
781   if (struct_return)
782     integer_reg++;
783 
784   for (i = 0; i < nargs; i++)
785     {
786       struct type *type = value_type (args[i]);
787       int len = TYPE_LENGTH (type);
788       enum amd64_reg_class class[2];
789       int needed_integer_regs = 0;
790       int needed_sse_regs = 0;
791       int j;
792 
793       /* Classify argument.  */
794       tdep->classify (type, class);
795 
796       /* Calculate the number of integer and SSE registers needed for
797          this argument.  */
798       for (j = 0; j < 2; j++)
799 	{
800 	  if (class[j] == AMD64_INTEGER)
801 	    needed_integer_regs++;
802 	  else if (class[j] == AMD64_SSE)
803 	    needed_sse_regs++;
804 	}
805 
806       /* Check whether enough registers are available, and if the
807          argument should be passed in registers at all.  */
808       if (integer_reg + needed_integer_regs > num_integer_regs
809 	  || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
810 	  || (needed_integer_regs == 0 && needed_sse_regs == 0))
811 	{
812 	  /* The argument will be passed on the stack.  */
813 	  num_elements += ((len + 7) / 8);
814 	  stack_args[num_stack_args] = args[i];
815           /* If this is an AMD64_MEMORY argument whose address must also
816              be passed in one of the integer registers, reserve that
817              register and associate this value to that register so that
818              we can store the argument address as soon as we know it.  */
819           if (class[0] == AMD64_MEMORY
820               && tdep->memory_args_by_pointer
821               && integer_reg < tdep->call_dummy_num_integer_regs)
822             arg_addr_regno[num_stack_args] =
823               tdep->call_dummy_integer_regs[integer_reg++];
824           else
825             arg_addr_regno[num_stack_args] = -1;
826           num_stack_args++;
827 	}
828       else
829 	{
830 	  /* The argument will be passed in registers.  */
831 	  const gdb_byte *valbuf = value_contents (args[i]);
832 	  gdb_byte buf[8];
833 
834 	  gdb_assert (len <= 16);
835 
836 	  for (j = 0; len > 0; j++, len -= 8)
837 	    {
838 	      int regnum = -1;
839 	      int offset = 0;
840 
841 	      switch (class[j])
842 		{
843 		case AMD64_INTEGER:
844 		  regnum = integer_regs[integer_reg++];
845 		  break;
846 
847 		case AMD64_SSE:
848 		  regnum = sse_regnum[sse_reg++];
849 		  break;
850 
851 		case AMD64_SSEUP:
852 		  gdb_assert (sse_reg > 0);
853 		  regnum = sse_regnum[sse_reg - 1];
854 		  offset = 8;
855 		  break;
856 
857 		default:
858 		  gdb_assert (!"Unexpected register class.");
859 		}
860 
861 	      gdb_assert (regnum != -1);
862 	      memset (buf, 0, sizeof buf);
863 	      memcpy (buf, valbuf + j * 8, min (len, 8));
864 	      regcache_raw_write_part (regcache, regnum, offset, 8, buf);
865 	    }
866 	}
867     }
868 
869   /* Allocate space for the arguments on the stack.  */
870   sp -= num_elements * 8;
871 
872   /* The psABI says that "The end of the input argument area shall be
873      aligned on a 16 byte boundary."  */
874   sp &= ~0xf;
875 
876   /* Write out the arguments to the stack.  */
877   for (i = 0; i < num_stack_args; i++)
878     {
879       struct type *type = value_type (stack_args[i]);
880       const gdb_byte *valbuf = value_contents (stack_args[i]);
881       CORE_ADDR arg_addr = sp + element * 8;
882 
883       write_memory (arg_addr, valbuf, TYPE_LENGTH (type));
884       if (arg_addr_regno[i] >= 0)
885         {
886           /* We also need to store the address of that argument in
887              the given register.  */
888           gdb_byte buf[8];
889           enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
890 
891           store_unsigned_integer (buf, 8, byte_order, arg_addr);
892           regcache_cooked_write (regcache, arg_addr_regno[i], buf);
893         }
894       element += ((TYPE_LENGTH (type) + 7) / 8);
895     }
896 
897   /* The psABI says that "For calls that may call functions that use
898      varargs or stdargs (prototype-less calls or calls to functions
899      containing ellipsis (...) in the declaration) %al is used as
900      hidden argument to specify the number of SSE registers used.  */
901   regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
902   return sp;
903 }
904 
905 static CORE_ADDR
amd64_push_dummy_call(struct gdbarch * gdbarch,struct value * function,struct regcache * regcache,CORE_ADDR bp_addr,int nargs,struct value ** args,CORE_ADDR sp,int struct_return,CORE_ADDR struct_addr)906 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
907 		       struct regcache *regcache, CORE_ADDR bp_addr,
908 		       int nargs, struct value **args,	CORE_ADDR sp,
909 		       int struct_return, CORE_ADDR struct_addr)
910 {
911   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
912   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
913   gdb_byte buf[8];
914 
915   /* Pass arguments.  */
916   sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
917 
918   /* Pass "hidden" argument".  */
919   if (struct_return)
920     {
921       /* The "hidden" argument is passed throught the first argument
922          register.  */
923       const int arg_regnum = tdep->call_dummy_integer_regs[0];
924 
925       store_unsigned_integer (buf, 8, byte_order, struct_addr);
926       regcache_cooked_write (regcache, arg_regnum, buf);
927     }
928 
929   /* Reserve some memory on the stack for the integer-parameter registers,
930      if required by the ABI.  */
931   if (tdep->integer_param_regs_saved_in_caller_frame)
932     sp -= tdep->call_dummy_num_integer_regs * 8;
933 
934   /* Store return address.  */
935   sp -= 8;
936   store_unsigned_integer (buf, 8, byte_order, bp_addr);
937   write_memory (sp, buf, 8);
938 
939   /* Finally, update the stack pointer...  */
940   store_unsigned_integer (buf, 8, byte_order, sp);
941   regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
942 
943   /* ...and fake a frame pointer.  */
944   regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
945 
946   return sp + 16;
947 }
948 
949 /* Displaced instruction handling.  */
950 
951 /* A partially decoded instruction.
952    This contains enough details for displaced stepping purposes.  */
953 
954 struct amd64_insn
955 {
956   /* The number of opcode bytes.  */
957   int opcode_len;
958   /* The offset of the rex prefix or -1 if not present.  */
959   int rex_offset;
960   /* The offset to the first opcode byte.  */
961   int opcode_offset;
962   /* The offset to the modrm byte or -1 if not present.  */
963   int modrm_offset;
964 
965   /* The raw instruction.  */
966   gdb_byte *raw_insn;
967 };
968 
969 struct displaced_step_closure
970 {
971   /* For rip-relative insns, saved copy of the reg we use instead of %rip.  */
972   int tmp_used;
973   int tmp_regno;
974   ULONGEST tmp_save;
975 
976   /* Details of the instruction.  */
977   struct amd64_insn insn_details;
978 
979   /* Amount of space allocated to insn_buf.  */
980   int max_len;
981 
982   /* The possibly modified insn.
983      This is a variable-length field.  */
984   gdb_byte insn_buf[1];
985 };
986 
987 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
988    ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
989    at which point delete these in favor of libopcodes' versions).  */
990 
991 static const unsigned char onebyte_has_modrm[256] = {
992   /*	   0 1 2 3 4 5 6 7 8 9 a b c d e f	  */
993   /*	   -------------------------------	  */
994   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
995   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
996   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
997   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
998   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
999   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1000   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1001   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1002   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1003   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1004   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1005   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1006   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1007   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1008   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1009   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1010   /*	   -------------------------------	  */
1011   /*	   0 1 2 3 4 5 6 7 8 9 a b c d e f	  */
1012 };
1013 
1014 static const unsigned char twobyte_has_modrm[256] = {
1015   /*	   0 1 2 3 4 5 6 7 8 9 a b c d e f	  */
1016   /*	   -------------------------------	  */
1017   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1018   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1019   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1020   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1021   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1022   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1023   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1024   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1025   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1026   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1027   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1028   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1029   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1030   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1031   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1032   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1033   /*	   -------------------------------	  */
1034   /*	   0 1 2 3 4 5 6 7 8 9 a b c d e f	  */
1035 };
1036 
1037 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1038 
1039 static int
rex_prefix_p(gdb_byte pfx)1040 rex_prefix_p (gdb_byte pfx)
1041 {
1042   return REX_PREFIX_P (pfx);
1043 }
1044 
1045 /* Skip the legacy instruction prefixes in INSN.
1046    We assume INSN is properly sentineled so we don't have to worry
1047    about falling off the end of the buffer.  */
1048 
1049 static gdb_byte *
amd64_skip_prefixes(gdb_byte * insn)1050 amd64_skip_prefixes (gdb_byte *insn)
1051 {
1052   while (1)
1053     {
1054       switch (*insn)
1055 	{
1056 	case DATA_PREFIX_OPCODE:
1057 	case ADDR_PREFIX_OPCODE:
1058 	case CS_PREFIX_OPCODE:
1059 	case DS_PREFIX_OPCODE:
1060 	case ES_PREFIX_OPCODE:
1061 	case FS_PREFIX_OPCODE:
1062 	case GS_PREFIX_OPCODE:
1063 	case SS_PREFIX_OPCODE:
1064 	case LOCK_PREFIX_OPCODE:
1065 	case REPE_PREFIX_OPCODE:
1066 	case REPNE_PREFIX_OPCODE:
1067 	  ++insn;
1068 	  continue;
1069 	default:
1070 	  break;
1071 	}
1072       break;
1073     }
1074 
1075   return insn;
1076 }
1077 
1078 /* Return an integer register (other than RSP) that is unused as an input
1079    operand in INSN.
1080    In order to not require adding a rex prefix if the insn doesn't already
1081    have one, the result is restricted to RAX ... RDI, sans RSP.
1082    The register numbering of the result follows architecture ordering,
1083    e.g. RDI = 7.  */
1084 
1085 static int
amd64_get_unused_input_int_reg(const struct amd64_insn * details)1086 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1087 {
1088   /* 1 bit for each reg */
1089   int used_regs_mask = 0;
1090 
1091   /* There can be at most 3 int regs used as inputs in an insn, and we have
1092      7 to choose from (RAX ... RDI, sans RSP).
1093      This allows us to take a conservative approach and keep things simple.
1094      E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1095      that implicitly specify RAX.  */
1096 
1097   /* Avoid RAX.  */
1098   used_regs_mask |= 1 << EAX_REG_NUM;
1099   /* Similarily avoid RDX, implicit operand in divides.  */
1100   used_regs_mask |= 1 << EDX_REG_NUM;
1101   /* Avoid RSP.  */
1102   used_regs_mask |= 1 << ESP_REG_NUM;
1103 
1104   /* If the opcode is one byte long and there's no ModRM byte,
1105      assume the opcode specifies a register.  */
1106   if (details->opcode_len == 1 && details->modrm_offset == -1)
1107     used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1108 
1109   /* Mark used regs in the modrm/sib bytes.  */
1110   if (details->modrm_offset != -1)
1111     {
1112       int modrm = details->raw_insn[details->modrm_offset];
1113       int mod = MODRM_MOD_FIELD (modrm);
1114       int reg = MODRM_REG_FIELD (modrm);
1115       int rm = MODRM_RM_FIELD (modrm);
1116       int have_sib = mod != 3 && rm == 4;
1117 
1118       /* Assume the reg field of the modrm byte specifies a register.  */
1119       used_regs_mask |= 1 << reg;
1120 
1121       if (have_sib)
1122 	{
1123 	  int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1124 	  int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1125 	  used_regs_mask |= 1 << base;
1126 	  used_regs_mask |= 1 << idx;
1127 	}
1128       else
1129 	{
1130 	  used_regs_mask |= 1 << rm;
1131 	}
1132     }
1133 
1134   gdb_assert (used_regs_mask < 256);
1135   gdb_assert (used_regs_mask != 255);
1136 
1137   /* Finally, find a free reg.  */
1138   {
1139     int i;
1140 
1141     for (i = 0; i < 8; ++i)
1142       {
1143 	if (! (used_regs_mask & (1 << i)))
1144 	  return i;
1145       }
1146 
1147     /* We shouldn't get here.  */
1148     internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1149   }
1150 }
1151 
1152 /* Extract the details of INSN that we need.  */
1153 
1154 static void
amd64_get_insn_details(gdb_byte * insn,struct amd64_insn * details)1155 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1156 {
1157   gdb_byte *start = insn;
1158   int need_modrm;
1159 
1160   details->raw_insn = insn;
1161 
1162   details->opcode_len = -1;
1163   details->rex_offset = -1;
1164   details->opcode_offset = -1;
1165   details->modrm_offset = -1;
1166 
1167   /* Skip legacy instruction prefixes.  */
1168   insn = amd64_skip_prefixes (insn);
1169 
1170   /* Skip REX instruction prefix.  */
1171   if (rex_prefix_p (*insn))
1172     {
1173       details->rex_offset = insn - start;
1174       ++insn;
1175     }
1176 
1177   details->opcode_offset = insn - start;
1178 
1179   if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1180     {
1181       /* Two or three-byte opcode.  */
1182       ++insn;
1183       need_modrm = twobyte_has_modrm[*insn];
1184 
1185       /* Check for three-byte opcode.  */
1186       switch (*insn)
1187 	{
1188 	case 0x24:
1189 	case 0x25:
1190 	case 0x38:
1191 	case 0x3a:
1192 	case 0x7a:
1193 	case 0x7b:
1194 	  ++insn;
1195 	  details->opcode_len = 3;
1196 	  break;
1197 	default:
1198 	  details->opcode_len = 2;
1199 	  break;
1200 	}
1201     }
1202   else
1203     {
1204       /* One-byte opcode.  */
1205       need_modrm = onebyte_has_modrm[*insn];
1206       details->opcode_len = 1;
1207     }
1208 
1209   if (need_modrm)
1210     {
1211       ++insn;
1212       details->modrm_offset = insn - start;
1213     }
1214 }
1215 
1216 /* Update %rip-relative addressing in INSN.
1217 
1218    %rip-relative addressing only uses a 32-bit displacement.
1219    32 bits is not enough to be guaranteed to cover the distance between where
1220    the real instruction is and where its copy is.
1221    Convert the insn to use base+disp addressing.
1222    We set base = pc + insn_length so we can leave disp unchanged.  */
1223 
1224 static void
fixup_riprel(struct gdbarch * gdbarch,struct displaced_step_closure * dsc,CORE_ADDR from,CORE_ADDR to,struct regcache * regs)1225 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1226 	      CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1227 {
1228   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1229   const struct amd64_insn *insn_details = &dsc->insn_details;
1230   int modrm_offset = insn_details->modrm_offset;
1231   gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1232   CORE_ADDR rip_base;
1233   int32_t disp;
1234   int insn_length;
1235   int arch_tmp_regno, tmp_regno;
1236   ULONGEST orig_value;
1237 
1238   /* %rip+disp32 addressing mode, displacement follows ModRM byte.  */
1239   ++insn;
1240 
1241   /* Compute the rip-relative address.	*/
1242   disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1243   insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1244 					  dsc->max_len, from);
1245   rip_base = from + insn_length;
1246 
1247   /* We need a register to hold the address.
1248      Pick one not used in the insn.
1249      NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7.  */
1250   arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1251   tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1252 
1253   /* REX.B should be unset as we were using rip-relative addressing,
1254      but ensure it's unset anyway, tmp_regno is not r8-r15.  */
1255   if (insn_details->rex_offset != -1)
1256     dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1257 
1258   regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1259   dsc->tmp_regno = tmp_regno;
1260   dsc->tmp_save = orig_value;
1261   dsc->tmp_used = 1;
1262 
1263   /* Convert the ModRM field to be base+disp.  */
1264   dsc->insn_buf[modrm_offset] &= ~0xc7;
1265   dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1266 
1267   regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1268 
1269   if (debug_displaced)
1270     fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1271 			"displaced: using temp reg %d, old value %s, new value %s\n",
1272 			dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1273 			paddress (gdbarch, rip_base));
1274 }
1275 
1276 static void
fixup_displaced_copy(struct gdbarch * gdbarch,struct displaced_step_closure * dsc,CORE_ADDR from,CORE_ADDR to,struct regcache * regs)1277 fixup_displaced_copy (struct gdbarch *gdbarch,
1278 		      struct displaced_step_closure *dsc,
1279 		      CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1280 {
1281   const struct amd64_insn *details = &dsc->insn_details;
1282 
1283   if (details->modrm_offset != -1)
1284     {
1285       gdb_byte modrm = details->raw_insn[details->modrm_offset];
1286 
1287       if ((modrm & 0xc7) == 0x05)
1288 	{
1289 	  /* The insn uses rip-relative addressing.
1290 	     Deal with it.  */
1291 	  fixup_riprel (gdbarch, dsc, from, to, regs);
1292 	}
1293     }
1294 }
1295 
1296 struct displaced_step_closure *
amd64_displaced_step_copy_insn(struct gdbarch * gdbarch,CORE_ADDR from,CORE_ADDR to,struct regcache * regs)1297 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1298 				CORE_ADDR from, CORE_ADDR to,
1299 				struct regcache *regs)
1300 {
1301   int len = gdbarch_max_insn_length (gdbarch);
1302   /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1303      continually watch for running off the end of the buffer.  */
1304   int fixup_sentinel_space = len;
1305   struct displaced_step_closure *dsc =
1306     xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1307   gdb_byte *buf = &dsc->insn_buf[0];
1308   struct amd64_insn *details = &dsc->insn_details;
1309 
1310   dsc->tmp_used = 0;
1311   dsc->max_len = len + fixup_sentinel_space;
1312 
1313   read_memory (from, buf, len);
1314 
1315   /* Set up the sentinel space so we don't have to worry about running
1316      off the end of the buffer.  An excessive number of leading prefixes
1317      could otherwise cause this.  */
1318   memset (buf + len, 0, fixup_sentinel_space);
1319 
1320   amd64_get_insn_details (buf, details);
1321 
1322   /* GDB may get control back after the insn after the syscall.
1323      Presumably this is a kernel bug.
1324      If this is a syscall, make sure there's a nop afterwards.  */
1325   {
1326     int syscall_length;
1327 
1328     if (amd64_syscall_p (details, &syscall_length))
1329       buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1330   }
1331 
1332   /* Modify the insn to cope with the address where it will be executed from.
1333      In particular, handle any rip-relative addressing.	 */
1334   fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1335 
1336   write_memory (to, buf, len);
1337 
1338   if (debug_displaced)
1339     {
1340       fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1341 			  paddress (gdbarch, from), paddress (gdbarch, to));
1342       displaced_step_dump_bytes (gdb_stdlog, buf, len);
1343     }
1344 
1345   return dsc;
1346 }
1347 
1348 static int
amd64_absolute_jmp_p(const struct amd64_insn * details)1349 amd64_absolute_jmp_p (const struct amd64_insn *details)
1350 {
1351   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1352 
1353   if (insn[0] == 0xff)
1354     {
1355       /* jump near, absolute indirect (/4) */
1356       if ((insn[1] & 0x38) == 0x20)
1357 	return 1;
1358 
1359       /* jump far, absolute indirect (/5) */
1360       if ((insn[1] & 0x38) == 0x28)
1361 	return 1;
1362     }
1363 
1364   return 0;
1365 }
1366 
1367 static int
amd64_absolute_call_p(const struct amd64_insn * details)1368 amd64_absolute_call_p (const struct amd64_insn *details)
1369 {
1370   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1371 
1372   if (insn[0] == 0xff)
1373     {
1374       /* Call near, absolute indirect (/2) */
1375       if ((insn[1] & 0x38) == 0x10)
1376 	return 1;
1377 
1378       /* Call far, absolute indirect (/3) */
1379       if ((insn[1] & 0x38) == 0x18)
1380 	return 1;
1381     }
1382 
1383   return 0;
1384 }
1385 
1386 static int
amd64_ret_p(const struct amd64_insn * details)1387 amd64_ret_p (const struct amd64_insn *details)
1388 {
1389   /* NOTE: gcc can emit "repz ; ret".  */
1390   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1391 
1392   switch (insn[0])
1393     {
1394     case 0xc2: /* ret near, pop N bytes */
1395     case 0xc3: /* ret near */
1396     case 0xca: /* ret far, pop N bytes */
1397     case 0xcb: /* ret far */
1398     case 0xcf: /* iret */
1399       return 1;
1400 
1401     default:
1402       return 0;
1403     }
1404 }
1405 
1406 static int
amd64_call_p(const struct amd64_insn * details)1407 amd64_call_p (const struct amd64_insn *details)
1408 {
1409   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1410 
1411   if (amd64_absolute_call_p (details))
1412     return 1;
1413 
1414   /* call near, relative */
1415   if (insn[0] == 0xe8)
1416     return 1;
1417 
1418   return 0;
1419 }
1420 
1421 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1422    length in bytes.  Otherwise, return zero.  */
1423 
1424 static int
amd64_syscall_p(const struct amd64_insn * details,int * lengthp)1425 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1426 {
1427   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1428 
1429   if (insn[0] == 0x0f && insn[1] == 0x05)
1430     {
1431       *lengthp = 2;
1432       return 1;
1433     }
1434 
1435   return 0;
1436 }
1437 
1438 /* Fix up the state of registers and memory after having single-stepped
1439    a displaced instruction.  */
1440 
1441 void
amd64_displaced_step_fixup(struct gdbarch * gdbarch,struct displaced_step_closure * dsc,CORE_ADDR from,CORE_ADDR to,struct regcache * regs)1442 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1443 			    struct displaced_step_closure *dsc,
1444 			    CORE_ADDR from, CORE_ADDR to,
1445 			    struct regcache *regs)
1446 {
1447   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1448   /* The offset we applied to the instruction's address.  */
1449   ULONGEST insn_offset = to - from;
1450   gdb_byte *insn = dsc->insn_buf;
1451   const struct amd64_insn *insn_details = &dsc->insn_details;
1452 
1453   if (debug_displaced)
1454     fprintf_unfiltered (gdb_stdlog,
1455 			"displaced: fixup (%s, %s), "
1456 			"insn = 0x%02x 0x%02x ...\n",
1457 			paddress (gdbarch, from), paddress (gdbarch, to),
1458 			insn[0], insn[1]);
1459 
1460   /* If we used a tmp reg, restore it.	*/
1461 
1462   if (dsc->tmp_used)
1463     {
1464       if (debug_displaced)
1465 	fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1466 			    dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1467       regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1468     }
1469 
1470   /* The list of issues to contend with here is taken from
1471      resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1472      Yay for Free Software!  */
1473 
1474   /* Relocate the %rip back to the program's instruction stream,
1475      if necessary.  */
1476 
1477   /* Except in the case of absolute or indirect jump or call
1478      instructions, or a return instruction, the new rip is relative to
1479      the displaced instruction; make it relative to the original insn.
1480      Well, signal handler returns don't need relocation either, but we use the
1481      value of %rip to recognize those; see below.  */
1482   if (! amd64_absolute_jmp_p (insn_details)
1483       && ! amd64_absolute_call_p (insn_details)
1484       && ! amd64_ret_p (insn_details))
1485     {
1486       ULONGEST orig_rip;
1487       int insn_len;
1488 
1489       regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1490 
1491       /* A signal trampoline system call changes the %rip, resuming
1492 	 execution of the main program after the signal handler has
1493 	 returned.  That makes them like 'return' instructions; we
1494 	 shouldn't relocate %rip.
1495 
1496 	 But most system calls don't, and we do need to relocate %rip.
1497 
1498 	 Our heuristic for distinguishing these cases: if stepping
1499 	 over the system call instruction left control directly after
1500 	 the instruction, the we relocate --- control almost certainly
1501 	 doesn't belong in the displaced copy.	Otherwise, we assume
1502 	 the instruction has put control where it belongs, and leave
1503 	 it unrelocated.  Goodness help us if there are PC-relative
1504 	 system calls.	*/
1505       if (amd64_syscall_p (insn_details, &insn_len)
1506 	  && orig_rip != to + insn_len
1507 	  /* GDB can get control back after the insn after the syscall.
1508 	     Presumably this is a kernel bug.
1509 	     Fixup ensures its a nop, we add one to the length for it.  */
1510 	  && orig_rip != to + insn_len + 1)
1511 	{
1512 	  if (debug_displaced)
1513 	    fprintf_unfiltered (gdb_stdlog,
1514 				"displaced: syscall changed %%rip; "
1515 				"not relocating\n");
1516 	}
1517       else
1518 	{
1519 	  ULONGEST rip = orig_rip - insn_offset;
1520 
1521 	  /* If we just stepped over a breakpoint insn, we don't backup
1522 	     the pc on purpose; this is to match behaviour without
1523 	     stepping.  */
1524 
1525 	  regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1526 
1527 	  if (debug_displaced)
1528 	    fprintf_unfiltered (gdb_stdlog,
1529 				"displaced: "
1530 				"relocated %%rip from %s to %s\n",
1531 				paddress (gdbarch, orig_rip),
1532 				paddress (gdbarch, rip));
1533 	}
1534     }
1535 
1536   /* If the instruction was PUSHFL, then the TF bit will be set in the
1537      pushed value, and should be cleared.  We'll leave this for later,
1538      since GDB already messes up the TF flag when stepping over a
1539      pushfl.  */
1540 
1541   /* If the instruction was a call, the return address now atop the
1542      stack is the address following the copied instruction.  We need
1543      to make it the address following the original instruction.	 */
1544   if (amd64_call_p (insn_details))
1545     {
1546       ULONGEST rsp;
1547       ULONGEST retaddr;
1548       const ULONGEST retaddr_len = 8;
1549 
1550       regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1551       retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1552       retaddr = (retaddr - insn_offset) & 0xffffffffUL;
1553       write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1554 
1555       if (debug_displaced)
1556 	fprintf_unfiltered (gdb_stdlog,
1557 			    "displaced: relocated return addr at %s "
1558 			    "to %s\n",
1559 			    paddress (gdbarch, rsp),
1560 			    paddress (gdbarch, retaddr));
1561     }
1562 }
1563 
1564 /* If the instruction INSN uses RIP-relative addressing, return the
1565    offset into the raw INSN where the displacement to be adjusted is
1566    found.  Returns 0 if the instruction doesn't use RIP-relative
1567    addressing.  */
1568 
1569 static int
rip_relative_offset(struct amd64_insn * insn)1570 rip_relative_offset (struct amd64_insn *insn)
1571 {
1572   if (insn->modrm_offset != -1)
1573     {
1574       gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1575 
1576       if ((modrm & 0xc7) == 0x05)
1577 	{
1578 	  /* The displacement is found right after the ModRM byte.  */
1579 	  return insn->modrm_offset + 1;
1580 	}
1581     }
1582 
1583   return 0;
1584 }
1585 
1586 static void
append_insns(CORE_ADDR * to,ULONGEST len,const gdb_byte * buf)1587 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1588 {
1589   target_write_memory (*to, buf, len);
1590   *to += len;
1591 }
1592 
1593 static void
amd64_relocate_instruction(struct gdbarch * gdbarch,CORE_ADDR * to,CORE_ADDR oldloc)1594 amd64_relocate_instruction (struct gdbarch *gdbarch,
1595 			    CORE_ADDR *to, CORE_ADDR oldloc)
1596 {
1597   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1598   int len = gdbarch_max_insn_length (gdbarch);
1599   /* Extra space for sentinels.  */
1600   int fixup_sentinel_space = len;
1601   gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1602   struct amd64_insn insn_details;
1603   int offset = 0;
1604   LONGEST rel32, newrel;
1605   gdb_byte *insn;
1606   int insn_length;
1607 
1608   read_memory (oldloc, buf, len);
1609 
1610   /* Set up the sentinel space so we don't have to worry about running
1611      off the end of the buffer.  An excessive number of leading prefixes
1612      could otherwise cause this.  */
1613   memset (buf + len, 0, fixup_sentinel_space);
1614 
1615   insn = buf;
1616   amd64_get_insn_details (insn, &insn_details);
1617 
1618   insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1619 
1620   /* Skip legacy instruction prefixes.  */
1621   insn = amd64_skip_prefixes (insn);
1622 
1623   /* Adjust calls with 32-bit relative addresses as push/jump, with
1624      the address pushed being the location where the original call in
1625      the user program would return to.  */
1626   if (insn[0] == 0xe8)
1627     {
1628       gdb_byte push_buf[16];
1629       unsigned int ret_addr;
1630 
1631       /* Where "ret" in the original code will return to.  */
1632       ret_addr = oldloc + insn_length;
1633       push_buf[0] = 0x68; /* pushq $...  */
1634       store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1635       /* Push the push.  */
1636       append_insns (to, 5, push_buf);
1637 
1638       /* Convert the relative call to a relative jump.  */
1639       insn[0] = 0xe9;
1640 
1641       /* Adjust the destination offset.  */
1642       rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1643       newrel = (oldloc - *to) + rel32;
1644       store_signed_integer (insn + 1, 4, byte_order, newrel);
1645 
1646       if (debug_displaced)
1647 	fprintf_unfiltered (gdb_stdlog,
1648 			    "Adjusted insn rel32=%s at %s to"
1649 			    " rel32=%s at %s\n",
1650 			    hex_string (rel32), paddress (gdbarch, oldloc),
1651 			    hex_string (newrel), paddress (gdbarch, *to));
1652 
1653       /* Write the adjusted jump into its displaced location.  */
1654       append_insns (to, 5, insn);
1655       return;
1656     }
1657 
1658   offset = rip_relative_offset (&insn_details);
1659   if (!offset)
1660     {
1661       /* Adjust jumps with 32-bit relative addresses.  Calls are
1662 	 already handled above.  */
1663       if (insn[0] == 0xe9)
1664 	offset = 1;
1665       /* Adjust conditional jumps.  */
1666       else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1667 	offset = 2;
1668     }
1669 
1670   if (offset)
1671     {
1672       rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1673       newrel = (oldloc - *to) + rel32;
1674       store_signed_integer (insn + offset, 4, byte_order, newrel);
1675       if (debug_displaced)
1676 	fprintf_unfiltered (gdb_stdlog,
1677 			    "Adjusted insn rel32=%s at %s to"
1678 			    " rel32=%s at %s\n",
1679 			    hex_string (rel32), paddress (gdbarch, oldloc),
1680 			    hex_string (newrel), paddress (gdbarch, *to));
1681     }
1682 
1683   /* Write the adjusted instruction into its displaced location.  */
1684   append_insns (to, insn_length, buf);
1685 }
1686 
1687 
1688 /* The maximum number of saved registers.  This should include %rip.  */
1689 #define AMD64_NUM_SAVED_REGS	AMD64_NUM_GREGS
1690 
1691 struct amd64_frame_cache
1692 {
1693   /* Base address.  */
1694   CORE_ADDR base;
1695   int base_p;
1696   CORE_ADDR sp_offset;
1697   CORE_ADDR pc;
1698 
1699   /* Saved registers.  */
1700   CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1701   CORE_ADDR saved_sp;
1702   int saved_sp_reg;
1703 
1704   /* Do we have a frame?  */
1705   int frameless_p;
1706 };
1707 
1708 /* Initialize a frame cache.  */
1709 
1710 static void
amd64_init_frame_cache(struct amd64_frame_cache * cache)1711 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1712 {
1713   int i;
1714 
1715   /* Base address.  */
1716   cache->base = 0;
1717   cache->base_p = 0;
1718   cache->sp_offset = -8;
1719   cache->pc = 0;
1720 
1721   /* Saved registers.  We initialize these to -1 since zero is a valid
1722      offset (that's where %rbp is supposed to be stored).
1723      The values start out as being offsets, and are later converted to
1724      addresses (at which point -1 is interpreted as an address, still meaning
1725      "invalid").  */
1726   for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1727     cache->saved_regs[i] = -1;
1728   cache->saved_sp = 0;
1729   cache->saved_sp_reg = -1;
1730 
1731   /* Frameless until proven otherwise.  */
1732   cache->frameless_p = 1;
1733 }
1734 
1735 /* Allocate and initialize a frame cache.  */
1736 
1737 static struct amd64_frame_cache *
amd64_alloc_frame_cache(void)1738 amd64_alloc_frame_cache (void)
1739 {
1740   struct amd64_frame_cache *cache;
1741 
1742   cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1743   amd64_init_frame_cache (cache);
1744   return cache;
1745 }
1746 
1747 /* GCC 4.4 and later, can put code in the prologue to realign the
1748    stack pointer.  Check whether PC points to such code, and update
1749    CACHE accordingly.  Return the first instruction after the code
1750    sequence or CURRENT_PC, whichever is smaller.  If we don't
1751    recognize the code, return PC.  */
1752 
1753 static CORE_ADDR
amd64_analyze_stack_align(CORE_ADDR pc,CORE_ADDR current_pc,struct amd64_frame_cache * cache)1754 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1755 			   struct amd64_frame_cache *cache)
1756 {
1757   /* There are 2 code sequences to re-align stack before the frame
1758      gets set up:
1759 
1760 	1. Use a caller-saved saved register:
1761 
1762 		leaq  8(%rsp), %reg
1763 		andq  $-XXX, %rsp
1764 		pushq -8(%reg)
1765 
1766 	2. Use a callee-saved saved register:
1767 
1768 		pushq %reg
1769 		leaq  16(%rsp), %reg
1770 		andq  $-XXX, %rsp
1771 		pushq -8(%reg)
1772 
1773      "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1774 
1775      	0x48 0x83 0xe4 0xf0			andq $-16, %rsp
1776      	0x48 0x81 0xe4 0x00 0xff 0xff 0xff	andq $-256, %rsp
1777    */
1778 
1779   gdb_byte buf[18];
1780   int reg, r;
1781   int offset, offset_and;
1782 
1783   if (target_read_memory (pc, buf, sizeof buf))
1784     return pc;
1785 
1786   /* Check caller-saved saved register.  The first instruction has
1787      to be "leaq 8(%rsp), %reg".  */
1788   if ((buf[0] & 0xfb) == 0x48
1789       && buf[1] == 0x8d
1790       && buf[3] == 0x24
1791       && buf[4] == 0x8)
1792     {
1793       /* MOD must be binary 10 and R/M must be binary 100.  */
1794       if ((buf[2] & 0xc7) != 0x44)
1795 	return pc;
1796 
1797       /* REG has register number.  */
1798       reg = (buf[2] >> 3) & 7;
1799 
1800       /* Check the REX.R bit.  */
1801       if (buf[0] == 0x4c)
1802 	reg += 8;
1803 
1804       offset = 5;
1805     }
1806   else
1807     {
1808       /* Check callee-saved saved register.  The first instruction
1809 	 has to be "pushq %reg".  */
1810       reg = 0;
1811       if ((buf[0] & 0xf8) == 0x50)
1812 	offset = 0;
1813       else if ((buf[0] & 0xf6) == 0x40
1814 	       && (buf[1] & 0xf8) == 0x50)
1815 	{
1816 	  /* Check the REX.B bit.  */
1817 	  if ((buf[0] & 1) != 0)
1818 	    reg = 8;
1819 
1820 	  offset = 1;
1821 	}
1822       else
1823 	return pc;
1824 
1825       /* Get register.  */
1826       reg += buf[offset] & 0x7;
1827 
1828       offset++;
1829 
1830       /* The next instruction has to be "leaq 16(%rsp), %reg".  */
1831       if ((buf[offset] & 0xfb) != 0x48
1832 	  || buf[offset + 1] != 0x8d
1833 	  || buf[offset + 3] != 0x24
1834 	  || buf[offset + 4] != 0x10)
1835 	return pc;
1836 
1837       /* MOD must be binary 10 and R/M must be binary 100.  */
1838       if ((buf[offset + 2] & 0xc7) != 0x44)
1839 	return pc;
1840 
1841       /* REG has register number.  */
1842       r = (buf[offset + 2] >> 3) & 7;
1843 
1844       /* Check the REX.R bit.  */
1845       if (buf[offset] == 0x4c)
1846 	r += 8;
1847 
1848       /* Registers in pushq and leaq have to be the same.  */
1849       if (reg != r)
1850 	return pc;
1851 
1852       offset += 5;
1853     }
1854 
1855   /* Rigister can't be %rsp nor %rbp.  */
1856   if (reg == 4 || reg == 5)
1857     return pc;
1858 
1859   /* The next instruction has to be "andq $-XXX, %rsp".  */
1860   if (buf[offset] != 0x48
1861       || buf[offset + 2] != 0xe4
1862       || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1863     return pc;
1864 
1865   offset_and = offset;
1866   offset += buf[offset + 1] == 0x81 ? 7 : 4;
1867 
1868   /* The next instruction has to be "pushq -8(%reg)".  */
1869   r = 0;
1870   if (buf[offset] == 0xff)
1871     offset++;
1872   else if ((buf[offset] & 0xf6) == 0x40
1873 	   && buf[offset + 1] == 0xff)
1874     {
1875       /* Check the REX.B bit.  */
1876       if ((buf[offset] & 0x1) != 0)
1877 	r = 8;
1878       offset += 2;
1879     }
1880   else
1881     return pc;
1882 
1883   /* 8bit -8 is 0xf8.  REG must be binary 110 and MOD must be binary
1884      01.  */
1885   if (buf[offset + 1] != 0xf8
1886       || (buf[offset] & 0xf8) != 0x70)
1887     return pc;
1888 
1889   /* R/M has register.  */
1890   r += buf[offset] & 7;
1891 
1892   /* Registers in leaq and pushq have to be the same.  */
1893   if (reg != r)
1894     return pc;
1895 
1896   if (current_pc > pc + offset_and)
1897     cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
1898 
1899   return min (pc + offset + 2, current_pc);
1900 }
1901 
1902 /* Similar to amd64_analyze_stack_align for x32.  */
1903 
1904 static CORE_ADDR
amd64_x32_analyze_stack_align(CORE_ADDR pc,CORE_ADDR current_pc,struct amd64_frame_cache * cache)1905 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1906 			       struct amd64_frame_cache *cache)
1907 {
1908   /* There are 2 code sequences to re-align stack before the frame
1909      gets set up:
1910 
1911 	1. Use a caller-saved saved register:
1912 
1913 		leaq  8(%rsp), %reg
1914 		andq  $-XXX, %rsp
1915 		pushq -8(%reg)
1916 
1917 	   or
1918 
1919 		[addr32] leal  8(%rsp), %reg
1920 		andl  $-XXX, %esp
1921 		[addr32] pushq -8(%reg)
1922 
1923 	2. Use a callee-saved saved register:
1924 
1925 		pushq %reg
1926 		leaq  16(%rsp), %reg
1927 		andq  $-XXX, %rsp
1928 		pushq -8(%reg)
1929 
1930 	   or
1931 
1932 		pushq %reg
1933 		[addr32] leal  16(%rsp), %reg
1934 		andl  $-XXX, %esp
1935 		[addr32] pushq -8(%reg)
1936 
1937      "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1938 
1939      	0x48 0x83 0xe4 0xf0			andq $-16, %rsp
1940      	0x48 0x81 0xe4 0x00 0xff 0xff 0xff	andq $-256, %rsp
1941 
1942      "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1943 
1944      	0x83 0xe4 0xf0			andl $-16, %esp
1945      	0x81 0xe4 0x00 0xff 0xff 0xff	andl $-256, %esp
1946    */
1947 
1948   gdb_byte buf[19];
1949   int reg, r;
1950   int offset, offset_and;
1951 
1952   if (target_read_memory (pc, buf, sizeof buf))
1953     return pc;
1954 
1955   /* Skip optional addr32 prefix.  */
1956   offset = buf[0] == 0x67 ? 1 : 0;
1957 
1958   /* Check caller-saved saved register.  The first instruction has
1959      to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg".  */
1960   if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
1961       && buf[offset + 1] == 0x8d
1962       && buf[offset + 3] == 0x24
1963       && buf[offset + 4] == 0x8)
1964     {
1965       /* MOD must be binary 10 and R/M must be binary 100.  */
1966       if ((buf[offset + 2] & 0xc7) != 0x44)
1967 	return pc;
1968 
1969       /* REG has register number.  */
1970       reg = (buf[offset + 2] >> 3) & 7;
1971 
1972       /* Check the REX.R bit.  */
1973       if ((buf[offset] & 0x4) != 0)
1974 	reg += 8;
1975 
1976       offset += 5;
1977     }
1978   else
1979     {
1980       /* Check callee-saved saved register.  The first instruction
1981 	 has to be "pushq %reg".  */
1982       reg = 0;
1983       if ((buf[offset] & 0xf6) == 0x40
1984 	  && (buf[offset + 1] & 0xf8) == 0x50)
1985 	{
1986 	  /* Check the REX.B bit.  */
1987 	  if ((buf[offset] & 1) != 0)
1988 	    reg = 8;
1989 
1990 	  offset += 1;
1991 	}
1992       else if ((buf[offset] & 0xf8) != 0x50)
1993 	return pc;
1994 
1995       /* Get register.  */
1996       reg += buf[offset] & 0x7;
1997 
1998       offset++;
1999 
2000       /* Skip optional addr32 prefix.  */
2001       if (buf[offset] == 0x67)
2002 	offset++;
2003 
2004       /* The next instruction has to be "leaq 16(%rsp), %reg" or
2005 	 "leal 16(%rsp), %reg".  */
2006       if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2007 	  || buf[offset + 1] != 0x8d
2008 	  || buf[offset + 3] != 0x24
2009 	  || buf[offset + 4] != 0x10)
2010 	return pc;
2011 
2012       /* MOD must be binary 10 and R/M must be binary 100.  */
2013       if ((buf[offset + 2] & 0xc7) != 0x44)
2014 	return pc;
2015 
2016       /* REG has register number.  */
2017       r = (buf[offset + 2] >> 3) & 7;
2018 
2019       /* Check the REX.R bit.  */
2020       if ((buf[offset] & 0x4) != 0)
2021 	r += 8;
2022 
2023       /* Registers in pushq and leaq have to be the same.  */
2024       if (reg != r)
2025 	return pc;
2026 
2027       offset += 5;
2028     }
2029 
2030   /* Rigister can't be %rsp nor %rbp.  */
2031   if (reg == 4 || reg == 5)
2032     return pc;
2033 
2034   /* The next instruction may be "andq $-XXX, %rsp" or
2035      "andl $-XXX, %esp".  */
2036   if (buf[offset] != 0x48)
2037     offset--;
2038 
2039   if (buf[offset + 2] != 0xe4
2040       || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2041     return pc;
2042 
2043   offset_and = offset;
2044   offset += buf[offset + 1] == 0x81 ? 7 : 4;
2045 
2046   /* Skip optional addr32 prefix.  */
2047   if (buf[offset] == 0x67)
2048     offset++;
2049 
2050   /* The next instruction has to be "pushq -8(%reg)".  */
2051   r = 0;
2052   if (buf[offset] == 0xff)
2053     offset++;
2054   else if ((buf[offset] & 0xf6) == 0x40
2055 	   && buf[offset + 1] == 0xff)
2056     {
2057       /* Check the REX.B bit.  */
2058       if ((buf[offset] & 0x1) != 0)
2059 	r = 8;
2060       offset += 2;
2061     }
2062   else
2063     return pc;
2064 
2065   /* 8bit -8 is 0xf8.  REG must be binary 110 and MOD must be binary
2066      01.  */
2067   if (buf[offset + 1] != 0xf8
2068       || (buf[offset] & 0xf8) != 0x70)
2069     return pc;
2070 
2071   /* R/M has register.  */
2072   r += buf[offset] & 7;
2073 
2074   /* Registers in leaq and pushq have to be the same.  */
2075   if (reg != r)
2076     return pc;
2077 
2078   if (current_pc > pc + offset_and)
2079     cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2080 
2081   return min (pc + offset + 2, current_pc);
2082 }
2083 
2084 /* Do a limited analysis of the prologue at PC and update CACHE
2085    accordingly.  Bail out early if CURRENT_PC is reached.  Return the
2086    address where the analysis stopped.
2087 
2088    We will handle only functions beginning with:
2089 
2090       pushq %rbp        0x55
2091       movq %rsp, %rbp   0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2092 
2093    or (for the X32 ABI):
2094 
2095       pushq %rbp        0x55
2096       movl %esp, %ebp   0x89 0xe5 (or 0x8b 0xec)
2097 
2098    Any function that doesn't start with one of these sequences will be
2099    assumed to have no prologue and thus no valid frame pointer in
2100    %rbp.  */
2101 
2102 static CORE_ADDR
amd64_analyze_prologue(struct gdbarch * gdbarch,CORE_ADDR pc,CORE_ADDR current_pc,struct amd64_frame_cache * cache)2103 amd64_analyze_prologue (struct gdbarch *gdbarch,
2104 			CORE_ADDR pc, CORE_ADDR current_pc,
2105 			struct amd64_frame_cache *cache)
2106 {
2107   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2108   /* There are two variations of movq %rsp, %rbp.  */
2109   static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2110   static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2111   /* Ditto for movl %esp, %ebp.  */
2112   static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2113   static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2114 
2115   gdb_byte buf[3];
2116   gdb_byte op;
2117 
2118   if (current_pc <= pc)
2119     return current_pc;
2120 
2121   if (gdbarch_ptr_bit (gdbarch) == 32)
2122     pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2123   else
2124     pc = amd64_analyze_stack_align (pc, current_pc, cache);
2125 
2126   op = read_memory_unsigned_integer (pc, 1, byte_order);
2127 
2128   if (op == 0x55)		/* pushq %rbp */
2129     {
2130       /* Take into account that we've executed the `pushq %rbp' that
2131          starts this instruction sequence.  */
2132       cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2133       cache->sp_offset += 8;
2134 
2135       /* If that's all, return now.  */
2136       if (current_pc <= pc + 1)
2137         return current_pc;
2138 
2139       read_memory (pc + 1, buf, 3);
2140 
2141       /* Check for `movq %rsp, %rbp'.  */
2142       if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2143 	  || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2144 	{
2145 	  /* OK, we actually have a frame.  */
2146 	  cache->frameless_p = 0;
2147 	  return pc + 4;
2148 	}
2149 
2150       /* For X32, also check for `movq %esp, %ebp'.  */
2151       if (gdbarch_ptr_bit (gdbarch) == 32)
2152 	{
2153 	  if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2154 	      || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2155 	    {
2156 	      /* OK, we actually have a frame.  */
2157 	      cache->frameless_p = 0;
2158 	      return pc + 3;
2159 	    }
2160 	}
2161 
2162       return pc + 1;
2163     }
2164 
2165   return pc;
2166 }
2167 
2168 /* Work around false termination of prologue - GCC PR debug/48827.
2169 
2170    START_PC is the first instruction of a function, PC is its minimal already
2171    determined advanced address.  Function returns PC if it has nothing to do.
2172 
2173    84 c0                test   %al,%al
2174    74 23                je     after
2175    <-- here is 0 lines advance - the false prologue end marker.
2176    0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2177    0f 29 4d 80          movaps %xmm1,-0x80(%rbp)
2178    0f 29 55 90          movaps %xmm2,-0x70(%rbp)
2179    0f 29 5d a0          movaps %xmm3,-0x60(%rbp)
2180    0f 29 65 b0          movaps %xmm4,-0x50(%rbp)
2181    0f 29 6d c0          movaps %xmm5,-0x40(%rbp)
2182    0f 29 75 d0          movaps %xmm6,-0x30(%rbp)
2183    0f 29 7d e0          movaps %xmm7,-0x20(%rbp)
2184    after:  */
2185 
2186 static CORE_ADDR
amd64_skip_xmm_prologue(CORE_ADDR pc,CORE_ADDR start_pc)2187 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2188 {
2189   struct symtab_and_line start_pc_sal, next_sal;
2190   gdb_byte buf[4 + 8 * 7];
2191   int offset, xmmreg;
2192 
2193   if (pc == start_pc)
2194     return pc;
2195 
2196   start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2197   if (start_pc_sal.symtab == NULL
2198       || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6
2199       || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2200     return pc;
2201 
2202   next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2203   if (next_sal.line != start_pc_sal.line)
2204     return pc;
2205 
2206   /* START_PC can be from overlayed memory, ignored here.  */
2207   if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2208     return pc;
2209 
2210   /* test %al,%al */
2211   if (buf[0] != 0x84 || buf[1] != 0xc0)
2212     return pc;
2213   /* je AFTER */
2214   if (buf[2] != 0x74)
2215     return pc;
2216 
2217   offset = 4;
2218   for (xmmreg = 0; xmmreg < 8; xmmreg++)
2219     {
2220       /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2221       if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2222           || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2223 	return pc;
2224 
2225       /* 0b01?????? */
2226       if ((buf[offset + 2] & 0xc0) == 0x40)
2227 	{
2228 	  /* 8-bit displacement.  */
2229 	  offset += 4;
2230 	}
2231       /* 0b10?????? */
2232       else if ((buf[offset + 2] & 0xc0) == 0x80)
2233 	{
2234 	  /* 32-bit displacement.  */
2235 	  offset += 7;
2236 	}
2237       else
2238 	return pc;
2239     }
2240 
2241   /* je AFTER */
2242   if (offset - 4 != buf[3])
2243     return pc;
2244 
2245   return next_sal.end;
2246 }
2247 
2248 /* Return PC of first real instruction.  */
2249 
2250 static CORE_ADDR
amd64_skip_prologue(struct gdbarch * gdbarch,CORE_ADDR start_pc)2251 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2252 {
2253   struct amd64_frame_cache cache;
2254   CORE_ADDR pc;
2255   CORE_ADDR func_addr;
2256 
2257   if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2258     {
2259       CORE_ADDR post_prologue_pc
2260 	= skip_prologue_using_sal (gdbarch, func_addr);
2261       struct symtab *s = find_pc_symtab (func_addr);
2262 
2263       /* Clang always emits a line note before the prologue and another
2264 	 one after.  We trust clang to emit usable line notes.  */
2265       if (post_prologue_pc
2266 	  && (s != NULL
2267 	      && s->producer != NULL
2268 	      && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
2269         return max (start_pc, post_prologue_pc);
2270     }
2271 
2272   amd64_init_frame_cache (&cache);
2273   pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2274 			       &cache);
2275   if (cache.frameless_p)
2276     return start_pc;
2277 
2278   return amd64_skip_xmm_prologue (pc, start_pc);
2279 }
2280 
2281 
2282 /* Normal frames.  */
2283 
2284 static void
amd64_frame_cache_1(struct frame_info * this_frame,struct amd64_frame_cache * cache)2285 amd64_frame_cache_1 (struct frame_info *this_frame,
2286 		     struct amd64_frame_cache *cache)
2287 {
2288   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2289   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2290   gdb_byte buf[8];
2291   int i;
2292 
2293   cache->pc = get_frame_func (this_frame);
2294   if (cache->pc != 0)
2295     amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2296 			    cache);
2297 
2298   if (cache->frameless_p)
2299     {
2300       /* We didn't find a valid frame.  If we're at the start of a
2301 	 function, or somewhere half-way its prologue, the function's
2302 	 frame probably hasn't been fully setup yet.  Try to
2303 	 reconstruct the base address for the stack frame by looking
2304 	 at the stack pointer.  For truly "frameless" functions this
2305 	 might work too.  */
2306 
2307       if (cache->saved_sp_reg != -1)
2308 	{
2309 	  /* Stack pointer has been saved.  */
2310 	  get_frame_register (this_frame, cache->saved_sp_reg, buf);
2311 	  cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2312 
2313 	  /* We're halfway aligning the stack.  */
2314 	  cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2315 	  cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2316 
2317 	  /* This will be added back below.  */
2318 	  cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2319 	}
2320       else
2321 	{
2322 	  get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2323 	  cache->base = extract_unsigned_integer (buf, 8, byte_order)
2324 			+ cache->sp_offset;
2325 	}
2326     }
2327   else
2328     {
2329       get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2330       cache->base = extract_unsigned_integer (buf, 8, byte_order);
2331     }
2332 
2333   /* Now that we have the base address for the stack frame we can
2334      calculate the value of %rsp in the calling frame.  */
2335   cache->saved_sp = cache->base + 16;
2336 
2337   /* For normal frames, %rip is stored at 8(%rbp).  If we don't have a
2338      frame we find it at the same offset from the reconstructed base
2339      address.  If we're halfway aligning the stack, %rip is handled
2340      differently (see above).  */
2341   if (!cache->frameless_p || cache->saved_sp_reg == -1)
2342     cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2343 
2344   /* Adjust all the saved registers such that they contain addresses
2345      instead of offsets.  */
2346   for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2347     if (cache->saved_regs[i] != -1)
2348       cache->saved_regs[i] += cache->base;
2349 
2350   cache->base_p = 1;
2351 }
2352 
2353 static struct amd64_frame_cache *
amd64_frame_cache(struct frame_info * this_frame,void ** this_cache)2354 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2355 {
2356   volatile struct gdb_exception ex;
2357   struct amd64_frame_cache *cache;
2358 
2359   if (*this_cache)
2360     return *this_cache;
2361 
2362   cache = amd64_alloc_frame_cache ();
2363   *this_cache = cache;
2364 
2365   TRY_CATCH (ex, RETURN_MASK_ERROR)
2366     {
2367       amd64_frame_cache_1 (this_frame, cache);
2368     }
2369   if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2370     throw_exception (ex);
2371 
2372   return cache;
2373 }
2374 
2375 static enum unwind_stop_reason
amd64_frame_unwind_stop_reason(struct frame_info * this_frame,void ** this_cache)2376 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2377 				void **this_cache)
2378 {
2379   struct amd64_frame_cache *cache =
2380     amd64_frame_cache (this_frame, this_cache);
2381 
2382   if (!cache->base_p)
2383     return UNWIND_UNAVAILABLE;
2384 
2385   /* This marks the outermost frame.  */
2386   if (cache->base == 0)
2387     return UNWIND_OUTERMOST;
2388 
2389   return UNWIND_NO_REASON;
2390 }
2391 
2392 static void
amd64_frame_this_id(struct frame_info * this_frame,void ** this_cache,struct frame_id * this_id)2393 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2394 		     struct frame_id *this_id)
2395 {
2396   struct amd64_frame_cache *cache =
2397     amd64_frame_cache (this_frame, this_cache);
2398 
2399   if (!cache->base_p)
2400     return;
2401 
2402   /* This marks the outermost frame.  */
2403   if (cache->base == 0)
2404     return;
2405 
2406   (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2407 }
2408 
2409 static struct value *
amd64_frame_prev_register(struct frame_info * this_frame,void ** this_cache,int regnum)2410 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2411 			   int regnum)
2412 {
2413   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2414   struct amd64_frame_cache *cache =
2415     amd64_frame_cache (this_frame, this_cache);
2416 
2417   gdb_assert (regnum >= 0);
2418 
2419   if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2420     return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2421 
2422   if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2423     return frame_unwind_got_memory (this_frame, regnum,
2424 				    cache->saved_regs[regnum]);
2425 
2426   return frame_unwind_got_register (this_frame, regnum, regnum);
2427 }
2428 
2429 static const struct frame_unwind amd64_frame_unwind =
2430 {
2431   NORMAL_FRAME,
2432   amd64_frame_unwind_stop_reason,
2433   amd64_frame_this_id,
2434   amd64_frame_prev_register,
2435   NULL,
2436   default_frame_sniffer
2437 };
2438 
2439 /* Generate a bytecode expression to get the value of the saved PC.  */
2440 
2441 static void
amd64_gen_return_address(struct gdbarch * gdbarch,struct agent_expr * ax,struct axs_value * value,CORE_ADDR scope)2442 amd64_gen_return_address (struct gdbarch *gdbarch,
2443 			  struct agent_expr *ax, struct axs_value *value,
2444 			  CORE_ADDR scope)
2445 {
2446   /* The following sequence assumes the traditional use of the base
2447      register.  */
2448   ax_reg (ax, AMD64_RBP_REGNUM);
2449   ax_const_l (ax, 8);
2450   ax_simple (ax, aop_add);
2451   value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2452   value->kind = axs_lvalue_memory;
2453 }
2454 
2455 
2456 /* Signal trampolines.  */
2457 
2458 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2459    64-bit variants.  This would require using identical frame caches
2460    on both platforms.  */
2461 
2462 static struct amd64_frame_cache *
amd64_sigtramp_frame_cache(struct frame_info * this_frame,void ** this_cache)2463 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2464 {
2465   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2466   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2467   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2468   volatile struct gdb_exception ex;
2469   struct amd64_frame_cache *cache;
2470   CORE_ADDR addr;
2471   gdb_byte buf[8];
2472   int i;
2473 
2474   if (*this_cache)
2475     return *this_cache;
2476 
2477   cache = amd64_alloc_frame_cache ();
2478 
2479   TRY_CATCH (ex, RETURN_MASK_ERROR)
2480     {
2481       get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2482       cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2483 
2484       addr = tdep->sigcontext_addr (this_frame);
2485       gdb_assert (tdep->sc_reg_offset);
2486       gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2487       for (i = 0; i < tdep->sc_num_regs; i++)
2488 	if (tdep->sc_reg_offset[i] != -1)
2489 	  cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2490 
2491       cache->base_p = 1;
2492     }
2493   if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2494     throw_exception (ex);
2495 
2496   *this_cache = cache;
2497   return cache;
2498 }
2499 
2500 static enum unwind_stop_reason
amd64_sigtramp_frame_unwind_stop_reason(struct frame_info * this_frame,void ** this_cache)2501 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2502 					 void **this_cache)
2503 {
2504   struct amd64_frame_cache *cache =
2505     amd64_sigtramp_frame_cache (this_frame, this_cache);
2506 
2507   if (!cache->base_p)
2508     return UNWIND_UNAVAILABLE;
2509 
2510   return UNWIND_NO_REASON;
2511 }
2512 
2513 static void
amd64_sigtramp_frame_this_id(struct frame_info * this_frame,void ** this_cache,struct frame_id * this_id)2514 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2515 			      void **this_cache, struct frame_id *this_id)
2516 {
2517   struct amd64_frame_cache *cache =
2518     amd64_sigtramp_frame_cache (this_frame, this_cache);
2519 
2520   if (!cache->base_p)
2521     return;
2522 
2523   (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2524 }
2525 
2526 static struct value *
amd64_sigtramp_frame_prev_register(struct frame_info * this_frame,void ** this_cache,int regnum)2527 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2528 				    void **this_cache, int regnum)
2529 {
2530   /* Make sure we've initialized the cache.  */
2531   amd64_sigtramp_frame_cache (this_frame, this_cache);
2532 
2533   return amd64_frame_prev_register (this_frame, this_cache, regnum);
2534 }
2535 
2536 static int
amd64_sigtramp_frame_sniffer(const struct frame_unwind * self,struct frame_info * this_frame,void ** this_cache)2537 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2538 			      struct frame_info *this_frame,
2539 			      void **this_cache)
2540 {
2541   struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2542 
2543   /* We shouldn't even bother if we don't have a sigcontext_addr
2544      handler.  */
2545   if (tdep->sigcontext_addr == NULL)
2546     return 0;
2547 
2548   if (tdep->sigtramp_p != NULL)
2549     {
2550       if (tdep->sigtramp_p (this_frame))
2551 	return 1;
2552     }
2553 
2554   if (tdep->sigtramp_start != 0)
2555     {
2556       CORE_ADDR pc = get_frame_pc (this_frame);
2557 
2558       gdb_assert (tdep->sigtramp_end != 0);
2559       if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2560 	return 1;
2561     }
2562 
2563   return 0;
2564 }
2565 
2566 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2567 {
2568   SIGTRAMP_FRAME,
2569   amd64_sigtramp_frame_unwind_stop_reason,
2570   amd64_sigtramp_frame_this_id,
2571   amd64_sigtramp_frame_prev_register,
2572   NULL,
2573   amd64_sigtramp_frame_sniffer
2574 };
2575 
2576 
2577 static CORE_ADDR
amd64_frame_base_address(struct frame_info * this_frame,void ** this_cache)2578 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2579 {
2580   struct amd64_frame_cache *cache =
2581     amd64_frame_cache (this_frame, this_cache);
2582 
2583   return cache->base;
2584 }
2585 
2586 static const struct frame_base amd64_frame_base =
2587 {
2588   &amd64_frame_unwind,
2589   amd64_frame_base_address,
2590   amd64_frame_base_address,
2591   amd64_frame_base_address
2592 };
2593 
2594 /* Normal frames, but in a function epilogue.  */
2595 
2596 /* The epilogue is defined here as the 'ret' instruction, which will
2597    follow any instruction such as 'leave' or 'pop %ebp' that destroys
2598    the function's stack frame.  */
2599 
2600 static int
amd64_in_function_epilogue_p(struct gdbarch * gdbarch,CORE_ADDR pc)2601 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2602 {
2603   gdb_byte insn;
2604   struct symtab *symtab;
2605 
2606   symtab = find_pc_symtab (pc);
2607   if (symtab && symtab->epilogue_unwind_valid)
2608     return 0;
2609 
2610   if (target_read_memory (pc, &insn, 1))
2611     return 0;   /* Can't read memory at pc.  */
2612 
2613   if (insn != 0xc3)     /* 'ret' instruction.  */
2614     return 0;
2615 
2616   return 1;
2617 }
2618 
2619 static int
amd64_epilogue_frame_sniffer(const struct frame_unwind * self,struct frame_info * this_frame,void ** this_prologue_cache)2620 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2621 			      struct frame_info *this_frame,
2622 			      void **this_prologue_cache)
2623 {
2624   if (frame_relative_level (this_frame) == 0)
2625     return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
2626 					 get_frame_pc (this_frame));
2627   else
2628     return 0;
2629 }
2630 
2631 static struct amd64_frame_cache *
amd64_epilogue_frame_cache(struct frame_info * this_frame,void ** this_cache)2632 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2633 {
2634   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2635   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2636   volatile struct gdb_exception ex;
2637   struct amd64_frame_cache *cache;
2638   gdb_byte buf[8];
2639 
2640   if (*this_cache)
2641     return *this_cache;
2642 
2643   cache = amd64_alloc_frame_cache ();
2644   *this_cache = cache;
2645 
2646   TRY_CATCH (ex, RETURN_MASK_ERROR)
2647     {
2648       /* Cache base will be %esp plus cache->sp_offset (-8).  */
2649       get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2650       cache->base = extract_unsigned_integer (buf, 8,
2651 					      byte_order) + cache->sp_offset;
2652 
2653       /* Cache pc will be the frame func.  */
2654       cache->pc = get_frame_pc (this_frame);
2655 
2656       /* The saved %esp will be at cache->base plus 16.  */
2657       cache->saved_sp = cache->base + 16;
2658 
2659       /* The saved %eip will be at cache->base plus 8.  */
2660       cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2661 
2662       cache->base_p = 1;
2663     }
2664   if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2665     throw_exception (ex);
2666 
2667   return cache;
2668 }
2669 
2670 static enum unwind_stop_reason
amd64_epilogue_frame_unwind_stop_reason(struct frame_info * this_frame,void ** this_cache)2671 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2672 					 void **this_cache)
2673 {
2674   struct amd64_frame_cache *cache
2675     = amd64_epilogue_frame_cache (this_frame, this_cache);
2676 
2677   if (!cache->base_p)
2678     return UNWIND_UNAVAILABLE;
2679 
2680   return UNWIND_NO_REASON;
2681 }
2682 
2683 static void
amd64_epilogue_frame_this_id(struct frame_info * this_frame,void ** this_cache,struct frame_id * this_id)2684 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2685 			      void **this_cache,
2686 			      struct frame_id *this_id)
2687 {
2688   struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2689 							       this_cache);
2690 
2691   if (!cache->base_p)
2692     return;
2693 
2694   (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2695 }
2696 
2697 static const struct frame_unwind amd64_epilogue_frame_unwind =
2698 {
2699   NORMAL_FRAME,
2700   amd64_epilogue_frame_unwind_stop_reason,
2701   amd64_epilogue_frame_this_id,
2702   amd64_frame_prev_register,
2703   NULL,
2704   amd64_epilogue_frame_sniffer
2705 };
2706 
2707 static struct frame_id
amd64_dummy_id(struct gdbarch * gdbarch,struct frame_info * this_frame)2708 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2709 {
2710   CORE_ADDR fp;
2711 
2712   fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2713 
2714   return frame_id_build (fp + 16, get_frame_pc (this_frame));
2715 }
2716 
2717 /* 16 byte align the SP per frame requirements.  */
2718 
2719 static CORE_ADDR
amd64_frame_align(struct gdbarch * gdbarch,CORE_ADDR sp)2720 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2721 {
2722   return sp & -(CORE_ADDR)16;
2723 }
2724 
2725 
2726 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2727    in the floating-point register set REGSET to register cache
2728    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
2729 
2730 static void
amd64_supply_fpregset(const struct regset * regset,struct regcache * regcache,int regnum,const void * fpregs,size_t len)2731 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2732 		       int regnum, const void *fpregs, size_t len)
2733 {
2734   const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2735 
2736   gdb_assert (len == tdep->sizeof_fpregset);
2737   amd64_supply_fxsave (regcache, regnum, fpregs);
2738 }
2739 
2740 /* Collect register REGNUM from the register cache REGCACHE and store
2741    it in the buffer specified by FPREGS and LEN as described by the
2742    floating-point register set REGSET.  If REGNUM is -1, do this for
2743    all registers in REGSET.  */
2744 
2745 static void
amd64_collect_fpregset(const struct regset * regset,const struct regcache * regcache,int regnum,void * fpregs,size_t len)2746 amd64_collect_fpregset (const struct regset *regset,
2747 			const struct regcache *regcache,
2748 			int regnum, void *fpregs, size_t len)
2749 {
2750   const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2751 
2752   gdb_assert (len == tdep->sizeof_fpregset);
2753   amd64_collect_fxsave (regcache, regnum, fpregs);
2754 }
2755 
2756 /* Similar to amd64_supply_fpregset, but use XSAVE extended state.  */
2757 
2758 static void
amd64_supply_xstateregset(const struct regset * regset,struct regcache * regcache,int regnum,const void * xstateregs,size_t len)2759 amd64_supply_xstateregset (const struct regset *regset,
2760 			   struct regcache *regcache, int regnum,
2761 			   const void *xstateregs, size_t len)
2762 {
2763   amd64_supply_xsave (regcache, regnum, xstateregs);
2764 }
2765 
2766 /* Similar to amd64_collect_fpregset, but use XSAVE extended state.  */
2767 
2768 static void
amd64_collect_xstateregset(const struct regset * regset,const struct regcache * regcache,int regnum,void * xstateregs,size_t len)2769 amd64_collect_xstateregset (const struct regset *regset,
2770 			    const struct regcache *regcache,
2771 			    int regnum, void *xstateregs, size_t len)
2772 {
2773   amd64_collect_xsave (regcache, regnum, xstateregs, 1);
2774 }
2775 
2776 /* Return the appropriate register set for the core section identified
2777    by SECT_NAME and SECT_SIZE.  */
2778 
2779 static const struct regset *
amd64_regset_from_core_section(struct gdbarch * gdbarch,const char * sect_name,size_t sect_size)2780 amd64_regset_from_core_section (struct gdbarch *gdbarch,
2781 				const char *sect_name, size_t sect_size)
2782 {
2783   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2784 
2785   if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2786     {
2787       if (tdep->fpregset == NULL)
2788 	tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
2789 				       amd64_collect_fpregset);
2790 
2791       return tdep->fpregset;
2792     }
2793 
2794   if (strcmp (sect_name, ".reg-xstate") == 0)
2795     {
2796       if (tdep->xstateregset == NULL)
2797 	tdep->xstateregset = regset_alloc (gdbarch,
2798 					   amd64_supply_xstateregset,
2799 					   amd64_collect_xstateregset);
2800 
2801       return tdep->xstateregset;
2802     }
2803 
2804   return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
2805 }
2806 
2807 
2808 /* Figure out where the longjmp will land.  Slurp the jmp_buf out of
2809    %rdi.  We expect its value to be a pointer to the jmp_buf structure
2810    from which we extract the address that we will land at.  This
2811    address is copied into PC.  This routine returns non-zero on
2812    success.  */
2813 
2814 static int
amd64_get_longjmp_target(struct frame_info * frame,CORE_ADDR * pc)2815 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2816 {
2817   gdb_byte buf[8];
2818   CORE_ADDR jb_addr;
2819   struct gdbarch *gdbarch = get_frame_arch (frame);
2820   int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2821   int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2822 
2823   /* If JB_PC_OFFSET is -1, we have no way to find out where the
2824      longjmp will land.	 */
2825   if (jb_pc_offset == -1)
2826     return 0;
2827 
2828   get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2829   jb_addr= extract_typed_address
2830 	    (buf, builtin_type (gdbarch)->builtin_data_ptr);
2831   if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2832     return 0;
2833 
2834   *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2835 
2836   return 1;
2837 }
2838 
2839 static const int amd64_record_regmap[] =
2840 {
2841   AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2842   AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2843   AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2844   AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2845   AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2846   AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2847 };
2848 
2849 void
amd64_init_abi(struct gdbarch_info info,struct gdbarch * gdbarch)2850 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2851 {
2852   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2853   const struct target_desc *tdesc = info.target_desc;
2854 
2855   /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2856      floating-point registers.  */
2857   tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
2858 
2859   if (! tdesc_has_registers (tdesc))
2860     tdesc = tdesc_amd64;
2861   tdep->tdesc = tdesc;
2862 
2863   tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2864   tdep->register_names = amd64_register_names;
2865 
2866   if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2867     {
2868       tdep->ymmh_register_names = amd64_ymmh_names;
2869       tdep->num_ymm_regs = 16;
2870       tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
2871     }
2872 
2873   tdep->num_byte_regs = 20;
2874   tdep->num_word_regs = 16;
2875   tdep->num_dword_regs = 16;
2876   /* Avoid wiring in the MMX registers for now.  */
2877   tdep->num_mmx_regs = 0;
2878 
2879   set_gdbarch_pseudo_register_read_value (gdbarch,
2880 					  amd64_pseudo_register_read_value);
2881   set_gdbarch_pseudo_register_write (gdbarch,
2882 				     amd64_pseudo_register_write);
2883 
2884   set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
2885 
2886   /* AMD64 has an FPU and 16 SSE registers.  */
2887   tdep->st0_regnum = AMD64_ST0_REGNUM;
2888   tdep->num_xmm_regs = 16;
2889 
2890   /* This is what all the fuss is about.  */
2891   set_gdbarch_long_bit (gdbarch, 64);
2892   set_gdbarch_long_long_bit (gdbarch, 64);
2893   set_gdbarch_ptr_bit (gdbarch, 64);
2894 
2895   /* In contrast to the i386, on AMD64 a `long double' actually takes
2896      up 128 bits, even though it's still based on the i387 extended
2897      floating-point format which has only 80 significant bits.  */
2898   set_gdbarch_long_double_bit (gdbarch, 128);
2899 
2900   set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
2901 
2902   /* Register numbers of various important registers.  */
2903   set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
2904   set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
2905   set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
2906   set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
2907 
2908   /* The "default" register numbering scheme for AMD64 is referred to
2909      as the "DWARF Register Number Mapping" in the System V psABI.
2910      The preferred debugging format for all known AMD64 targets is
2911      actually DWARF2, and GCC doesn't seem to support DWARF (that is
2912      DWARF-1), but we provide the same mapping just in case.  This
2913      mapping is also used for stabs, which GCC does support.  */
2914   set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2915   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
2916 
2917   /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2918      be in use on any of the supported AMD64 targets.  */
2919 
2920   /* Call dummy code.  */
2921   set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
2922   set_gdbarch_frame_align (gdbarch, amd64_frame_align);
2923   set_gdbarch_frame_red_zone_size (gdbarch, 128);
2924   tdep->call_dummy_num_integer_regs =
2925     ARRAY_SIZE (amd64_dummy_call_integer_regs);
2926   tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs;
2927   tdep->classify = amd64_classify;
2928 
2929   set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
2930   set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
2931   set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
2932 
2933   set_gdbarch_return_value (gdbarch, amd64_return_value);
2934 
2935   set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
2936 
2937   tdep->record_regmap = amd64_record_regmap;
2938 
2939   set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
2940 
2941   /* Hook the function epilogue frame unwinder.  This unwinder is
2942      appended to the list first, so that it supercedes the other
2943      unwinders in function epilogues.  */
2944   frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
2945 
2946   /* Hook the prologue-based frame unwinders.  */
2947   frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
2948   frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
2949   frame_base_set_default (gdbarch, &amd64_frame_base);
2950 
2951   /* If we have a register mapping, enable the generic core file support.  */
2952   if (tdep->gregset_reg_offset)
2953     set_gdbarch_regset_from_core_section (gdbarch,
2954 					  amd64_regset_from_core_section);
2955 
2956   set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
2957 
2958   set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
2959 
2960   set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
2961 
2962   /* SystemTap variables and functions.  */
2963   set_gdbarch_stap_integer_prefix (gdbarch, "$");
2964   set_gdbarch_stap_register_prefix (gdbarch, "%");
2965   set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
2966   set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
2967   set_gdbarch_stap_is_single_operand (gdbarch,
2968 				      i386_stap_is_single_operand);
2969   set_gdbarch_stap_parse_special_token (gdbarch,
2970 					i386_stap_parse_special_token);
2971 }
2972 
2973 
2974 static struct type *
amd64_x32_pseudo_register_type(struct gdbarch * gdbarch,int regnum)2975 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2976 {
2977   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2978 
2979   switch (regnum - tdep->eax_regnum)
2980     {
2981     case AMD64_RBP_REGNUM:	/* %ebp */
2982     case AMD64_RSP_REGNUM:	/* %esp */
2983       return builtin_type (gdbarch)->builtin_data_ptr;
2984     case AMD64_RIP_REGNUM:	/* %eip */
2985       return builtin_type (gdbarch)->builtin_func_ptr;
2986     }
2987 
2988   return i386_pseudo_register_type (gdbarch, regnum);
2989 }
2990 
2991 void
amd64_x32_init_abi(struct gdbarch_info info,struct gdbarch * gdbarch)2992 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2993 {
2994   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2995   const struct target_desc *tdesc = info.target_desc;
2996 
2997   amd64_init_abi (info, gdbarch);
2998 
2999   if (! tdesc_has_registers (tdesc))
3000     tdesc = tdesc_x32;
3001   tdep->tdesc = tdesc;
3002 
3003   tdep->num_dword_regs = 17;
3004   set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3005 
3006   set_gdbarch_long_bit (gdbarch, 32);
3007   set_gdbarch_ptr_bit (gdbarch, 32);
3008 }
3009 
3010 /* Provide a prototype to silence -Wmissing-prototypes.  */
3011 void _initialize_amd64_tdep (void);
3012 
3013 void
_initialize_amd64_tdep(void)3014 _initialize_amd64_tdep (void)
3015 {
3016   initialize_tdesc_amd64 ();
3017   initialize_tdesc_amd64_avx ();
3018   initialize_tdesc_x32 ();
3019   initialize_tdesc_x32_avx ();
3020 }
3021 
3022 
3023 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3024    sense that the instruction pointer and data pointer are simply
3025    64-bit offsets into the code segment and the data segment instead
3026    of a selector offset pair.  The functions below store the upper 32
3027    bits of these pointers (instead of just the 16-bits of the segment
3028    selector).  */
3029 
3030 /* Fill register REGNUM in REGCACHE with the appropriate
3031    floating-point or SSE register value from *FXSAVE.  If REGNUM is
3032    -1, do this for all registers.  This function masks off any of the
3033    reserved bits in *FXSAVE.  */
3034 
3035 void
amd64_supply_fxsave(struct regcache * regcache,int regnum,const void * fxsave)3036 amd64_supply_fxsave (struct regcache *regcache, int regnum,
3037 		     const void *fxsave)
3038 {
3039   struct gdbarch *gdbarch = get_regcache_arch (regcache);
3040   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3041 
3042   i387_supply_fxsave (regcache, regnum, fxsave);
3043 
3044   if (fxsave
3045       && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3046     {
3047       const gdb_byte *regs = fxsave;
3048 
3049       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3050 	regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3051       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3052 	regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3053     }
3054 }
3055 
3056 /* Similar to amd64_supply_fxsave, but use XSAVE extended state.  */
3057 
3058 void
amd64_supply_xsave(struct regcache * regcache,int regnum,const void * xsave)3059 amd64_supply_xsave (struct regcache *regcache, int regnum,
3060 		    const void *xsave)
3061 {
3062   struct gdbarch *gdbarch = get_regcache_arch (regcache);
3063   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3064 
3065   i387_supply_xsave (regcache, regnum, xsave);
3066 
3067   if (xsave
3068       && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3069     {
3070       const gdb_byte *regs = xsave;
3071 
3072       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3073 	regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3074 			     regs + 12);
3075       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3076 	regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3077 			     regs + 20);
3078     }
3079 }
3080 
3081 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3082    *FXSAVE with the value from REGCACHE.  If REGNUM is -1, do this for
3083    all registers.  This function doesn't touch any of the reserved
3084    bits in *FXSAVE.  */
3085 
3086 void
amd64_collect_fxsave(const struct regcache * regcache,int regnum,void * fxsave)3087 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3088 		      void *fxsave)
3089 {
3090   struct gdbarch *gdbarch = get_regcache_arch (regcache);
3091   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3092   gdb_byte *regs = fxsave;
3093 
3094   i387_collect_fxsave (regcache, regnum, fxsave);
3095 
3096   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3097     {
3098       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3099 	regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3100       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3101 	regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3102     }
3103 }
3104 
3105 /* Similar to amd64_collect_fxsave, but use XSAVE extended state.  */
3106 
3107 void
amd64_collect_xsave(const struct regcache * regcache,int regnum,void * xsave,int gcore)3108 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3109 		     void *xsave, int gcore)
3110 {
3111   struct gdbarch *gdbarch = get_regcache_arch (regcache);
3112   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3113   gdb_byte *regs = xsave;
3114 
3115   i387_collect_xsave (regcache, regnum, xsave, gcore);
3116 
3117   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3118     {
3119       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3120 	regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3121 			      regs + 12);
3122       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3123 	regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
3124 			      regs + 20);
3125     }
3126 }
3127