1 /* $NetBSD: amdgpu_atombios.c,v 1.7 2021/12/19 10:59:01 riastradh Exp $ */
2
3 /*
4 * Copyright 2007-8 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors: Dave Airlie
26 * Alex Deucher
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_atombios.c,v 1.7 2021/12/19 10:59:01 riastradh Exp $");
31
32 #include <drm/amdgpu_drm.h>
33 #include "amdgpu.h"
34 #include "amdgpu_atombios.h"
35 #include "amdgpu_atomfirmware.h"
36 #include "amdgpu_i2c.h"
37 #include "amdgpu_display.h"
38
39 #include "atom.h"
40 #include "atom-bits.h"
41 #include "atombios_encoders.h"
42 #include "bif/bif_4_1_d.h"
43
44 #include <linux/nbsd-namespace.h>
45
amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device * adev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)46 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
47 ATOM_GPIO_I2C_ASSIGMENT *gpio,
48 u8 index)
49 {
50
51 }
52
amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)53 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
54 {
55 struct amdgpu_i2c_bus_rec i2c;
56
57 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
58
59 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
60 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
61 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
62 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
63 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
64 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
65 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
66 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
67 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
68 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
69 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
70 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
71 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
72 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
73 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
74 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
75
76 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
77 i2c.hw_capable = true;
78 else
79 i2c.hw_capable = false;
80
81 if (gpio->sucI2cId.ucAccess == 0xa0)
82 i2c.mm_i2c = true;
83 else
84 i2c.mm_i2c = false;
85
86 i2c.i2c_id = gpio->sucI2cId.ucAccess;
87
88 if (i2c.mask_clk_reg)
89 i2c.valid = true;
90 else
91 i2c.valid = false;
92
93 return i2c;
94 }
95
amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device * adev,uint8_t id)96 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
97 uint8_t id)
98 {
99 struct atom_context *ctx = adev->mode_info.atom_context;
100 ATOM_GPIO_I2C_ASSIGMENT *gpio;
101 struct amdgpu_i2c_bus_rec i2c;
102 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
103 struct _ATOM_GPIO_I2C_INFO *i2c_info;
104 uint16_t data_offset, size;
105 int i, num_indices;
106
107 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
108 i2c.valid = false;
109
110 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
111 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
112
113 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
114 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
115
116 gpio = &i2c_info->asGPIO_Info[0];
117 for (i = 0; i < num_indices; i++) {
118
119 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
120
121 if (gpio->sucI2cId.ucAccess == id) {
122 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
123 break;
124 }
125 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
126 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
127 }
128 }
129
130 return i2c;
131 }
132
amdgpu_atombios_i2c_init(struct amdgpu_device * adev)133 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
134 {
135 struct atom_context *ctx = adev->mode_info.atom_context;
136 ATOM_GPIO_I2C_ASSIGMENT *gpio;
137 struct amdgpu_i2c_bus_rec i2c;
138 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
139 struct _ATOM_GPIO_I2C_INFO *i2c_info;
140 uint16_t data_offset, size;
141 int i, num_indices;
142 char stmp[32];
143
144 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
145 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
146
147 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
148 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
149
150 gpio = &i2c_info->asGPIO_Info[0];
151 for (i = 0; i < num_indices; i++) {
152 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
153
154 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
155
156 if (i2c.valid) {
157 snprintf(stmp, sizeof stmp, "0x%x", i2c.i2c_id);
158 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
159 }
160 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
161 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
162 }
163 }
164 }
165
166 struct amdgpu_gpio_rec
amdgpu_atombios_lookup_gpio(struct amdgpu_device * adev,u8 id)167 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
168 u8 id)
169 {
170 struct atom_context *ctx = adev->mode_info.atom_context;
171 struct amdgpu_gpio_rec gpio;
172 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
173 struct _ATOM_GPIO_PIN_LUT *gpio_info;
174 ATOM_GPIO_PIN_ASSIGNMENT *pin;
175 u16 data_offset, size;
176 int i, num_indices;
177
178 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
179 gpio.valid = false;
180
181 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
182 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
183
184 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
185 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
186
187 pin = gpio_info->asGPIO_Pin;
188 for (i = 0; i < num_indices; i++) {
189 if (id == pin->ucGPIO_ID) {
190 gpio.id = pin->ucGPIO_ID;
191 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
192 gpio.shift = pin->ucGpioPinBitShift;
193 gpio.mask = (1 << pin->ucGpioPinBitShift);
194 gpio.valid = true;
195 break;
196 }
197 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
198 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
199 }
200 }
201
202 return gpio;
203 }
204
205 static struct amdgpu_hpd
amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device * adev,struct amdgpu_gpio_rec * gpio)206 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
207 struct amdgpu_gpio_rec *gpio)
208 {
209 struct amdgpu_hpd hpd;
210 u32 reg;
211
212 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
213
214 reg = amdgpu_display_hpd_get_gpio_reg(adev);
215
216 hpd.gpio = *gpio;
217 if (gpio->reg == reg) {
218 switch(gpio->mask) {
219 case (1 << 0):
220 hpd.hpd = AMDGPU_HPD_1;
221 break;
222 case (1 << 8):
223 hpd.hpd = AMDGPU_HPD_2;
224 break;
225 case (1 << 16):
226 hpd.hpd = AMDGPU_HPD_3;
227 break;
228 case (1 << 24):
229 hpd.hpd = AMDGPU_HPD_4;
230 break;
231 case (1 << 26):
232 hpd.hpd = AMDGPU_HPD_5;
233 break;
234 case (1 << 28):
235 hpd.hpd = AMDGPU_HPD_6;
236 break;
237 default:
238 hpd.hpd = AMDGPU_HPD_NONE;
239 break;
240 }
241 } else
242 hpd.hpd = AMDGPU_HPD_NONE;
243 return hpd;
244 }
245
246 static const int object_connector_convert[] = {
247 DRM_MODE_CONNECTOR_Unknown,
248 DRM_MODE_CONNECTOR_DVII,
249 DRM_MODE_CONNECTOR_DVII,
250 DRM_MODE_CONNECTOR_DVID,
251 DRM_MODE_CONNECTOR_DVID,
252 DRM_MODE_CONNECTOR_VGA,
253 DRM_MODE_CONNECTOR_Composite,
254 DRM_MODE_CONNECTOR_SVIDEO,
255 DRM_MODE_CONNECTOR_Unknown,
256 DRM_MODE_CONNECTOR_Unknown,
257 DRM_MODE_CONNECTOR_9PinDIN,
258 DRM_MODE_CONNECTOR_Unknown,
259 DRM_MODE_CONNECTOR_HDMIA,
260 DRM_MODE_CONNECTOR_HDMIB,
261 DRM_MODE_CONNECTOR_LVDS,
262 DRM_MODE_CONNECTOR_9PinDIN,
263 DRM_MODE_CONNECTOR_Unknown,
264 DRM_MODE_CONNECTOR_Unknown,
265 DRM_MODE_CONNECTOR_Unknown,
266 DRM_MODE_CONNECTOR_DisplayPort,
267 DRM_MODE_CONNECTOR_eDP,
268 DRM_MODE_CONNECTOR_Unknown
269 };
270
amdgpu_atombios_has_dce_engine_info(struct amdgpu_device * adev)271 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
272 {
273 struct amdgpu_mode_info *mode_info = &adev->mode_info;
274 struct atom_context *ctx = mode_info->atom_context;
275 int index = GetIndexIntoMasterTable(DATA, Object_Header);
276 u16 size, data_offset;
277 u8 frev, crev;
278 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
279 ATOM_OBJECT_HEADER *obj_header;
280
281 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
282 return false;
283
284 if (crev < 2)
285 return false;
286
287 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
288 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
289 (ctx->bios + data_offset +
290 le16_to_cpu(obj_header->usDisplayPathTableOffset));
291
292 if (path_obj->ucNumOfDispPath)
293 return true;
294 else
295 return false;
296 }
297
amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * adev)298 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
299 {
300 struct amdgpu_mode_info *mode_info = &adev->mode_info;
301 struct atom_context *ctx = mode_info->atom_context;
302 int index = GetIndexIntoMasterTable(DATA, Object_Header);
303 u16 size, data_offset;
304 u8 frev, crev;
305 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
306 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
307 ATOM_OBJECT_TABLE *router_obj;
308 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
309 ATOM_OBJECT_HEADER *obj_header;
310 int i, j, k, path_size, device_support;
311 int connector_type;
312 u16 conn_id, connector_object_id;
313 struct amdgpu_i2c_bus_rec ddc_bus;
314 struct amdgpu_router router;
315 struct amdgpu_gpio_rec gpio;
316 struct amdgpu_hpd hpd;
317
318 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
319 return false;
320
321 if (crev < 2)
322 return false;
323
324 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
325 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
326 (ctx->bios + data_offset +
327 le16_to_cpu(obj_header->usDisplayPathTableOffset));
328 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
329 (ctx->bios + data_offset +
330 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
331 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
332 (ctx->bios + data_offset +
333 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
334 router_obj = (ATOM_OBJECT_TABLE *)
335 (ctx->bios + data_offset +
336 le16_to_cpu(obj_header->usRouterObjectTableOffset));
337 device_support = le16_to_cpu(obj_header->usDeviceSupport);
338
339 path_size = 0;
340 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
341 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
342 ATOM_DISPLAY_OBJECT_PATH *path;
343 addr += path_size;
344 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
345 path_size += le16_to_cpu(path->usSize);
346
347 if (device_support & le16_to_cpu(path->usDeviceTag)) {
348 uint8_t con_obj_id =
349 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
350 >> OBJECT_ID_SHIFT;
351
352 /* Skip TV/CV support */
353 if ((le16_to_cpu(path->usDeviceTag) ==
354 ATOM_DEVICE_TV1_SUPPORT) ||
355 (le16_to_cpu(path->usDeviceTag) ==
356 ATOM_DEVICE_CV_SUPPORT))
357 continue;
358
359 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
360 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
361 con_obj_id, le16_to_cpu(path->usDeviceTag));
362 continue;
363 }
364
365 connector_type =
366 object_connector_convert[con_obj_id];
367 connector_object_id = con_obj_id;
368
369 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
370 continue;
371
372 router.ddc_valid = false;
373 router.cd_valid = false;
374 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
375 uint8_t grph_obj_type =
376 (le16_to_cpu(path->usGraphicObjIds[j]) &
377 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
378
379 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
380 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
381 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
382 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
383 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
384 (ctx->bios + data_offset +
385 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
386 ATOM_ENCODER_CAP_RECORD *cap_record;
387 u16 caps = 0;
388
389 while (record->ucRecordSize > 0 &&
390 record->ucRecordType > 0 &&
391 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
392 switch (record->ucRecordType) {
393 case ATOM_ENCODER_CAP_RECORD_TYPE:
394 cap_record =(ATOM_ENCODER_CAP_RECORD *)
395 record;
396 caps = le16_to_cpu(cap_record->usEncoderCap);
397 break;
398 }
399 record = (ATOM_COMMON_RECORD_HEADER *)
400 ((char *)record + record->ucRecordSize);
401 }
402 amdgpu_display_add_encoder(adev, encoder_obj,
403 le16_to_cpu(path->usDeviceTag),
404 caps);
405 }
406 }
407 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
408 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
409 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
410 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
411 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
412 (ctx->bios + data_offset +
413 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
414 ATOM_I2C_RECORD *i2c_record;
415 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
416 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
417 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
418 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
419 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
420 (ctx->bios + data_offset +
421 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
422 u8 *num_dst_objs = (u8 *)
423 ((u8 *)router_src_dst_table + 1 +
424 (router_src_dst_table->ucNumberOfSrc * 2));
425 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
426 int enum_id;
427
428 router.router_id = router_obj_id;
429 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
430 if (le16_to_cpu(path->usConnObjectId) ==
431 le16_to_cpu(dst_objs[enum_id]))
432 break;
433 }
434
435 while (record->ucRecordSize > 0 &&
436 record->ucRecordType > 0 &&
437 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
438 switch (record->ucRecordType) {
439 case ATOM_I2C_RECORD_TYPE:
440 i2c_record =
441 (ATOM_I2C_RECORD *)
442 record;
443 i2c_config =
444 (ATOM_I2C_ID_CONFIG_ACCESS *)
445 &i2c_record->sucI2cId;
446 router.i2c_info =
447 amdgpu_atombios_lookup_i2c_gpio(adev,
448 i2c_config->
449 ucAccess);
450 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
451 break;
452 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
453 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
454 record;
455 router.ddc_valid = true;
456 router.ddc_mux_type = ddc_path->ucMuxType;
457 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
458 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
459 break;
460 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
461 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
462 record;
463 router.cd_valid = true;
464 router.cd_mux_type = cd_path->ucMuxType;
465 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
466 router.cd_mux_state = cd_path->ucMuxState[enum_id];
467 break;
468 }
469 record = (ATOM_COMMON_RECORD_HEADER *)
470 ((char *)record + record->ucRecordSize);
471 }
472 }
473 }
474 }
475 }
476
477 /* look up gpio for ddc, hpd */
478 ddc_bus.valid = false;
479 hpd.hpd = AMDGPU_HPD_NONE;
480 if ((le16_to_cpu(path->usDeviceTag) &
481 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
482 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
483 if (le16_to_cpu(path->usConnObjectId) ==
484 le16_to_cpu(con_obj->asObjects[j].
485 usObjectID)) {
486 ATOM_COMMON_RECORD_HEADER
487 *record =
488 (ATOM_COMMON_RECORD_HEADER
489 *)
490 (ctx->bios + data_offset +
491 le16_to_cpu(con_obj->
492 asObjects[j].
493 usRecordOffset));
494 ATOM_I2C_RECORD *i2c_record;
495 ATOM_HPD_INT_RECORD *hpd_record;
496 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
497
498 while (record->ucRecordSize > 0 &&
499 record->ucRecordType > 0 &&
500 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
501 switch (record->ucRecordType) {
502 case ATOM_I2C_RECORD_TYPE:
503 i2c_record =
504 (ATOM_I2C_RECORD *)
505 record;
506 i2c_config =
507 (ATOM_I2C_ID_CONFIG_ACCESS *)
508 &i2c_record->sucI2cId;
509 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
510 i2c_config->
511 ucAccess);
512 break;
513 case ATOM_HPD_INT_RECORD_TYPE:
514 hpd_record =
515 (ATOM_HPD_INT_RECORD *)
516 record;
517 gpio = amdgpu_atombios_lookup_gpio(adev,
518 hpd_record->ucHPDIntGPIOID);
519 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
520 hpd.plugged_state = hpd_record->ucPlugged_PinState;
521 break;
522 }
523 record =
524 (ATOM_COMMON_RECORD_HEADER
525 *) ((char *)record
526 +
527 record->
528 ucRecordSize);
529 }
530 break;
531 }
532 }
533 }
534
535 /* needed for aux chan transactions */
536 ddc_bus.hpd = hpd.hpd;
537
538 conn_id = le16_to_cpu(path->usConnObjectId);
539
540 amdgpu_display_add_connector(adev,
541 conn_id,
542 le16_to_cpu(path->usDeviceTag),
543 connector_type, &ddc_bus,
544 connector_object_id,
545 &hpd,
546 &router);
547
548 }
549 }
550
551 amdgpu_link_encoder_connector(adev->ddev);
552
553 return true;
554 }
555
556 union firmware_info {
557 ATOM_FIRMWARE_INFO info;
558 ATOM_FIRMWARE_INFO_V1_2 info_12;
559 ATOM_FIRMWARE_INFO_V1_3 info_13;
560 ATOM_FIRMWARE_INFO_V1_4 info_14;
561 ATOM_FIRMWARE_INFO_V2_1 info_21;
562 ATOM_FIRMWARE_INFO_V2_2 info_22;
563 };
564
amdgpu_atombios_get_clock_info(struct amdgpu_device * adev)565 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
566 {
567 struct amdgpu_mode_info *mode_info = &adev->mode_info;
568 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
569 uint8_t frev, crev;
570 uint16_t data_offset;
571 int ret = -EINVAL;
572
573 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
574 &frev, &crev, &data_offset)) {
575 int i;
576 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
577 struct amdgpu_pll *spll = &adev->clock.spll;
578 struct amdgpu_pll *mpll = &adev->clock.mpll;
579 union firmware_info *firmware_info =
580 (union firmware_info *)(mode_info->atom_context->bios +
581 data_offset);
582 /* pixel clocks */
583 ppll->reference_freq =
584 le16_to_cpu(firmware_info->info.usReferenceClock);
585 ppll->reference_div = 0;
586
587 ppll->pll_out_min =
588 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
589 ppll->pll_out_max =
590 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
591
592 ppll->lcd_pll_out_min =
593 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
594 if (ppll->lcd_pll_out_min == 0)
595 ppll->lcd_pll_out_min = ppll->pll_out_min;
596 ppll->lcd_pll_out_max =
597 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
598 if (ppll->lcd_pll_out_max == 0)
599 ppll->lcd_pll_out_max = ppll->pll_out_max;
600
601 if (ppll->pll_out_min == 0)
602 ppll->pll_out_min = 64800;
603
604 ppll->pll_in_min =
605 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
606 ppll->pll_in_max =
607 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
608
609 ppll->min_post_div = 2;
610 ppll->max_post_div = 0x7f;
611 ppll->min_frac_feedback_div = 0;
612 ppll->max_frac_feedback_div = 9;
613 ppll->min_ref_div = 2;
614 ppll->max_ref_div = 0x3ff;
615 ppll->min_feedback_div = 4;
616 ppll->max_feedback_div = 0xfff;
617 ppll->best_vco = 0;
618
619 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
620 adev->clock.ppll[i] = *ppll;
621
622 /* system clock */
623 spll->reference_freq =
624 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
625 spll->reference_div = 0;
626
627 spll->pll_out_min =
628 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
629 spll->pll_out_max =
630 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
631
632 /* ??? */
633 if (spll->pll_out_min == 0)
634 spll->pll_out_min = 64800;
635
636 spll->pll_in_min =
637 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
638 spll->pll_in_max =
639 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
640
641 spll->min_post_div = 1;
642 spll->max_post_div = 1;
643 spll->min_ref_div = 2;
644 spll->max_ref_div = 0xff;
645 spll->min_feedback_div = 4;
646 spll->max_feedback_div = 0xff;
647 spll->best_vco = 0;
648
649 /* memory clock */
650 mpll->reference_freq =
651 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
652 mpll->reference_div = 0;
653
654 mpll->pll_out_min =
655 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
656 mpll->pll_out_max =
657 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
658
659 /* ??? */
660 if (mpll->pll_out_min == 0)
661 mpll->pll_out_min = 64800;
662
663 mpll->pll_in_min =
664 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
665 mpll->pll_in_max =
666 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
667
668 adev->clock.default_sclk =
669 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
670 adev->clock.default_mclk =
671 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
672
673 mpll->min_post_div = 1;
674 mpll->max_post_div = 1;
675 mpll->min_ref_div = 2;
676 mpll->max_ref_div = 0xff;
677 mpll->min_feedback_div = 4;
678 mpll->max_feedback_div = 0xff;
679 mpll->best_vco = 0;
680
681 /* disp clock */
682 adev->clock.default_dispclk =
683 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
684 /* set a reasonable default for DP */
685 if (adev->clock.default_dispclk < 53900) {
686 DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
687 adev->clock.default_dispclk / 100);
688 adev->clock.default_dispclk = 60000;
689 } else if (adev->clock.default_dispclk <= 60000) {
690 DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
691 adev->clock.default_dispclk / 100);
692 adev->clock.default_dispclk = 62500;
693 }
694 adev->clock.dp_extclk =
695 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
696 adev->clock.current_dispclk = adev->clock.default_dispclk;
697
698 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
699 if (adev->clock.max_pixel_clock == 0)
700 adev->clock.max_pixel_clock = 40000;
701
702 /* not technically a clock, but... */
703 adev->mode_info.firmware_flags =
704 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
705
706 ret = 0;
707 }
708
709 adev->pm.current_sclk = adev->clock.default_sclk;
710 adev->pm.current_mclk = adev->clock.default_mclk;
711
712 return ret;
713 }
714
715 union gfx_info {
716 ATOM_GFX_INFO_V2_1 info;
717 };
718
amdgpu_atombios_get_gfx_info(struct amdgpu_device * adev)719 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
720 {
721 struct amdgpu_mode_info *mode_info = &adev->mode_info;
722 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
723 uint8_t frev, crev;
724 uint16_t data_offset;
725 int ret = -EINVAL;
726
727 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
728 &frev, &crev, &data_offset)) {
729 union gfx_info *gfx_info = (union gfx_info *)
730 (mode_info->atom_context->bios + data_offset);
731
732 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
733 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
734 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
735 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
736 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
737 adev->gfx.config.max_texture_channel_caches =
738 gfx_info->info.max_texture_channel_caches;
739
740 ret = 0;
741 }
742 return ret;
743 }
744
745 union igp_info {
746 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
747 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
748 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
749 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
750 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
751 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
752 };
753
754 /*
755 * Return vram width from integrated system info table, if available,
756 * or 0 if not.
757 */
amdgpu_atombios_get_vram_width(struct amdgpu_device * adev)758 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
759 {
760 struct amdgpu_mode_info *mode_info = &adev->mode_info;
761 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
762 u16 data_offset, size;
763 union igp_info *igp_info;
764 u8 frev, crev;
765
766 /* get any igp specific overrides */
767 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
768 &frev, &crev, &data_offset)) {
769 igp_info = (union igp_info *)
770 (mode_info->atom_context->bios + data_offset);
771 switch (crev) {
772 case 8:
773 case 9:
774 return igp_info->info_8.ucUMAChannelNumber * 64;
775 default:
776 return 0;
777 }
778 }
779
780 return 0;
781 }
782
amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device * adev,struct amdgpu_atom_ss * ss,int id)783 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
784 struct amdgpu_atom_ss *ss,
785 int id)
786 {
787 struct amdgpu_mode_info *mode_info = &adev->mode_info;
788 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
789 u16 data_offset, size;
790 union igp_info *igp_info;
791 u8 frev, crev;
792 u16 percentage = 0, rate = 0;
793
794 /* get any igp specific overrides */
795 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
796 &frev, &crev, &data_offset)) {
797 igp_info = (union igp_info *)
798 (mode_info->atom_context->bios + data_offset);
799 switch (crev) {
800 case 6:
801 switch (id) {
802 case ASIC_INTERNAL_SS_ON_TMDS:
803 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
804 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
805 break;
806 case ASIC_INTERNAL_SS_ON_HDMI:
807 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
808 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
809 break;
810 case ASIC_INTERNAL_SS_ON_LVDS:
811 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
812 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
813 break;
814 }
815 break;
816 case 7:
817 switch (id) {
818 case ASIC_INTERNAL_SS_ON_TMDS:
819 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
820 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
821 break;
822 case ASIC_INTERNAL_SS_ON_HDMI:
823 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
824 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
825 break;
826 case ASIC_INTERNAL_SS_ON_LVDS:
827 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
828 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
829 break;
830 }
831 break;
832 case 8:
833 switch (id) {
834 case ASIC_INTERNAL_SS_ON_TMDS:
835 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
836 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
837 break;
838 case ASIC_INTERNAL_SS_ON_HDMI:
839 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
840 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
841 break;
842 case ASIC_INTERNAL_SS_ON_LVDS:
843 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
844 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
845 break;
846 }
847 break;
848 case 9:
849 switch (id) {
850 case ASIC_INTERNAL_SS_ON_TMDS:
851 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
852 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
853 break;
854 case ASIC_INTERNAL_SS_ON_HDMI:
855 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
856 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
857 break;
858 case ASIC_INTERNAL_SS_ON_LVDS:
859 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
860 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
861 break;
862 }
863 break;
864 default:
865 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
866 break;
867 }
868 if (percentage)
869 ss->percentage = percentage;
870 if (rate)
871 ss->rate = rate;
872 }
873 }
874
875 union asic_ss_info {
876 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
877 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
878 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
879 };
880
881 union asic_ss_assignment {
882 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
883 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
884 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
885 };
886
amdgpu_atombios_get_asic_ss_info(struct amdgpu_device * adev,struct amdgpu_atom_ss * ss,int id,u32 clock)887 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
888 struct amdgpu_atom_ss *ss,
889 int id, u32 clock)
890 {
891 struct amdgpu_mode_info *mode_info = &adev->mode_info;
892 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
893 uint16_t data_offset, size;
894 union asic_ss_info *ss_info;
895 union asic_ss_assignment *ss_assign;
896 uint8_t frev, crev;
897 int i, num_indices;
898
899 if (id == ASIC_INTERNAL_MEMORY_SS) {
900 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
901 return false;
902 }
903 if (id == ASIC_INTERNAL_ENGINE_SS) {
904 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
905 return false;
906 }
907
908 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
909 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
910 &frev, &crev, &data_offset)) {
911
912 ss_info =
913 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
914
915 switch (frev) {
916 case 1:
917 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
918 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
919
920 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
921 for (i = 0; i < num_indices; i++) {
922 if ((ss_assign->v1.ucClockIndication == id) &&
923 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
924 ss->percentage =
925 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
926 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
927 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
928 ss->percentage_divider = 100;
929 return true;
930 }
931 ss_assign = (union asic_ss_assignment *)
932 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
933 }
934 break;
935 case 2:
936 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
937 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
938 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
939 for (i = 0; i < num_indices; i++) {
940 if ((ss_assign->v2.ucClockIndication == id) &&
941 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
942 ss->percentage =
943 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
944 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
945 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
946 ss->percentage_divider = 100;
947 if ((crev == 2) &&
948 ((id == ASIC_INTERNAL_ENGINE_SS) ||
949 (id == ASIC_INTERNAL_MEMORY_SS)))
950 ss->rate /= 100;
951 return true;
952 }
953 ss_assign = (union asic_ss_assignment *)
954 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
955 }
956 break;
957 case 3:
958 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
959 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
960 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
961 for (i = 0; i < num_indices; i++) {
962 if ((ss_assign->v3.ucClockIndication == id) &&
963 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
964 ss->percentage =
965 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
966 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
967 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
968 if (ss_assign->v3.ucSpreadSpectrumMode &
969 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
970 ss->percentage_divider = 1000;
971 else
972 ss->percentage_divider = 100;
973 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
974 (id == ASIC_INTERNAL_MEMORY_SS))
975 ss->rate /= 100;
976 if (adev->flags & AMD_IS_APU)
977 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
978 return true;
979 }
980 ss_assign = (union asic_ss_assignment *)
981 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
982 }
983 break;
984 default:
985 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
986 break;
987 }
988
989 }
990 return false;
991 }
992
993 union get_clock_dividers {
994 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
995 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
996 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
997 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
998 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
999 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
1000 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
1001 };
1002
amdgpu_atombios_get_clock_dividers(struct amdgpu_device * adev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)1003 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1004 u8 clock_type,
1005 u32 clock,
1006 bool strobe_mode,
1007 struct atom_clock_dividers *dividers)
1008 {
1009 union get_clock_dividers args;
1010 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1011 u8 frev, crev;
1012
1013 memset(&args, 0, sizeof(args));
1014 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1015
1016 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1017 return -EINVAL;
1018
1019 switch (crev) {
1020 case 2:
1021 case 3:
1022 case 5:
1023 /* r6xx, r7xx, evergreen, ni, si.
1024 * TODO: add support for asic_type <= CHIP_RV770*/
1025 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1026 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1027
1028 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1029
1030 dividers->post_div = args.v3.ucPostDiv;
1031 dividers->enable_post_div = (args.v3.ucCntlFlag &
1032 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1033 dividers->enable_dithen = (args.v3.ucCntlFlag &
1034 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1035 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1036 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1037 dividers->ref_div = args.v3.ucRefDiv;
1038 dividers->vco_mode = (args.v3.ucCntlFlag &
1039 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1040 } else {
1041 /* for SI we use ComputeMemoryClockParam for memory plls */
1042 if (adev->asic_type >= CHIP_TAHITI)
1043 return -EINVAL;
1044 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1045 if (strobe_mode)
1046 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1047
1048 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1049
1050 dividers->post_div = args.v5.ucPostDiv;
1051 dividers->enable_post_div = (args.v5.ucCntlFlag &
1052 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1053 dividers->enable_dithen = (args.v5.ucCntlFlag &
1054 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1055 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1056 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1057 dividers->ref_div = args.v5.ucRefDiv;
1058 dividers->vco_mode = (args.v5.ucCntlFlag &
1059 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1060 }
1061 break;
1062 case 4:
1063 /* fusion */
1064 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
1065
1066 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1067
1068 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1069 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1070 break;
1071 case 6:
1072 /* CI */
1073 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1074 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1075 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
1076
1077 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1078
1079 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1080 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1081 dividers->ref_div = args.v6_out.ucPllRefDiv;
1082 dividers->post_div = args.v6_out.ucPllPostDiv;
1083 dividers->flags = args.v6_out.ucPllCntlFlag;
1084 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1085 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1086 break;
1087 default:
1088 return -EINVAL;
1089 }
1090 return 0;
1091 }
1092
amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device * adev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)1093 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1094 u32 clock,
1095 bool strobe_mode,
1096 struct atom_mpll_param *mpll_param)
1097 {
1098 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1099 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1100 u8 frev, crev;
1101
1102 memset(&args, 0, sizeof(args));
1103 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1104
1105 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1106 return -EINVAL;
1107
1108 switch (frev) {
1109 case 2:
1110 switch (crev) {
1111 case 1:
1112 /* SI */
1113 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1114 args.ucInputFlag = 0;
1115 if (strobe_mode)
1116 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1117
1118 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1119
1120 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1121 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1122 mpll_param->post_div = args.ucPostDiv;
1123 mpll_param->dll_speed = args.ucDllSpeed;
1124 mpll_param->bwcntl = args.ucBWCntl;
1125 mpll_param->vco_mode =
1126 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1127 mpll_param->yclk_sel =
1128 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1129 mpll_param->qdr =
1130 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1131 mpll_param->half_rate =
1132 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1133 break;
1134 default:
1135 return -EINVAL;
1136 }
1137 break;
1138 default:
1139 return -EINVAL;
1140 }
1141 return 0;
1142 }
1143
amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device * adev,u32 eng_clock,u32 mem_clock)1144 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1145 u32 eng_clock, u32 mem_clock)
1146 {
1147 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1148 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1149 u32 tmp;
1150
1151 memset(&args, 0, sizeof(args));
1152
1153 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1154 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1155
1156 args.ulTargetEngineClock = cpu_to_le32(tmp);
1157 if (mem_clock)
1158 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1159
1160 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1161 }
1162
amdgpu_atombios_get_default_voltages(struct amdgpu_device * adev,u16 * vddc,u16 * vddci,u16 * mvdd)1163 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1164 u16 *vddc, u16 *vddci, u16 *mvdd)
1165 {
1166 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1167 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1168 u8 frev, crev;
1169 u16 data_offset;
1170 union firmware_info *firmware_info;
1171
1172 *vddc = 0;
1173 *vddci = 0;
1174 *mvdd = 0;
1175
1176 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1177 &frev, &crev, &data_offset)) {
1178 firmware_info =
1179 (union firmware_info *)(mode_info->atom_context->bios +
1180 data_offset);
1181 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1182 if ((frev == 2) && (crev >= 2)) {
1183 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1184 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1185 }
1186 }
1187 }
1188
1189 union set_voltage {
1190 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1191 struct _SET_VOLTAGE_PARAMETERS v1;
1192 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1193 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1194 };
1195
amdgpu_atombios_get_max_vddc(struct amdgpu_device * adev,u8 voltage_type,u16 voltage_id,u16 * voltage)1196 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1197 u16 voltage_id, u16 *voltage)
1198 {
1199 union set_voltage args;
1200 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1201 u8 frev, crev;
1202
1203 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1204 return -EINVAL;
1205
1206 switch (crev) {
1207 case 1:
1208 return -EINVAL;
1209 case 2:
1210 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1211 args.v2.ucVoltageMode = 0;
1212 args.v2.usVoltageLevel = 0;
1213
1214 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1215
1216 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1217 break;
1218 case 3:
1219 args.v3.ucVoltageType = voltage_type;
1220 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1221 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1222
1223 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1224
1225 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1226 break;
1227 default:
1228 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1229 return -EINVAL;
1230 }
1231
1232 return 0;
1233 }
1234
amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device * adev,u16 * voltage,u16 leakage_idx)1235 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1236 u16 *voltage,
1237 u16 leakage_idx)
1238 {
1239 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1240 }
1241
amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device * adev,u16 * leakage_id)1242 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1243 u16 *leakage_id)
1244 {
1245 union set_voltage args;
1246 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1247 u8 frev, crev;
1248
1249 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1250 return -EINVAL;
1251
1252 switch (crev) {
1253 case 3:
1254 case 4:
1255 args.v3.ucVoltageType = 0;
1256 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1257 args.v3.usVoltageLevel = 0;
1258
1259 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1260
1261 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1262 break;
1263 default:
1264 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1265 return -EINVAL;
1266 }
1267
1268 return 0;
1269 }
1270
amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device * adev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)1271 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1272 u16 *vddc, u16 *vddci,
1273 u16 virtual_voltage_id,
1274 u16 vbios_voltage_id)
1275 {
1276 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1277 u8 frev, crev;
1278 u16 data_offset, size;
1279 int i, j;
1280 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1281 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1282
1283 *vddc = 0;
1284 *vddci = 0;
1285
1286 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1287 &frev, &crev, &data_offset))
1288 return -EINVAL;
1289
1290 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1291 (adev->mode_info.atom_context->bios + data_offset);
1292
1293 switch (frev) {
1294 case 1:
1295 return -EINVAL;
1296 case 2:
1297 switch (crev) {
1298 case 1:
1299 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1300 return -EINVAL;
1301 leakage_bin = (u16 *)
1302 (adev->mode_info.atom_context->bios + data_offset +
1303 le16_to_cpu(profile->usLeakageBinArrayOffset));
1304 vddc_id_buf = (u16 *)
1305 (adev->mode_info.atom_context->bios + data_offset +
1306 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1307 vddc_buf = (u16 *)
1308 (adev->mode_info.atom_context->bios + data_offset +
1309 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1310 vddci_id_buf = (u16 *)
1311 (adev->mode_info.atom_context->bios + data_offset +
1312 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1313 vddci_buf = (u16 *)
1314 (adev->mode_info.atom_context->bios + data_offset +
1315 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1316
1317 if (profile->ucElbVDDC_Num > 0) {
1318 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1319 if (vddc_id_buf[i] == virtual_voltage_id) {
1320 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1321 if (vbios_voltage_id <= leakage_bin[j]) {
1322 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1323 break;
1324 }
1325 }
1326 break;
1327 }
1328 }
1329 }
1330 if (profile->ucElbVDDCI_Num > 0) {
1331 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1332 if (vddci_id_buf[i] == virtual_voltage_id) {
1333 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1334 if (vbios_voltage_id <= leakage_bin[j]) {
1335 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1336 break;
1337 }
1338 }
1339 break;
1340 }
1341 }
1342 }
1343 break;
1344 default:
1345 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1346 return -EINVAL;
1347 }
1348 break;
1349 default:
1350 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1351 return -EINVAL;
1352 }
1353
1354 return 0;
1355 }
1356
1357 union get_voltage_info {
1358 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1359 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1360 };
1361
amdgpu_atombios_get_voltage_evv(struct amdgpu_device * adev,u16 virtual_voltage_id,u16 * voltage)1362 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1363 u16 virtual_voltage_id,
1364 u16 *voltage)
1365 {
1366 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1367 u32 entry_id;
1368 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1369 union get_voltage_info args;
1370
1371 for (entry_id = 0; entry_id < count; entry_id++) {
1372 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1373 virtual_voltage_id)
1374 break;
1375 }
1376
1377 if (entry_id >= count)
1378 return -EINVAL;
1379
1380 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1381 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1382 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1383 args.in.ulSCLKFreq =
1384 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1385
1386 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1387
1388 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1389
1390 return 0;
1391 }
1392
1393 union voltage_object_info {
1394 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1395 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1396 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1397 };
1398
1399 union voltage_object {
1400 struct _ATOM_VOLTAGE_OBJECT v1;
1401 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1402 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1403 };
1404
1405
amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)1406 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1407 u8 voltage_type, u8 voltage_mode)
1408 {
1409 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1410 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1411 u8 *start = (u8*)v3;
1412
1413 while (offset < size) {
1414 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1415 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1416 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1417 return vo;
1418 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1419 }
1420 return NULL;
1421 }
1422
amdgpu_atombios_get_svi2_info(struct amdgpu_device * adev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)1423 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1424 u8 voltage_type,
1425 u8 *svd_gpio_id, u8 *svc_gpio_id)
1426 {
1427 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1428 u8 frev, crev;
1429 u16 data_offset, size;
1430 union voltage_object_info *voltage_info;
1431 union voltage_object *voltage_object = NULL;
1432
1433 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1434 &frev, &crev, &data_offset)) {
1435 voltage_info = (union voltage_object_info *)
1436 (adev->mode_info.atom_context->bios + data_offset);
1437
1438 switch (frev) {
1439 case 3:
1440 switch (crev) {
1441 case 1:
1442 voltage_object = (union voltage_object *)
1443 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1444 voltage_type,
1445 VOLTAGE_OBJ_SVID2);
1446 if (voltage_object) {
1447 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1448 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1449 } else {
1450 return -EINVAL;
1451 }
1452 break;
1453 default:
1454 DRM_ERROR("unknown voltage object table\n");
1455 return -EINVAL;
1456 }
1457 break;
1458 default:
1459 DRM_ERROR("unknown voltage object table\n");
1460 return -EINVAL;
1461 }
1462
1463 }
1464 return 0;
1465 }
1466
1467 bool
amdgpu_atombios_is_voltage_gpio(struct amdgpu_device * adev,u8 voltage_type,u8 voltage_mode)1468 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1469 u8 voltage_type, u8 voltage_mode)
1470 {
1471 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1472 u8 frev, crev;
1473 u16 data_offset, size;
1474 union voltage_object_info *voltage_info;
1475
1476 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1477 &frev, &crev, &data_offset)) {
1478 voltage_info = (union voltage_object_info *)
1479 (adev->mode_info.atom_context->bios + data_offset);
1480
1481 switch (frev) {
1482 case 3:
1483 switch (crev) {
1484 case 1:
1485 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1486 voltage_type, voltage_mode))
1487 return true;
1488 break;
1489 default:
1490 DRM_ERROR("unknown voltage object table\n");
1491 return false;
1492 }
1493 break;
1494 default:
1495 DRM_ERROR("unknown voltage object table\n");
1496 return false;
1497 }
1498
1499 }
1500 return false;
1501 }
1502
amdgpu_atombios_get_voltage_table(struct amdgpu_device * adev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)1503 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1504 u8 voltage_type, u8 voltage_mode,
1505 struct atom_voltage_table *voltage_table)
1506 {
1507 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1508 u8 frev, crev;
1509 u16 data_offset, size;
1510 int i;
1511 union voltage_object_info *voltage_info;
1512 union voltage_object *voltage_object = NULL;
1513
1514 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1515 &frev, &crev, &data_offset)) {
1516 voltage_info = (union voltage_object_info *)
1517 (adev->mode_info.atom_context->bios + data_offset);
1518
1519 switch (frev) {
1520 case 3:
1521 switch (crev) {
1522 case 1:
1523 voltage_object = (union voltage_object *)
1524 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1525 voltage_type, voltage_mode);
1526 if (voltage_object) {
1527 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1528 &voltage_object->v3.asGpioVoltageObj;
1529 VOLTAGE_LUT_ENTRY_V2 *lut;
1530 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1531 return -EINVAL;
1532 lut = &gpio->asVolGpioLut[0];
1533 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1534 voltage_table->entries[i].value =
1535 le16_to_cpu(lut->usVoltageValue);
1536 voltage_table->entries[i].smio_low =
1537 le32_to_cpu(lut->ulVoltageId);
1538 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1539 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1540 }
1541 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1542 voltage_table->count = gpio->ucGpioEntryNum;
1543 voltage_table->phase_delay = gpio->ucPhaseDelay;
1544 return 0;
1545 }
1546 break;
1547 default:
1548 DRM_ERROR("unknown voltage object table\n");
1549 return -EINVAL;
1550 }
1551 break;
1552 default:
1553 DRM_ERROR("unknown voltage object table\n");
1554 return -EINVAL;
1555 }
1556 }
1557 return -EINVAL;
1558 }
1559
1560 union vram_info {
1561 struct _ATOM_VRAM_INFO_V3 v1_3;
1562 struct _ATOM_VRAM_INFO_V4 v1_4;
1563 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1564 };
1565
1566 #define MEM_ID_MASK 0xff000000
1567 #define MEM_ID_SHIFT 24
1568 #define CLOCK_RANGE_MASK 0x00ffffff
1569 #define CLOCK_RANGE_SHIFT 0
1570 #define LOW_NIBBLE_MASK 0xf
1571 #define DATA_EQU_PREV 0
1572 #define DATA_FROM_TABLE 4
1573
amdgpu_atombios_init_mc_reg_table(struct amdgpu_device * adev,u8 module_index,struct atom_mc_reg_table * reg_table)1574 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1575 u8 module_index,
1576 struct atom_mc_reg_table *reg_table)
1577 {
1578 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1579 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1580 u32 i = 0, j;
1581 u16 data_offset, size;
1582 union vram_info *vram_info;
1583
1584 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1585
1586 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1587 &frev, &crev, &data_offset)) {
1588 vram_info = (union vram_info *)
1589 (adev->mode_info.atom_context->bios + data_offset);
1590 switch (frev) {
1591 case 1:
1592 DRM_ERROR("old table version %d, %d\n", frev, crev);
1593 return -EINVAL;
1594 case 2:
1595 switch (crev) {
1596 case 1:
1597 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1598 ATOM_INIT_REG_BLOCK *reg_block =
1599 (ATOM_INIT_REG_BLOCK *)
1600 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1601 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1602 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1603 ((u8 *)reg_block + (2 * sizeof(u16)) +
1604 le16_to_cpu(reg_block->usRegIndexTblSize));
1605 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
1606 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1607 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1608 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1609 return -EINVAL;
1610 while (i < num_entries) {
1611 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1612 break;
1613 reg_table->mc_reg_address[i].s1 =
1614 (u16)(le16_to_cpu(format->usRegIndex));
1615 reg_table->mc_reg_address[i].pre_reg_data =
1616 (u8)(format->ucPreRegDataLength);
1617 i++;
1618 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1619 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1620 }
1621 reg_table->last = i;
1622 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1623 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1624 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1625 >> MEM_ID_SHIFT);
1626 if (module_index == t_mem_id) {
1627 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1628 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1629 >> CLOCK_RANGE_SHIFT);
1630 for (i = 0, j = 1; i < reg_table->last; i++) {
1631 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1632 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1633 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1634 j++;
1635 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1636 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1637 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1638 }
1639 }
1640 num_ranges++;
1641 }
1642 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1643 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1644 }
1645 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1646 return -EINVAL;
1647 reg_table->num_entries = num_ranges;
1648 } else
1649 return -EINVAL;
1650 break;
1651 default:
1652 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1653 return -EINVAL;
1654 }
1655 break;
1656 default:
1657 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1658 return -EINVAL;
1659 }
1660 return 0;
1661 }
1662 return -EINVAL;
1663 }
1664
amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device * adev)1665 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1666 {
1667 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1668 u8 frev, crev;
1669 u16 data_offset, size;
1670
1671 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1672 &frev, &crev, &data_offset))
1673 return true;
1674
1675 return false;
1676 }
1677
amdgpu_atombios_scratch_regs_lock(struct amdgpu_device * adev,bool lock)1678 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1679 {
1680 uint32_t bios_6_scratch;
1681
1682 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1683
1684 if (lock) {
1685 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1686 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1687 } else {
1688 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1689 bios_6_scratch |= ATOM_S6_ACC_MODE;
1690 }
1691
1692 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1693 }
1694
amdgpu_atombios_scratch_regs_init(struct amdgpu_device * adev)1695 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1696 {
1697 uint32_t bios_2_scratch, bios_6_scratch;
1698
1699 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1700
1701 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1702 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1703
1704 /* let the bios control the backlight */
1705 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1706
1707 /* tell the bios not to handle mode switching */
1708 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1709
1710 /* clear the vbios dpms state */
1711 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1712
1713 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1714 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1715 }
1716
amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device * adev,bool hung)1717 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1718 bool hung)
1719 {
1720 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1721
1722 if (hung)
1723 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1724 else
1725 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1726
1727 WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1728 }
1729
amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device * adev)1730 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1731 {
1732 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1733
1734 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1735 return false;
1736 else
1737 return true;
1738 }
1739
1740 /* Atom needs data in little endian format so swap as appropriate when copying
1741 * data to or from atom. Note that atom operates on dw units.
1742 *
1743 * Use to_le=true when sending data to atom and provide at least
1744 * ALIGN(num_bytes,4) bytes in the dst buffer.
1745 *
1746 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1747 * byes in the src buffer.
1748 */
amdgpu_atombios_copy_swap(u8 * dst,u8 * src,u8 num_bytes,bool to_le)1749 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1750 {
1751 #ifdef __BIG_ENDIAN
1752 u32 src_tmp[5], dst_tmp[5];
1753 int i;
1754 u8 align_num_bytes = ALIGN(num_bytes, 4);
1755
1756 if (to_le) {
1757 memcpy(src_tmp, src, num_bytes);
1758 for (i = 0; i < align_num_bytes / 4; i++)
1759 dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1760 memcpy(dst, dst_tmp, align_num_bytes);
1761 } else {
1762 memcpy(src_tmp, src, align_num_bytes);
1763 for (i = 0; i < align_num_bytes / 4; i++)
1764 dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1765 memcpy(dst, dst_tmp, num_bytes);
1766 }
1767 #else
1768 memcpy(dst, src, num_bytes);
1769 #endif
1770 }
1771
amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device * adev)1772 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1773 {
1774 struct atom_context *ctx = adev->mode_info.atom_context;
1775 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1776 uint16_t data_offset;
1777 int usage_bytes = 0;
1778 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1779 u64 start_addr;
1780 u64 size;
1781
1782 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1783 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1784
1785 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1786 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1787 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1788
1789 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
1790 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
1791
1792 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
1793 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
1794 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
1795 /* Firmware request VRAM reservation for SR-IOV */
1796 adev->fw_vram_usage.start_offset = (start_addr &
1797 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
1798 adev->fw_vram_usage.size = size << 10;
1799 /* Use the default scratch size */
1800 usage_bytes = 0;
1801 } else {
1802 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1803 }
1804 }
1805 ctx->scratch_size_bytes = 0;
1806 if (usage_bytes == 0)
1807 usage_bytes = 20 * 1024;
1808 /* allocate some scratch memory */
1809 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1810 if (!ctx->scratch)
1811 return -ENOMEM;
1812 ctx->scratch_size_bytes = usage_bytes;
1813 return 0;
1814 }
1815
1816 /* ATOM accessor methods */
1817 /*
1818 * ATOM is an interpreted byte code stored in tables in the vbios. The
1819 * driver registers callbacks to access registers and the interpreter
1820 * in the driver parses the tables and executes then to program specific
1821 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
1822 * atombios.h, and atom.c
1823 */
1824
1825 /**
1826 * cail_pll_read - read PLL register
1827 *
1828 * @info: atom card_info pointer
1829 * @reg: PLL register offset
1830 *
1831 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1832 * Returns the value of the PLL register.
1833 */
cail_pll_read(struct card_info * info,uint32_t reg)1834 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
1835 {
1836 return 0;
1837 }
1838
1839 /**
1840 * cail_pll_write - write PLL register
1841 *
1842 * @info: atom card_info pointer
1843 * @reg: PLL register offset
1844 * @val: value to write to the pll register
1845 *
1846 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1847 */
cail_pll_write(struct card_info * info,uint32_t reg,uint32_t val)1848 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
1849 {
1850
1851 }
1852
1853 /**
1854 * cail_mc_read - read MC (Memory Controller) register
1855 *
1856 * @info: atom card_info pointer
1857 * @reg: MC register offset
1858 *
1859 * Provides an MC register accessor for the atom interpreter (r4xx+).
1860 * Returns the value of the MC register.
1861 */
cail_mc_read(struct card_info * info,uint32_t reg)1862 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
1863 {
1864 return 0;
1865 }
1866
1867 /**
1868 * cail_mc_write - write MC (Memory Controller) register
1869 *
1870 * @info: atom card_info pointer
1871 * @reg: MC register offset
1872 * @val: value to write to the pll register
1873 *
1874 * Provides a MC register accessor for the atom interpreter (r4xx+).
1875 */
cail_mc_write(struct card_info * info,uint32_t reg,uint32_t val)1876 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
1877 {
1878
1879 }
1880
1881 /**
1882 * cail_reg_write - write MMIO register
1883 *
1884 * @info: atom card_info pointer
1885 * @reg: MMIO register offset
1886 * @val: value to write to the pll register
1887 *
1888 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
1889 */
cail_reg_write(struct card_info * info,uint32_t reg,uint32_t val)1890 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
1891 {
1892 struct amdgpu_device *adev = info->dev->dev_private;
1893
1894 WREG32(reg, val);
1895 }
1896
1897 /**
1898 * cail_reg_read - read MMIO register
1899 *
1900 * @info: atom card_info pointer
1901 * @reg: MMIO register offset
1902 *
1903 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
1904 * Returns the value of the MMIO register.
1905 */
cail_reg_read(struct card_info * info,uint32_t reg)1906 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1907 {
1908 struct amdgpu_device *adev = info->dev->dev_private;
1909 uint32_t r;
1910
1911 r = RREG32(reg);
1912 return r;
1913 }
1914
1915 /**
1916 * cail_ioreg_write - write IO register
1917 *
1918 * @info: atom card_info pointer
1919 * @reg: IO register offset
1920 * @val: value to write to the pll register
1921 *
1922 * Provides a IO register accessor for the atom interpreter (r4xx+).
1923 */
cail_ioreg_write(struct card_info * info,uint32_t reg,uint32_t val)1924 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1925 {
1926 struct amdgpu_device *adev = info->dev->dev_private;
1927
1928 WREG32_IO(reg, val);
1929 }
1930
1931 /**
1932 * cail_ioreg_read - read IO register
1933 *
1934 * @info: atom card_info pointer
1935 * @reg: IO register offset
1936 *
1937 * Provides an IO register accessor for the atom interpreter (r4xx+).
1938 * Returns the value of the IO register.
1939 */
cail_ioreg_read(struct card_info * info,uint32_t reg)1940 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1941 {
1942 struct amdgpu_device *adev = info->dev->dev_private;
1943 uint32_t r;
1944
1945 r = RREG32_IO(reg);
1946 return r;
1947 }
1948
1949 #ifdef CONFIG_SYSFS
amdgpu_atombios_get_vbios_version(struct device * dev,struct device_attribute * attr,char * buf)1950 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1951 struct device_attribute *attr,
1952 char *buf)
1953 {
1954 struct drm_device *ddev = dev_get_drvdata(dev);
1955 struct amdgpu_device *adev = ddev->dev_private;
1956 struct atom_context *ctx = adev->mode_info.atom_context;
1957
1958 return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1959 }
1960
1961 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1962 NULL);
1963 #endif
1964
1965 /**
1966 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1967 *
1968 * @adev: amdgpu_device pointer
1969 *
1970 * Frees the driver info and register access callbacks for the ATOM
1971 * interpreter (r4xx+).
1972 * Called at driver shutdown.
1973 */
amdgpu_atombios_fini(struct amdgpu_device * adev)1974 void amdgpu_atombios_fini(struct amdgpu_device *adev)
1975 {
1976 if (adev->mode_info.atom_context) {
1977 mutex_destroy(&adev->mode_info.atom_context->mutex);
1978 kfree(adev->mode_info.atom_context->scratch);
1979 kfree(adev->mode_info.atom_context->iio);
1980 }
1981 kfree(adev->mode_info.atom_context);
1982 adev->mode_info.atom_context = NULL;
1983 kfree(adev->mode_info.atom_card_info);
1984 adev->mode_info.atom_card_info = NULL;
1985 #ifdef CONFIG_SYSFS
1986 device_remove_file(adev->dev, &dev_attr_vbios_version);
1987 #endif
1988 }
1989
1990 /**
1991 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1992 *
1993 * @adev: amdgpu_device pointer
1994 *
1995 * Initializes the driver info and register access callbacks for the
1996 * ATOM interpreter (r4xx+).
1997 * Returns 0 on sucess, -ENOMEM on failure.
1998 * Called at driver startup.
1999 */
amdgpu_atombios_init(struct amdgpu_device * adev)2000 int amdgpu_atombios_init(struct amdgpu_device *adev)
2001 {
2002 struct card_info *atom_card_info =
2003 kzalloc(sizeof(struct card_info), GFP_KERNEL);
2004 int ret;
2005
2006 if (!atom_card_info)
2007 return -ENOMEM;
2008
2009 adev->mode_info.atom_card_info = atom_card_info;
2010 atom_card_info->dev = adev->ddev;
2011 atom_card_info->reg_read = cail_reg_read;
2012 atom_card_info->reg_write = cail_reg_write;
2013 /* needed for iio ops */
2014 #ifdef __NetBSD__
2015 if (adev->rio_mem_size)
2016 #else
2017 if (adev->rio_mem)
2018 #endif
2019 {
2020 atom_card_info->ioreg_read = cail_ioreg_read;
2021 atom_card_info->ioreg_write = cail_ioreg_write;
2022 } else {
2023 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
2024 atom_card_info->ioreg_read = cail_reg_read;
2025 atom_card_info->ioreg_write = cail_reg_write;
2026 }
2027 atom_card_info->mc_read = cail_mc_read;
2028 atom_card_info->mc_write = cail_mc_write;
2029 atom_card_info->pll_read = cail_pll_read;
2030 atom_card_info->pll_write = cail_pll_write;
2031
2032 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
2033 if (!adev->mode_info.atom_context) {
2034 amdgpu_atombios_fini(adev);
2035 return -ENOMEM;
2036 }
2037
2038 mutex_init(&adev->mode_info.atom_context->mutex);
2039 if (adev->is_atom_fw) {
2040 amdgpu_atomfirmware_scratch_regs_init(adev);
2041 amdgpu_atomfirmware_allocate_fb_scratch(adev);
2042 ret = amdgpu_atomfirmware_get_mem_train_info(adev);
2043 if (ret) {
2044 DRM_ERROR("Failed to get mem train fb location.\n");
2045 return ret;
2046 }
2047 } else {
2048 amdgpu_atombios_scratch_regs_init(adev);
2049 amdgpu_atombios_allocate_fb_scratch(adev);
2050 }
2051
2052 #ifdef CONFIG_SYSFS
2053 ret = device_create_file(adev->dev, &dev_attr_vbios_version);
2054 if (ret) {
2055 DRM_ERROR("Failed to create device file for VBIOS version\n");
2056 return ret;
2057 }
2058 #endif
2059
2060 return 0;
2061 }
2062
2063