1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include "amdgpu.h"
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_drv.h>
32 #include <drm/drm_fb_helper.h>
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "atom.h"
36
37 #include <linux/vga_switcheroo.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/pci.h>
41 #include <linux/pm_runtime.h>
42 #include "amdgpu_amdkfd.h"
43 #include "amdgpu_gem.h"
44 #include "amdgpu_display.h"
45 #include "amdgpu_ras.h"
46 #include "amd_pcie.h"
47
amdgpu_unregister_gpu_instance(struct amdgpu_device * adev)48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
49 {
50 struct amdgpu_gpu_instance *gpu_instance;
51 int i;
52
53 mutex_lock(&mgpu_info.mutex);
54
55 for (i = 0; i < mgpu_info.num_gpu; i++) {
56 gpu_instance = &(mgpu_info.gpu_ins[i]);
57 if (gpu_instance->adev == adev) {
58 mgpu_info.gpu_ins[i] =
59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
60 mgpu_info.num_gpu--;
61 if (adev->flags & AMD_IS_APU)
62 mgpu_info.num_apu--;
63 else
64 mgpu_info.num_dgpu--;
65 break;
66 }
67 }
68
69 mutex_unlock(&mgpu_info.mutex);
70 }
71
72 /**
73 * amdgpu_driver_unload_kms - Main unload function for KMS.
74 *
75 * @dev: drm dev pointer
76 *
77 * This is the main unload function for KMS (all asics).
78 * Returns 0 on success.
79 */
amdgpu_driver_unload_kms(struct drm_device * dev)80 void amdgpu_driver_unload_kms(struct drm_device *dev)
81 {
82 struct amdgpu_device *adev = drm_to_adev(dev);
83
84 if (adev == NULL)
85 return;
86
87 amdgpu_unregister_gpu_instance(adev);
88
89 if (adev->rmmio == NULL)
90 return;
91
92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
93 DRM_WARN("smart shift update failed\n");
94
95 amdgpu_acpi_fini(adev);
96 amdgpu_device_fini_hw(adev);
97 }
98
amdgpu_register_gpu_instance(struct amdgpu_device * adev)99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
100 {
101 struct amdgpu_gpu_instance *gpu_instance;
102
103 mutex_lock(&mgpu_info.mutex);
104
105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
106 DRM_ERROR("Cannot register more gpu instance\n");
107 mutex_unlock(&mgpu_info.mutex);
108 return;
109 }
110
111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
112 gpu_instance->adev = adev;
113 gpu_instance->mgpu_fan_enabled = 0;
114
115 mgpu_info.num_gpu++;
116 if (adev->flags & AMD_IS_APU)
117 mgpu_info.num_apu++;
118 else
119 mgpu_info.num_dgpu++;
120
121 mutex_unlock(&mgpu_info.mutex);
122 }
123
124 /**
125 * amdgpu_driver_load_kms - Main load function for KMS.
126 *
127 * @adev: pointer to struct amdgpu_device
128 * @flags: device flags
129 *
130 * This is the main load function for KMS (all asics).
131 * Returns 0 on success, error on failure.
132 */
amdgpu_driver_load_kms(struct amdgpu_device * adev,unsigned long flags)133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
134 {
135 struct drm_device *dev;
136 int r, acpi_status;
137
138 dev = adev_to_drm(adev);
139
140 /* amdgpu_device_init should report only fatal error
141 * like memory allocation failure or iomapping failure,
142 * or memory manager initialization failure, it must
143 * properly initialize the GPU MC controller and permit
144 * VRAM allocation
145 */
146 r = amdgpu_device_init(adev, flags);
147 if (r) {
148 dev_err(dev->dev, "Fatal error during GPU init\n");
149 goto out;
150 }
151
152 amdgpu_device_detect_runtime_pm_mode(adev);
153
154 /* Call ACPI methods: require modeset init
155 * but failure is not fatal
156 */
157
158 acpi_status = amdgpu_acpi_init(adev);
159 if (acpi_status)
160 dev_dbg(dev->dev, "Error during ACPI methods call\n");
161
162 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
163 DRM_WARN("smart shift update failed\n");
164
165 out:
166 if (r)
167 amdgpu_driver_unload_kms(dev);
168
169 return r;
170 }
171
172 static enum amd_ip_block_type
amdgpu_ip_get_block_type(struct amdgpu_device * adev,uint32_t ip)173 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)
174 {
175 enum amd_ip_block_type type;
176
177 switch (ip) {
178 case AMDGPU_HW_IP_GFX:
179 type = AMD_IP_BLOCK_TYPE_GFX;
180 break;
181 case AMDGPU_HW_IP_COMPUTE:
182 type = AMD_IP_BLOCK_TYPE_GFX;
183 break;
184 case AMDGPU_HW_IP_DMA:
185 type = AMD_IP_BLOCK_TYPE_SDMA;
186 break;
187 case AMDGPU_HW_IP_UVD:
188 case AMDGPU_HW_IP_UVD_ENC:
189 type = AMD_IP_BLOCK_TYPE_UVD;
190 break;
191 case AMDGPU_HW_IP_VCE:
192 type = AMD_IP_BLOCK_TYPE_VCE;
193 break;
194 case AMDGPU_HW_IP_VCN_DEC:
195 case AMDGPU_HW_IP_VCN_ENC:
196 type = AMD_IP_BLOCK_TYPE_VCN;
197 break;
198 case AMDGPU_HW_IP_VCN_JPEG:
199 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
200 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
201 break;
202 default:
203 type = AMD_IP_BLOCK_TYPE_NUM;
204 break;
205 }
206
207 return type;
208 }
209
amdgpu_firmware_info(struct drm_amdgpu_info_firmware * fw_info,struct drm_amdgpu_query_fw * query_fw,struct amdgpu_device * adev)210 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
211 struct drm_amdgpu_query_fw *query_fw,
212 struct amdgpu_device *adev)
213 {
214 switch (query_fw->fw_type) {
215 case AMDGPU_INFO_FW_VCE:
216 fw_info->ver = adev->vce.fw_version;
217 fw_info->feature = adev->vce.fb_version;
218 break;
219 case AMDGPU_INFO_FW_UVD:
220 fw_info->ver = adev->uvd.fw_version;
221 fw_info->feature = 0;
222 break;
223 case AMDGPU_INFO_FW_VCN:
224 fw_info->ver = adev->vcn.fw_version;
225 fw_info->feature = 0;
226 break;
227 case AMDGPU_INFO_FW_GMC:
228 fw_info->ver = adev->gmc.fw_version;
229 fw_info->feature = 0;
230 break;
231 case AMDGPU_INFO_FW_GFX_ME:
232 fw_info->ver = adev->gfx.me_fw_version;
233 fw_info->feature = adev->gfx.me_feature_version;
234 break;
235 case AMDGPU_INFO_FW_GFX_PFP:
236 fw_info->ver = adev->gfx.pfp_fw_version;
237 fw_info->feature = adev->gfx.pfp_feature_version;
238 break;
239 case AMDGPU_INFO_FW_GFX_CE:
240 fw_info->ver = adev->gfx.ce_fw_version;
241 fw_info->feature = adev->gfx.ce_feature_version;
242 break;
243 case AMDGPU_INFO_FW_GFX_RLC:
244 fw_info->ver = adev->gfx.rlc_fw_version;
245 fw_info->feature = adev->gfx.rlc_feature_version;
246 break;
247 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
248 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
249 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
250 break;
251 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
252 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
253 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
254 break;
255 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
256 fw_info->ver = adev->gfx.rlc_srls_fw_version;
257 fw_info->feature = adev->gfx.rlc_srls_feature_version;
258 break;
259 case AMDGPU_INFO_FW_GFX_RLCP:
260 fw_info->ver = adev->gfx.rlcp_ucode_version;
261 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
262 break;
263 case AMDGPU_INFO_FW_GFX_RLCV:
264 fw_info->ver = adev->gfx.rlcv_ucode_version;
265 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
266 break;
267 case AMDGPU_INFO_FW_GFX_MEC:
268 if (query_fw->index == 0) {
269 fw_info->ver = adev->gfx.mec_fw_version;
270 fw_info->feature = adev->gfx.mec_feature_version;
271 } else if (query_fw->index == 1) {
272 fw_info->ver = adev->gfx.mec2_fw_version;
273 fw_info->feature = adev->gfx.mec2_feature_version;
274 } else
275 return -EINVAL;
276 break;
277 case AMDGPU_INFO_FW_SMC:
278 fw_info->ver = adev->pm.fw_version;
279 fw_info->feature = 0;
280 break;
281 case AMDGPU_INFO_FW_TA:
282 switch (query_fw->index) {
283 case TA_FW_TYPE_PSP_XGMI:
284 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
285 fw_info->feature = adev->psp.xgmi_context.context
286 .bin_desc.feature_version;
287 break;
288 case TA_FW_TYPE_PSP_RAS:
289 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
290 fw_info->feature = adev->psp.ras_context.context
291 .bin_desc.feature_version;
292 break;
293 case TA_FW_TYPE_PSP_HDCP:
294 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
295 fw_info->feature = adev->psp.hdcp_context.context
296 .bin_desc.feature_version;
297 break;
298 case TA_FW_TYPE_PSP_DTM:
299 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
300 fw_info->feature = adev->psp.dtm_context.context
301 .bin_desc.feature_version;
302 break;
303 case TA_FW_TYPE_PSP_RAP:
304 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
305 fw_info->feature = adev->psp.rap_context.context
306 .bin_desc.feature_version;
307 break;
308 case TA_FW_TYPE_PSP_SECUREDISPLAY:
309 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
310 fw_info->feature =
311 adev->psp.securedisplay_context.context.bin_desc
312 .feature_version;
313 break;
314 default:
315 return -EINVAL;
316 }
317 break;
318 case AMDGPU_INFO_FW_SDMA:
319 if (query_fw->index >= adev->sdma.num_instances)
320 return -EINVAL;
321 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
322 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
323 break;
324 case AMDGPU_INFO_FW_SOS:
325 fw_info->ver = adev->psp.sos.fw_version;
326 fw_info->feature = adev->psp.sos.feature_version;
327 break;
328 case AMDGPU_INFO_FW_ASD:
329 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
330 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
331 break;
332 case AMDGPU_INFO_FW_DMCU:
333 fw_info->ver = adev->dm.dmcu_fw_version;
334 fw_info->feature = 0;
335 break;
336 case AMDGPU_INFO_FW_DMCUB:
337 fw_info->ver = adev->dm.dmcub_fw_version;
338 fw_info->feature = 0;
339 break;
340 case AMDGPU_INFO_FW_TOC:
341 fw_info->ver = adev->psp.toc.fw_version;
342 fw_info->feature = adev->psp.toc.feature_version;
343 break;
344 case AMDGPU_INFO_FW_CAP:
345 fw_info->ver = adev->psp.cap_fw_version;
346 fw_info->feature = adev->psp.cap_feature_version;
347 break;
348 case AMDGPU_INFO_FW_MES_KIQ:
349 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
350 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
351 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
352 break;
353 case AMDGPU_INFO_FW_MES:
354 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
355 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
356 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
357 break;
358 case AMDGPU_INFO_FW_IMU:
359 fw_info->ver = adev->gfx.imu_fw_version;
360 fw_info->feature = 0;
361 break;
362 case AMDGPU_INFO_FW_VPE:
363 fw_info->ver = adev->vpe.fw_version;
364 fw_info->feature = adev->vpe.feature_version;
365 break;
366 default:
367 return -EINVAL;
368 }
369 return 0;
370 }
371
amdgpu_hw_ip_info(struct amdgpu_device * adev,struct drm_amdgpu_info * info,struct drm_amdgpu_info_hw_ip * result)372 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
373 struct drm_amdgpu_info *info,
374 struct drm_amdgpu_info_hw_ip *result)
375 {
376 uint32_t ib_start_alignment = 0;
377 uint32_t ib_size_alignment = 0;
378 enum amd_ip_block_type type;
379 unsigned int num_rings = 0;
380 unsigned int i, j;
381
382 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
383 return -EINVAL;
384
385 switch (info->query_hw_ip.type) {
386 case AMDGPU_HW_IP_GFX:
387 type = AMD_IP_BLOCK_TYPE_GFX;
388 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
389 if (adev->gfx.gfx_ring[i].sched.ready)
390 ++num_rings;
391 ib_start_alignment = 32;
392 ib_size_alignment = 32;
393 break;
394 case AMDGPU_HW_IP_COMPUTE:
395 type = AMD_IP_BLOCK_TYPE_GFX;
396 for (i = 0; i < adev->gfx.num_compute_rings; i++)
397 if (adev->gfx.compute_ring[i].sched.ready)
398 ++num_rings;
399 ib_start_alignment = 32;
400 ib_size_alignment = 32;
401 break;
402 case AMDGPU_HW_IP_DMA:
403 type = AMD_IP_BLOCK_TYPE_SDMA;
404 for (i = 0; i < adev->sdma.num_instances; i++)
405 if (adev->sdma.instance[i].ring.sched.ready)
406 ++num_rings;
407 ib_start_alignment = 256;
408 ib_size_alignment = 4;
409 break;
410 case AMDGPU_HW_IP_UVD:
411 type = AMD_IP_BLOCK_TYPE_UVD;
412 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
413 if (adev->uvd.harvest_config & (1 << i))
414 continue;
415
416 if (adev->uvd.inst[i].ring.sched.ready)
417 ++num_rings;
418 }
419 ib_start_alignment = 256;
420 ib_size_alignment = 64;
421 break;
422 case AMDGPU_HW_IP_VCE:
423 type = AMD_IP_BLOCK_TYPE_VCE;
424 for (i = 0; i < adev->vce.num_rings; i++)
425 if (adev->vce.ring[i].sched.ready)
426 ++num_rings;
427 ib_start_alignment = 256;
428 ib_size_alignment = 4;
429 break;
430 case AMDGPU_HW_IP_UVD_ENC:
431 type = AMD_IP_BLOCK_TYPE_UVD;
432 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
433 if (adev->uvd.harvest_config & (1 << i))
434 continue;
435
436 for (j = 0; j < adev->uvd.num_enc_rings; j++)
437 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
438 ++num_rings;
439 }
440 ib_start_alignment = 256;
441 ib_size_alignment = 4;
442 break;
443 case AMDGPU_HW_IP_VCN_DEC:
444 type = AMD_IP_BLOCK_TYPE_VCN;
445 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
446 if (adev->vcn.harvest_config & (1 << i))
447 continue;
448
449 if (adev->vcn.inst[i].ring_dec.sched.ready)
450 ++num_rings;
451 }
452 ib_start_alignment = 256;
453 ib_size_alignment = 64;
454 break;
455 case AMDGPU_HW_IP_VCN_ENC:
456 type = AMD_IP_BLOCK_TYPE_VCN;
457 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
458 if (adev->vcn.harvest_config & (1 << i))
459 continue;
460
461 for (j = 0; j < adev->vcn.num_enc_rings; j++)
462 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
463 ++num_rings;
464 }
465 ib_start_alignment = 256;
466 ib_size_alignment = 4;
467 break;
468 case AMDGPU_HW_IP_VCN_JPEG:
469 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
470 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
471
472 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
473 if (adev->jpeg.harvest_config & (1 << i))
474 continue;
475
476 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
477 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
478 ++num_rings;
479 }
480 ib_start_alignment = 256;
481 ib_size_alignment = 64;
482 break;
483 case AMDGPU_HW_IP_VPE:
484 type = AMD_IP_BLOCK_TYPE_VPE;
485 if (adev->vpe.ring.sched.ready)
486 ++num_rings;
487 ib_start_alignment = 256;
488 ib_size_alignment = 4;
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 for (i = 0; i < adev->num_ip_blocks; i++)
495 if (adev->ip_blocks[i].version->type == type &&
496 adev->ip_blocks[i].status.valid)
497 break;
498
499 if (i == adev->num_ip_blocks)
500 return 0;
501
502 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
503 num_rings);
504
505 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
506 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
507
508 if (adev->asic_type >= CHIP_VEGA10) {
509 switch (type) {
510 case AMD_IP_BLOCK_TYPE_GFX:
511 result->ip_discovery_version =
512 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0));
513 break;
514 case AMD_IP_BLOCK_TYPE_SDMA:
515 result->ip_discovery_version =
516 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));
517 break;
518 case AMD_IP_BLOCK_TYPE_UVD:
519 case AMD_IP_BLOCK_TYPE_VCN:
520 case AMD_IP_BLOCK_TYPE_JPEG:
521 result->ip_discovery_version =
522 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
523 break;
524 case AMD_IP_BLOCK_TYPE_VCE:
525 result->ip_discovery_version =
526 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0));
527 break;
528 case AMD_IP_BLOCK_TYPE_VPE:
529 result->ip_discovery_version =
530 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
531 break;
532 default:
533 result->ip_discovery_version = 0;
534 break;
535 }
536 } else {
537 result->ip_discovery_version = 0;
538 }
539 result->capabilities_flags = 0;
540 result->available_rings = (1 << num_rings) - 1;
541 result->ib_start_alignment = ib_start_alignment;
542 result->ib_size_alignment = ib_size_alignment;
543 return 0;
544 }
545
546 /*
547 * Userspace get information ioctl
548 */
549 /**
550 * amdgpu_info_ioctl - answer a device specific request.
551 *
552 * @dev: drm device pointer
553 * @data: request object
554 * @filp: drm filp
555 *
556 * This function is used to pass device specific parameters to the userspace
557 * drivers. Examples include: pci device id, pipeline parms, tiling params,
558 * etc. (all asics).
559 * Returns 0 on success, -EINVAL on failure.
560 */
amdgpu_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)561 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
562 {
563 struct amdgpu_device *adev = drm_to_adev(dev);
564 struct drm_amdgpu_info *info = data;
565 struct amdgpu_mode_info *minfo = &adev->mode_info;
566 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
567 struct amdgpu_fpriv *fpriv;
568 struct amdgpu_ip_block *ip_block;
569 enum amd_ip_block_type type;
570 struct amdgpu_xcp *xcp;
571 u32 count, inst_mask;
572 uint32_t size = info->return_size;
573 struct drm_crtc *crtc;
574 uint32_t ui32 = 0;
575 uint64_t ui64 = 0;
576 int i, found, ret;
577 int ui32_size = sizeof(ui32);
578
579 if (!info->return_size || !info->return_pointer)
580 return -EINVAL;
581
582 switch (info->query) {
583 case AMDGPU_INFO_ACCEL_WORKING:
584 ui32 = adev->accel_working;
585 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
586 case AMDGPU_INFO_CRTC_FROM_ID:
587 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
588 crtc = (struct drm_crtc *)minfo->crtcs[i];
589 if (crtc && crtc->base.id == info->mode_crtc.id) {
590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
591
592 ui32 = amdgpu_crtc->crtc_id;
593 found = 1;
594 break;
595 }
596 }
597 if (!found) {
598 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
599 return -EINVAL;
600 }
601 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
602 case AMDGPU_INFO_HW_IP_INFO: {
603 struct drm_amdgpu_info_hw_ip ip = {};
604
605 ret = amdgpu_hw_ip_info(adev, info, &ip);
606 if (ret)
607 return ret;
608
609 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
610 return ret ? -EFAULT : 0;
611 }
612 case AMDGPU_INFO_HW_IP_COUNT: {
613 fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
614 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
615 ip_block = amdgpu_device_ip_get_ip_block(adev, type);
616
617 if (!ip_block || !ip_block->status.valid)
618 return -EINVAL;
619
620 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
621 fpriv->xcp_id >= 0 && fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
622 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
623 switch (type) {
624 case AMD_IP_BLOCK_TYPE_GFX:
625 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
626 count = hweight32(inst_mask);
627 break;
628 case AMD_IP_BLOCK_TYPE_SDMA:
629 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask);
630 count = hweight32(inst_mask);
631 break;
632 case AMD_IP_BLOCK_TYPE_JPEG:
633 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
634 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings;
635 break;
636 case AMD_IP_BLOCK_TYPE_VCN:
637 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
638 count = hweight32(inst_mask);
639 break;
640 default:
641 return -EINVAL;
642 }
643 if (ret)
644 return ret;
645 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
646 }
647
648 switch (type) {
649 case AMD_IP_BLOCK_TYPE_GFX:
650 case AMD_IP_BLOCK_TYPE_VCE:
651 count = 1;
652 break;
653 case AMD_IP_BLOCK_TYPE_SDMA:
654 count = adev->sdma.num_instances;
655 break;
656 case AMD_IP_BLOCK_TYPE_JPEG:
657 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings;
658 break;
659 case AMD_IP_BLOCK_TYPE_VCN:
660 count = adev->vcn.num_vcn_inst;
661 break;
662 case AMD_IP_BLOCK_TYPE_UVD:
663 count = adev->uvd.num_uvd_inst;
664 break;
665 /* For all other IP block types not listed in the switch statement
666 * the ip status is valid here and the instance count is one.
667 */
668 default:
669 count = 1;
670 break;
671 }
672
673 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
674 }
675 case AMDGPU_INFO_TIMESTAMP:
676 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
677 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
678 case AMDGPU_INFO_FW_VERSION: {
679 struct drm_amdgpu_info_firmware fw_info;
680
681 /* We only support one instance of each IP block right now. */
682 if (info->query_fw.ip_instance != 0)
683 return -EINVAL;
684
685 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
686 if (ret)
687 return ret;
688
689 return copy_to_user(out, &fw_info,
690 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
691 }
692 case AMDGPU_INFO_NUM_BYTES_MOVED:
693 ui64 = atomic64_read(&adev->num_bytes_moved);
694 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
695 case AMDGPU_INFO_NUM_EVICTIONS:
696 ui64 = atomic64_read(&adev->num_evictions);
697 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
698 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
699 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
700 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
701 case AMDGPU_INFO_VRAM_USAGE:
702 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
703 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
704 case AMDGPU_INFO_VIS_VRAM_USAGE:
705 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
706 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
707 case AMDGPU_INFO_GTT_USAGE:
708 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
709 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
710 case AMDGPU_INFO_GDS_CONFIG: {
711 struct drm_amdgpu_info_gds gds_info;
712
713 memset(&gds_info, 0, sizeof(gds_info));
714 gds_info.compute_partition_size = adev->gds.gds_size;
715 gds_info.gds_total_size = adev->gds.gds_size;
716 gds_info.gws_per_compute_partition = adev->gds.gws_size;
717 gds_info.oa_per_compute_partition = adev->gds.oa_size;
718 return copy_to_user(out, &gds_info,
719 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
720 }
721 case AMDGPU_INFO_VRAM_GTT: {
722 struct drm_amdgpu_info_vram_gtt vram_gtt;
723
724 vram_gtt.vram_size = adev->gmc.real_vram_size -
725 atomic64_read(&adev->vram_pin_size) -
726 AMDGPU_VM_RESERVED_VRAM;
727 vram_gtt.vram_cpu_accessible_size =
728 min(adev->gmc.visible_vram_size -
729 atomic64_read(&adev->visible_pin_size),
730 vram_gtt.vram_size);
731 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
732 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
733 return copy_to_user(out, &vram_gtt,
734 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
735 }
736 case AMDGPU_INFO_MEMORY: {
737 struct drm_amdgpu_memory_info mem;
738 struct ttm_resource_manager *gtt_man =
739 &adev->mman.gtt_mgr.manager;
740 struct ttm_resource_manager *vram_man =
741 &adev->mman.vram_mgr.manager;
742
743 memset(&mem, 0, sizeof(mem));
744 mem.vram.total_heap_size = adev->gmc.real_vram_size;
745 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
746 atomic64_read(&adev->vram_pin_size) -
747 AMDGPU_VM_RESERVED_VRAM;
748 mem.vram.heap_usage =
749 ttm_resource_manager_usage(vram_man);
750 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
751
752 mem.cpu_accessible_vram.total_heap_size =
753 adev->gmc.visible_vram_size;
754 mem.cpu_accessible_vram.usable_heap_size =
755 min(adev->gmc.visible_vram_size -
756 atomic64_read(&adev->visible_pin_size),
757 mem.vram.usable_heap_size);
758 mem.cpu_accessible_vram.heap_usage =
759 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
760 mem.cpu_accessible_vram.max_allocation =
761 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
762
763 mem.gtt.total_heap_size = gtt_man->size;
764 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
765 atomic64_read(&adev->gart_pin_size);
766 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
767 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
768
769 return copy_to_user(out, &mem,
770 min((size_t)size, sizeof(mem)))
771 ? -EFAULT : 0;
772 }
773 case AMDGPU_INFO_READ_MMR_REG: {
774 unsigned int n, alloc_size;
775 uint32_t *regs;
776 unsigned int se_num = (info->read_mmr_reg.instance >>
777 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
778 AMDGPU_INFO_MMR_SE_INDEX_MASK;
779 unsigned int sh_num = (info->read_mmr_reg.instance >>
780 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
781 AMDGPU_INFO_MMR_SH_INDEX_MASK;
782
783 /* set full masks if the userspace set all bits
784 * in the bitfields
785 */
786 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
787 se_num = 0xffffffff;
788 else if (se_num >= AMDGPU_GFX_MAX_SE)
789 return -EINVAL;
790 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
791 sh_num = 0xffffffff;
792 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
793 return -EINVAL;
794
795 if (info->read_mmr_reg.count > 128)
796 return -EINVAL;
797
798 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
799 if (!regs)
800 return -ENOMEM;
801 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
802
803 amdgpu_gfx_off_ctrl(adev, false);
804 for (i = 0; i < info->read_mmr_reg.count; i++) {
805 if (amdgpu_asic_read_register(adev, se_num, sh_num,
806 info->read_mmr_reg.dword_offset + i,
807 ®s[i])) {
808 DRM_DEBUG_KMS("unallowed offset %#x\n",
809 info->read_mmr_reg.dword_offset + i);
810 kfree(regs);
811 amdgpu_gfx_off_ctrl(adev, true);
812 return -EFAULT;
813 }
814 }
815 amdgpu_gfx_off_ctrl(adev, true);
816 n = copy_to_user(out, regs, min(size, alloc_size));
817 kfree(regs);
818 return n ? -EFAULT : 0;
819 }
820 case AMDGPU_INFO_DEV_INFO: {
821 struct drm_amdgpu_info_device *dev_info;
822 uint64_t vm_size;
823 uint32_t pcie_gen_mask;
824
825 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
826 if (!dev_info)
827 return -ENOMEM;
828
829 dev_info->device_id = adev->pdev->device;
830 dev_info->chip_rev = adev->rev_id;
831 dev_info->external_rev = adev->external_rev_id;
832 dev_info->pci_rev = adev->pdev->revision;
833 dev_info->family = adev->family;
834 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
835 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
836 /* return all clocks in KHz */
837 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
838 if (adev->pm.dpm_enabled) {
839 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
840 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
841 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
842 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
843 } else {
844 dev_info->max_engine_clock =
845 dev_info->min_engine_clock =
846 adev->clock.default_sclk * 10;
847 dev_info->max_memory_clock =
848 dev_info->min_memory_clock =
849 adev->clock.default_mclk * 10;
850 }
851 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
852 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
853 adev->gfx.config.max_shader_engines;
854 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
855 dev_info->ids_flags = 0;
856 if (adev->flags & AMD_IS_APU)
857 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
858 if (adev->gfx.mcbp)
859 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
860 if (amdgpu_is_tmz(adev))
861 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
862 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
863 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
864
865 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
866 vm_size -= AMDGPU_VA_RESERVED_TOP;
867
868 /* Older VCE FW versions are buggy and can handle only 40bits */
869 if (adev->vce.fw_version &&
870 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
871 vm_size = min(vm_size, 1ULL << 40);
872
873 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM;
874 dev_info->virtual_address_max =
875 min(vm_size, AMDGPU_GMC_HOLE_START);
876
877 if (vm_size > AMDGPU_GMC_HOLE_START) {
878 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
879 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
880 }
881 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
882 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
883 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
884 dev_info->cu_active_number = adev->gfx.cu_info.number;
885 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
886 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
887 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
888 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
889 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
890 sizeof(dev_info->cu_bitmap));
891 dev_info->vram_type = adev->gmc.vram_type;
892 dev_info->vram_bit_width = adev->gmc.vram_width;
893 dev_info->vce_harvest_config = adev->vce.harvest_config;
894 dev_info->gc_double_offchip_lds_buf =
895 adev->gfx.config.double_offchip_lds_buf;
896 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
897 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
898 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
899 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
900 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
901 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
902 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
903
904 if (adev->family >= AMDGPU_FAMILY_NV)
905 dev_info->pa_sc_tile_steering_override =
906 adev->gfx.config.pa_sc_tile_steering_override;
907
908 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
909
910 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
911 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
912 dev_info->pcie_gen = fls(pcie_gen_mask);
913 dev_info->pcie_num_lanes =
914 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
915 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
916 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
917 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
918 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
919 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
920
921 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
922 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
923 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
924 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
925 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
926 adev->gfx.config.gc_gl1c_per_sa;
927 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
928 dev_info->mall_size = adev->gmc.mall_size;
929
930
931 if (adev->gfx.funcs->get_gfx_shadow_info) {
932 struct amdgpu_gfx_shadow_info shadow_info;
933
934 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
935 if (!ret) {
936 dev_info->shadow_size = shadow_info.shadow_size;
937 dev_info->shadow_alignment = shadow_info.shadow_alignment;
938 dev_info->csa_size = shadow_info.csa_size;
939 dev_info->csa_alignment = shadow_info.csa_alignment;
940 }
941 }
942
943 ret = copy_to_user(out, dev_info,
944 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
945 kfree(dev_info);
946 return ret;
947 }
948 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
949 unsigned int i;
950 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
951 struct amd_vce_state *vce_state;
952
953 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
954 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
955 if (vce_state) {
956 vce_clk_table.entries[i].sclk = vce_state->sclk;
957 vce_clk_table.entries[i].mclk = vce_state->mclk;
958 vce_clk_table.entries[i].eclk = vce_state->evclk;
959 vce_clk_table.num_valid_entries++;
960 }
961 }
962
963 return copy_to_user(out, &vce_clk_table,
964 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
965 }
966 case AMDGPU_INFO_VBIOS: {
967 uint32_t bios_size = adev->bios_size;
968
969 switch (info->vbios_info.type) {
970 case AMDGPU_INFO_VBIOS_SIZE:
971 return copy_to_user(out, &bios_size,
972 min((size_t)size, sizeof(bios_size)))
973 ? -EFAULT : 0;
974 case AMDGPU_INFO_VBIOS_IMAGE: {
975 uint8_t *bios;
976 uint32_t bios_offset = info->vbios_info.offset;
977
978 if (bios_offset >= bios_size)
979 return -EINVAL;
980
981 bios = adev->bios + bios_offset;
982 return copy_to_user(out, bios,
983 min((size_t)size, (size_t)(bios_size - bios_offset)))
984 ? -EFAULT : 0;
985 }
986 case AMDGPU_INFO_VBIOS_INFO: {
987 struct drm_amdgpu_info_vbios vbios_info = {};
988 struct atom_context *atom_context;
989
990 atom_context = adev->mode_info.atom_context;
991 if (atom_context) {
992 memcpy(vbios_info.name, atom_context->name,
993 sizeof(atom_context->name));
994 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
995 sizeof(atom_context->vbios_pn));
996 vbios_info.version = atom_context->version;
997 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
998 sizeof(atom_context->vbios_ver_str));
999 memcpy(vbios_info.date, atom_context->date,
1000 sizeof(atom_context->date));
1001 }
1002
1003 return copy_to_user(out, &vbios_info,
1004 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
1005 }
1006 default:
1007 DRM_DEBUG_KMS("Invalid request %d\n",
1008 info->vbios_info.type);
1009 return -EINVAL;
1010 }
1011 }
1012 case AMDGPU_INFO_NUM_HANDLES: {
1013 struct drm_amdgpu_info_num_handles handle;
1014
1015 switch (info->query_hw_ip.type) {
1016 case AMDGPU_HW_IP_UVD:
1017 /* Starting Polaris, we support unlimited UVD handles */
1018 if (adev->asic_type < CHIP_POLARIS10) {
1019 handle.uvd_max_handles = adev->uvd.max_handles;
1020 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
1021
1022 return copy_to_user(out, &handle,
1023 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
1024 } else {
1025 return -ENODATA;
1026 }
1027
1028 break;
1029 default:
1030 return -EINVAL;
1031 }
1032 }
1033 case AMDGPU_INFO_SENSOR: {
1034 if (!adev->pm.dpm_enabled)
1035 return -ENOENT;
1036
1037 switch (info->sensor_info.type) {
1038 case AMDGPU_INFO_SENSOR_GFX_SCLK:
1039 /* get sclk in Mhz */
1040 if (amdgpu_dpm_read_sensor(adev,
1041 AMDGPU_PP_SENSOR_GFX_SCLK,
1042 (void *)&ui32, &ui32_size)) {
1043 return -EINVAL;
1044 }
1045 ui32 /= 100;
1046 break;
1047 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1048 /* get mclk in Mhz */
1049 if (amdgpu_dpm_read_sensor(adev,
1050 AMDGPU_PP_SENSOR_GFX_MCLK,
1051 (void *)&ui32, &ui32_size)) {
1052 return -EINVAL;
1053 }
1054 ui32 /= 100;
1055 break;
1056 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1057 /* get temperature in millidegrees C */
1058 if (amdgpu_dpm_read_sensor(adev,
1059 AMDGPU_PP_SENSOR_GPU_TEMP,
1060 (void *)&ui32, &ui32_size)) {
1061 return -EINVAL;
1062 }
1063 break;
1064 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1065 /* get GPU load */
1066 if (amdgpu_dpm_read_sensor(adev,
1067 AMDGPU_PP_SENSOR_GPU_LOAD,
1068 (void *)&ui32, &ui32_size)) {
1069 return -EINVAL;
1070 }
1071 break;
1072 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1073 /* get average GPU power */
1074 if (amdgpu_dpm_read_sensor(adev,
1075 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1076 (void *)&ui32, &ui32_size)) {
1077 /* fall back to input power for backwards compat */
1078 if (amdgpu_dpm_read_sensor(adev,
1079 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1080 (void *)&ui32, &ui32_size)) {
1081 return -EINVAL;
1082 }
1083 }
1084 ui32 >>= 8;
1085 break;
1086 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER:
1087 /* get input GPU power */
1088 if (amdgpu_dpm_read_sensor(adev,
1089 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1090 (void *)&ui32, &ui32_size)) {
1091 return -EINVAL;
1092 }
1093 ui32 >>= 8;
1094 break;
1095 case AMDGPU_INFO_SENSOR_VDDNB:
1096 /* get VDDNB in millivolts */
1097 if (amdgpu_dpm_read_sensor(adev,
1098 AMDGPU_PP_SENSOR_VDDNB,
1099 (void *)&ui32, &ui32_size)) {
1100 return -EINVAL;
1101 }
1102 break;
1103 case AMDGPU_INFO_SENSOR_VDDGFX:
1104 /* get VDDGFX in millivolts */
1105 if (amdgpu_dpm_read_sensor(adev,
1106 AMDGPU_PP_SENSOR_VDDGFX,
1107 (void *)&ui32, &ui32_size)) {
1108 return -EINVAL;
1109 }
1110 break;
1111 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1112 /* get stable pstate sclk in Mhz */
1113 if (amdgpu_dpm_read_sensor(adev,
1114 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1115 (void *)&ui32, &ui32_size)) {
1116 return -EINVAL;
1117 }
1118 ui32 /= 100;
1119 break;
1120 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1121 /* get stable pstate mclk in Mhz */
1122 if (amdgpu_dpm_read_sensor(adev,
1123 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1124 (void *)&ui32, &ui32_size)) {
1125 return -EINVAL;
1126 }
1127 ui32 /= 100;
1128 break;
1129 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1130 /* get peak pstate sclk in Mhz */
1131 if (amdgpu_dpm_read_sensor(adev,
1132 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1133 (void *)&ui32, &ui32_size)) {
1134 return -EINVAL;
1135 }
1136 ui32 /= 100;
1137 break;
1138 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1139 /* get peak pstate mclk in Mhz */
1140 if (amdgpu_dpm_read_sensor(adev,
1141 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1142 (void *)&ui32, &ui32_size)) {
1143 return -EINVAL;
1144 }
1145 ui32 /= 100;
1146 break;
1147 default:
1148 DRM_DEBUG_KMS("Invalid request %d\n",
1149 info->sensor_info.type);
1150 return -EINVAL;
1151 }
1152 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1153 }
1154 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1155 ui32 = atomic_read(&adev->vram_lost_counter);
1156 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1157 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1158 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1159 uint64_t ras_mask;
1160
1161 if (!ras)
1162 return -EINVAL;
1163 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1164
1165 return copy_to_user(out, &ras_mask,
1166 min_t(u64, size, sizeof(ras_mask))) ?
1167 -EFAULT : 0;
1168 }
1169 case AMDGPU_INFO_VIDEO_CAPS: {
1170 const struct amdgpu_video_codecs *codecs;
1171 struct drm_amdgpu_info_video_caps *caps;
1172 int r;
1173
1174 if (!adev->asic_funcs->query_video_codecs)
1175 return -EINVAL;
1176
1177 switch (info->video_cap.type) {
1178 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1179 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1180 if (r)
1181 return -EINVAL;
1182 break;
1183 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1184 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1185 if (r)
1186 return -EINVAL;
1187 break;
1188 default:
1189 DRM_DEBUG_KMS("Invalid request %d\n",
1190 info->video_cap.type);
1191 return -EINVAL;
1192 }
1193
1194 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1195 if (!caps)
1196 return -ENOMEM;
1197
1198 for (i = 0; i < codecs->codec_count; i++) {
1199 int idx = codecs->codec_array[i].codec_type;
1200
1201 switch (idx) {
1202 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1203 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1204 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1205 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1206 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1207 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1208 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1209 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1210 caps->codec_info[idx].valid = 1;
1211 caps->codec_info[idx].max_width =
1212 codecs->codec_array[i].max_width;
1213 caps->codec_info[idx].max_height =
1214 codecs->codec_array[i].max_height;
1215 caps->codec_info[idx].max_pixels_per_frame =
1216 codecs->codec_array[i].max_pixels_per_frame;
1217 caps->codec_info[idx].max_level =
1218 codecs->codec_array[i].max_level;
1219 break;
1220 default:
1221 break;
1222 }
1223 }
1224 r = copy_to_user(out, caps,
1225 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1226 kfree(caps);
1227 return r;
1228 }
1229 case AMDGPU_INFO_MAX_IBS: {
1230 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1231
1232 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1233 max_ibs[i] = amdgpu_ring_max_ibs(i);
1234
1235 return copy_to_user(out, max_ibs,
1236 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1237 }
1238 case AMDGPU_INFO_GPUVM_FAULT: {
1239 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1240 struct amdgpu_vm *vm = &fpriv->vm;
1241 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault;
1242 unsigned long flags;
1243
1244 if (!vm)
1245 return -EINVAL;
1246
1247 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault));
1248
1249 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
1250 gpuvm_fault.addr = vm->fault_info.addr;
1251 gpuvm_fault.status = vm->fault_info.status;
1252 gpuvm_fault.vmhub = vm->fault_info.vmhub;
1253 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
1254
1255 return copy_to_user(out, &gpuvm_fault,
1256 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
1257 }
1258 default:
1259 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1260 return -EINVAL;
1261 }
1262 return 0;
1263 }
1264
1265
1266 /*
1267 * Outdated mess for old drm with Xorg being in charge (void function now).
1268 */
1269 /**
1270 * amdgpu_driver_lastclose_kms - drm callback for last close
1271 *
1272 * @dev: drm dev pointer
1273 *
1274 * Switch vga_switcheroo state after last close (all asics).
1275 */
amdgpu_driver_lastclose_kms(struct drm_device * dev)1276 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1277 {
1278 drm_fb_helper_lastclose(dev);
1279 vga_switcheroo_process_delayed_switch();
1280 }
1281
1282 /**
1283 * amdgpu_driver_open_kms - drm callback for open
1284 *
1285 * @dev: drm dev pointer
1286 * @file_priv: drm file
1287 *
1288 * On device open, init vm on cayman+ (all asics).
1289 * Returns 0 on success, error on failure.
1290 */
amdgpu_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)1291 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1292 {
1293 struct amdgpu_device *adev = drm_to_adev(dev);
1294 struct amdgpu_fpriv *fpriv;
1295 int r, pasid;
1296
1297 /* Ensure IB tests are run on ring */
1298 flush_delayed_work(&adev->delayed_init_work);
1299
1300
1301 if (amdgpu_ras_intr_triggered()) {
1302 DRM_ERROR("RAS Intr triggered, device disabled!!");
1303 return -EHWPOISON;
1304 }
1305
1306 file_priv->driver_priv = NULL;
1307
1308 r = pm_runtime_get_sync(dev->dev);
1309 if (r < 0)
1310 goto pm_put;
1311
1312 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1313 if (unlikely(!fpriv)) {
1314 r = -ENOMEM;
1315 goto out_suspend;
1316 }
1317
1318 pasid = amdgpu_pasid_alloc(16);
1319 if (pasid < 0) {
1320 dev_warn(adev->dev, "No more PASIDs available!");
1321 pasid = 0;
1322 }
1323
1324 r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1325 if (r)
1326 goto error_pasid;
1327
1328 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1329 if (r)
1330 goto error_pasid;
1331
1332 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1333 if (r)
1334 goto error_vm;
1335
1336 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1337 if (!fpriv->prt_va) {
1338 r = -ENOMEM;
1339 goto error_vm;
1340 }
1341
1342 if (adev->gfx.mcbp) {
1343 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1344
1345 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1346 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1347 if (r)
1348 goto error_vm;
1349 }
1350
1351 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va);
1352 if (r)
1353 goto error_vm;
1354
1355 mutex_init(&fpriv->bo_list_lock);
1356 idr_init_base(&fpriv->bo_list_handles, 1);
1357
1358 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1359
1360 file_priv->driver_priv = fpriv;
1361 goto out_suspend;
1362
1363 error_vm:
1364 amdgpu_vm_fini(adev, &fpriv->vm);
1365
1366 error_pasid:
1367 if (pasid) {
1368 amdgpu_pasid_free(pasid);
1369 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1370 }
1371
1372 kfree(fpriv);
1373
1374 out_suspend:
1375 pm_runtime_mark_last_busy(dev->dev);
1376 pm_put:
1377 pm_runtime_put_autosuspend(dev->dev);
1378
1379 return r;
1380 }
1381
1382 /**
1383 * amdgpu_driver_postclose_kms - drm callback for post close
1384 *
1385 * @dev: drm dev pointer
1386 * @file_priv: drm file
1387 *
1388 * On device post close, tear down vm on cayman+ (all asics).
1389 */
amdgpu_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)1390 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1391 struct drm_file *file_priv)
1392 {
1393 struct amdgpu_device *adev = drm_to_adev(dev);
1394 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1395 struct amdgpu_bo_list *list;
1396 struct amdgpu_bo *pd;
1397 u32 pasid;
1398 int handle;
1399
1400 if (!fpriv)
1401 return;
1402
1403 pm_runtime_get_sync(dev->dev);
1404
1405 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1406 amdgpu_uvd_free_handles(adev, file_priv);
1407 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1408 amdgpu_vce_free_handles(adev, file_priv);
1409
1410 if (fpriv->csa_va) {
1411 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1412
1413 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1414 fpriv->csa_va, csa_addr));
1415 fpriv->csa_va = NULL;
1416 }
1417
1418 amdgpu_seq64_unmap(adev, fpriv);
1419
1420 pasid = fpriv->vm.pasid;
1421 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1422 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1423 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1424 amdgpu_bo_unreserve(pd);
1425 }
1426
1427 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1428 amdgpu_vm_fini(adev, &fpriv->vm);
1429
1430 if (pasid)
1431 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1432 amdgpu_bo_unref(&pd);
1433
1434 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1435 amdgpu_bo_list_put(list);
1436
1437 idr_destroy(&fpriv->bo_list_handles);
1438 mutex_destroy(&fpriv->bo_list_lock);
1439
1440 kfree(fpriv);
1441 file_priv->driver_priv = NULL;
1442
1443 pm_runtime_mark_last_busy(dev->dev);
1444 pm_runtime_put_autosuspend(dev->dev);
1445 }
1446
1447
amdgpu_driver_release_kms(struct drm_device * dev)1448 void amdgpu_driver_release_kms(struct drm_device *dev)
1449 {
1450 struct amdgpu_device *adev = drm_to_adev(dev);
1451
1452 amdgpu_device_fini_sw(adev);
1453 pci_set_drvdata(adev->pdev, NULL);
1454 }
1455
1456 /*
1457 * VBlank related functions.
1458 */
1459 /**
1460 * amdgpu_get_vblank_counter_kms - get frame count
1461 *
1462 * @crtc: crtc to get the frame count from
1463 *
1464 * Gets the frame count on the requested crtc (all asics).
1465 * Returns frame count on success, -EINVAL on failure.
1466 */
amdgpu_get_vblank_counter_kms(struct drm_crtc * crtc)1467 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1468 {
1469 struct drm_device *dev = crtc->dev;
1470 unsigned int pipe = crtc->index;
1471 struct amdgpu_device *adev = drm_to_adev(dev);
1472 int vpos, hpos, stat;
1473 u32 count;
1474
1475 if (pipe >= adev->mode_info.num_crtc) {
1476 DRM_ERROR("Invalid crtc %u\n", pipe);
1477 return -EINVAL;
1478 }
1479
1480 /* The hw increments its frame counter at start of vsync, not at start
1481 * of vblank, as is required by DRM core vblank counter handling.
1482 * Cook the hw count here to make it appear to the caller as if it
1483 * incremented at start of vblank. We measure distance to start of
1484 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1485 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1486 * result by 1 to give the proper appearance to caller.
1487 */
1488 if (adev->mode_info.crtcs[pipe]) {
1489 /* Repeat readout if needed to provide stable result if
1490 * we cross start of vsync during the queries.
1491 */
1492 do {
1493 count = amdgpu_display_vblank_get_counter(adev, pipe);
1494 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1495 * vpos as distance to start of vblank, instead of
1496 * regular vertical scanout pos.
1497 */
1498 stat = amdgpu_display_get_crtc_scanoutpos(
1499 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1500 &vpos, &hpos, NULL, NULL,
1501 &adev->mode_info.crtcs[pipe]->base.hwmode);
1502 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1503
1504 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1505 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1506 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1507 } else {
1508 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1509 pipe, vpos);
1510
1511 /* Bump counter if we are at >= leading edge of vblank,
1512 * but before vsync where vpos would turn negative and
1513 * the hw counter really increments.
1514 */
1515 if (vpos >= 0)
1516 count++;
1517 }
1518 } else {
1519 /* Fallback to use value as is. */
1520 count = amdgpu_display_vblank_get_counter(adev, pipe);
1521 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1522 }
1523
1524 return count;
1525 }
1526
1527 /**
1528 * amdgpu_enable_vblank_kms - enable vblank interrupt
1529 *
1530 * @crtc: crtc to enable vblank interrupt for
1531 *
1532 * Enable the interrupt on the requested crtc (all asics).
1533 * Returns 0 on success, -EINVAL on failure.
1534 */
amdgpu_enable_vblank_kms(struct drm_crtc * crtc)1535 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1536 {
1537 struct drm_device *dev = crtc->dev;
1538 unsigned int pipe = crtc->index;
1539 struct amdgpu_device *adev = drm_to_adev(dev);
1540 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1541
1542 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1543 }
1544
1545 /**
1546 * amdgpu_disable_vblank_kms - disable vblank interrupt
1547 *
1548 * @crtc: crtc to disable vblank interrupt for
1549 *
1550 * Disable the interrupt on the requested crtc (all asics).
1551 */
amdgpu_disable_vblank_kms(struct drm_crtc * crtc)1552 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1553 {
1554 struct drm_device *dev = crtc->dev;
1555 unsigned int pipe = crtc->index;
1556 struct amdgpu_device *adev = drm_to_adev(dev);
1557 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1558
1559 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1560 }
1561
1562 /*
1563 * Debugfs info
1564 */
1565 #if defined(CONFIG_DEBUG_FS)
1566
amdgpu_debugfs_firmware_info_show(struct seq_file * m,void * unused)1567 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1568 {
1569 struct amdgpu_device *adev = m->private;
1570 struct drm_amdgpu_info_firmware fw_info;
1571 struct drm_amdgpu_query_fw query_fw;
1572 struct atom_context *ctx = adev->mode_info.atom_context;
1573 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1574 int ret, i;
1575
1576 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1577 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1578 TA_FW_NAME(XGMI),
1579 TA_FW_NAME(RAS),
1580 TA_FW_NAME(HDCP),
1581 TA_FW_NAME(DTM),
1582 TA_FW_NAME(RAP),
1583 TA_FW_NAME(SECUREDISPLAY),
1584 #undef TA_FW_NAME
1585 };
1586
1587 /* VCE */
1588 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1589 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1590 if (ret)
1591 return ret;
1592 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1593 fw_info.feature, fw_info.ver);
1594
1595 /* UVD */
1596 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1597 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1598 if (ret)
1599 return ret;
1600 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1601 fw_info.feature, fw_info.ver);
1602
1603 /* GMC */
1604 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1605 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1606 if (ret)
1607 return ret;
1608 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1609 fw_info.feature, fw_info.ver);
1610
1611 /* ME */
1612 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1613 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1614 if (ret)
1615 return ret;
1616 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1617 fw_info.feature, fw_info.ver);
1618
1619 /* PFP */
1620 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1621 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1622 if (ret)
1623 return ret;
1624 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1625 fw_info.feature, fw_info.ver);
1626
1627 /* CE */
1628 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1629 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1630 if (ret)
1631 return ret;
1632 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1633 fw_info.feature, fw_info.ver);
1634
1635 /* RLC */
1636 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1637 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1638 if (ret)
1639 return ret;
1640 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1641 fw_info.feature, fw_info.ver);
1642
1643 /* RLC SAVE RESTORE LIST CNTL */
1644 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1645 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1646 if (ret)
1647 return ret;
1648 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1649 fw_info.feature, fw_info.ver);
1650
1651 /* RLC SAVE RESTORE LIST GPM MEM */
1652 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1653 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1654 if (ret)
1655 return ret;
1656 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1657 fw_info.feature, fw_info.ver);
1658
1659 /* RLC SAVE RESTORE LIST SRM MEM */
1660 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1661 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1662 if (ret)
1663 return ret;
1664 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1665 fw_info.feature, fw_info.ver);
1666
1667 /* RLCP */
1668 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1669 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1670 if (ret)
1671 return ret;
1672 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1673 fw_info.feature, fw_info.ver);
1674
1675 /* RLCV */
1676 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1677 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1678 if (ret)
1679 return ret;
1680 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1681 fw_info.feature, fw_info.ver);
1682
1683 /* MEC */
1684 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1685 query_fw.index = 0;
1686 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1687 if (ret)
1688 return ret;
1689 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1690 fw_info.feature, fw_info.ver);
1691
1692 /* MEC2 */
1693 if (adev->gfx.mec2_fw) {
1694 query_fw.index = 1;
1695 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1696 if (ret)
1697 return ret;
1698 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1699 fw_info.feature, fw_info.ver);
1700 }
1701
1702 /* IMU */
1703 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1704 query_fw.index = 0;
1705 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1706 if (ret)
1707 return ret;
1708 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1709 fw_info.feature, fw_info.ver);
1710
1711 /* PSP SOS */
1712 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1713 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1714 if (ret)
1715 return ret;
1716 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1717 fw_info.feature, fw_info.ver);
1718
1719
1720 /* PSP ASD */
1721 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1722 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1723 if (ret)
1724 return ret;
1725 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1726 fw_info.feature, fw_info.ver);
1727
1728 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1729 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1730 query_fw.index = i;
1731 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1732 if (ret)
1733 continue;
1734
1735 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1736 ta_fw_name[i], fw_info.feature, fw_info.ver);
1737 }
1738
1739 /* SMC */
1740 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1741 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1742 if (ret)
1743 return ret;
1744 smu_program = (fw_info.ver >> 24) & 0xff;
1745 smu_major = (fw_info.ver >> 16) & 0xff;
1746 smu_minor = (fw_info.ver >> 8) & 0xff;
1747 smu_debug = (fw_info.ver >> 0) & 0xff;
1748 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1749 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1750
1751 /* SDMA */
1752 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1753 for (i = 0; i < adev->sdma.num_instances; i++) {
1754 query_fw.index = i;
1755 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1756 if (ret)
1757 return ret;
1758 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1759 i, fw_info.feature, fw_info.ver);
1760 }
1761
1762 /* VCN */
1763 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1764 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1765 if (ret)
1766 return ret;
1767 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1768 fw_info.feature, fw_info.ver);
1769
1770 /* DMCU */
1771 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1772 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1773 if (ret)
1774 return ret;
1775 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1776 fw_info.feature, fw_info.ver);
1777
1778 /* DMCUB */
1779 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1780 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1781 if (ret)
1782 return ret;
1783 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1784 fw_info.feature, fw_info.ver);
1785
1786 /* TOC */
1787 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1788 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1789 if (ret)
1790 return ret;
1791 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1792 fw_info.feature, fw_info.ver);
1793
1794 /* CAP */
1795 if (adev->psp.cap_fw) {
1796 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1797 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1798 if (ret)
1799 return ret;
1800 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1801 fw_info.feature, fw_info.ver);
1802 }
1803
1804 /* MES_KIQ */
1805 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1806 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1807 if (ret)
1808 return ret;
1809 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1810 fw_info.feature, fw_info.ver);
1811
1812 /* MES */
1813 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1814 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1815 if (ret)
1816 return ret;
1817 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1818 fw_info.feature, fw_info.ver);
1819
1820 /* VPE */
1821 query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1822 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1823 if (ret)
1824 return ret;
1825 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1826 fw_info.feature, fw_info.ver);
1827
1828 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1829
1830 return 0;
1831 }
1832
1833 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1834
1835 #endif
1836
amdgpu_debugfs_firmware_init(struct amdgpu_device * adev)1837 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1838 {
1839 #if defined(CONFIG_DEBUG_FS)
1840 struct drm_minor *minor = adev_to_drm(adev)->primary;
1841 struct dentry *root = minor->debugfs_root;
1842
1843 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1844 adev, &amdgpu_debugfs_firmware_info_fops);
1845
1846 #endif
1847 }
1848