1 /*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_fbdev_generic.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_managed.h>
30 #include <drm/drm_pciids.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/drm_vblank.h>
33
34 #include <linux/cc_platform.h>
35 #include <linux/dynamic_debug.h>
36 #include <linux/module.h>
37 #include <linux/mmu_notifier.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/suspend.h>
40 #include <linux/vga_switcheroo.h>
41
42 #include "amdgpu.h"
43 #include "amdgpu_amdkfd.h"
44 #include "amdgpu_dma_buf.h"
45 #include "amdgpu_drv.h"
46 #include "amdgpu_fdinfo.h"
47 #include "amdgpu_irq.h"
48 #include "amdgpu_psp.h"
49 #include "amdgpu_ras.h"
50 #include "amdgpu_reset.h"
51 #include "amdgpu_sched.h"
52 #include "amdgpu_xgmi.h"
53 #include "../amdxcp/amdgpu_xcp_drv.h"
54
55 /*
56 * KMS wrapper.
57 * - 3.0.0 - initial driver
58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60 * at the end of IBs.
61 * - 3.3.0 - Add VM support for UVD on supported hardware.
62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
63 * - 3.5.0 - Add support for new UVD_NO_OP register.
64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
65 * - 3.7.0 - Add support for VCE clock list packet
66 * - 3.8.0 - Add support raster config init in the kernel
67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
70 * - 3.12.0 - Add query for double offchip LDS buffers
71 * - 3.13.0 - Add PRT support
72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
73 * - 3.15.0 - Export more gpu info for gfx9
74 * - 3.16.0 - Add reserved vmid support
75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
76 * - 3.18.0 - Export gpu always on cu bitmap
77 * - 3.19.0 - Add support for UVD MJPEG decode
78 * - 3.20.0 - Add support for local BOs
79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
81 * - 3.23.0 - Add query for VRAM lost counter
82 * - 3.24.0 - Add high priority compute support for gfx9
83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
94 * - 3.36.0 - Allow reading more status registers on si/cik
95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
99 * - 3.41.0 - Add video codec query
100 * - 3.42.0 - Add 16bpc fixed point display support
101 * - 3.43.0 - Add device hot plug/unplug support
102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
103 * - 3.45.0 - Add context ioctl stable pstate interface
104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106 * - 3.48.0 - Add IP discovery version info to HW INFO
107 * - 3.49.0 - Add gang submit into CS IOCTL
108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
114 * 3.53.0 - Support for GFX11 CP GFX shadowing
115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
116 */
117 #define KMS_DRIVER_MAJOR 3
118 #define KMS_DRIVER_MINOR 54
119 #define KMS_DRIVER_PATCHLEVEL 0
120
121 unsigned int amdgpu_vram_limit = UINT_MAX;
122 int amdgpu_vis_vram_limit;
123 int amdgpu_gart_size = -1; /* auto */
124 int amdgpu_gtt_size = -1; /* auto */
125 int amdgpu_moverate = -1; /* auto */
126 int amdgpu_audio = -1;
127 int amdgpu_disp_priority;
128 int amdgpu_hw_i2c;
129 int amdgpu_pcie_gen2 = -1;
130 int amdgpu_msi = -1;
131 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
132 int amdgpu_dpm = -1;
133 int amdgpu_fw_load_type = -1;
134 int amdgpu_aspm = -1;
135 int amdgpu_runtime_pm = -1;
136 uint amdgpu_ip_block_mask = 0xffffffff;
137 int amdgpu_bapm = -1;
138 int amdgpu_deep_color;
139 int amdgpu_vm_size = -1;
140 int amdgpu_vm_fragment_size = -1;
141 int amdgpu_vm_block_size = -1;
142 int amdgpu_vm_fault_stop;
143 int amdgpu_vm_debug;
144 int amdgpu_vm_update_mode = -1;
145 int amdgpu_exp_hw_support;
146 int amdgpu_dc = -1;
147 int amdgpu_sched_jobs = 32;
148 int amdgpu_sched_hw_submission = 2;
149 uint amdgpu_pcie_gen_cap;
150 uint amdgpu_pcie_lane_cap;
151 u64 amdgpu_cg_mask = 0xffffffffffffffff;
152 uint amdgpu_pg_mask = 0xffffffff;
153 uint amdgpu_sdma_phase_quantum = 32;
154 char *amdgpu_disable_cu;
155 char *amdgpu_virtual_display;
156 bool enforce_isolation;
157 /*
158 * OverDrive(bit 14) disabled by default
159 * GFX DCS(bit 19) disabled by default
160 */
161 uint amdgpu_pp_feature_mask = 0xfff7bfff;
162 uint amdgpu_force_long_training;
163 int amdgpu_lbpw = -1;
164 int amdgpu_compute_multipipe = -1;
165 int amdgpu_gpu_recovery = -1; /* auto */
166 int amdgpu_emu_mode;
167 uint amdgpu_smu_memory_pool_size;
168 int amdgpu_smu_pptable_id = -1;
169 /*
170 * FBC (bit 0) disabled by default
171 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
172 * - With this, for multiple monitors in sync(e.g. with the same model),
173 * mclk switching will be allowed. And the mclk will be not foced to the
174 * highest. That helps saving some idle power.
175 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
176 * PSR (bit 3) disabled by default
177 * EDP NO POWER SEQUENCING (bit 4) disabled by default
178 */
179 uint amdgpu_dc_feature_mask = 2;
180 uint amdgpu_dc_debug_mask;
181 uint amdgpu_dc_visual_confirm;
182 int amdgpu_async_gfx_ring = 1;
183 int amdgpu_mcbp = -1;
184 int amdgpu_discovery = -1;
185 int amdgpu_mes;
186 int amdgpu_mes_kiq;
187 int amdgpu_noretry = -1;
188 int amdgpu_force_asic_type = -1;
189 int amdgpu_tmz = -1; /* auto */
190 int amdgpu_reset_method = -1; /* auto */
191 int amdgpu_num_kcq = -1;
192 int amdgpu_smartshift_bias;
193 int amdgpu_use_xgmi_p2p = 1;
194 int amdgpu_vcnfw_log;
195 int amdgpu_sg_display = -1; /* auto */
196 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
197
198 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
199
200 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
201 "DRM_UT_CORE",
202 "DRM_UT_DRIVER",
203 "DRM_UT_KMS",
204 "DRM_UT_PRIME",
205 "DRM_UT_ATOMIC",
206 "DRM_UT_VBL",
207 "DRM_UT_STATE",
208 "DRM_UT_LEASE",
209 "DRM_UT_DP",
210 "DRM_UT_DRMRES");
211
212 struct amdgpu_mgpu_info mgpu_info = {
213 .mutex = RWLOCK_INITIALIZER("mgpu_info"),
214 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
215 mgpu_info.delayed_reset_work,
216 amdgpu_drv_delayed_reset_work_handler, 0),
217 };
218 int amdgpu_ras_enable = -1;
219 uint amdgpu_ras_mask = 0xffffffff;
220 int amdgpu_bad_page_threshold = -1;
221 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
222 .timeout_fatal_disable = false,
223 .period = 0x0, /* default to 0x0 (timeout disable) */
224 };
225
226 /**
227 * DOC: vramlimit (int)
228 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
229 */
230 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
231 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
232
233 /**
234 * DOC: vis_vramlimit (int)
235 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
236 */
237 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
238 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
239
240 /**
241 * DOC: gartsize (uint)
242 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
243 * The default is -1 (The size depends on asic).
244 */
245 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
246 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
247
248 /**
249 * DOC: gttsize (int)
250 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
251 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
252 */
253 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
254 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
255
256 /**
257 * DOC: moverate (int)
258 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
259 */
260 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
261 module_param_named(moverate, amdgpu_moverate, int, 0600);
262
263 /**
264 * DOC: audio (int)
265 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
266 */
267 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
268 module_param_named(audio, amdgpu_audio, int, 0444);
269
270 /**
271 * DOC: disp_priority (int)
272 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
273 */
274 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
275 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
276
277 /**
278 * DOC: hw_i2c (int)
279 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
280 */
281 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
282 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
283
284 /**
285 * DOC: pcie_gen2 (int)
286 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
287 */
288 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
289 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
290
291 /**
292 * DOC: msi (int)
293 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
294 */
295 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
296 module_param_named(msi, amdgpu_msi, int, 0444);
297
298 /**
299 * DOC: lockup_timeout (string)
300 * Set GPU scheduler timeout value in ms.
301 *
302 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
303 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
304 * to the default timeout.
305 *
306 * - With one value specified, the setting will apply to all non-compute jobs.
307 * - With multiple values specified, the first one will be for GFX.
308 * The second one is for Compute. The third and fourth ones are
309 * for SDMA and Video.
310 *
311 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
312 * jobs is 10000. The timeout for compute is 60000.
313 */
314 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
315 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
316 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
317 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
318
319 /**
320 * DOC: dpm (int)
321 * Override for dynamic power management setting
322 * (0 = disable, 1 = enable)
323 * The default is -1 (auto).
324 */
325 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
326 module_param_named(dpm, amdgpu_dpm, int, 0444);
327
328 /**
329 * DOC: fw_load_type (int)
330 * Set different firmware loading type for debugging, if supported.
331 * Set to 0 to force direct loading if supported by the ASIC. Set
332 * to -1 to select the default loading mode for the ASIC, as defined
333 * by the driver. The default is -1 (auto).
334 */
335 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
336 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
337
338 /**
339 * DOC: aspm (int)
340 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
341 */
342 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
343 module_param_named(aspm, amdgpu_aspm, int, 0444);
344
345 /**
346 * DOC: runpm (int)
347 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
348 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
349 * Setting the value to 0 disables this functionality.
350 * Setting the value to -2 is auto enabled with power down when displays are attached.
351 */
352 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)");
353 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
354
355 /**
356 * DOC: ip_block_mask (uint)
357 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
358 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
359 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
360 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
361 */
362 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
363 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
364
365 /**
366 * DOC: bapm (int)
367 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
368 * The default -1 (auto, enabled)
369 */
370 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
371 module_param_named(bapm, amdgpu_bapm, int, 0444);
372
373 /**
374 * DOC: deep_color (int)
375 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
376 */
377 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
378 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
379
380 /**
381 * DOC: vm_size (int)
382 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
383 */
384 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
385 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
386
387 /**
388 * DOC: vm_fragment_size (int)
389 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
390 */
391 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
392 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
393
394 /**
395 * DOC: vm_block_size (int)
396 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
397 */
398 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
399 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
400
401 /**
402 * DOC: vm_fault_stop (int)
403 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
404 */
405 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
406 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
407
408 /**
409 * DOC: vm_debug (int)
410 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
411 */
412 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
413 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
414
415 /**
416 * DOC: vm_update_mode (int)
417 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
418 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
419 */
420 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
421 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
422
423 /**
424 * DOC: exp_hw_support (int)
425 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
426 */
427 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
428 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
429
430 /**
431 * DOC: dc (int)
432 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
433 */
434 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
435 module_param_named(dc, amdgpu_dc, int, 0444);
436
437 /**
438 * DOC: sched_jobs (int)
439 * Override the max number of jobs supported in the sw queue. The default is 32.
440 */
441 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
442 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
443
444 /**
445 * DOC: sched_hw_submission (int)
446 * Override the max number of HW submissions. The default is 2.
447 */
448 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
449 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
450
451 /**
452 * DOC: ppfeaturemask (hexint)
453 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
454 * The default is the current set of stable power features.
455 */
456 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
457 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
458
459 /**
460 * DOC: forcelongtraining (uint)
461 * Force long memory training in resume.
462 * The default is zero, indicates short training in resume.
463 */
464 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
465 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
466
467 /**
468 * DOC: pcie_gen_cap (uint)
469 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
470 * The default is 0 (automatic for each asic).
471 */
472 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
473 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
474
475 /**
476 * DOC: pcie_lane_cap (uint)
477 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
478 * The default is 0 (automatic for each asic).
479 */
480 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
481 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
482
483 /**
484 * DOC: cg_mask (ullong)
485 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
486 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
487 */
488 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
489 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
490
491 /**
492 * DOC: pg_mask (uint)
493 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
494 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
495 */
496 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
497 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
498
499 /**
500 * DOC: sdma_phase_quantum (uint)
501 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
502 */
503 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
504 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
505
506 /**
507 * DOC: disable_cu (charp)
508 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
509 */
510 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
511 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
512
513 /**
514 * DOC: virtual_display (charp)
515 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
516 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
517 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
518 * device at 26:00.0. The default is NULL.
519 */
520 MODULE_PARM_DESC(virtual_display,
521 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
522 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
523
524 /**
525 * DOC: lbpw (int)
526 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
527 */
528 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
529 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
530
531 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
532 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
533
534 /**
535 * DOC: gpu_recovery (int)
536 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
537 */
538 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
539 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
540
541 /**
542 * DOC: emu_mode (int)
543 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
544 */
545 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
546 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
547
548 /**
549 * DOC: ras_enable (int)
550 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
551 */
552 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
553 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
554
555 /**
556 * DOC: ras_mask (uint)
557 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
558 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
559 */
560 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
561 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
562
563 /**
564 * DOC: timeout_fatal_disable (bool)
565 * Disable Watchdog timeout fatal error event
566 */
567 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
568 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
569
570 /**
571 * DOC: timeout_period (uint)
572 * Modify the watchdog timeout max_cycles as (1 << period)
573 */
574 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
575 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
576
577 /**
578 * DOC: si_support (int)
579 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
581 * otherwise using amdgpu driver.
582 */
583 #ifdef CONFIG_DRM_AMDGPU_SI
584
585 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
586 int amdgpu_si_support = 0;
587 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
588 #else
589 int amdgpu_si_support = 1;
590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
591 #endif
592
593 module_param_named(si_support, amdgpu_si_support, int, 0444);
594 #endif
595
596 /**
597 * DOC: cik_support (int)
598 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
599 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
600 * otherwise using amdgpu driver.
601 */
602 #ifdef CONFIG_DRM_AMDGPU_CIK
603
604 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
605 int amdgpu_cik_support = 0;
606 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
607 #else
608 int amdgpu_cik_support = 1;
609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
610 #endif
611
612 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
613 #endif
614
615 /**
616 * DOC: smu_memory_pool_size (uint)
617 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
618 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
619 */
620 MODULE_PARM_DESC(smu_memory_pool_size,
621 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
622 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
623
624 /**
625 * DOC: async_gfx_ring (int)
626 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
627 */
628 MODULE_PARM_DESC(async_gfx_ring,
629 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
630 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
631
632 /**
633 * DOC: mcbp (int)
634 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
635 */
636 MODULE_PARM_DESC(mcbp,
637 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
638 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
639
640 /**
641 * DOC: discovery (int)
642 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
643 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
644 */
645 MODULE_PARM_DESC(discovery,
646 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
647 module_param_named(discovery, amdgpu_discovery, int, 0444);
648
649 /**
650 * DOC: mes (int)
651 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
652 * (0 = disabled (default), 1 = enabled)
653 */
654 MODULE_PARM_DESC(mes,
655 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
656 module_param_named(mes, amdgpu_mes, int, 0444);
657
658 /**
659 * DOC: mes_kiq (int)
660 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
661 * (0 = disabled (default), 1 = enabled)
662 */
663 MODULE_PARM_DESC(mes_kiq,
664 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
665 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
666
667 /**
668 * DOC: noretry (int)
669 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
670 * do not support per-process XNACK this also disables retry page faults.
671 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
672 */
673 MODULE_PARM_DESC(noretry,
674 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
675 module_param_named(noretry, amdgpu_noretry, int, 0644);
676
677 /**
678 * DOC: force_asic_type (int)
679 * A non negative value used to specify the asic type for all supported GPUs.
680 */
681 MODULE_PARM_DESC(force_asic_type,
682 "A non negative value used to specify the asic type for all supported GPUs");
683 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
684
685 /**
686 * DOC: use_xgmi_p2p (int)
687 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
688 */
689 MODULE_PARM_DESC(use_xgmi_p2p,
690 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
691 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
692
693
694 #ifdef CONFIG_HSA_AMD
695 /**
696 * DOC: sched_policy (int)
697 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
698 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
699 * assigns queues to HQDs.
700 */
701 int sched_policy = KFD_SCHED_POLICY_HWS;
702 module_param(sched_policy, int, 0444);
703 MODULE_PARM_DESC(sched_policy,
704 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
705
706 /**
707 * DOC: hws_max_conc_proc (int)
708 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
709 * number of VMIDs assigned to the HWS, which is also the default.
710 */
711 int hws_max_conc_proc = -1;
712 module_param(hws_max_conc_proc, int, 0444);
713 MODULE_PARM_DESC(hws_max_conc_proc,
714 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
715
716 /**
717 * DOC: cwsr_enable (int)
718 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
719 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
720 * disables it.
721 */
722 int cwsr_enable = 1;
723 module_param(cwsr_enable, int, 0444);
724 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
725
726 /**
727 * DOC: max_num_of_queues_per_device (int)
728 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
729 * is 4096.
730 */
731 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
732 module_param(max_num_of_queues_per_device, int, 0444);
733 MODULE_PARM_DESC(max_num_of_queues_per_device,
734 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
735
736 /**
737 * DOC: send_sigterm (int)
738 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
739 * but just print errors on dmesg. Setting 1 enables sending sigterm.
740 */
741 int send_sigterm;
742 module_param(send_sigterm, int, 0444);
743 MODULE_PARM_DESC(send_sigterm,
744 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
745
746 /**
747 * DOC: debug_largebar (int)
748 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
749 * system. This limits the VRAM size reported to ROCm applications to the visible
750 * size, usually 256MB.
751 * Default value is 0, diabled.
752 */
753 int debug_largebar;
754 module_param(debug_largebar, int, 0444);
755 MODULE_PARM_DESC(debug_largebar,
756 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
757
758 /**
759 * DOC: halt_if_hws_hang (int)
760 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
761 * Setting 1 enables halt on hang.
762 */
763 int halt_if_hws_hang;
764 module_param(halt_if_hws_hang, int, 0644);
765 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
766
767 /**
768 * DOC: hws_gws_support(bool)
769 * Assume that HWS supports GWS barriers regardless of what firmware version
770 * check says. Default value: false (rely on MEC2 firmware version check).
771 */
772 bool hws_gws_support;
773 module_param(hws_gws_support, bool, 0444);
774 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
775
776 /**
777 * DOC: queue_preemption_timeout_ms (int)
778 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
779 */
780 int queue_preemption_timeout_ms = 9000;
781 module_param(queue_preemption_timeout_ms, int, 0644);
782 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
783
784 /**
785 * DOC: debug_evictions(bool)
786 * Enable extra debug messages to help determine the cause of evictions
787 */
788 bool debug_evictions;
789 module_param(debug_evictions, bool, 0644);
790 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
791
792 /**
793 * DOC: no_system_mem_limit(bool)
794 * Disable system memory limit, to support multiple process shared memory
795 */
796 bool no_system_mem_limit;
797 module_param(no_system_mem_limit, bool, 0644);
798 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
799
800 /**
801 * DOC: no_queue_eviction_on_vm_fault (int)
802 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
803 */
804 int amdgpu_no_queue_eviction_on_vm_fault;
805 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
806 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
807 #endif
808
809 /**
810 * DOC: mtype_local (int)
811 */
812 int amdgpu_mtype_local;
813 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
814 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);
815
816 /**
817 * DOC: pcie_p2p (bool)
818 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
819 */
820 #ifdef CONFIG_HSA_AMD_P2P
821 bool pcie_p2p = true;
822 module_param(pcie_p2p, bool, 0444);
823 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
824 #endif
825
826 /**
827 * DOC: dcfeaturemask (uint)
828 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
829 * The default is the current set of stable display features.
830 */
831 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
832 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
833
834 /**
835 * DOC: dcdebugmask (uint)
836 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
837 */
838 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
839 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
840
841 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
842 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
843
844 /**
845 * DOC: abmlevel (uint)
846 * Override the default ABM (Adaptive Backlight Management) level used for DC
847 * enabled hardware. Requires DMCU to be supported and loaded.
848 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
849 * default. Values 1-4 control the maximum allowable brightness reduction via
850 * the ABM algorithm, with 1 being the least reduction and 4 being the most
851 * reduction.
852 *
853 * Defaults to 0, or disabled. Userspace can still override this level later
854 * after boot.
855 */
856 uint amdgpu_dm_abm_level;
857 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
858 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
859
860 int amdgpu_backlight = -1;
861 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
862 module_param_named(backlight, amdgpu_backlight, bint, 0444);
863
864 /**
865 * DOC: tmz (int)
866 * Trusted Memory Zone (TMZ) is a method to protect data being written
867 * to or read from memory.
868 *
869 * The default value: 0 (off). TODO: change to auto till it is completed.
870 */
871 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
872 module_param_named(tmz, amdgpu_tmz, int, 0444);
873
874 /**
875 * DOC: reset_method (int)
876 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
877 */
878 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
879 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
880
881 /**
882 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
883 * threshold value of faulty pages detected by RAS ECC, which may
884 * result in the GPU entering bad status when the number of total
885 * faulty pages by ECC exceeds the threshold value.
886 */
887 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
888 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
889
890 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
891 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
892
893 /**
894 * DOC: vcnfw_log (int)
895 * Enable vcnfw log output for debugging, the default is disabled.
896 */
897 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
898 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
899
900 /**
901 * DOC: sg_display (int)
902 * Disable S/G (scatter/gather) display (i.e., display from system memory).
903 * This option is only relevant on APUs. Set this option to 0 to disable
904 * S/G display if you experience flickering or other issues under memory
905 * pressure and report the issue.
906 */
907 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
908 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
909
910 /**
911 * DOC: smu_pptable_id (int)
912 * Used to override pptable id. id = 0 use VBIOS pptable.
913 * id > 0 use the soft pptable with specicfied id.
914 */
915 MODULE_PARM_DESC(smu_pptable_id,
916 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
917 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
918
919 /**
920 * DOC: partition_mode (int)
921 * Used to override the default SPX mode.
922 */
923 MODULE_PARM_DESC(
924 user_partt_mode,
925 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
926 0 = AMDGPU_SPX_PARTITION_MODE, \
927 1 = AMDGPU_DPX_PARTITION_MODE, \
928 2 = AMDGPU_TPX_PARTITION_MODE, \
929 3 = AMDGPU_QPX_PARTITION_MODE, \
930 4 = AMDGPU_CPX_PARTITION_MODE)");
931 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
932
933
934 /**
935 * DOC: enforce_isolation (bool)
936 * enforce process isolation between graphics and compute via using the same reserved vmid.
937 */
938 module_param(enforce_isolation, bool, 0444);
939 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on");
940
941 /* These devices are not supported by amdgpu.
942 * They are supported by the mach64, r128, radeon drivers
943 */
944 static const u16 amdgpu_unsupported_pciidlist[] = {
945 /* mach64 */
946 0x4354,
947 0x4358,
948 0x4554,
949 0x4742,
950 0x4744,
951 0x4749,
952 0x474C,
953 0x474D,
954 0x474E,
955 0x474F,
956 0x4750,
957 0x4751,
958 0x4752,
959 0x4753,
960 0x4754,
961 0x4755,
962 0x4756,
963 0x4757,
964 0x4758,
965 0x4759,
966 0x475A,
967 0x4C42,
968 0x4C44,
969 0x4C47,
970 0x4C49,
971 0x4C4D,
972 0x4C4E,
973 0x4C50,
974 0x4C51,
975 0x4C52,
976 0x4C53,
977 0x5654,
978 0x5655,
979 0x5656,
980 /* r128 */
981 0x4c45,
982 0x4c46,
983 0x4d46,
984 0x4d4c,
985 0x5041,
986 0x5042,
987 0x5043,
988 0x5044,
989 0x5045,
990 0x5046,
991 0x5047,
992 0x5048,
993 0x5049,
994 0x504A,
995 0x504B,
996 0x504C,
997 0x504D,
998 0x504E,
999 0x504F,
1000 0x5050,
1001 0x5051,
1002 0x5052,
1003 0x5053,
1004 0x5054,
1005 0x5055,
1006 0x5056,
1007 0x5057,
1008 0x5058,
1009 0x5245,
1010 0x5246,
1011 0x5247,
1012 0x524b,
1013 0x524c,
1014 0x534d,
1015 0x5446,
1016 0x544C,
1017 0x5452,
1018 /* radeon */
1019 0x3150,
1020 0x3151,
1021 0x3152,
1022 0x3154,
1023 0x3155,
1024 0x3E50,
1025 0x3E54,
1026 0x4136,
1027 0x4137,
1028 0x4144,
1029 0x4145,
1030 0x4146,
1031 0x4147,
1032 0x4148,
1033 0x4149,
1034 0x414A,
1035 0x414B,
1036 0x4150,
1037 0x4151,
1038 0x4152,
1039 0x4153,
1040 0x4154,
1041 0x4155,
1042 0x4156,
1043 0x4237,
1044 0x4242,
1045 0x4336,
1046 0x4337,
1047 0x4437,
1048 0x4966,
1049 0x4967,
1050 0x4A48,
1051 0x4A49,
1052 0x4A4A,
1053 0x4A4B,
1054 0x4A4C,
1055 0x4A4D,
1056 0x4A4E,
1057 0x4A4F,
1058 0x4A50,
1059 0x4A54,
1060 0x4B48,
1061 0x4B49,
1062 0x4B4A,
1063 0x4B4B,
1064 0x4B4C,
1065 0x4C57,
1066 0x4C58,
1067 0x4C59,
1068 0x4C5A,
1069 0x4C64,
1070 0x4C66,
1071 0x4C67,
1072 0x4E44,
1073 0x4E45,
1074 0x4E46,
1075 0x4E47,
1076 0x4E48,
1077 0x4E49,
1078 0x4E4A,
1079 0x4E4B,
1080 0x4E50,
1081 0x4E51,
1082 0x4E52,
1083 0x4E53,
1084 0x4E54,
1085 0x4E56,
1086 0x5144,
1087 0x5145,
1088 0x5146,
1089 0x5147,
1090 0x5148,
1091 0x514C,
1092 0x514D,
1093 0x5157,
1094 0x5158,
1095 0x5159,
1096 0x515A,
1097 0x515E,
1098 0x5460,
1099 0x5462,
1100 0x5464,
1101 0x5548,
1102 0x5549,
1103 0x554A,
1104 0x554B,
1105 0x554C,
1106 0x554D,
1107 0x554E,
1108 0x554F,
1109 0x5550,
1110 0x5551,
1111 0x5552,
1112 0x5554,
1113 0x564A,
1114 0x564B,
1115 0x564F,
1116 0x5652,
1117 0x5653,
1118 0x5657,
1119 0x5834,
1120 0x5835,
1121 0x5954,
1122 0x5955,
1123 0x5974,
1124 0x5975,
1125 0x5960,
1126 0x5961,
1127 0x5962,
1128 0x5964,
1129 0x5965,
1130 0x5969,
1131 0x5a41,
1132 0x5a42,
1133 0x5a61,
1134 0x5a62,
1135 0x5b60,
1136 0x5b62,
1137 0x5b63,
1138 0x5b64,
1139 0x5b65,
1140 0x5c61,
1141 0x5c63,
1142 0x5d48,
1143 0x5d49,
1144 0x5d4a,
1145 0x5d4c,
1146 0x5d4d,
1147 0x5d4e,
1148 0x5d4f,
1149 0x5d50,
1150 0x5d52,
1151 0x5d57,
1152 0x5e48,
1153 0x5e4a,
1154 0x5e4b,
1155 0x5e4c,
1156 0x5e4d,
1157 0x5e4f,
1158 0x6700,
1159 0x6701,
1160 0x6702,
1161 0x6703,
1162 0x6704,
1163 0x6705,
1164 0x6706,
1165 0x6707,
1166 0x6708,
1167 0x6709,
1168 0x6718,
1169 0x6719,
1170 0x671c,
1171 0x671d,
1172 0x671f,
1173 0x6720,
1174 0x6721,
1175 0x6722,
1176 0x6723,
1177 0x6724,
1178 0x6725,
1179 0x6726,
1180 0x6727,
1181 0x6728,
1182 0x6729,
1183 0x6738,
1184 0x6739,
1185 0x673e,
1186 0x6740,
1187 0x6741,
1188 0x6742,
1189 0x6743,
1190 0x6744,
1191 0x6745,
1192 0x6746,
1193 0x6747,
1194 0x6748,
1195 0x6749,
1196 0x674A,
1197 0x6750,
1198 0x6751,
1199 0x6758,
1200 0x6759,
1201 0x675B,
1202 0x675D,
1203 0x675F,
1204 0x6760,
1205 0x6761,
1206 0x6762,
1207 0x6763,
1208 0x6764,
1209 0x6765,
1210 0x6766,
1211 0x6767,
1212 0x6768,
1213 0x6770,
1214 0x6771,
1215 0x6772,
1216 0x6778,
1217 0x6779,
1218 0x677B,
1219 0x6840,
1220 0x6841,
1221 0x6842,
1222 0x6843,
1223 0x6849,
1224 0x684C,
1225 0x6850,
1226 0x6858,
1227 0x6859,
1228 0x6880,
1229 0x6888,
1230 0x6889,
1231 0x688A,
1232 0x688C,
1233 0x688D,
1234 0x6898,
1235 0x6899,
1236 0x689b,
1237 0x689c,
1238 0x689d,
1239 0x689e,
1240 0x68a0,
1241 0x68a1,
1242 0x68a8,
1243 0x68a9,
1244 0x68b0,
1245 0x68b8,
1246 0x68b9,
1247 0x68ba,
1248 0x68be,
1249 0x68bf,
1250 0x68c0,
1251 0x68c1,
1252 0x68c7,
1253 0x68c8,
1254 0x68c9,
1255 0x68d8,
1256 0x68d9,
1257 0x68da,
1258 0x68de,
1259 0x68e0,
1260 0x68e1,
1261 0x68e4,
1262 0x68e5,
1263 0x68e8,
1264 0x68e9,
1265 0x68f1,
1266 0x68f2,
1267 0x68f8,
1268 0x68f9,
1269 0x68fa,
1270 0x68fe,
1271 0x7100,
1272 0x7101,
1273 0x7102,
1274 0x7103,
1275 0x7104,
1276 0x7105,
1277 0x7106,
1278 0x7108,
1279 0x7109,
1280 0x710A,
1281 0x710B,
1282 0x710C,
1283 0x710E,
1284 0x710F,
1285 0x7140,
1286 0x7141,
1287 0x7142,
1288 0x7143,
1289 0x7144,
1290 0x7145,
1291 0x7146,
1292 0x7147,
1293 0x7149,
1294 0x714A,
1295 0x714B,
1296 0x714C,
1297 0x714D,
1298 0x714E,
1299 0x714F,
1300 0x7151,
1301 0x7152,
1302 0x7153,
1303 0x715E,
1304 0x715F,
1305 0x7180,
1306 0x7181,
1307 0x7183,
1308 0x7186,
1309 0x7187,
1310 0x7188,
1311 0x718A,
1312 0x718B,
1313 0x718C,
1314 0x718D,
1315 0x718F,
1316 0x7193,
1317 0x7196,
1318 0x719B,
1319 0x719F,
1320 0x71C0,
1321 0x71C1,
1322 0x71C2,
1323 0x71C3,
1324 0x71C4,
1325 0x71C5,
1326 0x71C6,
1327 0x71C7,
1328 0x71CD,
1329 0x71CE,
1330 0x71D2,
1331 0x71D4,
1332 0x71D5,
1333 0x71D6,
1334 0x71DA,
1335 0x71DE,
1336 0x7200,
1337 0x7210,
1338 0x7211,
1339 0x7240,
1340 0x7243,
1341 0x7244,
1342 0x7245,
1343 0x7246,
1344 0x7247,
1345 0x7248,
1346 0x7249,
1347 0x724A,
1348 0x724B,
1349 0x724C,
1350 0x724D,
1351 0x724E,
1352 0x724F,
1353 0x7280,
1354 0x7281,
1355 0x7283,
1356 0x7284,
1357 0x7287,
1358 0x7288,
1359 0x7289,
1360 0x728B,
1361 0x728C,
1362 0x7290,
1363 0x7291,
1364 0x7293,
1365 0x7297,
1366 0x7834,
1367 0x7835,
1368 0x791e,
1369 0x791f,
1370 0x793f,
1371 0x7941,
1372 0x7942,
1373 0x796c,
1374 0x796d,
1375 0x796e,
1376 0x796f,
1377 0x9400,
1378 0x9401,
1379 0x9402,
1380 0x9403,
1381 0x9405,
1382 0x940A,
1383 0x940B,
1384 0x940F,
1385 0x94A0,
1386 0x94A1,
1387 0x94A3,
1388 0x94B1,
1389 0x94B3,
1390 0x94B4,
1391 0x94B5,
1392 0x94B9,
1393 0x9440,
1394 0x9441,
1395 0x9442,
1396 0x9443,
1397 0x9444,
1398 0x9446,
1399 0x944A,
1400 0x944B,
1401 0x944C,
1402 0x944E,
1403 0x9450,
1404 0x9452,
1405 0x9456,
1406 0x945A,
1407 0x945B,
1408 0x945E,
1409 0x9460,
1410 0x9462,
1411 0x946A,
1412 0x946B,
1413 0x947A,
1414 0x947B,
1415 0x9480,
1416 0x9487,
1417 0x9488,
1418 0x9489,
1419 0x948A,
1420 0x948F,
1421 0x9490,
1422 0x9491,
1423 0x9495,
1424 0x9498,
1425 0x949C,
1426 0x949E,
1427 0x949F,
1428 0x94C0,
1429 0x94C1,
1430 0x94C3,
1431 0x94C4,
1432 0x94C5,
1433 0x94C6,
1434 0x94C7,
1435 0x94C8,
1436 0x94C9,
1437 0x94CB,
1438 0x94CC,
1439 0x94CD,
1440 0x9500,
1441 0x9501,
1442 0x9504,
1443 0x9505,
1444 0x9506,
1445 0x9507,
1446 0x9508,
1447 0x9509,
1448 0x950F,
1449 0x9511,
1450 0x9515,
1451 0x9517,
1452 0x9519,
1453 0x9540,
1454 0x9541,
1455 0x9542,
1456 0x954E,
1457 0x954F,
1458 0x9552,
1459 0x9553,
1460 0x9555,
1461 0x9557,
1462 0x955f,
1463 0x9580,
1464 0x9581,
1465 0x9583,
1466 0x9586,
1467 0x9587,
1468 0x9588,
1469 0x9589,
1470 0x958A,
1471 0x958B,
1472 0x958C,
1473 0x958D,
1474 0x958E,
1475 0x958F,
1476 0x9590,
1477 0x9591,
1478 0x9593,
1479 0x9595,
1480 0x9596,
1481 0x9597,
1482 0x9598,
1483 0x9599,
1484 0x959B,
1485 0x95C0,
1486 0x95C2,
1487 0x95C4,
1488 0x95C5,
1489 0x95C6,
1490 0x95C7,
1491 0x95C9,
1492 0x95CC,
1493 0x95CD,
1494 0x95CE,
1495 0x95CF,
1496 0x9610,
1497 0x9611,
1498 0x9612,
1499 0x9613,
1500 0x9614,
1501 0x9615,
1502 0x9616,
1503 0x9640,
1504 0x9641,
1505 0x9642,
1506 0x9643,
1507 0x9644,
1508 0x9645,
1509 0x9647,
1510 0x9648,
1511 0x9649,
1512 0x964a,
1513 0x964b,
1514 0x964c,
1515 0x964e,
1516 0x964f,
1517 0x9710,
1518 0x9711,
1519 0x9712,
1520 0x9713,
1521 0x9714,
1522 0x9715,
1523 0x9802,
1524 0x9803,
1525 0x9804,
1526 0x9805,
1527 0x9806,
1528 0x9807,
1529 0x9808,
1530 0x9809,
1531 0x980A,
1532 0x9900,
1533 0x9901,
1534 0x9903,
1535 0x9904,
1536 0x9905,
1537 0x9906,
1538 0x9907,
1539 0x9908,
1540 0x9909,
1541 0x990A,
1542 0x990B,
1543 0x990C,
1544 0x990D,
1545 0x990E,
1546 0x990F,
1547 0x9910,
1548 0x9913,
1549 0x9917,
1550 0x9918,
1551 0x9919,
1552 0x9990,
1553 0x9991,
1554 0x9992,
1555 0x9993,
1556 0x9994,
1557 0x9995,
1558 0x9996,
1559 0x9997,
1560 0x9998,
1561 0x9999,
1562 0x999A,
1563 0x999B,
1564 0x999C,
1565 0x999D,
1566 0x99A0,
1567 0x99A2,
1568 0x99A4,
1569 /* radeon secondary ids */
1570 0x3171,
1571 0x3e70,
1572 0x4164,
1573 0x4165,
1574 0x4166,
1575 0x4168,
1576 0x4170,
1577 0x4171,
1578 0x4172,
1579 0x4173,
1580 0x496e,
1581 0x4a69,
1582 0x4a6a,
1583 0x4a6b,
1584 0x4a70,
1585 0x4a74,
1586 0x4b69,
1587 0x4b6b,
1588 0x4b6c,
1589 0x4c6e,
1590 0x4e64,
1591 0x4e65,
1592 0x4e66,
1593 0x4e67,
1594 0x4e68,
1595 0x4e69,
1596 0x4e6a,
1597 0x4e71,
1598 0x4f73,
1599 0x5569,
1600 0x556b,
1601 0x556d,
1602 0x556f,
1603 0x5571,
1604 0x5854,
1605 0x5874,
1606 0x5940,
1607 0x5941,
1608 0x5b70,
1609 0x5b72,
1610 0x5b73,
1611 0x5b74,
1612 0x5b75,
1613 0x5d44,
1614 0x5d45,
1615 0x5d6d,
1616 0x5d6f,
1617 0x5d72,
1618 0x5d77,
1619 0x5e6b,
1620 0x5e6d,
1621 0x7120,
1622 0x7124,
1623 0x7129,
1624 0x712e,
1625 0x712f,
1626 0x7162,
1627 0x7163,
1628 0x7166,
1629 0x7167,
1630 0x7172,
1631 0x7173,
1632 0x71a0,
1633 0x71a1,
1634 0x71a3,
1635 0x71a7,
1636 0x71bb,
1637 0x71e0,
1638 0x71e1,
1639 0x71e2,
1640 0x71e6,
1641 0x71e7,
1642 0x71f2,
1643 0x7269,
1644 0x726b,
1645 0x726e,
1646 0x72a0,
1647 0x72a8,
1648 0x72b1,
1649 0x72b3,
1650 0x793f,
1651 };
1652
1653 static const struct pci_device_id pciidlist[] = {
1654 #ifdef CONFIG_DRM_AMDGPU_SI
1655 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1656 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1657 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1658 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1659 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1660 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1661 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1662 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1663 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1664 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1665 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1666 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1667 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1668 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1669 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1670 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1671 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1672 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1673 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1674 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1675 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1676 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1677 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1678 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1679 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1680 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1681 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1682 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1683 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1684 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1685 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1686 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1687 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1688 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1689 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1690 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1691 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1692 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1693 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1694 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1695 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1696 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1697 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1698 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1699 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1700 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1701 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1702 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1703 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1704 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1705 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1706 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1707 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1708 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1709 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1710 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1711 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1712 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1713 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1714 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1715 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1716 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1717 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1718 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1719 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1720 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1721 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1722 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1723 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1724 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1725 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1726 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1727 #endif
1728 #ifdef CONFIG_DRM_AMDGPU_CIK
1729 /* Kaveri */
1730 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1731 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1732 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1733 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1734 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1735 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1736 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1737 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1738 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1739 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1740 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1741 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1742 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1743 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1744 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1745 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1746 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1747 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1748 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1749 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1750 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1751 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1752 /* Bonaire */
1753 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1754 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1755 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1756 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1757 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1758 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1759 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1760 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1761 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1762 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1763 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1764 /* Hawaii */
1765 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1766 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1767 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1768 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1769 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1770 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1771 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1772 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1773 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1774 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1775 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1776 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1777 /* Kabini */
1778 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1779 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1780 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1781 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1782 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1783 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1784 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1785 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1786 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1787 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1788 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1789 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1790 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1791 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1792 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1793 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1794 /* mullins */
1795 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1796 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1797 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1798 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1799 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1800 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1801 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1802 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1803 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1804 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1805 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1806 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1807 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1808 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1809 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1810 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1811 #endif
1812 /* topaz */
1813 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1814 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1815 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1816 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1817 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1818 /* tonga */
1819 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1820 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1821 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1822 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1823 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1824 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1825 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1826 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1827 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1828 /* fiji */
1829 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1830 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1831 /* carrizo */
1832 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1833 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1834 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1835 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1836 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1837 /* stoney */
1838 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1839 /* Polaris11 */
1840 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1841 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1842 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1843 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1844 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1845 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1846 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1847 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1848 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1849 /* Polaris10 */
1850 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1851 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1852 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1853 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1854 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1855 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1856 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1857 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1858 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1859 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1860 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1861 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1862 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1863 /* Polaris12 */
1864 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1865 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1866 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1867 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1868 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1869 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1870 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1871 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1872 /* VEGAM */
1873 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1874 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1875 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1876 /* Vega 10 */
1877 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1878 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1879 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1880 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1881 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1882 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1883 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1884 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1885 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1886 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1887 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1888 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1889 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1890 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1891 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1892 /* Vega 12 */
1893 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1894 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1895 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1896 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1897 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1898 /* Vega 20 */
1899 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1900 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1901 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1902 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1903 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1904 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1905 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1906 /* Raven */
1907 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1908 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1909 /* Arcturus */
1910 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1911 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1912 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1913 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1914 /* Navi10 */
1915 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1916 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1917 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1918 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1919 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1920 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1921 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1922 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1923 /* Navi14 */
1924 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1925 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1926 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1927 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1928
1929 /* Renoir */
1930 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1931 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1932 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1933 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1934
1935 /* Navi12 */
1936 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1937 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1938
1939 /* Sienna_Cichlid */
1940 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1941 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1942 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1943 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1944 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1945 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1946 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1947 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1948 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1949 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1950 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1951 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1952 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1953
1954 /* Yellow Carp */
1955 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1956 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1957
1958 /* Navy_Flounder */
1959 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1960 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1961 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1962 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1963 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1964 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1965 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1966 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1967 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1968
1969 /* DIMGREY_CAVEFISH */
1970 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1971 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1972 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1973 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1974 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1975 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1976 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1977 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1978 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1979 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1980 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1981 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1982
1983 /* Aldebaran */
1984 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1985 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1986 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1987 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1988
1989 /* CYAN_SKILLFISH */
1990 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1991 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1992
1993 /* BEIGE_GOBY */
1994 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1995 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1996 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1997 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1998 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1999 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2000
2001 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2002 .class = PCI_CLASS_DISPLAY_VGA << 8,
2003 .class_mask = 0xffffff,
2004 .driver_data = CHIP_IP_DISCOVERY },
2005
2006 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2007 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2008 .class_mask = 0xffffff,
2009 .driver_data = CHIP_IP_DISCOVERY },
2010
2011 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2012 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
2013 .class_mask = 0xffffff,
2014 .driver_data = CHIP_IP_DISCOVERY },
2015
2016 {0, 0, 0}
2017 };
2018
2019 MODULE_DEVICE_TABLE(pci, pciidlist);
2020
2021 static const struct drm_driver amdgpu_kms_driver;
2022
amdgpu_get_secondary_funcs(struct amdgpu_device * adev)2023 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2024 {
2025 STUB();
2026 #ifdef notyet
2027 struct pci_dev *p = NULL;
2028 int i;
2029
2030 /* 0 - GPU
2031 * 1 - audio
2032 * 2 - USB
2033 * 3 - UCSI
2034 */
2035 for (i = 1; i < 4; i++) {
2036 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2037 adev->pdev->bus->number, i);
2038 if (p) {
2039 pm_runtime_get_sync(&p->dev);
2040 pm_runtime_mark_last_busy(&p->dev);
2041 pm_runtime_put_autosuspend(&p->dev);
2042 pci_dev_put(p);
2043 }
2044 }
2045 #endif
2046 }
2047
2048 #ifdef notyet
amdgpu_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2049 static int amdgpu_pci_probe(struct pci_dev *pdev,
2050 const struct pci_device_id *ent)
2051 {
2052 struct drm_device *ddev;
2053 struct amdgpu_device *adev;
2054 unsigned long flags = ent->driver_data;
2055 int ret, retry = 0, i;
2056 bool supports_atomic = false;
2057
2058 /* skip devices which are owned by radeon */
2059 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2060 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2061 return -ENODEV;
2062 }
2063
2064 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2065 amdgpu_aspm = 0;
2066
2067 if (amdgpu_virtual_display ||
2068 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2069 supports_atomic = true;
2070
2071 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2072 DRM_INFO("This hardware requires experimental hardware support.\n"
2073 "See modparam exp_hw_support\n");
2074 return -ENODEV;
2075 }
2076 /* differentiate between P10 and P11 asics with the same DID */
2077 if (pdev->device == 0x67FF &&
2078 (pdev->revision == 0xE3 ||
2079 pdev->revision == 0xE7 ||
2080 pdev->revision == 0xF3 ||
2081 pdev->revision == 0xF7)) {
2082 flags &= ~AMD_ASIC_MASK;
2083 flags |= CHIP_POLARIS10;
2084 }
2085
2086 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2087 * however, SME requires an indirect IOMMU mapping because the encryption
2088 * bit is beyond the DMA mask of the chip.
2089 */
2090 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2091 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2092 dev_info(&pdev->dev,
2093 "SME is not compatible with RAVEN\n");
2094 return -ENOTSUPP;
2095 }
2096
2097 #ifdef CONFIG_DRM_AMDGPU_SI
2098 if (!amdgpu_si_support) {
2099 switch (flags & AMD_ASIC_MASK) {
2100 case CHIP_TAHITI:
2101 case CHIP_PITCAIRN:
2102 case CHIP_VERDE:
2103 case CHIP_OLAND:
2104 case CHIP_HAINAN:
2105 dev_info(&pdev->dev,
2106 "SI support provided by radeon.\n");
2107 dev_info(&pdev->dev,
2108 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2109 );
2110 return -ENODEV;
2111 }
2112 }
2113 #endif
2114 #ifdef CONFIG_DRM_AMDGPU_CIK
2115 if (!amdgpu_cik_support) {
2116 switch (flags & AMD_ASIC_MASK) {
2117 case CHIP_KAVERI:
2118 case CHIP_BONAIRE:
2119 case CHIP_HAWAII:
2120 case CHIP_KABINI:
2121 case CHIP_MULLINS:
2122 dev_info(&pdev->dev,
2123 "CIK support provided by radeon.\n");
2124 dev_info(&pdev->dev,
2125 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2126 );
2127 return -ENODEV;
2128 }
2129 }
2130 #endif
2131
2132 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2133 if (IS_ERR(adev))
2134 return PTR_ERR(adev);
2135
2136 adev->dev = &pdev->dev;
2137 adev->pdev = pdev;
2138 ddev = adev_to_drm(adev);
2139
2140 if (!supports_atomic)
2141 ddev->driver_features &= ~DRIVER_ATOMIC;
2142
2143 ret = pci_enable_device(pdev);
2144 if (ret)
2145 return ret;
2146
2147 pci_set_drvdata(pdev, ddev);
2148
2149 ret = amdgpu_driver_load_kms(adev, flags);
2150 if (ret)
2151 goto err_pci;
2152
2153 retry_init:
2154 ret = drm_dev_register(ddev, flags);
2155 if (ret == -EAGAIN && ++retry <= 3) {
2156 DRM_INFO("retry init %d\n", retry);
2157 /* Don't request EX mode too frequently which is attacking */
2158 drm_msleep(5000);
2159 goto retry_init;
2160 } else if (ret) {
2161 goto err_pci;
2162 }
2163
2164 ret = amdgpu_xcp_dev_register(adev, ent);
2165 if (ret)
2166 goto err_pci;
2167
2168 /*
2169 * 1. don't init fbdev on hw without DCE
2170 * 2. don't init fbdev if there are no connectors
2171 */
2172 if (adev->mode_info.mode_config_initialized &&
2173 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2174 /* select 8 bpp console on low vram cards */
2175 if (adev->gmc.real_vram_size <= (32*1024*1024))
2176 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2177 else
2178 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2179 }
2180
2181 ret = amdgpu_debugfs_init(adev);
2182 if (ret)
2183 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2184
2185 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2186 /* only need to skip on ATPX */
2187 if (amdgpu_device_supports_px(ddev))
2188 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2189 /* we want direct complete for BOCO */
2190 if (amdgpu_device_supports_boco(ddev))
2191 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2192 DPM_FLAG_SMART_SUSPEND |
2193 DPM_FLAG_MAY_SKIP_RESUME);
2194 pm_runtime_use_autosuspend(ddev->dev);
2195 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2196
2197 pm_runtime_allow(ddev->dev);
2198
2199 pm_runtime_mark_last_busy(ddev->dev);
2200 pm_runtime_put_autosuspend(ddev->dev);
2201
2202 pci_wake_from_d3(pdev, TRUE);
2203
2204 /*
2205 * For runpm implemented via BACO, PMFW will handle the
2206 * timing for BACO in and out:
2207 * - put ASIC into BACO state only when both video and
2208 * audio functions are in D3 state.
2209 * - pull ASIC out of BACO state when either video or
2210 * audio function is in D0 state.
2211 * Also, at startup, PMFW assumes both functions are in
2212 * D0 state.
2213 *
2214 * So if snd driver was loaded prior to amdgpu driver
2215 * and audio function was put into D3 state, there will
2216 * be no PMFW-aware D-state transition(D0->D3) on runpm
2217 * suspend. Thus the BACO will be not correctly kicked in.
2218 *
2219 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2220 * into D0 state. Then there will be a PMFW-aware D-state
2221 * transition(D0->D3) on runpm suspend.
2222 */
2223 if (amdgpu_device_supports_baco(ddev) &&
2224 !(adev->flags & AMD_IS_APU) &&
2225 (adev->asic_type >= CHIP_NAVI10))
2226 amdgpu_get_secondary_funcs(adev);
2227 }
2228
2229 return 0;
2230
2231 err_pci:
2232 pci_disable_device(pdev);
2233 return ret;
2234 }
2235
2236 static void
amdgpu_pci_remove(struct pci_dev * pdev)2237 amdgpu_pci_remove(struct pci_dev *pdev)
2238 {
2239 struct drm_device *dev = pci_get_drvdata(pdev);
2240 struct amdgpu_device *adev = drm_to_adev(dev);
2241
2242 amdgpu_xcp_dev_unplug(adev);
2243 drm_dev_unplug(dev);
2244
2245 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2246 pm_runtime_get_sync(dev->dev);
2247 pm_runtime_forbid(dev->dev);
2248 }
2249
2250 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2251 !amdgpu_sriov_vf(adev)) {
2252 bool need_to_reset_gpu = false;
2253
2254 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2255 struct amdgpu_hive_info *hive;
2256
2257 hive = amdgpu_get_xgmi_hive(adev);
2258 if (hive->device_remove_count == 0)
2259 need_to_reset_gpu = true;
2260 hive->device_remove_count++;
2261 amdgpu_put_xgmi_hive(hive);
2262 } else {
2263 need_to_reset_gpu = true;
2264 }
2265
2266 /* Workaround for ASICs need to reset SMU.
2267 * Called only when the first device is removed.
2268 */
2269 if (need_to_reset_gpu) {
2270 struct amdgpu_reset_context reset_context;
2271
2272 adev->shutdown = true;
2273 memset(&reset_context, 0, sizeof(reset_context));
2274 reset_context.method = AMD_RESET_METHOD_NONE;
2275 reset_context.reset_req_dev = adev;
2276 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2277 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2278 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2279 }
2280 }
2281
2282 amdgpu_driver_unload_kms(dev);
2283
2284 /*
2285 * Flush any in flight DMA operations from device.
2286 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2287 * StatusTransactions Pending bit.
2288 */
2289 pci_disable_device(pdev);
2290 pci_wait_for_pending_transaction(pdev);
2291 }
2292
2293 static void
amdgpu_pci_shutdown(struct pci_dev * pdev)2294 amdgpu_pci_shutdown(struct pci_dev *pdev)
2295 {
2296 struct drm_device *dev = pci_get_drvdata(pdev);
2297 struct amdgpu_device *adev = drm_to_adev(dev);
2298
2299 if (amdgpu_ras_intr_triggered())
2300 return;
2301
2302 /* if we are running in a VM, make sure the device
2303 * torn down properly on reboot/shutdown.
2304 * unfortunately we can't detect certain
2305 * hypervisors so just do this all the time.
2306 */
2307 if (!amdgpu_passthrough(adev))
2308 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2309 amdgpu_device_ip_suspend(adev);
2310 adev->mp1_state = PP_MP1_STATE_NONE;
2311 }
2312 #endif
2313
2314 /**
2315 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2316 *
2317 * @work: work_struct.
2318 */
amdgpu_drv_delayed_reset_work_handler(struct work_struct * work)2319 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2320 {
2321 struct list_head device_list;
2322 struct amdgpu_device *adev;
2323 int i, r;
2324 struct amdgpu_reset_context reset_context;
2325
2326 memset(&reset_context, 0, sizeof(reset_context));
2327
2328 mutex_lock(&mgpu_info.mutex);
2329 if (mgpu_info.pending_reset == true) {
2330 mutex_unlock(&mgpu_info.mutex);
2331 return;
2332 }
2333 mgpu_info.pending_reset = true;
2334 mutex_unlock(&mgpu_info.mutex);
2335
2336 /* Use a common context, just need to make sure full reset is done */
2337 reset_context.method = AMD_RESET_METHOD_NONE;
2338 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2339
2340 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2341 adev = mgpu_info.gpu_ins[i].adev;
2342 reset_context.reset_req_dev = adev;
2343 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2344 if (r) {
2345 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2346 r, adev_to_drm(adev)->unique);
2347 }
2348 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2349 r = -EALREADY;
2350 }
2351 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2352 adev = mgpu_info.gpu_ins[i].adev;
2353 flush_work(&adev->xgmi_reset_work);
2354 adev->gmc.xgmi.pending_reset = false;
2355 }
2356
2357 /* reset function will rebuild the xgmi hive info , clear it now */
2358 for (i = 0; i < mgpu_info.num_dgpu; i++)
2359 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2360
2361 INIT_LIST_HEAD(&device_list);
2362
2363 for (i = 0; i < mgpu_info.num_dgpu; i++)
2364 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2365
2366 /* unregister the GPU first, reset function will add them back */
2367 list_for_each_entry(adev, &device_list, reset_list)
2368 amdgpu_unregister_gpu_instance(adev);
2369
2370 /* Use a common context, just need to make sure full reset is done */
2371 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2372 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2373
2374 if (r) {
2375 DRM_ERROR("reinit gpus failure");
2376 return;
2377 }
2378 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2379 adev = mgpu_info.gpu_ins[i].adev;
2380 if (!adev->kfd.init_complete)
2381 amdgpu_amdkfd_device_init(adev);
2382 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2383 }
2384 }
2385
2386 #ifdef notyet
2387
amdgpu_pmops_prepare(struct device * dev)2388 static int amdgpu_pmops_prepare(struct device *dev)
2389 {
2390 struct drm_device *drm_dev = dev_get_drvdata(dev);
2391 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2392
2393 /* Return a positive number here so
2394 * DPM_FLAG_SMART_SUSPEND works properly
2395 */
2396 if (amdgpu_device_supports_boco(drm_dev) &&
2397 pm_runtime_suspended(dev))
2398 return 1;
2399
2400 /* if we will not support s3 or s2i for the device
2401 * then skip suspend
2402 */
2403 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2404 !amdgpu_acpi_is_s3_active(adev))
2405 return 1;
2406
2407 return amdgpu_device_prepare(drm_dev);
2408 }
2409
amdgpu_pmops_complete(struct device * dev)2410 static void amdgpu_pmops_complete(struct device *dev)
2411 {
2412 /* nothing to do */
2413 }
2414
amdgpu_pmops_suspend(struct device * dev)2415 static int amdgpu_pmops_suspend(struct device *dev)
2416 {
2417 struct drm_device *drm_dev = dev_get_drvdata(dev);
2418 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2419
2420 adev->suspend_complete = false;
2421 if (amdgpu_acpi_is_s0ix_active(adev))
2422 adev->in_s0ix = true;
2423 else if (amdgpu_acpi_is_s3_active(adev))
2424 adev->in_s3 = true;
2425 if (!adev->in_s0ix && !adev->in_s3)
2426 return 0;
2427 return amdgpu_device_suspend(drm_dev, true);
2428 }
2429
amdgpu_pmops_suspend_noirq(struct device * dev)2430 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2431 {
2432 struct drm_device *drm_dev = dev_get_drvdata(dev);
2433 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2434
2435 adev->suspend_complete = true;
2436 if (amdgpu_acpi_should_gpu_reset(adev))
2437 return amdgpu_asic_reset(adev);
2438
2439 return 0;
2440 }
2441
amdgpu_pmops_resume(struct device * dev)2442 static int amdgpu_pmops_resume(struct device *dev)
2443 {
2444 struct drm_device *drm_dev = dev_get_drvdata(dev);
2445 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2446 int r;
2447
2448 if (!adev->in_s0ix && !adev->in_s3)
2449 return 0;
2450
2451 /* Avoids registers access if device is physically gone */
2452 if (!pci_device_is_present(adev->pdev))
2453 adev->no_hw_access = true;
2454
2455 r = amdgpu_device_resume(drm_dev, true);
2456 if (amdgpu_acpi_is_s0ix_active(adev))
2457 adev->in_s0ix = false;
2458 else
2459 adev->in_s3 = false;
2460 return r;
2461 }
2462
amdgpu_pmops_freeze(struct device * dev)2463 static int amdgpu_pmops_freeze(struct device *dev)
2464 {
2465 struct drm_device *drm_dev = dev_get_drvdata(dev);
2466 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2467 int r;
2468
2469 adev->in_s4 = true;
2470 r = amdgpu_device_suspend(drm_dev, true);
2471 adev->in_s4 = false;
2472 if (r)
2473 return r;
2474
2475 if (amdgpu_acpi_should_gpu_reset(adev))
2476 return amdgpu_asic_reset(adev);
2477 return 0;
2478 }
2479
amdgpu_pmops_thaw(struct device * dev)2480 static int amdgpu_pmops_thaw(struct device *dev)
2481 {
2482 struct drm_device *drm_dev = dev_get_drvdata(dev);
2483
2484 return amdgpu_device_resume(drm_dev, true);
2485 }
2486
amdgpu_pmops_poweroff(struct device * dev)2487 static int amdgpu_pmops_poweroff(struct device *dev)
2488 {
2489 struct drm_device *drm_dev = dev_get_drvdata(dev);
2490
2491 return amdgpu_device_suspend(drm_dev, true);
2492 }
2493
amdgpu_pmops_restore(struct device * dev)2494 static int amdgpu_pmops_restore(struct device *dev)
2495 {
2496 struct drm_device *drm_dev = dev_get_drvdata(dev);
2497
2498 return amdgpu_device_resume(drm_dev, true);
2499 }
2500
amdgpu_runtime_idle_check_display(struct device * dev)2501 static int amdgpu_runtime_idle_check_display(struct device *dev)
2502 {
2503 struct pci_dev *pdev = to_pci_dev(dev);
2504 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2505 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2506
2507 if (adev->mode_info.num_crtc) {
2508 struct drm_connector *list_connector;
2509 struct drm_connector_list_iter iter;
2510 int ret = 0;
2511
2512 if (amdgpu_runtime_pm != -2) {
2513 /* XXX: Return busy if any displays are connected to avoid
2514 * possible display wakeups after runtime resume due to
2515 * hotplug events in case any displays were connected while
2516 * the GPU was in suspend. Remove this once that is fixed.
2517 */
2518 mutex_lock(&drm_dev->mode_config.mutex);
2519 drm_connector_list_iter_begin(drm_dev, &iter);
2520 drm_for_each_connector_iter(list_connector, &iter) {
2521 if (list_connector->status == connector_status_connected) {
2522 ret = -EBUSY;
2523 break;
2524 }
2525 }
2526 drm_connector_list_iter_end(&iter);
2527 mutex_unlock(&drm_dev->mode_config.mutex);
2528
2529 if (ret)
2530 return ret;
2531 }
2532
2533 if (adev->dc_enabled) {
2534 struct drm_crtc *crtc;
2535
2536 drm_for_each_crtc(crtc, drm_dev) {
2537 drm_modeset_lock(&crtc->mutex, NULL);
2538 if (crtc->state->active)
2539 ret = -EBUSY;
2540 drm_modeset_unlock(&crtc->mutex);
2541 if (ret < 0)
2542 break;
2543 }
2544 } else {
2545 mutex_lock(&drm_dev->mode_config.mutex);
2546 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2547
2548 drm_connector_list_iter_begin(drm_dev, &iter);
2549 drm_for_each_connector_iter(list_connector, &iter) {
2550 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2551 ret = -EBUSY;
2552 break;
2553 }
2554 }
2555
2556 drm_connector_list_iter_end(&iter);
2557
2558 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2559 mutex_unlock(&drm_dev->mode_config.mutex);
2560 }
2561 if (ret)
2562 return ret;
2563 }
2564
2565 return 0;
2566 }
2567
amdgpu_pmops_runtime_suspend(struct device * dev)2568 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2569 {
2570 struct pci_dev *pdev = to_pci_dev(dev);
2571 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2572 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2573 int ret, i;
2574
2575 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2576 pm_runtime_forbid(dev);
2577 return -EBUSY;
2578 }
2579
2580 ret = amdgpu_runtime_idle_check_display(dev);
2581 if (ret)
2582 return ret;
2583
2584 /* wait for all rings to drain before suspending */
2585 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2586 struct amdgpu_ring *ring = adev->rings[i];
2587
2588 if (ring && ring->sched.ready) {
2589 ret = amdgpu_fence_wait_empty(ring);
2590 if (ret)
2591 return -EBUSY;
2592 }
2593 }
2594
2595 adev->in_runpm = true;
2596 if (amdgpu_device_supports_px(drm_dev))
2597 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2598
2599 /*
2600 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2601 * proper cleanups and put itself into a state ready for PNP. That
2602 * can address some random resuming failure observed on BOCO capable
2603 * platforms.
2604 * TODO: this may be also needed for PX capable platform.
2605 */
2606 if (amdgpu_device_supports_boco(drm_dev))
2607 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2608
2609 ret = amdgpu_device_prepare(drm_dev);
2610 if (ret)
2611 return ret;
2612 ret = amdgpu_device_suspend(drm_dev, false);
2613 if (ret) {
2614 adev->in_runpm = false;
2615 if (amdgpu_device_supports_boco(drm_dev))
2616 adev->mp1_state = PP_MP1_STATE_NONE;
2617 return ret;
2618 }
2619
2620 if (amdgpu_device_supports_boco(drm_dev))
2621 adev->mp1_state = PP_MP1_STATE_NONE;
2622
2623 if (amdgpu_device_supports_px(drm_dev)) {
2624 /* Only need to handle PCI state in the driver for ATPX
2625 * PCI core handles it for _PR3.
2626 */
2627 amdgpu_device_cache_pci_state(pdev);
2628 pci_disable_device(pdev);
2629 pci_ignore_hotplug(pdev);
2630 pci_set_power_state(pdev, PCI_D3cold);
2631 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2632 } else if (amdgpu_device_supports_boco(drm_dev)) {
2633 /* nothing to do */
2634 } else if (amdgpu_device_supports_baco(drm_dev)) {
2635 amdgpu_device_baco_enter(drm_dev);
2636 }
2637
2638 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2639
2640 return 0;
2641 }
2642
amdgpu_pmops_runtime_resume(struct device * dev)2643 static int amdgpu_pmops_runtime_resume(struct device *dev)
2644 {
2645 struct pci_dev *pdev = to_pci_dev(dev);
2646 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2647 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2648 int ret;
2649
2650 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2651 return -EINVAL;
2652
2653 /* Avoids registers access if device is physically gone */
2654 if (!pci_device_is_present(adev->pdev))
2655 adev->no_hw_access = true;
2656
2657 if (amdgpu_device_supports_px(drm_dev)) {
2658 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2659
2660 /* Only need to handle PCI state in the driver for ATPX
2661 * PCI core handles it for _PR3.
2662 */
2663 pci_set_power_state(pdev, PCI_D0);
2664 amdgpu_device_load_pci_state(pdev);
2665 ret = pci_enable_device(pdev);
2666 if (ret)
2667 return ret;
2668 pci_set_master(pdev);
2669 } else if (amdgpu_device_supports_boco(drm_dev)) {
2670 /* Only need to handle PCI state in the driver for ATPX
2671 * PCI core handles it for _PR3.
2672 */
2673 pci_set_master(pdev);
2674 } else if (amdgpu_device_supports_baco(drm_dev)) {
2675 amdgpu_device_baco_exit(drm_dev);
2676 }
2677 ret = amdgpu_device_resume(drm_dev, false);
2678 if (ret) {
2679 if (amdgpu_device_supports_px(drm_dev))
2680 pci_disable_device(pdev);
2681 return ret;
2682 }
2683
2684 if (amdgpu_device_supports_px(drm_dev))
2685 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2686 adev->in_runpm = false;
2687 return 0;
2688 }
2689
amdgpu_pmops_runtime_idle(struct device * dev)2690 static int amdgpu_pmops_runtime_idle(struct device *dev)
2691 {
2692 struct drm_device *drm_dev = dev_get_drvdata(dev);
2693 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2694 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2695 int ret = 1;
2696
2697 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2698 pm_runtime_forbid(dev);
2699 return -EBUSY;
2700 }
2701
2702 ret = amdgpu_runtime_idle_check_display(dev);
2703
2704 pm_runtime_mark_last_busy(dev);
2705 pm_runtime_autosuspend(dev);
2706 return ret;
2707 }
2708 #endif /* notyet */
2709
2710 #ifdef __linux__
amdgpu_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)2711 long amdgpu_drm_ioctl(struct file *filp,
2712 unsigned int cmd, unsigned long arg)
2713 {
2714 struct drm_file *file_priv = filp->private_data;
2715 struct drm_device *dev;
2716 long ret;
2717
2718 dev = file_priv->minor->dev;
2719 ret = pm_runtime_get_sync(dev->dev);
2720 if (ret < 0)
2721 goto out;
2722
2723 ret = drm_ioctl(filp, cmd, arg);
2724
2725 pm_runtime_mark_last_busy(dev->dev);
2726 out:
2727 pm_runtime_put_autosuspend(dev->dev);
2728 return ret;
2729 }
2730
2731 static const struct dev_pm_ops amdgpu_pm_ops = {
2732 .prepare = amdgpu_pmops_prepare,
2733 .complete = amdgpu_pmops_complete,
2734 .suspend = amdgpu_pmops_suspend,
2735 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2736 .resume = amdgpu_pmops_resume,
2737 .freeze = amdgpu_pmops_freeze,
2738 .thaw = amdgpu_pmops_thaw,
2739 .poweroff = amdgpu_pmops_poweroff,
2740 .restore = amdgpu_pmops_restore,
2741 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2742 .runtime_resume = amdgpu_pmops_runtime_resume,
2743 .runtime_idle = amdgpu_pmops_runtime_idle,
2744 };
2745
amdgpu_flush(struct file * f,fl_owner_t id)2746 static int amdgpu_flush(struct file *f, fl_owner_t id)
2747 {
2748 struct drm_file *file_priv = f->private_data;
2749 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2750 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2751
2752 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2753 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2754
2755 return timeout >= 0 ? 0 : timeout;
2756 }
2757
2758 static const struct file_operations amdgpu_driver_kms_fops = {
2759 .owner = THIS_MODULE,
2760 .open = drm_open,
2761 .flush = amdgpu_flush,
2762 .release = drm_release,
2763 .unlocked_ioctl = amdgpu_drm_ioctl,
2764 .mmap = drm_gem_mmap,
2765 .poll = drm_poll,
2766 .read = drm_read,
2767 #ifdef CONFIG_COMPAT
2768 .compat_ioctl = amdgpu_kms_compat_ioctl,
2769 #endif
2770 #ifdef CONFIG_PROC_FS
2771 .show_fdinfo = drm_show_fdinfo,
2772 #endif
2773 };
2774
2775 #endif /* __linux__ */
2776
amdgpu_file_to_fpriv(struct file * filp,struct amdgpu_fpriv ** fpriv)2777 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2778 {
2779 STUB();
2780 return -ENOSYS;
2781 #ifdef notyet
2782 struct drm_file *file;
2783
2784 if (!filp)
2785 return -EINVAL;
2786
2787 if (filp->f_op != &amdgpu_driver_kms_fops)
2788 return -EINVAL;
2789
2790 file = filp->private_data;
2791 *fpriv = file->driver_priv;
2792 return 0;
2793 #endif
2794 }
2795
2796 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2797 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2798 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2799 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2800 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2801 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2802 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2803 /* KMS */
2804 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2805 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2806 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2807 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2808 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2809 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2810 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2811 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2812 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2813 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2814 };
2815
2816 static const struct drm_driver amdgpu_kms_driver = {
2817 .driver_features =
2818 DRIVER_ATOMIC |
2819 DRIVER_GEM |
2820 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2821 DRIVER_SYNCOBJ_TIMELINE,
2822 .open = amdgpu_driver_open_kms,
2823 #ifdef __OpenBSD__
2824 .mmap = drm_gem_mmap,
2825 #endif
2826 .postclose = amdgpu_driver_postclose_kms,
2827 .lastclose = amdgpu_driver_lastclose_kms,
2828 .ioctls = amdgpu_ioctls_kms,
2829 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2830 .dumb_create = amdgpu_mode_dumb_create,
2831 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2832 #ifdef __linux__
2833 .fops = &amdgpu_driver_kms_fops,
2834 #endif
2835 .release = &amdgpu_driver_release_kms,
2836 #ifdef CONFIG_PROC_FS
2837 .show_fdinfo = amdgpu_show_fdinfo,
2838 #endif
2839
2840 .gem_prime_import = amdgpu_gem_prime_import,
2841
2842 .name = DRIVER_NAME,
2843 .desc = DRIVER_DESC,
2844 .date = DRIVER_DATE,
2845 .major = KMS_DRIVER_MAJOR,
2846 .minor = KMS_DRIVER_MINOR,
2847 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2848 };
2849
2850 const struct drm_driver amdgpu_partition_driver = {
2851 .driver_features =
2852 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
2853 DRIVER_SYNCOBJ_TIMELINE,
2854 .open = amdgpu_driver_open_kms,
2855 .postclose = amdgpu_driver_postclose_kms,
2856 .lastclose = amdgpu_driver_lastclose_kms,
2857 .ioctls = amdgpu_ioctls_kms,
2858 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2859 .dumb_create = amdgpu_mode_dumb_create,
2860 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2861 #ifdef __linux__
2862 .fops = &amdgpu_driver_kms_fops,
2863 #endif
2864 .release = &amdgpu_driver_release_kms,
2865
2866 .gem_prime_import = amdgpu_gem_prime_import,
2867
2868 .name = DRIVER_NAME,
2869 .desc = DRIVER_DESC,
2870 .date = DRIVER_DATE,
2871 .major = KMS_DRIVER_MAJOR,
2872 .minor = KMS_DRIVER_MINOR,
2873 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2874 };
2875
2876 #ifdef __linux__
2877 static struct pci_error_handlers amdgpu_pci_err_handler = {
2878 .error_detected = amdgpu_pci_error_detected,
2879 .mmio_enabled = amdgpu_pci_mmio_enabled,
2880 .slot_reset = amdgpu_pci_slot_reset,
2881 .resume = amdgpu_pci_resume,
2882 };
2883
2884 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2885 &amdgpu_vram_mgr_attr_group,
2886 &amdgpu_gtt_mgr_attr_group,
2887 &amdgpu_flash_attr_group,
2888 NULL,
2889 };
2890
2891 static struct pci_driver amdgpu_kms_pci_driver = {
2892 .name = DRIVER_NAME,
2893 .id_table = pciidlist,
2894 .probe = amdgpu_pci_probe,
2895 .remove = amdgpu_pci_remove,
2896 .shutdown = amdgpu_pci_shutdown,
2897 .driver.pm = &amdgpu_pm_ops,
2898 .err_handler = &amdgpu_pci_err_handler,
2899 .dev_groups = amdgpu_sysfs_groups,
2900 };
2901
amdgpu_init(void)2902 static int __init amdgpu_init(void)
2903 {
2904 int r;
2905
2906 if (drm_firmware_drivers_only())
2907 return -EINVAL;
2908
2909 r = amdgpu_sync_init();
2910 if (r)
2911 goto error_sync;
2912
2913 r = amdgpu_fence_slab_init();
2914 if (r)
2915 goto error_fence;
2916
2917 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2918 amdgpu_register_atpx_handler();
2919 amdgpu_acpi_detect();
2920
2921 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2922 amdgpu_amdkfd_init();
2923
2924 /* let modprobe override vga console setting */
2925 return pci_register_driver(&amdgpu_kms_pci_driver);
2926
2927 error_fence:
2928 amdgpu_sync_fini();
2929
2930 error_sync:
2931 return r;
2932 }
2933
amdgpu_exit(void)2934 static void __exit amdgpu_exit(void)
2935 {
2936 amdgpu_amdkfd_fini();
2937 pci_unregister_driver(&amdgpu_kms_pci_driver);
2938 amdgpu_unregister_atpx_handler();
2939 amdgpu_acpi_release();
2940 amdgpu_sync_fini();
2941 amdgpu_fence_slab_fini();
2942 mmu_notifier_synchronize();
2943 amdgpu_xcp_drv_release();
2944 }
2945
2946 module_init(amdgpu_init);
2947 module_exit(amdgpu_exit);
2948
2949 MODULE_AUTHOR(DRIVER_AUTHOR);
2950 MODULE_DESCRIPTION(DRIVER_DESC);
2951 MODULE_LICENSE("GPL and additional rights");
2952 #endif /* __linux__ */
2953
2954 #include <drm/drm_drv.h>
2955 #include <drm/drm_utils.h>
2956 #include <drm/drm_fb_helper.h>
2957
2958 #include "vga.h"
2959
2960 #if NVGA > 0
2961 #include <dev/ic/mc6845reg.h>
2962 #include <dev/ic/pcdisplayvar.h>
2963 #include <dev/ic/vgareg.h>
2964 #include <dev/ic/vgavar.h>
2965
2966 extern int vga_console_attached;
2967 #endif
2968
2969 #ifdef __amd64__
2970 #include "efifb.h"
2971 #include <machine/biosvar.h>
2972 #endif
2973
2974 #if NEFIFB > 0
2975 #include <machine/efifbvar.h>
2976 #endif
2977
2978 int amdgpu_probe(struct device *, void *, void *);
2979 void amdgpu_attach(struct device *, struct device *, void *);
2980 int amdgpu_detach(struct device *, int);
2981 int amdgpu_activate(struct device *, int);
2982 void amdgpu_attachhook(struct device *);
2983 int amdgpu_forcedetach(struct amdgpu_device *);
2984
2985 bool amdgpu_msi_ok(struct amdgpu_device *);
2986
2987 /*
2988 * set if the mountroot hook has a fatal error
2989 * such as not being able to find the firmware
2990 */
2991 int amdgpu_fatal_error;
2992
2993 const struct cfattach amdgpu_ca = {
2994 sizeof (struct amdgpu_device), amdgpu_probe, amdgpu_attach,
2995 amdgpu_detach, amdgpu_activate
2996 };
2997
2998 struct cfdriver amdgpu_cd = {
2999 NULL, "amdgpu", DV_DULL
3000 };
3001
3002 int
amdgpu_probe(struct device * parent,void * match,void * aux)3003 amdgpu_probe(struct device *parent, void *match, void *aux)
3004 {
3005 struct pci_attach_args *pa = aux;
3006 const struct pci_device_id *id_entry;
3007 unsigned long flags = 0;
3008 int i;
3009
3010 if (amdgpu_fatal_error)
3011 return 0;
3012
3013 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
3014 PCI_PRODUCT(pa->pa_id), pciidlist);
3015 if (id_entry != NULL) {
3016 flags = id_entry->driver_data;
3017
3018 if (id_entry->device == PCI_ANY_ID) {
3019 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY)
3020 return 0;
3021 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA &&
3022 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_MISC)
3023 return 0;
3024 }
3025
3026 /* skip devices which are owned by radeon */
3027 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
3028 if (amdgpu_unsupported_pciidlist[i] ==
3029 PCI_PRODUCT(pa->pa_id))
3030 return 0;
3031 }
3032
3033 if (flags & AMD_EXP_HW_SUPPORT)
3034 return 0;
3035 else
3036 return 20;
3037 }
3038
3039 return 0;
3040 }
3041
3042 /*
3043 * some functions are only called once on init regardless of how many times
3044 * amdgpu attaches in linux this is handled via module_init()/module_exit()
3045 */
3046 int amdgpu_refcnt;
3047
3048 int __init drm_sched_fence_slab_init(void);
3049 void __exit drm_sched_fence_slab_fini(void);
3050 irqreturn_t amdgpu_irq_handler(void *);
3051
3052 void
amdgpu_attach(struct device * parent,struct device * self,void * aux)3053 amdgpu_attach(struct device *parent, struct device *self, void *aux)
3054 {
3055 struct amdgpu_device *adev = (struct amdgpu_device *)self;
3056 struct drm_device *dev;
3057 struct pci_attach_args *pa = aux;
3058 const struct pci_device_id *id_entry;
3059 pcireg_t type;
3060 int i;
3061 uint8_t rmmio_bar;
3062 paddr_t fb_aper;
3063 pcireg_t addr, mask;
3064 int s;
3065 bool supports_atomic = false;
3066
3067 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
3068 PCI_PRODUCT(pa->pa_id), pciidlist);
3069 adev->flags = id_entry->driver_data;
3070 adev->family = adev->flags & AMD_ASIC_MASK;
3071 adev->pc = pa->pa_pc;
3072 adev->pa_tag = pa->pa_tag;
3073 adev->iot = pa->pa_iot;
3074 adev->memt = pa->pa_memt;
3075 adev->dmat = pa->pa_dmat;
3076
3077 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY &&
3078 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA &&
3079 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
3080 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
3081 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) {
3082 adev->primary = 1;
3083 #if NVGA > 0
3084 adev->console = vga_is_console(pa->pa_iot, -1);
3085 vga_console_attached = 1;
3086 #endif
3087 }
3088 #if NEFIFB > 0
3089 if (efifb_is_primary(pa)) {
3090 adev->primary = 1;
3091 adev->console = efifb_is_console(pa);
3092 efifb_detach();
3093 }
3094 #endif
3095
3096 #define AMDGPU_PCI_MEM 0x10
3097
3098 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM);
3099 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
3100 pci_mapreg_info(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM,
3101 type, &adev->fb_aper_offset, &adev->fb_aper_size, NULL)) {
3102 printf(": can't get frambuffer info\n");
3103 return;
3104 }
3105
3106 if (adev->fb_aper_offset == 0) {
3107 bus_size_t start, end, pci_mem_end;
3108 bus_addr_t base;
3109
3110 KASSERT(pa->pa_memex != NULL);
3111
3112 start = max(PCI_MEM_START, pa->pa_memex->ex_start);
3113 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT)
3114 pci_mem_end = PCI_MEM64_END;
3115 else
3116 pci_mem_end = PCI_MEM_END;
3117 end = min(pci_mem_end, pa->pa_memex->ex_end);
3118 if (extent_alloc_subregion(pa->pa_memex, start, end,
3119 adev->fb_aper_size, adev->fb_aper_size, 0, 0, 0, &base)) {
3120 printf(": can't reserve framebuffer space\n");
3121 return;
3122 }
3123 pci_conf_write(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, base);
3124 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT)
3125 pci_conf_write(pa->pa_pc, pa->pa_tag,
3126 AMDGPU_PCI_MEM + 4, (uint64_t)base >> 32);
3127 adev->fb_aper_offset = base;
3128 }
3129
3130 if (adev->family >= CHIP_BONAIRE)
3131 rmmio_bar = 0x24;
3132 else
3133 rmmio_bar = 0x18;
3134
3135 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar);
3136 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
3137 pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR,
3138 &adev->rmmio_bst, &adev->rmmio_bsh, &adev->rmmio_base,
3139 &adev->rmmio_size, 0)) {
3140 printf(": can't map rmmio space\n");
3141 return;
3142 }
3143 adev->rmmio = bus_space_vaddr(adev->rmmio_bst, adev->rmmio_bsh);
3144
3145 /*
3146 * Make sure we have a base address for the ROM such that we
3147 * can map it later.
3148 */
3149 s = splhigh();
3150 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
3151 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
3152 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
3153 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr);
3154 splx(s);
3155
3156 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) {
3157 bus_size_t size, start, end;
3158 bus_addr_t base;
3159
3160 size = PCI_ROM_SIZE(mask);
3161 start = max(PCI_MEM_START, pa->pa_memex->ex_start);
3162 end = min(PCI_MEM_END, pa->pa_memex->ex_end);
3163 if (extent_alloc_subregion(pa->pa_memex, start, end, size,
3164 size, 0, 0, 0, &base) == 0)
3165 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base);
3166 }
3167
3168 printf("\n");
3169
3170 /* from amdgpu_pci_probe(), aspm test done later */
3171
3172 if (!amdgpu_virtual_display &&
3173 amdgpu_device_asic_has_dc_support(adev->family))
3174 supports_atomic = true;
3175
3176 if ((adev->flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
3177 DRM_INFO("This hardware requires experimental hardware support.\n");
3178 return;
3179 }
3180
3181 /*
3182 * Initialize amdkfd before starting radeon.
3183 */
3184 amdgpu_amdkfd_init();
3185
3186 dev = drm_attach_pci(&amdgpu_kms_driver, pa, 0, adev->primary,
3187 self, &adev->ddev);
3188 if (dev == NULL) {
3189 printf("%s: drm attach failed\n", adev->self.dv_xname);
3190 return;
3191 }
3192 adev->pdev = dev->pdev;
3193
3194 /* from amdgpu_pci_probe() */
3195 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(adev->pdev))
3196 amdgpu_aspm = 0;
3197
3198 if (!supports_atomic)
3199 dev->driver_features &= ~DRIVER_ATOMIC;
3200
3201 if (!amdgpu_msi_ok(adev))
3202 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED;
3203
3204 /* from amdgpu_init() */
3205 if (amdgpu_refcnt == 0) {
3206 drm_sched_fence_slab_init();
3207
3208 if (amdgpu_sync_init()) {
3209 printf("%s: amdgpu_sync_init failed\n",
3210 adev->self.dv_xname);
3211 return;
3212 }
3213
3214 if (amdgpu_fence_slab_init()) {
3215 amdgpu_sync_fini();
3216 printf("%s: amdgpu_fence_slab_init failed\n",
3217 adev->self.dv_xname);
3218 return;
3219 }
3220
3221 amdgpu_register_atpx_handler();
3222 amdgpu_acpi_detect();
3223 }
3224 amdgpu_refcnt++;
3225
3226 adev->irq.msi_enabled = false;
3227 if (pci_intr_map_msi(pa, &adev->intrh) == 0)
3228 adev->irq.msi_enabled = true;
3229 else if (pci_intr_map(pa, &adev->intrh) != 0) {
3230 printf("%s: couldn't map interrupt\n", adev->self.dv_xname);
3231 return;
3232 }
3233 printf("%s: %s\n", adev->self.dv_xname,
3234 pci_intr_string(pa->pa_pc, adev->intrh));
3235
3236 adev->irqh = pci_intr_establish(pa->pa_pc, adev->intrh, IPL_TTY,
3237 amdgpu_irq_handler, &adev->ddev, adev->self.dv_xname);
3238 if (adev->irqh == NULL) {
3239 printf("%s: couldn't establish interrupt\n",
3240 adev->self.dv_xname);
3241 return;
3242 }
3243 adev->pdev->irq = 0;
3244
3245 fb_aper = bus_space_mmap(adev->memt, adev->fb_aper_offset, 0, 0, 0);
3246 if (fb_aper != -1)
3247 rasops_claim_framebuffer(fb_aper, adev->fb_aper_size, self);
3248
3249
3250 adev->shutdown = true;
3251 config_mountroot(self, amdgpu_attachhook);
3252 }
3253
3254 int
amdgpu_forcedetach(struct amdgpu_device * adev)3255 amdgpu_forcedetach(struct amdgpu_device *adev)
3256 {
3257 struct pci_softc *sc = (struct pci_softc *)adev->self.dv_parent;
3258 pcitag_t tag = adev->pa_tag;
3259
3260 #if NVGA > 0
3261 if (adev->primary)
3262 vga_console_attached = 0;
3263 #endif
3264
3265 /* reprobe pci device for non efi systems */
3266 #if NEFIFB > 0
3267 if (bios_efiinfo == NULL && !efifb_cb_found()) {
3268 #endif
3269 config_detach(&adev->self, 0);
3270 return pci_probe_device(sc, tag, NULL, NULL);
3271 #if NEFIFB > 0
3272 } else if (adev->primary) {
3273 efifb_reattach();
3274 }
3275 #endif
3276
3277 return 0;
3278 }
3279
3280 void amdgpu_burner(void *, u_int, u_int);
3281 void amdgpu_burner_cb(void *);
3282 int amdgpu_wsioctl(void *, u_long, caddr_t, int, struct proc *);
3283 paddr_t amdgpu_wsmmap(void *, off_t, int);
3284 int amdgpu_alloc_screen(void *, const struct wsscreen_descr *,
3285 void **, int *, int *, uint32_t *);
3286 void amdgpu_free_screen(void *, void *);
3287 int amdgpu_show_screen(void *, void *, int,
3288 void (*)(void *, int, int), void *);
3289 void amdgpu_doswitch(void *);
3290 void amdgpu_enter_ddb(void *, void *);
3291
3292 struct wsscreen_descr amdgpu_stdscreen = {
3293 "std",
3294 0, 0,
3295 0,
3296 0, 0,
3297 WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
3298 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS
3299 };
3300
3301 const struct wsscreen_descr *amdgpu_scrlist[] = {
3302 &amdgpu_stdscreen,
3303 };
3304
3305 struct wsscreen_list amdgpu_screenlist = {
3306 nitems(amdgpu_scrlist), amdgpu_scrlist
3307 };
3308
3309 struct wsdisplay_accessops amdgpu_accessops = {
3310 .ioctl = amdgpu_wsioctl,
3311 .mmap = amdgpu_wsmmap,
3312 .alloc_screen = amdgpu_alloc_screen,
3313 .free_screen = amdgpu_free_screen,
3314 .show_screen = amdgpu_show_screen,
3315 .enter_ddb = amdgpu_enter_ddb,
3316 .getchar = rasops_getchar,
3317 .load_font = rasops_load_font,
3318 .list_font = rasops_list_font,
3319 .scrollback = rasops_scrollback,
3320 .burn_screen = amdgpu_burner
3321 };
3322
3323 int
amdgpu_wsioctl(void * v,u_long cmd,caddr_t data,int flag,struct proc * p)3324 amdgpu_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
3325 {
3326 struct rasops_info *ri = v;
3327 struct amdgpu_device *adev = ri->ri_hw;
3328 struct backlight_device *bd = adev->dm.backlight_dev[0];
3329 struct wsdisplay_param *dp = (struct wsdisplay_param *)data;
3330 struct wsdisplay_fbinfo *wdf;
3331
3332 switch (cmd) {
3333 case WSDISPLAYIO_GTYPE:
3334 *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM;
3335 return 0;
3336 case WSDISPLAYIO_GINFO:
3337 wdf = (struct wsdisplay_fbinfo *)data;
3338 wdf->width = ri->ri_width;
3339 wdf->height = ri->ri_height;
3340 wdf->depth = ri->ri_depth;
3341 wdf->stride = ri->ri_stride;
3342 wdf->offset = 0;
3343 wdf->cmsize = 0;
3344 return 0;
3345 case WSDISPLAYIO_GETPARAM:
3346 if (bd == NULL)
3347 return -1;
3348
3349 switch (dp->param) {
3350 case WSDISPLAYIO_PARAM_BRIGHTNESS:
3351 dp->min = 0;
3352 dp->max = bd->props.max_brightness;
3353 dp->curval = bd->props.brightness;
3354 return (dp->max > dp->min) ? 0 : -1;
3355 }
3356 break;
3357 case WSDISPLAYIO_SETPARAM:
3358 if (bd == NULL || dp->curval > bd->props.max_brightness)
3359 return -1;
3360
3361 switch (dp->param) {
3362 case WSDISPLAYIO_PARAM_BRIGHTNESS:
3363 bd->props.brightness = dp->curval;
3364 backlight_update_status(bd);
3365 knote_locked(&adev->ddev.note, NOTE_CHANGE);
3366 return 0;
3367 }
3368 break;
3369 case WSDISPLAYIO_SVIDEO:
3370 case WSDISPLAYIO_GVIDEO:
3371 return 0;
3372 }
3373
3374 return (-1);
3375 }
3376
3377 paddr_t
amdgpu_wsmmap(void * v,off_t off,int prot)3378 amdgpu_wsmmap(void *v, off_t off, int prot)
3379 {
3380 return (-1);
3381 }
3382
3383 int
amdgpu_alloc_screen(void * v,const struct wsscreen_descr * type,void ** cookiep,int * curxp,int * curyp,uint32_t * attrp)3384 amdgpu_alloc_screen(void *v, const struct wsscreen_descr *type,
3385 void **cookiep, int *curxp, int *curyp, uint32_t *attrp)
3386 {
3387 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp);
3388 }
3389
3390 void
amdgpu_free_screen(void * v,void * cookie)3391 amdgpu_free_screen(void *v, void *cookie)
3392 {
3393 return rasops_free_screen(v, cookie);
3394 }
3395
3396 int
amdgpu_show_screen(void * v,void * cookie,int waitok,void (* cb)(void *,int,int),void * cbarg)3397 amdgpu_show_screen(void *v, void *cookie, int waitok,
3398 void (*cb)(void *, int, int), void *cbarg)
3399 {
3400 struct rasops_info *ri = v;
3401 struct amdgpu_device *adev = ri->ri_hw;
3402
3403 if (cookie == ri->ri_active)
3404 return (0);
3405
3406 adev->switchcb = cb;
3407 adev->switchcbarg = cbarg;
3408 adev->switchcookie = cookie;
3409 if (cb) {
3410 task_add(systq, &adev->switchtask);
3411 return (EAGAIN);
3412 }
3413
3414 amdgpu_doswitch(v);
3415
3416 return (0);
3417 }
3418
3419 void
amdgpu_doswitch(void * v)3420 amdgpu_doswitch(void *v)
3421 {
3422 struct rasops_info *ri = v;
3423 struct amdgpu_device *adev = ri->ri_hw;
3424 struct amdgpu_crtc *amdgpu_crtc;
3425 int i, crtc;
3426
3427 rasops_show_screen(ri, adev->switchcookie, 0, NULL, NULL);
3428 drm_fb_helper_restore_fbdev_mode_unlocked(adev_to_drm(adev)->fb_helper);
3429
3430 if (adev->switchcb)
3431 (adev->switchcb)(adev->switchcbarg, 0, 0);
3432 }
3433
3434 void
amdgpu_enter_ddb(void * v,void * cookie)3435 amdgpu_enter_ddb(void *v, void *cookie)
3436 {
3437 struct rasops_info *ri = v;
3438 struct amdgpu_device *adev = ri->ri_hw;
3439 struct drm_fb_helper *fb_helper = adev_to_drm(adev)->fb_helper;
3440
3441 if (cookie == ri->ri_active)
3442 return;
3443
3444 rasops_show_screen(ri, cookie, 0, NULL, NULL);
3445 drm_fb_helper_debug_enter(fb_helper->info);
3446 }
3447
3448 void
amdgpu_init_backlight(struct amdgpu_device * adev)3449 amdgpu_init_backlight(struct amdgpu_device *adev)
3450 {
3451 struct drm_device *dev = &adev->ddev;
3452 struct backlight_device *bd = adev->dm.backlight_dev[0];
3453 struct drm_connector_list_iter conn_iter;
3454 struct drm_connector *connector;
3455 struct amdgpu_dm_connector *aconnector;
3456
3457 if (bd == NULL)
3458 return;
3459
3460 drm_connector_list_iter_begin(dev, &conn_iter);
3461 drm_for_each_connector_iter(connector, &conn_iter) {
3462 aconnector = to_amdgpu_dm_connector(connector);
3463
3464 if (connector->registration_state != DRM_CONNECTOR_REGISTERED)
3465 continue;
3466
3467 if (aconnector->bl_idx == -1)
3468 continue;
3469
3470 dev->registered = false;
3471 connector->registration_state = DRM_CONNECTOR_UNREGISTERED;
3472
3473 connector->backlight_device = bd;
3474 connector->backlight_property = drm_property_create_range(dev,
3475 0, "Backlight", 0, bd->props.max_brightness);
3476 drm_object_attach_property(&connector->base,
3477 connector->backlight_property, bd->props.brightness);
3478
3479 connector->registration_state = DRM_CONNECTOR_REGISTERED;
3480 dev->registered = true;
3481
3482 break;
3483 }
3484 drm_connector_list_iter_end(&conn_iter);
3485 }
3486
3487 void
amdgpu_attachhook(struct device * self)3488 amdgpu_attachhook(struct device *self)
3489 {
3490 struct amdgpu_device *adev = (struct amdgpu_device *)self;
3491 struct drm_device *dev = &adev->ddev;
3492 int r, acpi_status;
3493 struct rasops_info *ri = &adev->ro;
3494 struct drm_fb_helper *fb_helper;
3495 struct drm_framebuffer *fb;
3496 struct drm_gem_object *obj;
3497 struct amdgpu_bo *rbo;
3498
3499 r = amdgpu_driver_load_kms(adev, adev->flags);
3500 if (r)
3501 goto out;
3502
3503 /*
3504 * 1. don't init fbdev on hw without DCE
3505 * 2. don't init fbdev if there are no connectors
3506 */
3507 if (adev->mode_info.mode_config_initialized &&
3508 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
3509
3510 /*
3511 * in linux via amdgpu_pci_probe -> drm_dev_register
3512 * must be before drm_fbdev_generic_setup()
3513 */
3514 drm_dev_register(dev, adev->flags);
3515
3516 /* OpenBSD specific backlight property on connector */
3517 amdgpu_init_backlight(adev);
3518
3519 /* select 8 bpp console on low vram cards */
3520 if (adev->gmc.real_vram_size <= (32*1024*1024))
3521 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
3522 else
3523 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
3524
3525 fb_helper = adev_to_drm(adev)->fb_helper;
3526 if (fb_helper == NULL) {
3527 printf("fb_helper NULL\n");
3528 return;
3529 }
3530 fb = fb_helper->fb;
3531 obj = fb->obj[0];
3532 rbo = gem_to_amdgpu_bo(obj);
3533 amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM);
3534 amdgpu_bo_kmap(rbo, (void **)(&ri->ri_bits));
3535
3536 ri->ri_depth = fb->format->cpp[0] * 8;
3537 ri->ri_stride = fb->pitches[0];
3538 ri->ri_width = fb_helper->info->var.xres;
3539 ri->ri_height = fb_helper->info->var.yres;
3540
3541 switch (fb->format->format) {
3542 case DRM_FORMAT_XRGB8888:
3543 ri->ri_rnum = 8;
3544 ri->ri_rpos = 16;
3545 ri->ri_gnum = 8;
3546 ri->ri_gpos = 8;
3547 ri->ri_bnum = 8;
3548 ri->ri_bpos = 0;
3549 break;
3550 case DRM_FORMAT_RGB565:
3551 ri->ri_rnum = 5;
3552 ri->ri_rpos = 11;
3553 ri->ri_gnum = 6;
3554 ri->ri_gpos = 5;
3555 ri->ri_bnum = 5;
3556 ri->ri_bpos = 0;
3557 break;
3558 }
3559 }
3560 {
3561 struct wsemuldisplaydev_attach_args aa;
3562 int orientation_quirk;
3563
3564 task_set(&adev->switchtask, amdgpu_doswitch, ri);
3565 task_set(&adev->burner_task, amdgpu_burner_cb, adev);
3566
3567 if (ri->ri_bits == NULL)
3568 return;
3569
3570 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY;
3571
3572 orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width,
3573 ri->ri_height);
3574 if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP)
3575 ri->ri_flg |= RI_ROTATE_CCW;
3576 else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP)
3577 ri->ri_flg |= RI_ROTATE_CW;
3578
3579 rasops_init(ri, 160, 160);
3580
3581 ri->ri_hw = adev;
3582
3583 amdgpu_stdscreen.capabilities = ri->ri_caps;
3584 amdgpu_stdscreen.nrows = ri->ri_rows;
3585 amdgpu_stdscreen.ncols = ri->ri_cols;
3586 amdgpu_stdscreen.textops = &ri->ri_ops;
3587 amdgpu_stdscreen.fontwidth = ri->ri_font->fontwidth;
3588 amdgpu_stdscreen.fontheight = ri->ri_font->fontheight;
3589
3590 aa.console = adev->console;
3591 aa.primary = adev->primary;
3592 aa.scrdata = &amdgpu_screenlist;
3593 aa.accessops = &amdgpu_accessops;
3594 aa.accesscookie = ri;
3595 aa.defaultscreens = 0;
3596
3597 if (adev->console) {
3598 uint32_t defattr;
3599
3600 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr);
3601 wsdisplay_cnattach(&amdgpu_stdscreen, ri->ri_active,
3602 ri->ri_ccol, ri->ri_crow, defattr);
3603 }
3604
3605 /*
3606 * Now that we've taken over the console, disable decoding of
3607 * VGA legacy addresses, and opt out of arbitration.
3608 */
3609 amdgpu_asic_set_vga_state(adev, false);
3610 pci_disable_legacy_vga(&adev->self);
3611
3612 printf("%s: %dx%d, %dbpp\n", adev->self.dv_xname,
3613 ri->ri_width, ri->ri_height, ri->ri_depth);
3614
3615 config_found_sm(&adev->self, &aa, wsemuldisplaydevprint,
3616 wsemuldisplaydevsubmatch);
3617 }
3618
3619 out:
3620 if (r) {
3621 amdgpu_fatal_error = 1;
3622 amdgpu_forcedetach(adev);
3623 }
3624 }
3625
3626 /* from amdgpu_exit amdgpu_driver_unload_kms */
3627 int
amdgpu_detach(struct device * self,int flags)3628 amdgpu_detach(struct device *self, int flags)
3629 {
3630 struct amdgpu_device *adev = (struct amdgpu_device *)self;
3631 struct drm_device *dev = &adev->ddev;
3632
3633 if (adev == NULL)
3634 return 0;
3635
3636 amdgpu_refcnt--;
3637
3638 if (amdgpu_refcnt == 0)
3639 amdgpu_amdkfd_fini();
3640
3641 pci_intr_disestablish(adev->pc, adev->irqh);
3642
3643 amdgpu_unregister_gpu_instance(adev);
3644
3645 amdgpu_acpi_fini(adev);
3646 amdgpu_device_fini_hw(adev);
3647
3648 if (amdgpu_refcnt == 0) {
3649 amdgpu_unregister_atpx_handler();
3650 amdgpu_sync_fini();
3651 amdgpu_fence_slab_fini();
3652
3653 drm_sched_fence_slab_fini();
3654 }
3655
3656 config_detach(adev->ddev.dev, flags);
3657
3658 return 0;
3659 }
3660
3661 int
amdgpu_activate(struct device * self,int act)3662 amdgpu_activate(struct device *self, int act)
3663 {
3664 struct amdgpu_device *adev = (struct amdgpu_device *)self;
3665 struct drm_device *dev = &adev->ddev;
3666 int rv = 0;
3667
3668 if (dev->dev == NULL || amdgpu_fatal_error || adev->shutdown)
3669 return (0);
3670
3671 switch (act) {
3672 case DVACT_QUIESCE:
3673 rv = config_activate_children(self, act);
3674 amdgpu_device_prepare(dev);
3675 amdgpu_device_suspend(dev, true);
3676 break;
3677 case DVACT_SUSPEND:
3678 break;
3679 case DVACT_RESUME:
3680 break;
3681 case DVACT_WAKEUP:
3682 amdgpu_device_resume(dev, true);
3683 rv = config_activate_children(self, act);
3684 break;
3685 }
3686
3687 return (rv);
3688 }
3689
3690 void
amdgpu_burner(void * v,u_int on,u_int flags)3691 amdgpu_burner(void *v, u_int on, u_int flags)
3692 {
3693 struct rasops_info *ri = v;
3694 struct amdgpu_device *adev = ri->ri_hw;
3695
3696 task_del(systq, &adev->burner_task);
3697
3698 if (on)
3699 adev->burner_fblank = FB_BLANK_UNBLANK;
3700 else {
3701 if (flags & WSDISPLAY_BURN_VBLANK)
3702 adev->burner_fblank = FB_BLANK_VSYNC_SUSPEND;
3703 else
3704 adev->burner_fblank = FB_BLANK_NORMAL;
3705 }
3706
3707 /*
3708 * Setting the DPMS mode may sleep while waiting for vblank so
3709 * hand things off to a taskq.
3710 */
3711 task_add(systq, &adev->burner_task);
3712 }
3713
3714 void
amdgpu_burner_cb(void * arg1)3715 amdgpu_burner_cb(void *arg1)
3716 {
3717 struct amdgpu_device *adev = arg1;
3718 struct drm_fb_helper *helper = adev_to_drm(adev)->fb_helper;
3719
3720 drm_fb_helper_blank(adev->burner_fblank, helper->info);
3721 }
3722