1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/dma-mapping.h>
25
26 #include <drm/drm_legacy.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_ih.h"
30
31 /**
32 * amdgpu_ih_ring_init - initialize the IH state
33 *
34 * @adev: amdgpu_device pointer
35 * @ih: ih ring to initialize
36 * @ring_size: ring size to allocate
37 * @use_bus_addr: true when we can use dma_alloc_coherent
38 *
39 * Initializes the IH state and allocates a buffer
40 * for the IH ring buffer.
41 * Returns 0 for success, errors for failure.
42 */
amdgpu_ih_ring_init(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,unsigned ring_size,bool use_bus_addr)43 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
44 unsigned ring_size, bool use_bus_addr)
45 {
46 u32 rb_bufsz;
47 int r;
48 struct drm_dmamem *dmah;
49 int flags = 0;
50
51 /* Align ring size */
52 rb_bufsz = order_base_2(ring_size / 4);
53 ring_size = (1 << rb_bufsz) * 4;
54 ih->ring_size = ring_size;
55 ih->ptr_mask = ih->ring_size - 1;
56 ih->rptr = 0;
57 ih->use_bus_addr = use_bus_addr;
58
59 if (use_bus_addr) {
60 dma_addr_t dma_addr;
61
62 if (ih->ring)
63 return 0;
64
65 /* add 8 bytes for the rptr/wptr shadows and
66 * add them to the end of the ring allocation.
67 */
68 #ifdef __linux__
69 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
70 &dma_addr, GFP_KERNEL);
71 if (ih->ring == NULL)
72 return -ENOMEM;
73 #else
74 dmah = drm_dmamem_alloc(adev->dmat,
75 ih->ring_size + 8,
76 PAGE_SIZE, 1,
77 ih->ring_size + 8, flags, 0);
78 if (dmah == NULL)
79 return -ENOMEM;
80 ih->dmah = dmah;
81 dma_addr = dmah->map->dm_segs[0].ds_addr;
82 ih->ring = (volatile uint32_t *)dmah->kva;
83 #endif
84
85 ih->gpu_addr = dma_addr;
86 ih->wptr_addr = dma_addr + ih->ring_size;
87 ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
88 ih->rptr_addr = dma_addr + ih->ring_size + 4;
89 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
90 } else {
91 unsigned wptr_offs, rptr_offs;
92
93 r = amdgpu_device_wb_get(adev, &wptr_offs);
94 if (r)
95 return r;
96
97 r = amdgpu_device_wb_get(adev, &rptr_offs);
98 if (r) {
99 amdgpu_device_wb_free(adev, wptr_offs);
100 return r;
101 }
102
103 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
104 AMDGPU_GEM_DOMAIN_GTT,
105 &ih->ring_obj, &ih->gpu_addr,
106 (void **)&ih->ring);
107 if (r) {
108 amdgpu_device_wb_free(adev, rptr_offs);
109 amdgpu_device_wb_free(adev, wptr_offs);
110 return r;
111 }
112
113 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
114 ih->wptr_cpu = &adev->wb.wb[wptr_offs];
115 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
116 ih->rptr_cpu = &adev->wb.wb[rptr_offs];
117 }
118
119 init_waitqueue_head(&ih->wait_process);
120 return 0;
121 }
122
123 /**
124 * amdgpu_ih_ring_fini - tear down the IH state
125 *
126 * @adev: amdgpu_device pointer
127 * @ih: ih ring to tear down
128 *
129 * Tears down the IH state and frees buffer
130 * used for the IH ring buffer.
131 */
amdgpu_ih_ring_fini(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)132 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
133 {
134
135 if (!ih->ring)
136 return;
137
138 if (ih->use_bus_addr) {
139
140 /* add 8 bytes for the rptr/wptr shadows and
141 * add them to the end of the ring allocation.
142 */
143 #ifdef __linux__
144 dma_free_coherent(adev->dev, ih->ring_size + 8,
145 (void *)ih->ring, ih->gpu_addr);
146 #else
147 drm_dmamem_free(adev->dmat, ih->dmah);
148 #endif
149 ih->ring = NULL;
150 } else {
151 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
152 (void **)&ih->ring);
153 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
154 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
155 }
156 }
157
158 /**
159 * amdgpu_ih_ring_write - write IV to the ring buffer
160 *
161 * @adev: amdgpu_device pointer
162 * @ih: ih ring to write to
163 * @iv: the iv to write
164 * @num_dw: size of the iv in dw
165 *
166 * Writes an IV to the ring buffer using the CPU and increment the wptr.
167 * Used for testing and delegating IVs to a software ring.
168 */
amdgpu_ih_ring_write(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,const uint32_t * iv,unsigned int num_dw)169 void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
170 const uint32_t *iv, unsigned int num_dw)
171 {
172 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
173 unsigned int i;
174
175 for (i = 0; i < num_dw; ++i)
176 ih->ring[wptr++] = cpu_to_le32(iv[i]);
177
178 wptr <<= 2;
179 wptr &= ih->ptr_mask;
180
181 /* Only commit the new wptr if we don't overflow */
182 if (wptr != READ_ONCE(ih->rptr)) {
183 wmb();
184 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
185 } else if (adev->irq.retry_cam_enabled) {
186 dev_warn_once(adev->dev, "IH soft ring buffer overflow 0x%X, 0x%X\n",
187 wptr, ih->rptr);
188 }
189 }
190
191 /**
192 * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to checkpoint
193 *
194 * @adev: amdgpu_device pointer
195 * @ih: ih ring to process
196 *
197 * Used to ensure ring has processed IVs up to the checkpoint write pointer.
198 */
amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)199 int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
200 struct amdgpu_ih_ring *ih)
201 {
202 uint32_t checkpoint_wptr;
203 uint64_t checkpoint_ts;
204 long timeout = HZ;
205
206 if (!ih->enabled || adev->shutdown)
207 return -ENODEV;
208
209 checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
210 /* Order wptr with ring data. */
211 rmb();
212 checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
213
214 return wait_event_interruptible_timeout(ih->wait_process,
215 amdgpu_ih_ts_after(checkpoint_ts, ih->processed_timestamp) ||
216 ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout);
217 }
218
219 /**
220 * amdgpu_ih_process - interrupt handler
221 *
222 * @adev: amdgpu_device pointer
223 * @ih: ih ring to process
224 *
225 * Interrupt hander (VI), walk the IH ring.
226 * Returns irq process return code.
227 */
amdgpu_ih_process(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)228 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
229 {
230 unsigned int count;
231 u32 wptr;
232
233 if (!ih->enabled || adev->shutdown)
234 return IRQ_NONE;
235
236 wptr = amdgpu_ih_get_wptr(adev, ih);
237
238 restart_ih:
239 count = AMDGPU_IH_MAX_NUM_IVS;
240 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
241
242 /* Order reading of wptr vs. reading of IH ring data */
243 rmb();
244
245 while (ih->rptr != wptr && --count) {
246 amdgpu_irq_dispatch(adev, ih);
247 ih->rptr &= ih->ptr_mask;
248 }
249
250 amdgpu_ih_set_rptr(adev, ih);
251 wake_up_all(&ih->wait_process);
252
253 /* make sure wptr hasn't changed while processing */
254 wptr = amdgpu_ih_get_wptr(adev, ih);
255 if (wptr != ih->rptr)
256 goto restart_ih;
257
258 return IRQ_HANDLED;
259 }
260
261 /**
262 * amdgpu_ih_decode_iv_helper - decode an interrupt vector
263 *
264 * @adev: amdgpu_device pointer
265 * @ih: ih ring to process
266 * @entry: IV entry
267 *
268 * Decodes the interrupt vector at the current rptr
269 * position and also advance the position for Vega10
270 * and later GPUs.
271 */
amdgpu_ih_decode_iv_helper(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,struct amdgpu_iv_entry * entry)272 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
273 struct amdgpu_ih_ring *ih,
274 struct amdgpu_iv_entry *entry)
275 {
276 /* wptr/rptr are in bytes! */
277 u32 ring_index = ih->rptr >> 2;
278 uint32_t dw[8];
279
280 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
281 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
282 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
283 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
284 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
285 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
286 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
287 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
288
289 entry->client_id = dw[0] & 0xff;
290 entry->src_id = (dw[0] >> 8) & 0xff;
291 entry->ring_id = (dw[0] >> 16) & 0xff;
292 entry->vmid = (dw[0] >> 24) & 0xf;
293 entry->vmid_src = (dw[0] >> 31);
294 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
295 entry->timestamp_src = dw[2] >> 31;
296 entry->pasid = dw[3] & 0xffff;
297 entry->node_id = (dw[3] >> 16) & 0xff;
298 entry->src_data[0] = dw[4];
299 entry->src_data[1] = dw[5];
300 entry->src_data[2] = dw[6];
301 entry->src_data[3] = dw[7];
302
303 /* wptr/rptr are in bytes! */
304 ih->rptr += 32;
305 }
306
amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring * ih,u32 rptr,signed int offset)307 uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
308 signed int offset)
309 {
310 uint32_t iv_size = 32;
311 uint32_t ring_index;
312 uint32_t dw1, dw2;
313
314 rptr += iv_size * offset;
315 ring_index = (rptr & ih->ptr_mask) >> 2;
316
317 dw1 = le32_to_cpu(ih->ring[ring_index + 1]);
318 dw2 = le32_to_cpu(ih->ring[ring_index + 2]);
319 return dw1 | ((u64)(dw2 & 0xffff) << 32);
320 }
321