1 /* $NetBSD: amdgpu_irq.c,v 1.9 2021/12/19 12:38:49 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30
31 /**
32 * DOC: Interrupt Handling
33 *
34 * Interrupts generated within GPU hardware raise interrupt requests that are
35 * passed to amdgpu IRQ handler which is responsible for detecting source and
36 * type of the interrupt and dispatching matching handlers. If handling an
37 * interrupt requires calling kernel functions that may sleep processing is
38 * dispatched to work handlers.
39 *
40 * If MSI functionality is not disabled by module parameter then MSI
41 * support will be enabled.
42 *
43 * For GPU interrupt sources that may be driven by another driver, IRQ domain
44 * support is used (with mapping between virtual and hardware IRQs).
45 */
46
47 #include <sys/cdefs.h>
48 __KERNEL_RCSID(0, "$NetBSD: amdgpu_irq.c,v 1.9 2021/12/19 12:38:49 riastradh Exp $");
49
50 #include <linux/irq.h>
51 #include <linux/pci.h>
52
53 #include <drm/drm_crtc_helper.h>
54 #include <drm/drm_irq.h>
55 #include <drm/drm_vblank.h>
56 #include <drm/amdgpu_drm.h>
57 #include "amdgpu.h"
58 #include "amdgpu_ih.h"
59 #include "atom.h"
60 #include "amdgpu_connectors.h"
61 #include "amdgpu_trace.h"
62 #include "amdgpu_amdkfd.h"
63 #include "amdgpu_ras.h"
64
65 #include <linux/pm_runtime.h>
66
67 #ifdef CONFIG_DRM_AMD_DC
68 #include "amdgpu_dm_irq.h"
69 #endif
70
71 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
72
73 /**
74 * amdgpu_hotplug_work_func - work handler for display hotplug event
75 *
76 * @work: work struct pointer
77 *
78 * This is the hotplug event work handler (all ASICs).
79 * The work gets scheduled from the IRQ handler if there
80 * was a hotplug interrupt. It walks through the connector table
81 * and calls hotplug handler for each connector. After this, it sends
82 * a DRM hotplug event to alert userspace.
83 *
84 * This design approach is required in order to defer hotplug event handling
85 * from the IRQ handler to a work handler because hotplug handler has to use
86 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
87 * sleep).
88 */
amdgpu_hotplug_work_func(struct work_struct * work)89 static void amdgpu_hotplug_work_func(struct work_struct *work)
90 {
91 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
92 hotplug_work);
93 struct drm_device *dev = adev->ddev;
94 struct drm_mode_config *mode_config = &dev->mode_config;
95 struct drm_connector *connector;
96 struct drm_connector_list_iter iter;
97
98 mutex_lock(&mode_config->mutex);
99 drm_connector_list_iter_begin(dev, &iter);
100 drm_for_each_connector_iter(connector, &iter)
101 amdgpu_connector_hotplug(connector);
102 drm_connector_list_iter_end(&iter);
103 mutex_unlock(&mode_config->mutex);
104 /* Just fire off a uevent and let userspace tell us what to do */
105 drm_helper_hpd_irq_event(dev);
106 }
107
108 /**
109 * amdgpu_irq_disable_all - disable *all* interrupts
110 *
111 * @adev: amdgpu device pointer
112 *
113 * Disable all types of interrupts from all sources.
114 */
amdgpu_irq_disable_all(struct amdgpu_device * adev)115 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
116 {
117 unsigned long irqflags;
118 unsigned i, j, k;
119 int r;
120
121 spin_lock_irqsave(&adev->irq.lock, irqflags);
122 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
123 if (!adev->irq.client[i].sources)
124 continue;
125
126 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
127 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
128
129 if (!src || !src->funcs->set || !src->num_types)
130 continue;
131
132 for (k = 0; k < src->num_types; ++k) {
133 atomic_set(&src->enabled_types[k], 0);
134 r = src->funcs->set(adev, src, k,
135 AMDGPU_IRQ_STATE_DISABLE);
136 if (r)
137 DRM_ERROR("error disabling interrupt (%d)\n",
138 r);
139 }
140 }
141 }
142 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
143 }
144
145 /**
146 * amdgpu_irq_handler - IRQ handler
147 *
148 * @irq: IRQ number (unused)
149 * @arg: pointer to DRM device
150 *
151 * IRQ handler for amdgpu driver (all ASICs).
152 *
153 * Returns:
154 * result of handling the IRQ, as defined by &irqreturn_t
155 */
amdgpu_irq_handler(DRM_IRQ_ARGS)156 irqreturn_t amdgpu_irq_handler(DRM_IRQ_ARGS)
157 {
158 struct drm_device *dev = (struct drm_device *) arg;
159 struct amdgpu_device *adev = dev->dev_private;
160 irqreturn_t ret;
161
162 ret = amdgpu_ih_process(adev, &adev->irq.ih);
163 if (ret == IRQ_HANDLED)
164 pm_runtime_mark_last_busy(dev->dev);
165
166 /* For the hardware that cannot enable bif ring for both ras_controller_irq
167 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
168 * register to check whether the interrupt is triggered or not, and properly
169 * ack the interrupt if it is there
170 */
171 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
172 if (adev->nbio.funcs &&
173 adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
174 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
175
176 if (adev->nbio.funcs &&
177 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
178 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
179 }
180
181 return ret;
182 }
183
184 /**
185 * amdgpu_irq_handle_ih1 - kick of processing for IH1
186 *
187 * @work: work structure in struct amdgpu_irq
188 *
189 * Kick of processing IH ring 1.
190 */
amdgpu_irq_handle_ih1(struct work_struct * work)191 static void amdgpu_irq_handle_ih1(struct work_struct *work)
192 {
193 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
194 irq.ih1_work);
195
196 amdgpu_ih_process(adev, &adev->irq.ih1);
197 }
198
199 /**
200 * amdgpu_irq_handle_ih2 - kick of processing for IH2
201 *
202 * @work: work structure in struct amdgpu_irq
203 *
204 * Kick of processing IH ring 2.
205 */
amdgpu_irq_handle_ih2(struct work_struct * work)206 static void amdgpu_irq_handle_ih2(struct work_struct *work)
207 {
208 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
209 irq.ih2_work);
210
211 amdgpu_ih_process(adev, &adev->irq.ih2);
212 }
213
214 /**
215 * amdgpu_msi_ok - check whether MSI functionality is enabled
216 *
217 * @adev: amdgpu device pointer (unused)
218 *
219 * Checks whether MSI functionality has been disabled via module parameter
220 * (all ASICs).
221 *
222 * Returns:
223 * *true* if MSIs are allowed to be enabled or *false* otherwise
224 */
amdgpu_msi_ok(struct amdgpu_device * adev)225 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
226 {
227 if (amdgpu_msi == 1)
228 return true;
229 else if (amdgpu_msi == 0)
230 return false;
231
232 return true;
233 }
234
235 /**
236 * amdgpu_irq_init - initialize interrupt handling
237 *
238 * @adev: amdgpu device pointer
239 *
240 * Sets up work functions for hotplug and reset interrupts, enables MSI
241 * functionality, initializes vblank, hotplug and reset interrupt handling.
242 *
243 * Returns:
244 * 0 on success or error code on failure
245 */
amdgpu_irq_init(struct amdgpu_device * adev)246 int amdgpu_irq_init(struct amdgpu_device *adev)
247 {
248 int r = 0;
249
250 spin_lock_init(&adev->irq.lock);
251
252 /* Enable MSI if not disabled by module parameter */
253 adev->irq.msi_enabled = false;
254
255 if (amdgpu_msi_ok(adev)) {
256 #ifdef __NetBSD__ /* XXX amdgpu msix */
257 if (pci_enable_msi(adev->pdev) == 0) {
258 adev->irq.msi_enabled = true;
259 dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
260 } else {
261 dev_err(adev->dev, "amdgpu: failed to enable MSI\n");
262 }
263 #else
264 int nvec = pci_msix_vec_count(adev->pdev);
265 unsigned int flags;
266
267 if (nvec <= 0) {
268 flags = PCI_IRQ_MSI;
269 } else {
270 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
271 }
272 /* we only need one vector */
273 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
274 if (nvec > 0) {
275 adev->irq.msi_enabled = true;
276 dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
277 }
278 #endif
279 }
280
281 if (!amdgpu_device_has_dc_support(adev)) {
282 if (!adev->enable_virtual_display)
283 /* Disable vblank IRQs aggressively for power-saving */
284 /* XXX: can this be enabled for DC? */
285 adev->ddev->vblank_disable_immediate = true;
286
287 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
288 if (r)
289 return r;
290
291 /* Pre-DCE11 */
292 INIT_WORK(&adev->hotplug_work,
293 amdgpu_hotplug_work_func);
294 }
295
296 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
297 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
298
299 adev->irq.installed = true;
300 #ifdef __NetBSD__ /* XXX post-merge address comment below */
301 r = drm_irq_install(adev->ddev);
302 #else
303 /* Use vector 0 for MSI-X */
304 r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
305 #endif
306 if (r) {
307 adev->irq.installed = false;
308 if (!amdgpu_device_has_dc_support(adev))
309 flush_work(&adev->hotplug_work);
310 return r;
311 }
312 adev->ddev->max_vblank_count = 0x00ffffff;
313
314 DRM_DEBUG("amdgpu: irq initialized.\n");
315 return 0;
316 }
317
318 /**
319 * amdgpu_irq_fini - shut down interrupt handling
320 *
321 * @adev: amdgpu device pointer
322 *
323 * Tears down work functions for hotplug and reset interrupts, disables MSI
324 * functionality, shuts down vblank, hotplug and reset interrupt handling,
325 * turns off interrupts from all sources (all ASICs).
326 */
amdgpu_irq_fini(struct amdgpu_device * adev)327 void amdgpu_irq_fini(struct amdgpu_device *adev)
328 {
329 unsigned i, j;
330
331 if (adev->irq.installed) {
332 drm_irq_uninstall(adev->ddev);
333 adev->irq.installed = false;
334 #ifndef __NetBSD__ /* XXX amdgpu msix */
335 if (adev->irq.msi_enabled)
336 pci_free_irq_vectors(adev->pdev);
337 #endif
338 if (!amdgpu_device_has_dc_support(adev))
339 flush_work(&adev->hotplug_work);
340 }
341
342 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
343 if (!adev->irq.client[i].sources)
344 continue;
345
346 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
347 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
348
349 if (!src)
350 continue;
351
352 kfree(src->enabled_types);
353 src->enabled_types = NULL;
354 if (src->data) {
355 kfree(src->data);
356 kfree(src);
357 adev->irq.client[i].sources[j] = NULL;
358 }
359 }
360 kfree(adev->irq.client[i].sources);
361 adev->irq.client[i].sources = NULL;
362 }
363
364 spin_lock_destroy(&adev->irq.lock);
365 }
366
367 /**
368 * amdgpu_irq_add_id - register IRQ source
369 *
370 * @adev: amdgpu device pointer
371 * @client_id: client id
372 * @src_id: source id
373 * @source: IRQ source pointer
374 *
375 * Registers IRQ source on a client.
376 *
377 * Returns:
378 * 0 on success or error code otherwise
379 */
amdgpu_irq_add_id(struct amdgpu_device * adev,unsigned client_id,unsigned src_id,struct amdgpu_irq_src * source)380 int amdgpu_irq_add_id(struct amdgpu_device *adev,
381 unsigned client_id, unsigned src_id,
382 struct amdgpu_irq_src *source)
383 {
384 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
385 return -EINVAL;
386
387 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
388 return -EINVAL;
389
390 if (!source->funcs)
391 return -EINVAL;
392
393 if (!adev->irq.client[client_id].sources) {
394 adev->irq.client[client_id].sources =
395 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
396 sizeof(struct amdgpu_irq_src *),
397 GFP_KERNEL);
398 if (!adev->irq.client[client_id].sources)
399 return -ENOMEM;
400 }
401
402 if (adev->irq.client[client_id].sources[src_id] != NULL)
403 return -EINVAL;
404
405 if (source->num_types && !source->enabled_types) {
406 atomic_t *types;
407
408 types = kcalloc(source->num_types, sizeof(atomic_t),
409 GFP_KERNEL);
410 if (!types)
411 return -ENOMEM;
412
413 source->enabled_types = types;
414 }
415
416 adev->irq.client[client_id].sources[src_id] = source;
417 return 0;
418 }
419
420 /**
421 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
422 *
423 * @adev: amdgpu device pointer
424 * @ih: interrupt ring instance
425 *
426 * Dispatches IRQ to IP blocks.
427 */
amdgpu_irq_dispatch(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)428 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
429 struct amdgpu_ih_ring *ih)
430 {
431 u32 ring_index = ih->rptr >> 2;
432 struct amdgpu_iv_entry entry;
433 unsigned client_id, src_id;
434 struct amdgpu_irq_src *src;
435 bool handled = false;
436 int r;
437
438 entry.iv_entry = (const uint32_t *)__UNVOLATILE(&ih->ring[ring_index]);
439 amdgpu_ih_decode_iv(adev, &entry);
440
441 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
442
443 client_id = entry.client_id;
444 src_id = entry.src_id;
445
446 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
447 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
448
449 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
450 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
451
452 #ifndef __NetBSD__ /* XXX amdgpu irq */
453 } else if (adev->irq.virq[src_id]) {
454 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
455 #endif
456
457 } else if (!adev->irq.client[client_id].sources) {
458 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
459 client_id, src_id);
460
461 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
462 r = src->funcs->process(adev, src, &entry);
463 if (r < 0)
464 DRM_ERROR("error processing interrupt (%d)\n", r);
465 else if (r)
466 handled = true;
467
468 } else {
469 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
470 }
471
472 /* Send it to amdkfd as well if it isn't already handled */
473 if (!handled)
474 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
475 }
476
477 /**
478 * amdgpu_irq_update - update hardware interrupt state
479 *
480 * @adev: amdgpu device pointer
481 * @src: interrupt source pointer
482 * @type: type of interrupt
483 *
484 * Updates interrupt state for the specific source (all ASICs).
485 */
amdgpu_irq_update(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)486 int amdgpu_irq_update(struct amdgpu_device *adev,
487 struct amdgpu_irq_src *src, unsigned type)
488 {
489 unsigned long irqflags;
490 enum amdgpu_interrupt_state state;
491 int r;
492
493 spin_lock_irqsave(&adev->irq.lock, irqflags);
494
495 /* We need to determine after taking the lock, otherwise
496 we might disable just enabled interrupts again */
497 if (amdgpu_irq_enabled(adev, src, type))
498 state = AMDGPU_IRQ_STATE_ENABLE;
499 else
500 state = AMDGPU_IRQ_STATE_DISABLE;
501
502 r = src->funcs->set(adev, src, type, state);
503 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
504 return r;
505 }
506
507 /**
508 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
509 *
510 * @adev: amdgpu device pointer
511 *
512 * Updates state of all types of interrupts on all sources on resume after
513 * reset.
514 */
amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)515 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
516 {
517 int i, j, k;
518
519 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
520 if (!adev->irq.client[i].sources)
521 continue;
522
523 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
524 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
525
526 if (!src)
527 continue;
528 for (k = 0; k < src->num_types; k++)
529 amdgpu_irq_update(adev, src, k);
530 }
531 }
532 }
533
534 /**
535 * amdgpu_irq_get - enable interrupt
536 *
537 * @adev: amdgpu device pointer
538 * @src: interrupt source pointer
539 * @type: type of interrupt
540 *
541 * Enables specified type of interrupt on the specified source (all ASICs).
542 *
543 * Returns:
544 * 0 on success or error code otherwise
545 */
amdgpu_irq_get(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)546 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
547 unsigned type)
548 {
549 if (!adev->ddev->irq_enabled)
550 return -ENOENT;
551
552 if (type >= src->num_types)
553 return -EINVAL;
554
555 if (!src->enabled_types || !src->funcs->set)
556 return -EINVAL;
557
558 if (atomic_inc_return(&src->enabled_types[type]) == 1)
559 return amdgpu_irq_update(adev, src, type);
560
561 return 0;
562 }
563
564 /**
565 * amdgpu_irq_put - disable interrupt
566 *
567 * @adev: amdgpu device pointer
568 * @src: interrupt source pointer
569 * @type: type of interrupt
570 *
571 * Enables specified type of interrupt on the specified source (all ASICs).
572 *
573 * Returns:
574 * 0 on success or error code otherwise
575 */
amdgpu_irq_put(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)576 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
577 unsigned type)
578 {
579 if (!adev->ddev->irq_enabled)
580 return -ENOENT;
581
582 if (type >= src->num_types)
583 return -EINVAL;
584
585 if (!src->enabled_types || !src->funcs->set)
586 return -EINVAL;
587
588 if (atomic_dec_and_test(&src->enabled_types[type]))
589 return amdgpu_irq_update(adev, src, type);
590
591 return 0;
592 }
593
594 /**
595 * amdgpu_irq_enabled - check whether interrupt is enabled or not
596 *
597 * @adev: amdgpu device pointer
598 * @src: interrupt source pointer
599 * @type: type of interrupt
600 *
601 * Checks whether the given type of interrupt is enabled on the given source.
602 *
603 * Returns:
604 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
605 * invalid parameters
606 */
amdgpu_irq_enabled(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)607 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
608 unsigned type)
609 {
610 if (!adev->ddev->irq_enabled)
611 return false;
612
613 if (type >= src->num_types)
614 return false;
615
616 if (!src->enabled_types || !src->funcs->set)
617 return false;
618
619 return !!atomic_read(&src->enabled_types[type]);
620 }
621
622 #ifndef __NetBSD__ /* XXX amdgpu irq domain */
623
624 /* XXX: Generic IRQ handling */
amdgpu_irq_mask(struct irq_data * irqd)625 static void amdgpu_irq_mask(struct irq_data *irqd)
626 {
627 /* XXX */
628 }
629
amdgpu_irq_unmask(struct irq_data * irqd)630 static void amdgpu_irq_unmask(struct irq_data *irqd)
631 {
632 /* XXX */
633 }
634
635 /* amdgpu hardware interrupt chip descriptor */
636 static struct irq_chip amdgpu_irq_chip = {
637 .name = "amdgpu-ih",
638 .irq_mask = amdgpu_irq_mask,
639 .irq_unmask = amdgpu_irq_unmask,
640 };
641
642 /**
643 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
644 *
645 * @d: amdgpu IRQ domain pointer (unused)
646 * @irq: virtual IRQ number
647 * @hwirq: hardware irq number
648 *
649 * Current implementation assigns simple interrupt handler to the given virtual
650 * IRQ.
651 *
652 * Returns:
653 * 0 on success or error code otherwise
654 */
amdgpu_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)655 static int amdgpu_irqdomain_map(struct irq_domain *d,
656 unsigned int irq, irq_hw_number_t hwirq)
657 {
658 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
659 return -EPERM;
660
661 irq_set_chip_and_handler(irq,
662 &amdgpu_irq_chip, handle_simple_irq);
663 return 0;
664 }
665
666 /* Implementation of methods for amdgpu IRQ domain */
667 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
668 .map = amdgpu_irqdomain_map,
669 };
670
671 #endif /* __NetBSD__ */
672
673 /**
674 * amdgpu_irq_add_domain - create a linear IRQ domain
675 *
676 * @adev: amdgpu device pointer
677 *
678 * Creates an IRQ domain for GPU interrupt sources
679 * that may be driven by another driver (e.g., ACP).
680 *
681 * Returns:
682 * 0 on success or error code otherwise
683 */
amdgpu_irq_add_domain(struct amdgpu_device * adev)684 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
685 {
686 #ifndef __NetBSD__ /* XXX amdgpu irq domain */
687 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
688 &amdgpu_hw_irqdomain_ops, adev);
689 if (!adev->irq.domain) {
690 DRM_ERROR("GPU irq add domain failed\n");
691 return -ENODEV;
692 }
693 #endif
694
695 return 0;
696 }
697
698 /**
699 * amdgpu_irq_remove_domain - remove the IRQ domain
700 *
701 * @adev: amdgpu device pointer
702 *
703 * Removes the IRQ domain for GPU interrupt sources
704 * that may be driven by another driver (e.g., ACP).
705 */
amdgpu_irq_remove_domain(struct amdgpu_device * adev)706 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
707 {
708 #ifndef __NetBSD__ /* XXX amdgpu irq domain */
709 if (adev->irq.domain) {
710 irq_domain_remove(adev->irq.domain);
711 adev->irq.domain = NULL;
712 }
713 #endif
714 }
715
716 /**
717 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
718 *
719 * @adev: amdgpu device pointer
720 * @src_id: IH source id
721 *
722 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
723 * Use this for components that generate a GPU interrupt, but are driven
724 * by a different driver (e.g., ACP).
725 *
726 * Returns:
727 * Linux IRQ
728 */
amdgpu_irq_create_mapping(struct amdgpu_device * adev,unsigned src_id)729 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
730 {
731 #ifdef __NetBSD__ /* XXX amdgpu irq domain */
732 return 0;
733 #else
734 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
735
736 return adev->irq.virq[src_id];
737 #endif
738 }
739