1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
33
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/ttm/ttm_tt.h>
37 #include <drm/drm_exec.h>
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
41 #include "amdgpu_gmc.h"
42 #include "amdgpu_xgmi.h"
43 #include "amdgpu_dma_buf.h"
44 #include "amdgpu_res_cursor.h"
45 #include "kfd_svm.h"
46
47 /**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89 #define START(node) ((node)->start)
90 #define LAST(node) ((node)->last)
91
92 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95 #undef START
96 #undef LAST
97
98 /**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101 struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112 };
113
114 /**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117 struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127 };
128
129 /**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
amdgpu_vm_set_pasid(struct amdgpu_device * adev,struct amdgpu_vm * vm,u32 pasid)140 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142 {
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167 }
168
169 /**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base * vm_bo)177 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178 {
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189 }
190 /**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base * vm_bo)198 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199 {
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203 }
204
205 /**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base * vm_bo)213 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214 {
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219 }
220
221 /**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base * vm_bo)229 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230 {
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234 }
235
236 /**
237 * amdgpu_vm_bo_evicted_user - vm_bo is evicted
238 *
239 * @vm_bo: vm_bo which is evicted
240 *
241 * State for BOs used by user mode queues which are not at the location they
242 * should be.
243 */
amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base * vm_bo)244 static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)
245 {
246 vm_bo->moved = true;
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user);
249 spin_unlock(&vm_bo->vm->status_lock);
250 }
251
252 /**
253 * amdgpu_vm_bo_relocated - vm_bo is reloacted
254 *
255 * @vm_bo: vm_bo which is relocated
256 *
257 * State for PDs/PTs which needs to update their parent PD.
258 * For the root PD, just move to idle state.
259 */
amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base * vm_bo)260 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
261 {
262 if (vm_bo->bo->parent) {
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
265 spin_unlock(&vm_bo->vm->status_lock);
266 } else {
267 amdgpu_vm_bo_idle(vm_bo);
268 }
269 }
270
271 /**
272 * amdgpu_vm_bo_done - vm_bo is done
273 *
274 * @vm_bo: vm_bo which is now done
275 *
276 * State for normal BOs which are invalidated and that change has been updated
277 * in the PTs.
278 */
amdgpu_vm_bo_done(struct amdgpu_vm_bo_base * vm_bo)279 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
280 {
281 spin_lock(&vm_bo->vm->status_lock);
282 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
283 spin_unlock(&vm_bo->vm->status_lock);
284 }
285
286 /**
287 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
288 * @vm: the VM which state machine to reset
289 *
290 * Move all vm_bo object in the VM into a state where they will be updated
291 * again during validation.
292 */
amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm * vm)293 static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
294 {
295 struct amdgpu_vm_bo_base *vm_bo, *tmp;
296
297 spin_lock(&vm->status_lock);
298 list_splice_init(&vm->done, &vm->invalidated);
299 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
300 vm_bo->moved = true;
301 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
302 struct amdgpu_bo *bo = vm_bo->bo;
303
304 vm_bo->moved = true;
305 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
306 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
307 else if (bo->parent)
308 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
309 }
310 spin_unlock(&vm->status_lock);
311 }
312
313 /**
314 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
315 *
316 * @base: base structure for tracking BO usage in a VM
317 * @vm: vm to which bo is to be added
318 * @bo: amdgpu buffer object
319 *
320 * Initialize a bo_va_base structure and add it to the appropriate lists
321 *
322 */
amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base * base,struct amdgpu_vm * vm,struct amdgpu_bo * bo)323 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
324 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
325 {
326 base->vm = vm;
327 base->bo = bo;
328 base->next = NULL;
329 INIT_LIST_HEAD(&base->vm_status);
330
331 if (!bo)
332 return;
333 base->next = bo->vm_bo;
334 bo->vm_bo = base;
335
336 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
337 return;
338
339 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
340
341 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
342 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
343 amdgpu_vm_bo_relocated(base);
344 else
345 amdgpu_vm_bo_idle(base);
346
347 if (bo->preferred_domains &
348 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
349 return;
350
351 /*
352 * we checked all the prerequisites, but it looks like this per vm bo
353 * is currently evicted. add the bo to the evicted list to make sure it
354 * is validated on next vm use to avoid fault.
355 * */
356 amdgpu_vm_bo_evicted(base);
357 }
358
359 /**
360 * amdgpu_vm_lock_pd - lock PD in drm_exec
361 *
362 * @vm: vm providing the BOs
363 * @exec: drm execution context
364 * @num_fences: number of extra fences to reserve
365 *
366 * Lock the VM root PD in the DRM execution context.
367 */
amdgpu_vm_lock_pd(struct amdgpu_vm * vm,struct drm_exec * exec,unsigned int num_fences)368 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
369 unsigned int num_fences)
370 {
371 /* We need at least two fences for the VM PD/PT updates */
372 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
373 2 + num_fences);
374 }
375
376 /**
377 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
378 *
379 * @adev: amdgpu device pointer
380 * @vm: vm providing the BOs
381 *
382 * Move all BOs to the end of LRU and remember their positions to put them
383 * together.
384 */
amdgpu_vm_move_to_lru_tail(struct amdgpu_device * adev,struct amdgpu_vm * vm)385 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
386 struct amdgpu_vm *vm)
387 {
388 spin_lock(&adev->mman.bdev.lru_lock);
389 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
390 spin_unlock(&adev->mman.bdev.lru_lock);
391 }
392
393 /* Create scheduler entities for page table updates */
amdgpu_vm_init_entities(struct amdgpu_device * adev,struct amdgpu_vm * vm)394 static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm)
396 {
397 int r;
398
399 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
400 adev->vm_manager.vm_pte_scheds,
401 adev->vm_manager.vm_pte_num_scheds, NULL);
402 if (r)
403 goto error;
404
405 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
406 adev->vm_manager.vm_pte_scheds,
407 adev->vm_manager.vm_pte_num_scheds, NULL);
408
409 error:
410 drm_sched_entity_destroy(&vm->immediate);
411 return r;
412 }
413
414 /* Destroy the entities for page table updates again */
amdgpu_vm_fini_entities(struct amdgpu_vm * vm)415 static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
416 {
417 drm_sched_entity_destroy(&vm->immediate);
418 drm_sched_entity_destroy(&vm->delayed);
419 }
420
421 /**
422 * amdgpu_vm_generation - return the page table re-generation counter
423 * @adev: the amdgpu_device
424 * @vm: optional VM to check, might be NULL
425 *
426 * Returns a page table re-generation token to allow checking if submissions
427 * are still valid to use this VM. The VM parameter might be NULL in which case
428 * just the VRAM lost counter will be used.
429 */
amdgpu_vm_generation(struct amdgpu_device * adev,struct amdgpu_vm * vm)430 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
431 {
432 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
433
434 if (!vm)
435 return result;
436
437 result += vm->generation;
438 /* Add one if the page tables will be re-generated on next CS */
439 if (drm_sched_entity_error(&vm->delayed))
440 ++result;
441
442 return result;
443 }
444
445 /**
446 * amdgpu_vm_validate - validate evicted BOs tracked in the VM
447 *
448 * @adev: amdgpu device pointer
449 * @vm: vm providing the BOs
450 * @ticket: optional reservation ticket used to reserve the VM
451 * @validate: callback to do the validation
452 * @param: parameter for the validation callback
453 *
454 * Validate the page table BOs and per-VM BOs on command submission if
455 * necessary. If a ticket is given, also try to validate evicted user queue
456 * BOs. They must already be reserved with the given ticket.
457 *
458 * Returns:
459 * Validation result.
460 */
amdgpu_vm_validate(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct ww_acquire_ctx * ticket,int (* validate)(void * p,struct amdgpu_bo * bo),void * param)461 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
462 struct ww_acquire_ctx *ticket,
463 int (*validate)(void *p, struct amdgpu_bo *bo),
464 void *param)
465 {
466 struct amdgpu_vm_bo_base *bo_base;
467 struct amdgpu_bo *shadow;
468 struct amdgpu_bo *bo;
469 int r;
470
471 if (drm_sched_entity_error(&vm->delayed)) {
472 ++vm->generation;
473 amdgpu_vm_bo_reset_state_machine(vm);
474 amdgpu_vm_fini_entities(vm);
475 r = amdgpu_vm_init_entities(adev, vm);
476 if (r)
477 return r;
478 }
479
480 spin_lock(&vm->status_lock);
481 while (!list_empty(&vm->evicted)) {
482 bo_base = list_first_entry(&vm->evicted,
483 struct amdgpu_vm_bo_base,
484 vm_status);
485 spin_unlock(&vm->status_lock);
486
487 bo = bo_base->bo;
488 shadow = amdgpu_bo_shadowed(bo);
489
490 r = validate(param, bo);
491 if (r)
492 return r;
493 if (shadow) {
494 r = validate(param, shadow);
495 if (r)
496 return r;
497 }
498
499 if (bo->tbo.type != ttm_bo_type_kernel) {
500 amdgpu_vm_bo_moved(bo_base);
501 } else {
502 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
503 amdgpu_vm_bo_relocated(bo_base);
504 }
505 spin_lock(&vm->status_lock);
506 }
507 while (ticket && !list_empty(&vm->evicted_user)) {
508 bo_base = list_first_entry(&vm->evicted_user,
509 struct amdgpu_vm_bo_base,
510 vm_status);
511 spin_unlock(&vm->status_lock);
512
513 bo = bo_base->bo;
514
515 if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) {
516 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
517
518 pr_warn_ratelimited("Evicted user BO is not reserved\n");
519 if (ti) {
520 pr_warn_ratelimited("pid %d\n", ti->pid);
521 amdgpu_vm_put_task_info(ti);
522 }
523
524 return -EINVAL;
525 }
526
527 r = validate(param, bo);
528 if (r)
529 return r;
530
531 amdgpu_vm_bo_invalidated(bo_base);
532
533 spin_lock(&vm->status_lock);
534 }
535 spin_unlock(&vm->status_lock);
536
537 amdgpu_vm_eviction_lock(vm);
538 vm->evicting = false;
539 amdgpu_vm_eviction_unlock(vm);
540
541 return 0;
542 }
543
544 /**
545 * amdgpu_vm_ready - check VM is ready for updates
546 *
547 * @vm: VM to check
548 *
549 * Check if all VM PDs/PTs are ready for updates
550 *
551 * Returns:
552 * True if VM is not evicting.
553 */
amdgpu_vm_ready(struct amdgpu_vm * vm)554 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
555 {
556 bool empty;
557 bool ret;
558
559 amdgpu_vm_eviction_lock(vm);
560 ret = !vm->evicting;
561 amdgpu_vm_eviction_unlock(vm);
562
563 spin_lock(&vm->status_lock);
564 empty = list_empty(&vm->evicted);
565 spin_unlock(&vm->status_lock);
566
567 return ret && empty;
568 }
569
570 /**
571 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
572 *
573 * @adev: amdgpu_device pointer
574 */
amdgpu_vm_check_compute_bug(struct amdgpu_device * adev)575 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
576 {
577 const struct amdgpu_ip_block *ip_block;
578 bool has_compute_vm_bug;
579 struct amdgpu_ring *ring;
580 int i;
581
582 has_compute_vm_bug = false;
583
584 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
585 if (ip_block) {
586 /* Compute has a VM bug for GFX version < 7.
587 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
588 if (ip_block->version->major <= 7)
589 has_compute_vm_bug = true;
590 else if (ip_block->version->major == 8)
591 if (adev->gfx.mec_fw_version < 673)
592 has_compute_vm_bug = true;
593 }
594
595 for (i = 0; i < adev->num_rings; i++) {
596 ring = adev->rings[i];
597 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
598 /* only compute rings */
599 ring->has_compute_vm_bug = has_compute_vm_bug;
600 else
601 ring->has_compute_vm_bug = false;
602 }
603 }
604
605 /**
606 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
607 *
608 * @ring: ring on which the job will be submitted
609 * @job: job to submit
610 *
611 * Returns:
612 * True if sync is needed.
613 */
amdgpu_vm_need_pipeline_sync(struct amdgpu_ring * ring,struct amdgpu_job * job)614 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
615 struct amdgpu_job *job)
616 {
617 struct amdgpu_device *adev = ring->adev;
618 unsigned vmhub = ring->vm_hub;
619 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
620
621 if (job->vmid == 0)
622 return false;
623
624 if (job->vm_needs_flush || ring->has_compute_vm_bug)
625 return true;
626
627 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
628 return true;
629
630 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
631 return true;
632
633 return false;
634 }
635
636 /**
637 * amdgpu_vm_flush - hardware flush the vm
638 *
639 * @ring: ring to use for flush
640 * @job: related job
641 * @need_pipe_sync: is pipe sync needed
642 *
643 * Emit a VM flush when it is necessary.
644 *
645 * Returns:
646 * 0 on success, errno otherwise.
647 */
amdgpu_vm_flush(struct amdgpu_ring * ring,struct amdgpu_job * job,bool need_pipe_sync)648 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
649 bool need_pipe_sync)
650 {
651 struct amdgpu_device *adev = ring->adev;
652 unsigned vmhub = ring->vm_hub;
653 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
654 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
655 bool spm_update_needed = job->spm_update_needed;
656 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
657 job->gds_switch_needed;
658 bool vm_flush_needed = job->vm_needs_flush;
659 struct dma_fence *fence = NULL;
660 bool pasid_mapping_needed = false;
661 unsigned int patch;
662 int r;
663
664 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
665 gds_switch_needed = true;
666 vm_flush_needed = true;
667 pasid_mapping_needed = true;
668 spm_update_needed = true;
669 }
670
671 mutex_lock(&id_mgr->lock);
672 if (id->pasid != job->pasid || !id->pasid_mapping ||
673 !dma_fence_is_signaled(id->pasid_mapping))
674 pasid_mapping_needed = true;
675 mutex_unlock(&id_mgr->lock);
676
677 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
678 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
679 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
680 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
681 ring->funcs->emit_wreg;
682
683 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
684 return 0;
685
686 amdgpu_ring_ib_begin(ring);
687 if (ring->funcs->init_cond_exec)
688 patch = amdgpu_ring_init_cond_exec(ring,
689 ring->cond_exe_gpu_addr);
690
691 if (need_pipe_sync)
692 amdgpu_ring_emit_pipeline_sync(ring);
693
694 if (vm_flush_needed) {
695 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
696 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
697 }
698
699 if (pasid_mapping_needed)
700 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
701
702 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
703 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
704
705 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
706 gds_switch_needed) {
707 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
708 job->gds_size, job->gws_base,
709 job->gws_size, job->oa_base,
710 job->oa_size);
711 }
712
713 if (vm_flush_needed || pasid_mapping_needed) {
714 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
715 if (r)
716 return r;
717 }
718
719 if (vm_flush_needed) {
720 mutex_lock(&id_mgr->lock);
721 dma_fence_put(id->last_flush);
722 id->last_flush = dma_fence_get(fence);
723 id->current_gpu_reset_count =
724 atomic_read(&adev->gpu_reset_counter);
725 mutex_unlock(&id_mgr->lock);
726 }
727
728 if (pasid_mapping_needed) {
729 mutex_lock(&id_mgr->lock);
730 id->pasid = job->pasid;
731 dma_fence_put(id->pasid_mapping);
732 id->pasid_mapping = dma_fence_get(fence);
733 mutex_unlock(&id_mgr->lock);
734 }
735 dma_fence_put(fence);
736
737 amdgpu_ring_patch_cond_exec(ring, patch);
738
739 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
740 if (ring->funcs->emit_switch_buffer) {
741 amdgpu_ring_emit_switch_buffer(ring);
742 amdgpu_ring_emit_switch_buffer(ring);
743 }
744 amdgpu_ring_ib_end(ring);
745 return 0;
746 }
747
748 /**
749 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
750 *
751 * @vm: requested vm
752 * @bo: requested buffer object
753 *
754 * Find @bo inside the requested vm.
755 * Search inside the @bos vm list for the requested vm
756 * Returns the found bo_va or NULL if none is found
757 *
758 * Object has to be reserved!
759 *
760 * Returns:
761 * Found bo_va or NULL.
762 */
amdgpu_vm_bo_find(struct amdgpu_vm * vm,struct amdgpu_bo * bo)763 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
764 struct amdgpu_bo *bo)
765 {
766 struct amdgpu_vm_bo_base *base;
767
768 for (base = bo->vm_bo; base; base = base->next) {
769 if (base->vm != vm)
770 continue;
771
772 return container_of(base, struct amdgpu_bo_va, base);
773 }
774 return NULL;
775 }
776
777 /**
778 * amdgpu_vm_map_gart - Resolve gart mapping of addr
779 *
780 * @pages_addr: optional DMA address to use for lookup
781 * @addr: the unmapped addr
782 *
783 * Look up the physical address of the page that the pte resolves
784 * to.
785 *
786 * Returns:
787 * The pointer for the page table entry.
788 */
amdgpu_vm_map_gart(const dma_addr_t * pages_addr,uint64_t addr)789 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
790 {
791 uint64_t result;
792
793 /* page table offset */
794 result = pages_addr[addr >> PAGE_SHIFT];
795
796 /* in case cpu page size != gpu page size*/
797 result |= addr & (~PAGE_MASK);
798
799 result &= 0xFFFFFFFFFFFFF000ULL;
800
801 return result;
802 }
803
804 /**
805 * amdgpu_vm_update_pdes - make sure that all directories are valid
806 *
807 * @adev: amdgpu_device pointer
808 * @vm: requested vm
809 * @immediate: submit immediately to the paging queue
810 *
811 * Makes sure all directories are up to date.
812 *
813 * Returns:
814 * 0 for success, error for failure.
815 */
amdgpu_vm_update_pdes(struct amdgpu_device * adev,struct amdgpu_vm * vm,bool immediate)816 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
817 struct amdgpu_vm *vm, bool immediate)
818 {
819 struct amdgpu_vm_update_params params;
820 struct amdgpu_vm_bo_base *entry;
821 bool flush_tlb_needed = false;
822 LIST_HEAD(relocated);
823 int r, idx;
824
825 spin_lock(&vm->status_lock);
826 list_splice_init(&vm->relocated, &relocated);
827 spin_unlock(&vm->status_lock);
828
829 if (list_empty(&relocated))
830 return 0;
831
832 if (!drm_dev_enter(adev_to_drm(adev), &idx))
833 return -ENODEV;
834
835 memset(¶ms, 0, sizeof(params));
836 params.adev = adev;
837 params.vm = vm;
838 params.immediate = immediate;
839
840 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
841 if (r)
842 goto error;
843
844 list_for_each_entry(entry, &relocated, vm_status) {
845 /* vm_flush_needed after updating moved PDEs */
846 flush_tlb_needed |= entry->moved;
847
848 r = amdgpu_vm_pde_update(¶ms, entry);
849 if (r)
850 goto error;
851 }
852
853 r = vm->update_funcs->commit(¶ms, &vm->last_update);
854 if (r)
855 goto error;
856
857 if (flush_tlb_needed)
858 atomic64_inc(&vm->tlb_seq);
859
860 while (!list_empty(&relocated)) {
861 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
862 vm_status);
863 amdgpu_vm_bo_idle(entry);
864 }
865
866 error:
867 drm_dev_exit(idx);
868 return r;
869 }
870
871 /**
872 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
873 * @fence: unused
874 * @cb: the callback structure
875 *
876 * Increments the tlb sequence to make sure that future CS execute a VM flush.
877 */
amdgpu_vm_tlb_seq_cb(struct dma_fence * fence,struct dma_fence_cb * cb)878 static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
879 struct dma_fence_cb *cb)
880 {
881 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
882
883 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
884 atomic64_inc(&tlb_cb->vm->tlb_seq);
885 kfree(tlb_cb);
886 }
887
888 /**
889 * amdgpu_vm_tlb_flush - prepare TLB flush
890 *
891 * @params: parameters for update
892 * @fence: input fence to sync TLB flush with
893 * @tlb_cb: the callback structure
894 *
895 * Increments the tlb sequence to make sure that future CS execute a VM flush.
896 */
897 static void
amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params * params,struct dma_fence ** fence,struct amdgpu_vm_tlb_seq_struct * tlb_cb)898 amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,
899 struct dma_fence **fence,
900 struct amdgpu_vm_tlb_seq_struct *tlb_cb)
901 {
902 struct amdgpu_vm *vm = params->vm;
903
904 if (!fence || !*fence)
905 return;
906
907 tlb_cb->vm = vm;
908 if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
909 amdgpu_vm_tlb_seq_cb)) {
910 dma_fence_put(vm->last_tlb_flush);
911 vm->last_tlb_flush = dma_fence_get(*fence);
912 } else {
913 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
914 }
915
916 /* Prepare a TLB flush fence to be attached to PTs */
917 if (!params->unlocked && vm->is_compute_context) {
918 amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
919
920 /* Makes sure no PD/PT is freed before the flush */
921 dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence,
922 DMA_RESV_USAGE_BOOKKEEP);
923 }
924 }
925
926 /**
927 * amdgpu_vm_update_range - update a range in the vm page table
928 *
929 * @adev: amdgpu_device pointer to use for commands
930 * @vm: the VM to update the range
931 * @immediate: immediate submission in a page fault
932 * @unlocked: unlocked invalidation during MM callback
933 * @flush_tlb: trigger tlb invalidation after update completed
934 * @allow_override: change MTYPE for local NUMA nodes
935 * @resv: fences we need to sync to
936 * @start: start of mapped range
937 * @last: last mapped entry
938 * @flags: flags for the entries
939 * @offset: offset into nodes and pages_addr
940 * @vram_base: base for vram mappings
941 * @res: ttm_resource to map
942 * @pages_addr: DMA addresses to use for mapping
943 * @fence: optional resulting fence
944 *
945 * Fill in the page table entries between @start and @last.
946 *
947 * Returns:
948 * 0 for success, negative erro code for failure.
949 */
amdgpu_vm_update_range(struct amdgpu_device * adev,struct amdgpu_vm * vm,bool immediate,bool unlocked,bool flush_tlb,bool allow_override,struct dma_resv * resv,uint64_t start,uint64_t last,uint64_t flags,uint64_t offset,uint64_t vram_base,struct ttm_resource * res,dma_addr_t * pages_addr,struct dma_fence ** fence)950 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
951 bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
952 struct dma_resv *resv, uint64_t start, uint64_t last,
953 uint64_t flags, uint64_t offset, uint64_t vram_base,
954 struct ttm_resource *res, dma_addr_t *pages_addr,
955 struct dma_fence **fence)
956 {
957 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
958 struct amdgpu_vm_update_params params;
959 struct amdgpu_res_cursor cursor;
960 enum amdgpu_sync_mode sync_mode;
961 int r, idx;
962
963 if (!drm_dev_enter(adev_to_drm(adev), &idx))
964 return -ENODEV;
965
966 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
967 if (!tlb_cb) {
968 drm_dev_exit(idx);
969 return -ENOMEM;
970 }
971
972 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
973 * heavy-weight flush TLB unconditionally.
974 */
975 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
976 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
977
978 /*
979 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
980 */
981 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
982
983 memset(¶ms, 0, sizeof(params));
984 params.adev = adev;
985 params.vm = vm;
986 params.immediate = immediate;
987 params.pages_addr = pages_addr;
988 params.unlocked = unlocked;
989 params.needs_flush = flush_tlb;
990 params.allow_override = allow_override;
991 INIT_LIST_HEAD(¶ms.tlb_flush_waitlist);
992
993 /* Implicitly sync to command submissions in the same VM before
994 * unmapping. Sync to moving fences before mapping.
995 */
996 if (!(flags & AMDGPU_PTE_VALID))
997 sync_mode = AMDGPU_SYNC_EQ_OWNER;
998 else
999 sync_mode = AMDGPU_SYNC_EXPLICIT;
1000
1001 amdgpu_vm_eviction_lock(vm);
1002 if (vm->evicting) {
1003 r = -EBUSY;
1004 goto error_free;
1005 }
1006
1007 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1008 struct dma_fence *tmp = dma_fence_get_stub();
1009
1010 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1011 swap(vm->last_unlocked, tmp);
1012 dma_fence_put(tmp);
1013 }
1014
1015 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1016 if (r)
1017 goto error_free;
1018
1019 amdgpu_res_first(pages_addr ? NULL : res, offset,
1020 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1021 while (cursor.remaining) {
1022 uint64_t tmp, num_entries, addr;
1023
1024 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1025 if (pages_addr) {
1026 bool contiguous = true;
1027
1028 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1029 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1030 uint64_t count;
1031
1032 contiguous = pages_addr[pfn + 1] ==
1033 pages_addr[pfn] + PAGE_SIZE;
1034
1035 tmp = num_entries /
1036 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1037 for (count = 2; count < tmp; ++count) {
1038 uint64_t idx = pfn + count;
1039
1040 if (contiguous != (pages_addr[idx] ==
1041 pages_addr[idx - 1] + PAGE_SIZE))
1042 break;
1043 }
1044 if (!contiguous)
1045 count--;
1046 num_entries = count *
1047 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1048 }
1049
1050 if (!contiguous) {
1051 addr = cursor.start;
1052 params.pages_addr = pages_addr;
1053 } else {
1054 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1055 params.pages_addr = NULL;
1056 }
1057
1058 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1059 addr = vram_base + cursor.start;
1060 } else {
1061 addr = 0;
1062 }
1063
1064 tmp = start + num_entries;
1065 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
1066 if (r)
1067 goto error_free;
1068
1069 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1070 start = tmp;
1071 }
1072
1073 r = vm->update_funcs->commit(¶ms, fence);
1074 if (r)
1075 goto error_free;
1076
1077 if (params.needs_flush) {
1078 amdgpu_vm_tlb_flush(¶ms, fence, tlb_cb);
1079 tlb_cb = NULL;
1080 }
1081
1082 amdgpu_vm_pt_free_list(adev, ¶ms);
1083
1084 error_free:
1085 kfree(tlb_cb);
1086 amdgpu_vm_eviction_unlock(vm);
1087 drm_dev_exit(idx);
1088 return r;
1089 }
1090
amdgpu_vm_bo_get_memory(struct amdgpu_bo_va * bo_va,struct amdgpu_mem_stats * stats)1091 static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1092 struct amdgpu_mem_stats *stats)
1093 {
1094 struct amdgpu_vm *vm = bo_va->base.vm;
1095 struct amdgpu_bo *bo = bo_va->base.bo;
1096
1097 if (!bo)
1098 return;
1099
1100 /*
1101 * For now ignore BOs which are currently locked and potentially
1102 * changing their location.
1103 */
1104 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1105 !dma_resv_trylock(bo->tbo.base.resv))
1106 return;
1107
1108 amdgpu_bo_get_memory(bo, stats);
1109 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1110 dma_resv_unlock(bo->tbo.base.resv);
1111 }
1112
amdgpu_vm_get_memory(struct amdgpu_vm * vm,struct amdgpu_mem_stats * stats)1113 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1114 struct amdgpu_mem_stats *stats)
1115 {
1116 struct amdgpu_bo_va *bo_va, *tmp;
1117
1118 spin_lock(&vm->status_lock);
1119 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1120 amdgpu_vm_bo_get_memory(bo_va, stats);
1121
1122 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1123 amdgpu_vm_bo_get_memory(bo_va, stats);
1124
1125 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1126 amdgpu_vm_bo_get_memory(bo_va, stats);
1127
1128 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1129 amdgpu_vm_bo_get_memory(bo_va, stats);
1130
1131 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1132 amdgpu_vm_bo_get_memory(bo_va, stats);
1133
1134 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1135 amdgpu_vm_bo_get_memory(bo_va, stats);
1136 spin_unlock(&vm->status_lock);
1137 }
1138
1139 /**
1140 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1141 *
1142 * @adev: amdgpu_device pointer
1143 * @bo_va: requested BO and VM object
1144 * @clear: if true clear the entries
1145 *
1146 * Fill in the page table entries for @bo_va.
1147 *
1148 * Returns:
1149 * 0 for success, -EINVAL for failure.
1150 */
amdgpu_vm_bo_update(struct amdgpu_device * adev,struct amdgpu_bo_va * bo_va,bool clear)1151 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1152 bool clear)
1153 {
1154 struct amdgpu_bo *bo = bo_va->base.bo;
1155 struct amdgpu_vm *vm = bo_va->base.vm;
1156 struct amdgpu_bo_va_mapping *mapping;
1157 dma_addr_t *pages_addr = NULL;
1158 struct ttm_resource *mem;
1159 struct dma_fence **last_update;
1160 bool flush_tlb = clear;
1161 bool uncached;
1162 struct dma_resv *resv;
1163 uint64_t vram_base;
1164 uint64_t flags;
1165 int r;
1166
1167 if (clear || !bo) {
1168 mem = NULL;
1169 resv = vm->root.bo->tbo.base.resv;
1170 } else {
1171 struct drm_gem_object *obj = &bo->tbo.base;
1172
1173 resv = bo->tbo.base.resv;
1174 if (obj->import_attach && bo_va->is_xgmi) {
1175 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1176 struct drm_gem_object *gobj = dma_buf->priv;
1177 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1178
1179 if (abo->tbo.resource &&
1180 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1181 bo = gem_to_amdgpu_bo(gobj);
1182 }
1183 mem = bo->tbo.resource;
1184 if (mem && (mem->mem_type == TTM_PL_TT ||
1185 mem->mem_type == AMDGPU_PL_PREEMPT))
1186 pages_addr = bo->tbo.ttm->dma_address;
1187 }
1188
1189 if (bo) {
1190 struct amdgpu_device *bo_adev;
1191
1192 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1193
1194 if (amdgpu_bo_encrypted(bo))
1195 flags |= AMDGPU_PTE_TMZ;
1196
1197 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1198 vram_base = bo_adev->vm_manager.vram_base_offset;
1199 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1200 } else {
1201 flags = 0x0;
1202 vram_base = 0;
1203 uncached = false;
1204 }
1205
1206 if (clear || (bo && bo->tbo.base.resv ==
1207 vm->root.bo->tbo.base.resv))
1208 last_update = &vm->last_update;
1209 else
1210 last_update = &bo_va->last_pt_update;
1211
1212 if (!clear && bo_va->base.moved) {
1213 flush_tlb = true;
1214 list_splice_init(&bo_va->valids, &bo_va->invalids);
1215
1216 } else if (bo_va->cleared != clear) {
1217 list_splice_init(&bo_va->valids, &bo_va->invalids);
1218 }
1219
1220 list_for_each_entry(mapping, &bo_va->invalids, list) {
1221 uint64_t update_flags = flags;
1222
1223 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1224 * but in case of something, we filter the flags in first place
1225 */
1226 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1227 update_flags &= ~AMDGPU_PTE_READABLE;
1228 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1229 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1230
1231 /* Apply ASIC specific mapping flags */
1232 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1233
1234 trace_amdgpu_vm_bo_update(mapping);
1235
1236 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1237 !uncached, resv, mapping->start, mapping->last,
1238 update_flags, mapping->offset,
1239 vram_base, mem, pages_addr,
1240 last_update);
1241 if (r)
1242 return r;
1243 }
1244
1245 /* If the BO is not in its preferred location add it back to
1246 * the evicted list so that it gets validated again on the
1247 * next command submission.
1248 */
1249 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1250 uint32_t mem_type = bo->tbo.resource->mem_type;
1251
1252 if (!(bo->preferred_domains &
1253 amdgpu_mem_type_to_domain(mem_type)))
1254 amdgpu_vm_bo_evicted(&bo_va->base);
1255 else
1256 amdgpu_vm_bo_idle(&bo_va->base);
1257 } else {
1258 amdgpu_vm_bo_done(&bo_va->base);
1259 }
1260
1261 list_splice_init(&bo_va->invalids, &bo_va->valids);
1262 bo_va->cleared = clear;
1263 bo_va->base.moved = false;
1264
1265 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1266 list_for_each_entry(mapping, &bo_va->valids, list)
1267 trace_amdgpu_vm_bo_mapping(mapping);
1268 }
1269
1270 return 0;
1271 }
1272
1273 /**
1274 * amdgpu_vm_update_prt_state - update the global PRT state
1275 *
1276 * @adev: amdgpu_device pointer
1277 */
amdgpu_vm_update_prt_state(struct amdgpu_device * adev)1278 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1279 {
1280 unsigned long flags;
1281 bool enable;
1282
1283 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1284 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1285 adev->gmc.gmc_funcs->set_prt(adev, enable);
1286 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1287 }
1288
1289 /**
1290 * amdgpu_vm_prt_get - add a PRT user
1291 *
1292 * @adev: amdgpu_device pointer
1293 */
amdgpu_vm_prt_get(struct amdgpu_device * adev)1294 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1295 {
1296 if (!adev->gmc.gmc_funcs->set_prt)
1297 return;
1298
1299 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1300 amdgpu_vm_update_prt_state(adev);
1301 }
1302
1303 /**
1304 * amdgpu_vm_prt_put - drop a PRT user
1305 *
1306 * @adev: amdgpu_device pointer
1307 */
amdgpu_vm_prt_put(struct amdgpu_device * adev)1308 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1309 {
1310 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1311 amdgpu_vm_update_prt_state(adev);
1312 }
1313
1314 /**
1315 * amdgpu_vm_prt_cb - callback for updating the PRT status
1316 *
1317 * @fence: fence for the callback
1318 * @_cb: the callback function
1319 */
amdgpu_vm_prt_cb(struct dma_fence * fence,struct dma_fence_cb * _cb)1320 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1321 {
1322 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1323
1324 amdgpu_vm_prt_put(cb->adev);
1325 kfree(cb);
1326 }
1327
1328 /**
1329 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1330 *
1331 * @adev: amdgpu_device pointer
1332 * @fence: fence for the callback
1333 */
amdgpu_vm_add_prt_cb(struct amdgpu_device * adev,struct dma_fence * fence)1334 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1335 struct dma_fence *fence)
1336 {
1337 struct amdgpu_prt_cb *cb;
1338
1339 if (!adev->gmc.gmc_funcs->set_prt)
1340 return;
1341
1342 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1343 if (!cb) {
1344 /* Last resort when we are OOM */
1345 if (fence)
1346 dma_fence_wait(fence, false);
1347
1348 amdgpu_vm_prt_put(adev);
1349 } else {
1350 cb->adev = adev;
1351 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1352 amdgpu_vm_prt_cb))
1353 amdgpu_vm_prt_cb(fence, &cb->cb);
1354 }
1355 }
1356
1357 /**
1358 * amdgpu_vm_free_mapping - free a mapping
1359 *
1360 * @adev: amdgpu_device pointer
1361 * @vm: requested vm
1362 * @mapping: mapping to be freed
1363 * @fence: fence of the unmap operation
1364 *
1365 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1366 */
amdgpu_vm_free_mapping(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo_va_mapping * mapping,struct dma_fence * fence)1367 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1368 struct amdgpu_vm *vm,
1369 struct amdgpu_bo_va_mapping *mapping,
1370 struct dma_fence *fence)
1371 {
1372 if (mapping->flags & AMDGPU_PTE_PRT)
1373 amdgpu_vm_add_prt_cb(adev, fence);
1374 kfree(mapping);
1375 }
1376
1377 /**
1378 * amdgpu_vm_prt_fini - finish all prt mappings
1379 *
1380 * @adev: amdgpu_device pointer
1381 * @vm: requested vm
1382 *
1383 * Register a cleanup callback to disable PRT support after VM dies.
1384 */
amdgpu_vm_prt_fini(struct amdgpu_device * adev,struct amdgpu_vm * vm)1385 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1386 {
1387 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1388 struct dma_resv_iter cursor;
1389 struct dma_fence *fence;
1390
1391 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1392 /* Add a callback for each fence in the reservation object */
1393 amdgpu_vm_prt_get(adev);
1394 amdgpu_vm_add_prt_cb(adev, fence);
1395 }
1396 }
1397
1398 /**
1399 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1400 *
1401 * @adev: amdgpu_device pointer
1402 * @vm: requested vm
1403 * @fence: optional resulting fence (unchanged if no work needed to be done
1404 * or if an error occurred)
1405 *
1406 * Make sure all freed BOs are cleared in the PT.
1407 * PTs have to be reserved and mutex must be locked!
1408 *
1409 * Returns:
1410 * 0 for success.
1411 *
1412 */
amdgpu_vm_clear_freed(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct dma_fence ** fence)1413 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1414 struct amdgpu_vm *vm,
1415 struct dma_fence **fence)
1416 {
1417 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1418 struct amdgpu_bo_va_mapping *mapping;
1419 uint64_t init_pte_value = 0;
1420 struct dma_fence *f = NULL;
1421 int r;
1422
1423 while (!list_empty(&vm->freed)) {
1424 mapping = list_first_entry(&vm->freed,
1425 struct amdgpu_bo_va_mapping, list);
1426 list_del(&mapping->list);
1427
1428 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1429 resv, mapping->start, mapping->last,
1430 init_pte_value, 0, 0, NULL, NULL,
1431 &f);
1432 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1433 if (r) {
1434 dma_fence_put(f);
1435 return r;
1436 }
1437 }
1438
1439 if (fence && f) {
1440 dma_fence_put(*fence);
1441 *fence = f;
1442 } else {
1443 dma_fence_put(f);
1444 }
1445
1446 return 0;
1447
1448 }
1449
1450 /**
1451 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1452 *
1453 * @adev: amdgpu_device pointer
1454 * @vm: requested vm
1455 * @ticket: optional reservation ticket used to reserve the VM
1456 *
1457 * Make sure all BOs which are moved are updated in the PTs.
1458 *
1459 * Returns:
1460 * 0 for success.
1461 *
1462 * PTs have to be reserved!
1463 */
amdgpu_vm_handle_moved(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct ww_acquire_ctx * ticket)1464 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1465 struct amdgpu_vm *vm,
1466 struct ww_acquire_ctx *ticket)
1467 {
1468 struct amdgpu_bo_va *bo_va;
1469 struct dma_resv *resv;
1470 bool clear, unlock;
1471 int r;
1472
1473 spin_lock(&vm->status_lock);
1474 while (!list_empty(&vm->moved)) {
1475 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1476 base.vm_status);
1477 spin_unlock(&vm->status_lock);
1478
1479 /* Per VM BOs never need to bo cleared in the page tables */
1480 r = amdgpu_vm_bo_update(adev, bo_va, false);
1481 if (r)
1482 return r;
1483 spin_lock(&vm->status_lock);
1484 }
1485
1486 while (!list_empty(&vm->invalidated)) {
1487 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1488 base.vm_status);
1489 resv = bo_va->base.bo->tbo.base.resv;
1490 spin_unlock(&vm->status_lock);
1491
1492 /* Try to reserve the BO to avoid clearing its ptes */
1493 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1494 clear = false;
1495 unlock = true;
1496 /* The caller is already holding the reservation lock */
1497 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1498 clear = false;
1499 unlock = false;
1500 /* Somebody else is using the BO right now */
1501 } else {
1502 clear = true;
1503 unlock = false;
1504 }
1505
1506 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1507
1508 if (unlock)
1509 dma_resv_unlock(resv);
1510 if (r)
1511 return r;
1512
1513 /* Remember evicted DMABuf imports in compute VMs for later
1514 * validation
1515 */
1516 if (vm->is_compute_context &&
1517 bo_va->base.bo->tbo.base.import_attach &&
1518 (!bo_va->base.bo->tbo.resource ||
1519 bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM))
1520 amdgpu_vm_bo_evicted_user(&bo_va->base);
1521
1522 spin_lock(&vm->status_lock);
1523 }
1524 spin_unlock(&vm->status_lock);
1525
1526 return 0;
1527 }
1528
1529 /**
1530 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1531 *
1532 * @adev: amdgpu_device pointer
1533 * @vm: requested vm
1534 * @flush_type: flush type
1535 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1536 *
1537 * Flush TLB if needed for a compute VM.
1538 *
1539 * Returns:
1540 * 0 for success.
1541 */
amdgpu_vm_flush_compute_tlb(struct amdgpu_device * adev,struct amdgpu_vm * vm,uint32_t flush_type,uint32_t xcc_mask)1542 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1543 struct amdgpu_vm *vm,
1544 uint32_t flush_type,
1545 uint32_t xcc_mask)
1546 {
1547 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1548 bool all_hub = false;
1549 int xcc = 0, r = 0;
1550
1551 WARN_ON_ONCE(!vm->is_compute_context);
1552
1553 /*
1554 * It can be that we race and lose here, but that is extremely unlikely
1555 * and the worst thing which could happen is that we flush the changes
1556 * into the TLB once more which is harmless.
1557 */
1558 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1559 return 0;
1560
1561 if (adev->family == AMDGPU_FAMILY_AI ||
1562 adev->family == AMDGPU_FAMILY_RV)
1563 all_hub = true;
1564
1565 for_each_inst(xcc, xcc_mask) {
1566 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1567 all_hub, xcc);
1568 if (r)
1569 break;
1570 }
1571 return r;
1572 }
1573
1574 /**
1575 * amdgpu_vm_bo_add - add a bo to a specific vm
1576 *
1577 * @adev: amdgpu_device pointer
1578 * @vm: requested vm
1579 * @bo: amdgpu buffer object
1580 *
1581 * Add @bo into the requested vm.
1582 * Add @bo to the list of bos associated with the vm
1583 *
1584 * Returns:
1585 * Newly added bo_va or NULL for failure
1586 *
1587 * Object has to be reserved!
1588 */
amdgpu_vm_bo_add(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo * bo)1589 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1590 struct amdgpu_vm *vm,
1591 struct amdgpu_bo *bo)
1592 {
1593 struct amdgpu_bo_va *bo_va;
1594
1595 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1596 if (bo_va == NULL) {
1597 return NULL;
1598 }
1599 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1600
1601 bo_va->ref_count = 1;
1602 bo_va->last_pt_update = dma_fence_get_stub();
1603 INIT_LIST_HEAD(&bo_va->valids);
1604 INIT_LIST_HEAD(&bo_va->invalids);
1605
1606 if (!bo)
1607 return bo_va;
1608
1609 dma_resv_assert_held(bo->tbo.base.resv);
1610 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1611 bo_va->is_xgmi = true;
1612 /* Power up XGMI if it can be potentially used */
1613 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1614 }
1615
1616 return bo_va;
1617 }
1618
1619
1620 /**
1621 * amdgpu_vm_bo_insert_map - insert a new mapping
1622 *
1623 * @adev: amdgpu_device pointer
1624 * @bo_va: bo_va to store the address
1625 * @mapping: the mapping to insert
1626 *
1627 * Insert a new mapping into all structures.
1628 */
amdgpu_vm_bo_insert_map(struct amdgpu_device * adev,struct amdgpu_bo_va * bo_va,struct amdgpu_bo_va_mapping * mapping)1629 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1630 struct amdgpu_bo_va *bo_va,
1631 struct amdgpu_bo_va_mapping *mapping)
1632 {
1633 struct amdgpu_vm *vm = bo_va->base.vm;
1634 struct amdgpu_bo *bo = bo_va->base.bo;
1635
1636 mapping->bo_va = bo_va;
1637 list_add(&mapping->list, &bo_va->invalids);
1638 amdgpu_vm_it_insert(mapping, &vm->va);
1639
1640 if (mapping->flags & AMDGPU_PTE_PRT)
1641 amdgpu_vm_prt_get(adev);
1642
1643 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1644 !bo_va->base.moved) {
1645 amdgpu_vm_bo_moved(&bo_va->base);
1646 }
1647 trace_amdgpu_vm_bo_map(bo_va, mapping);
1648 }
1649
1650 /* Validate operation parameters to prevent potential abuse */
amdgpu_vm_verify_parameters(struct amdgpu_device * adev,struct amdgpu_bo * bo,uint64_t saddr,uint64_t offset,uint64_t size)1651 static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,
1652 struct amdgpu_bo *bo,
1653 uint64_t saddr,
1654 uint64_t offset,
1655 uint64_t size)
1656 {
1657 uint64_t tmp, lpfn;
1658
1659 if (saddr & AMDGPU_GPU_PAGE_MASK
1660 || offset & AMDGPU_GPU_PAGE_MASK
1661 || size & AMDGPU_GPU_PAGE_MASK)
1662 return -EINVAL;
1663
1664 if (check_add_overflow(saddr, size, &tmp)
1665 || check_add_overflow(offset, size, &tmp)
1666 || size == 0 /* which also leads to end < begin */)
1667 return -EINVAL;
1668
1669 /* make sure object fit at this offset */
1670 if (bo && offset + size > amdgpu_bo_size(bo))
1671 return -EINVAL;
1672
1673 /* Ensure last pfn not exceed max_pfn */
1674 lpfn = (saddr + size - 1) >> AMDGPU_GPU_PAGE_SHIFT;
1675 if (lpfn >= adev->vm_manager.max_pfn)
1676 return -EINVAL;
1677
1678 return 0;
1679 }
1680
1681 /**
1682 * amdgpu_vm_bo_map - map bo inside a vm
1683 *
1684 * @adev: amdgpu_device pointer
1685 * @bo_va: bo_va to store the address
1686 * @saddr: where to map the BO
1687 * @offset: requested offset in the BO
1688 * @size: BO size in bytes
1689 * @flags: attributes of pages (read/write/valid/etc.)
1690 *
1691 * Add a mapping of the BO at the specefied addr into the VM.
1692 *
1693 * Returns:
1694 * 0 for success, error for failure.
1695 *
1696 * Object has to be reserved and unreserved outside!
1697 */
amdgpu_vm_bo_map(struct amdgpu_device * adev,struct amdgpu_bo_va * bo_va,uint64_t saddr,uint64_t offset,uint64_t size,uint64_t flags)1698 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1699 struct amdgpu_bo_va *bo_va,
1700 uint64_t saddr, uint64_t offset,
1701 uint64_t size, uint64_t flags)
1702 {
1703 struct amdgpu_bo_va_mapping *mapping, *tmp;
1704 struct amdgpu_bo *bo = bo_va->base.bo;
1705 struct amdgpu_vm *vm = bo_va->base.vm;
1706 uint64_t eaddr;
1707 int r;
1708
1709 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1710 if (r)
1711 return r;
1712
1713 saddr /= AMDGPU_GPU_PAGE_SIZE;
1714 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1715
1716 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1717 if (tmp) {
1718 /* bo and tmp overlap, invalid addr */
1719 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1720 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1721 tmp->start, tmp->last + 1);
1722 return -EINVAL;
1723 }
1724
1725 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1726 if (!mapping)
1727 return -ENOMEM;
1728
1729 mapping->start = saddr;
1730 mapping->last = eaddr;
1731 mapping->offset = offset;
1732 mapping->flags = flags;
1733
1734 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1735
1736 return 0;
1737 }
1738
1739 /**
1740 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1741 *
1742 * @adev: amdgpu_device pointer
1743 * @bo_va: bo_va to store the address
1744 * @saddr: where to map the BO
1745 * @offset: requested offset in the BO
1746 * @size: BO size in bytes
1747 * @flags: attributes of pages (read/write/valid/etc.)
1748 *
1749 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1750 * mappings as we do so.
1751 *
1752 * Returns:
1753 * 0 for success, error for failure.
1754 *
1755 * Object has to be reserved and unreserved outside!
1756 */
amdgpu_vm_bo_replace_map(struct amdgpu_device * adev,struct amdgpu_bo_va * bo_va,uint64_t saddr,uint64_t offset,uint64_t size,uint64_t flags)1757 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1758 struct amdgpu_bo_va *bo_va,
1759 uint64_t saddr, uint64_t offset,
1760 uint64_t size, uint64_t flags)
1761 {
1762 struct amdgpu_bo_va_mapping *mapping;
1763 struct amdgpu_bo *bo = bo_va->base.bo;
1764 uint64_t eaddr;
1765 int r;
1766
1767 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1768 if (r)
1769 return r;
1770
1771 /* Allocate all the needed memory */
1772 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1773 if (!mapping)
1774 return -ENOMEM;
1775
1776 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1777 if (r) {
1778 kfree(mapping);
1779 return r;
1780 }
1781
1782 saddr /= AMDGPU_GPU_PAGE_SIZE;
1783 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1784
1785 mapping->start = saddr;
1786 mapping->last = eaddr;
1787 mapping->offset = offset;
1788 mapping->flags = flags;
1789
1790 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1791
1792 return 0;
1793 }
1794
1795 /**
1796 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1797 *
1798 * @adev: amdgpu_device pointer
1799 * @bo_va: bo_va to remove the address from
1800 * @saddr: where to the BO is mapped
1801 *
1802 * Remove a mapping of the BO at the specefied addr from the VM.
1803 *
1804 * Returns:
1805 * 0 for success, error for failure.
1806 *
1807 * Object has to be reserved and unreserved outside!
1808 */
amdgpu_vm_bo_unmap(struct amdgpu_device * adev,struct amdgpu_bo_va * bo_va,uint64_t saddr)1809 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1810 struct amdgpu_bo_va *bo_va,
1811 uint64_t saddr)
1812 {
1813 struct amdgpu_bo_va_mapping *mapping;
1814 struct amdgpu_vm *vm = bo_va->base.vm;
1815 bool valid = true;
1816
1817 saddr /= AMDGPU_GPU_PAGE_SIZE;
1818
1819 list_for_each_entry(mapping, &bo_va->valids, list) {
1820 if (mapping->start == saddr)
1821 break;
1822 }
1823
1824 if (&mapping->list == &bo_va->valids) {
1825 valid = false;
1826
1827 list_for_each_entry(mapping, &bo_va->invalids, list) {
1828 if (mapping->start == saddr)
1829 break;
1830 }
1831
1832 if (&mapping->list == &bo_va->invalids)
1833 return -ENOENT;
1834 }
1835
1836 list_del(&mapping->list);
1837 amdgpu_vm_it_remove(mapping, &vm->va);
1838 mapping->bo_va = NULL;
1839 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1840
1841 if (valid)
1842 list_add(&mapping->list, &vm->freed);
1843 else
1844 amdgpu_vm_free_mapping(adev, vm, mapping,
1845 bo_va->last_pt_update);
1846
1847 return 0;
1848 }
1849
1850 /**
1851 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1852 *
1853 * @adev: amdgpu_device pointer
1854 * @vm: VM structure to use
1855 * @saddr: start of the range
1856 * @size: size of the range
1857 *
1858 * Remove all mappings in a range, split them as appropriate.
1859 *
1860 * Returns:
1861 * 0 for success, error for failure.
1862 */
amdgpu_vm_bo_clear_mappings(struct amdgpu_device * adev,struct amdgpu_vm * vm,uint64_t saddr,uint64_t size)1863 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1864 struct amdgpu_vm *vm,
1865 uint64_t saddr, uint64_t size)
1866 {
1867 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1868 LIST_HEAD(removed);
1869 uint64_t eaddr;
1870 int r;
1871
1872 r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);
1873 if (r)
1874 return r;
1875
1876 saddr /= AMDGPU_GPU_PAGE_SIZE;
1877 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1878
1879 /* Allocate all the needed memory */
1880 before = kzalloc(sizeof(*before), GFP_KERNEL);
1881 if (!before)
1882 return -ENOMEM;
1883 INIT_LIST_HEAD(&before->list);
1884
1885 after = kzalloc(sizeof(*after), GFP_KERNEL);
1886 if (!after) {
1887 kfree(before);
1888 return -ENOMEM;
1889 }
1890 INIT_LIST_HEAD(&after->list);
1891
1892 /* Now gather all removed mappings */
1893 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1894 while (tmp) {
1895 /* Remember mapping split at the start */
1896 if (tmp->start < saddr) {
1897 before->start = tmp->start;
1898 before->last = saddr - 1;
1899 before->offset = tmp->offset;
1900 before->flags = tmp->flags;
1901 before->bo_va = tmp->bo_va;
1902 list_add(&before->list, &tmp->bo_va->invalids);
1903 }
1904
1905 /* Remember mapping split at the end */
1906 if (tmp->last > eaddr) {
1907 after->start = eaddr + 1;
1908 after->last = tmp->last;
1909 after->offset = tmp->offset;
1910 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1911 after->flags = tmp->flags;
1912 after->bo_va = tmp->bo_va;
1913 list_add(&after->list, &tmp->bo_va->invalids);
1914 }
1915
1916 list_del(&tmp->list);
1917 list_add(&tmp->list, &removed);
1918
1919 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1920 }
1921
1922 /* And free them up */
1923 list_for_each_entry_safe(tmp, next, &removed, list) {
1924 amdgpu_vm_it_remove(tmp, &vm->va);
1925 list_del(&tmp->list);
1926
1927 if (tmp->start < saddr)
1928 tmp->start = saddr;
1929 if (tmp->last > eaddr)
1930 tmp->last = eaddr;
1931
1932 tmp->bo_va = NULL;
1933 list_add(&tmp->list, &vm->freed);
1934 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1935 }
1936
1937 /* Insert partial mapping before the range */
1938 if (!list_empty(&before->list)) {
1939 struct amdgpu_bo *bo = before->bo_va->base.bo;
1940
1941 amdgpu_vm_it_insert(before, &vm->va);
1942 if (before->flags & AMDGPU_PTE_PRT)
1943 amdgpu_vm_prt_get(adev);
1944
1945 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1946 !before->bo_va->base.moved)
1947 amdgpu_vm_bo_moved(&before->bo_va->base);
1948 } else {
1949 kfree(before);
1950 }
1951
1952 /* Insert partial mapping after the range */
1953 if (!list_empty(&after->list)) {
1954 struct amdgpu_bo *bo = after->bo_va->base.bo;
1955
1956 amdgpu_vm_it_insert(after, &vm->va);
1957 if (after->flags & AMDGPU_PTE_PRT)
1958 amdgpu_vm_prt_get(adev);
1959
1960 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1961 !after->bo_va->base.moved)
1962 amdgpu_vm_bo_moved(&after->bo_va->base);
1963 } else {
1964 kfree(after);
1965 }
1966
1967 return 0;
1968 }
1969
1970 /**
1971 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1972 *
1973 * @vm: the requested VM
1974 * @addr: the address
1975 *
1976 * Find a mapping by it's address.
1977 *
1978 * Returns:
1979 * The amdgpu_bo_va_mapping matching for addr or NULL
1980 *
1981 */
amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm * vm,uint64_t addr)1982 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1983 uint64_t addr)
1984 {
1985 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1986 }
1987
1988 /**
1989 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1990 *
1991 * @vm: the requested vm
1992 * @ticket: CS ticket
1993 *
1994 * Trace all mappings of BOs reserved during a command submission.
1995 */
amdgpu_vm_bo_trace_cs(struct amdgpu_vm * vm,struct ww_acquire_ctx * ticket)1996 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1997 {
1998 struct amdgpu_bo_va_mapping *mapping;
1999
2000 if (!trace_amdgpu_vm_bo_cs_enabled())
2001 return;
2002
2003 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2004 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2005 if (mapping->bo_va && mapping->bo_va->base.bo) {
2006 struct amdgpu_bo *bo;
2007
2008 bo = mapping->bo_va->base.bo;
2009 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2010 ticket)
2011 continue;
2012 }
2013
2014 trace_amdgpu_vm_bo_cs(mapping);
2015 }
2016 }
2017
2018 /**
2019 * amdgpu_vm_bo_del - remove a bo from a specific vm
2020 *
2021 * @adev: amdgpu_device pointer
2022 * @bo_va: requested bo_va
2023 *
2024 * Remove @bo_va->bo from the requested vm.
2025 *
2026 * Object have to be reserved!
2027 */
amdgpu_vm_bo_del(struct amdgpu_device * adev,struct amdgpu_bo_va * bo_va)2028 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
2029 struct amdgpu_bo_va *bo_va)
2030 {
2031 struct amdgpu_bo_va_mapping *mapping, *next;
2032 struct amdgpu_bo *bo = bo_va->base.bo;
2033 struct amdgpu_vm *vm = bo_va->base.vm;
2034 struct amdgpu_vm_bo_base **base;
2035
2036 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
2037
2038 if (bo) {
2039 dma_resv_assert_held(bo->tbo.base.resv);
2040 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2041 ttm_bo_set_bulk_move(&bo->tbo, NULL);
2042
2043 for (base = &bo_va->base.bo->vm_bo; *base;
2044 base = &(*base)->next) {
2045 if (*base != &bo_va->base)
2046 continue;
2047
2048 *base = bo_va->base.next;
2049 break;
2050 }
2051 }
2052
2053 spin_lock(&vm->status_lock);
2054 list_del(&bo_va->base.vm_status);
2055 spin_unlock(&vm->status_lock);
2056
2057 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2058 list_del(&mapping->list);
2059 amdgpu_vm_it_remove(mapping, &vm->va);
2060 mapping->bo_va = NULL;
2061 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2062 list_add(&mapping->list, &vm->freed);
2063 }
2064 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2065 list_del(&mapping->list);
2066 amdgpu_vm_it_remove(mapping, &vm->va);
2067 amdgpu_vm_free_mapping(adev, vm, mapping,
2068 bo_va->last_pt_update);
2069 }
2070
2071 dma_fence_put(bo_va->last_pt_update);
2072
2073 if (bo && bo_va->is_xgmi)
2074 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2075
2076 kfree(bo_va);
2077 }
2078
2079 /**
2080 * amdgpu_vm_evictable - check if we can evict a VM
2081 *
2082 * @bo: A page table of the VM.
2083 *
2084 * Check if it is possible to evict a VM.
2085 */
amdgpu_vm_evictable(struct amdgpu_bo * bo)2086 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2087 {
2088 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2089
2090 /* Page tables of a destroyed VM can go away immediately */
2091 if (!bo_base || !bo_base->vm)
2092 return true;
2093
2094 /* Don't evict VM page tables while they are busy */
2095 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2096 return false;
2097
2098 /* Try to block ongoing updates */
2099 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2100 return false;
2101
2102 /* Don't evict VM page tables while they are updated */
2103 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2104 amdgpu_vm_eviction_unlock(bo_base->vm);
2105 return false;
2106 }
2107
2108 bo_base->vm->evicting = true;
2109 amdgpu_vm_eviction_unlock(bo_base->vm);
2110 return true;
2111 }
2112
2113 /**
2114 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2115 *
2116 * @adev: amdgpu_device pointer
2117 * @bo: amdgpu buffer object
2118 * @evicted: is the BO evicted
2119 *
2120 * Mark @bo as invalid.
2121 */
amdgpu_vm_bo_invalidate(struct amdgpu_device * adev,struct amdgpu_bo * bo,bool evicted)2122 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2123 struct amdgpu_bo *bo, bool evicted)
2124 {
2125 struct amdgpu_vm_bo_base *bo_base;
2126
2127 /* shadow bo doesn't have bo base, its validation needs its parent */
2128 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2129 bo = bo->parent;
2130
2131 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2132 struct amdgpu_vm *vm = bo_base->vm;
2133
2134 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2135 amdgpu_vm_bo_evicted(bo_base);
2136 continue;
2137 }
2138
2139 if (bo_base->moved)
2140 continue;
2141 bo_base->moved = true;
2142
2143 if (bo->tbo.type == ttm_bo_type_kernel)
2144 amdgpu_vm_bo_relocated(bo_base);
2145 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2146 amdgpu_vm_bo_moved(bo_base);
2147 else
2148 amdgpu_vm_bo_invalidated(bo_base);
2149 }
2150 }
2151
2152 /**
2153 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2154 *
2155 * @vm_size: VM size
2156 *
2157 * Returns:
2158 * VM page table as power of two
2159 */
amdgpu_vm_get_block_size(uint64_t vm_size)2160 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2161 {
2162 /* Total bits covered by PD + PTs */
2163 unsigned bits = ilog2(vm_size) + 18;
2164
2165 /* Make sure the PD is 4K in size up to 8GB address space.
2166 Above that split equal between PD and PTs */
2167 if (vm_size <= 8)
2168 return (bits - 9);
2169 else
2170 return ((bits + 3) / 2);
2171 }
2172
2173 /**
2174 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2175 *
2176 * @adev: amdgpu_device pointer
2177 * @min_vm_size: the minimum vm size in GB if it's set auto
2178 * @fragment_size_default: Default PTE fragment size
2179 * @max_level: max VMPT level
2180 * @max_bits: max address space size in bits
2181 *
2182 */
amdgpu_vm_adjust_size(struct amdgpu_device * adev,uint32_t min_vm_size,uint32_t fragment_size_default,unsigned max_level,unsigned max_bits)2183 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2184 uint32_t fragment_size_default, unsigned max_level,
2185 unsigned max_bits)
2186 {
2187 unsigned int max_size = 1 << (max_bits - 30);
2188 unsigned int vm_size;
2189 uint64_t tmp;
2190
2191 /* adjust vm size first */
2192 if (amdgpu_vm_size != -1) {
2193 vm_size = amdgpu_vm_size;
2194 if (vm_size > max_size) {
2195 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2196 amdgpu_vm_size, max_size);
2197 vm_size = max_size;
2198 }
2199 } else {
2200 struct sysinfo si;
2201 unsigned int phys_ram_gb;
2202
2203 /* Optimal VM size depends on the amount of physical
2204 * RAM available. Underlying requirements and
2205 * assumptions:
2206 *
2207 * - Need to map system memory and VRAM from all GPUs
2208 * - VRAM from other GPUs not known here
2209 * - Assume VRAM <= system memory
2210 * - On GFX8 and older, VM space can be segmented for
2211 * different MTYPEs
2212 * - Need to allow room for fragmentation, guard pages etc.
2213 *
2214 * This adds up to a rough guess of system memory x3.
2215 * Round up to power of two to maximize the available
2216 * VM size with the given page table size.
2217 */
2218 si_meminfo(&si);
2219 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2220 (1 << 30) - 1) >> 30;
2221 vm_size = roundup_pow_of_two(
2222 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2223 }
2224
2225 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2226
2227 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2228 if (amdgpu_vm_block_size != -1)
2229 tmp >>= amdgpu_vm_block_size - 9;
2230 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2231 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2232 switch (adev->vm_manager.num_level) {
2233 case 3:
2234 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2235 break;
2236 case 2:
2237 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2238 break;
2239 case 1:
2240 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2241 break;
2242 default:
2243 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2244 }
2245 /* block size depends on vm size and hw setup*/
2246 if (amdgpu_vm_block_size != -1)
2247 adev->vm_manager.block_size =
2248 min((unsigned)amdgpu_vm_block_size, max_bits
2249 - AMDGPU_GPU_PAGE_SHIFT
2250 - 9 * adev->vm_manager.num_level);
2251 else if (adev->vm_manager.num_level > 1)
2252 adev->vm_manager.block_size = 9;
2253 else
2254 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2255
2256 if (amdgpu_vm_fragment_size == -1)
2257 adev->vm_manager.fragment_size = fragment_size_default;
2258 else
2259 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2260
2261 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2262 vm_size, adev->vm_manager.num_level + 1,
2263 adev->vm_manager.block_size,
2264 adev->vm_manager.fragment_size);
2265 }
2266
2267 /**
2268 * amdgpu_vm_wait_idle - wait for the VM to become idle
2269 *
2270 * @vm: VM object to wait for
2271 * @timeout: timeout to wait for VM to become idle
2272 */
amdgpu_vm_wait_idle(struct amdgpu_vm * vm,long timeout)2273 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2274 {
2275 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2276 DMA_RESV_USAGE_BOOKKEEP,
2277 true, timeout);
2278 if (timeout <= 0)
2279 return timeout;
2280
2281 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2282 }
2283
amdgpu_vm_destroy_task_info(struct kref * kref)2284 static void amdgpu_vm_destroy_task_info(struct kref *kref)
2285 {
2286 struct amdgpu_task_info *ti = container_of(kref, struct amdgpu_task_info, refcount);
2287
2288 kfree(ti);
2289 }
2290
2291 static inline struct amdgpu_vm *
amdgpu_vm_get_vm_from_pasid(struct amdgpu_device * adev,u32 pasid)2292 amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)
2293 {
2294 struct amdgpu_vm *vm;
2295 unsigned long flags;
2296
2297 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2298 vm = xa_load(&adev->vm_manager.pasids, pasid);
2299 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2300
2301 return vm;
2302 }
2303
2304 /**
2305 * amdgpu_vm_put_task_info - reference down the vm task_info ptr
2306 *
2307 * @task_info: task_info struct under discussion.
2308 *
2309 * frees the vm task_info ptr at the last put
2310 */
amdgpu_vm_put_task_info(struct amdgpu_task_info * task_info)2311 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)
2312 {
2313 kref_put(&task_info->refcount, amdgpu_vm_destroy_task_info);
2314 }
2315
2316 /**
2317 * amdgpu_vm_get_task_info_vm - Extracts task info for a vm.
2318 *
2319 * @vm: VM to get info from
2320 *
2321 * Returns the reference counted task_info structure, which must be
2322 * referenced down with amdgpu_vm_put_task_info.
2323 */
2324 struct amdgpu_task_info *
amdgpu_vm_get_task_info_vm(struct amdgpu_vm * vm)2325 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm)
2326 {
2327 struct amdgpu_task_info *ti = NULL;
2328
2329 if (vm) {
2330 ti = vm->task_info;
2331 kref_get(&vm->task_info->refcount);
2332 }
2333
2334 return ti;
2335 }
2336
2337 /**
2338 * amdgpu_vm_get_task_info_pasid - Extracts task info for a PASID.
2339 *
2340 * @adev: drm device pointer
2341 * @pasid: PASID identifier for VM
2342 *
2343 * Returns the reference counted task_info structure, which must be
2344 * referenced down with amdgpu_vm_put_task_info.
2345 */
2346 struct amdgpu_task_info *
amdgpu_vm_get_task_info_pasid(struct amdgpu_device * adev,u32 pasid)2347 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)
2348 {
2349 return amdgpu_vm_get_task_info_vm(
2350 amdgpu_vm_get_vm_from_pasid(adev, pasid));
2351 }
2352
amdgpu_vm_create_task_info(struct amdgpu_vm * vm)2353 static int amdgpu_vm_create_task_info(struct amdgpu_vm *vm)
2354 {
2355 vm->task_info = kzalloc(sizeof(struct amdgpu_task_info), GFP_KERNEL);
2356 if (!vm->task_info)
2357 return -ENOMEM;
2358
2359 kref_init(&vm->task_info->refcount);
2360 return 0;
2361 }
2362
2363 /**
2364 * amdgpu_vm_set_task_info - Sets VMs task info.
2365 *
2366 * @vm: vm for which to set the info
2367 */
amdgpu_vm_set_task_info(struct amdgpu_vm * vm)2368 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2369 {
2370 if (!vm->task_info)
2371 return;
2372
2373 if (vm->task_info->pid == current->pid)
2374 return;
2375
2376 vm->task_info->pid = current->pid;
2377 get_task_comm(vm->task_info->task_name, current);
2378
2379 if (current->group_leader->mm != current->mm)
2380 return;
2381
2382 vm->task_info->tgid = current->group_leader->pid;
2383 get_task_comm(vm->task_info->process_name, current->group_leader);
2384 }
2385
2386 /**
2387 * amdgpu_vm_init - initialize a vm instance
2388 *
2389 * @adev: amdgpu_device pointer
2390 * @vm: requested vm
2391 * @xcp_id: GPU partition selection id
2392 *
2393 * Init @vm fields.
2394 *
2395 * Returns:
2396 * 0 for success, error for failure.
2397 */
amdgpu_vm_init(struct amdgpu_device * adev,struct amdgpu_vm * vm,int32_t xcp_id)2398 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2399 int32_t xcp_id)
2400 {
2401 struct amdgpu_bo *root_bo;
2402 struct amdgpu_bo_vm *root;
2403 int r, i;
2404
2405 vm->va = RB_ROOT_CACHED;
2406 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2407 vm->reserved_vmid[i] = NULL;
2408 INIT_LIST_HEAD(&vm->evicted);
2409 INIT_LIST_HEAD(&vm->evicted_user);
2410 INIT_LIST_HEAD(&vm->relocated);
2411 INIT_LIST_HEAD(&vm->moved);
2412 INIT_LIST_HEAD(&vm->idle);
2413 INIT_LIST_HEAD(&vm->invalidated);
2414 spin_lock_init(&vm->status_lock);
2415 INIT_LIST_HEAD(&vm->freed);
2416 INIT_LIST_HEAD(&vm->done);
2417 INIT_LIST_HEAD(&vm->pt_freed);
2418 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2419 INIT_KFIFO(vm->faults);
2420
2421 r = amdgpu_vm_init_entities(adev, vm);
2422 if (r)
2423 return r;
2424
2425 vm->is_compute_context = false;
2426
2427 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2428 AMDGPU_VM_USE_CPU_FOR_GFX);
2429
2430 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2431 vm->use_cpu_for_update ? "CPU" : "SDMA");
2432 WARN_ONCE((vm->use_cpu_for_update &&
2433 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2434 "CPU update of VM recommended only for large BAR system\n");
2435
2436 if (vm->use_cpu_for_update)
2437 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2438 else
2439 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2440
2441 vm->last_update = dma_fence_get_stub();
2442 vm->last_unlocked = dma_fence_get_stub();
2443 vm->last_tlb_flush = dma_fence_get_stub();
2444 vm->generation = 0;
2445
2446 mutex_init(&vm->eviction_lock);
2447 vm->evicting = false;
2448 vm->tlb_fence_context = dma_fence_context_alloc(1);
2449
2450 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2451 false, &root, xcp_id);
2452 if (r)
2453 goto error_free_delayed;
2454
2455 root_bo = amdgpu_bo_ref(&root->bo);
2456 r = amdgpu_bo_reserve(root_bo, true);
2457 if (r) {
2458 amdgpu_bo_unref(&root->shadow);
2459 amdgpu_bo_unref(&root_bo);
2460 goto error_free_delayed;
2461 }
2462
2463 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2464 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2465 if (r)
2466 goto error_free_root;
2467
2468 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2469 if (r)
2470 goto error_free_root;
2471
2472 r = amdgpu_vm_create_task_info(vm);
2473 if (r)
2474 DRM_DEBUG("Failed to create task info for VM\n");
2475
2476 amdgpu_bo_unreserve(vm->root.bo);
2477 amdgpu_bo_unref(&root_bo);
2478
2479 return 0;
2480
2481 error_free_root:
2482 amdgpu_vm_pt_free_root(adev, vm);
2483 amdgpu_bo_unreserve(vm->root.bo);
2484 amdgpu_bo_unref(&root_bo);
2485
2486 error_free_delayed:
2487 dma_fence_put(vm->last_tlb_flush);
2488 dma_fence_put(vm->last_unlocked);
2489 amdgpu_vm_fini_entities(vm);
2490
2491 return r;
2492 }
2493
2494 /**
2495 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2496 *
2497 * @adev: amdgpu_device pointer
2498 * @vm: requested vm
2499 *
2500 * This only works on GFX VMs that don't have any BOs added and no
2501 * page tables allocated yet.
2502 *
2503 * Changes the following VM parameters:
2504 * - use_cpu_for_update
2505 * - pte_supports_ats
2506 *
2507 * Reinitializes the page directory to reflect the changed ATS
2508 * setting.
2509 *
2510 * Returns:
2511 * 0 for success, -errno for errors.
2512 */
amdgpu_vm_make_compute(struct amdgpu_device * adev,struct amdgpu_vm * vm)2513 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2514 {
2515 int r;
2516
2517 r = amdgpu_bo_reserve(vm->root.bo, true);
2518 if (r)
2519 return r;
2520
2521 /* Update VM state */
2522 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2523 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2524 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2525 vm->use_cpu_for_update ? "CPU" : "SDMA");
2526 WARN_ONCE((vm->use_cpu_for_update &&
2527 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2528 "CPU update of VM recommended only for large BAR system\n");
2529
2530 if (vm->use_cpu_for_update) {
2531 /* Sync with last SDMA update/clear before switching to CPU */
2532 r = amdgpu_bo_sync_wait(vm->root.bo,
2533 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2534 if (r)
2535 goto unreserve_bo;
2536
2537 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2538 r = amdgpu_vm_pt_map_tables(adev, vm);
2539 if (r)
2540 goto unreserve_bo;
2541
2542 } else {
2543 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2544 }
2545
2546 dma_fence_put(vm->last_update);
2547 vm->last_update = dma_fence_get_stub();
2548 vm->is_compute_context = true;
2549
2550 /* Free the shadow bo for compute VM */
2551 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2552
2553 goto unreserve_bo;
2554
2555 unreserve_bo:
2556 amdgpu_bo_unreserve(vm->root.bo);
2557 return r;
2558 }
2559
2560 /**
2561 * amdgpu_vm_release_compute - release a compute vm
2562 * @adev: amdgpu_device pointer
2563 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2564 *
2565 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2566 * pasid from vm. Compute should stop use of vm after this call.
2567 */
amdgpu_vm_release_compute(struct amdgpu_device * adev,struct amdgpu_vm * vm)2568 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2569 {
2570 amdgpu_vm_set_pasid(adev, vm, 0);
2571 vm->is_compute_context = false;
2572 }
2573
2574 /**
2575 * amdgpu_vm_fini - tear down a vm instance
2576 *
2577 * @adev: amdgpu_device pointer
2578 * @vm: requested vm
2579 *
2580 * Tear down @vm.
2581 * Unbind the VM and remove all bos from the vm bo list
2582 */
amdgpu_vm_fini(struct amdgpu_device * adev,struct amdgpu_vm * vm)2583 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2584 {
2585 struct amdgpu_bo_va_mapping *mapping, *tmp;
2586 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2587 struct amdgpu_bo *root;
2588 unsigned long flags;
2589 int i;
2590
2591 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2592
2593 flush_work(&vm->pt_free_work);
2594
2595 root = amdgpu_bo_ref(vm->root.bo);
2596 amdgpu_bo_reserve(root, true);
2597 amdgpu_vm_put_task_info(vm->task_info);
2598 amdgpu_vm_set_pasid(adev, vm, 0);
2599 dma_fence_wait(vm->last_unlocked, false);
2600 dma_fence_put(vm->last_unlocked);
2601 dma_fence_wait(vm->last_tlb_flush, false);
2602 /* Make sure that all fence callbacks have completed */
2603 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2604 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2605 dma_fence_put(vm->last_tlb_flush);
2606
2607 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2608 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2609 amdgpu_vm_prt_fini(adev, vm);
2610 prt_fini_needed = false;
2611 }
2612
2613 list_del(&mapping->list);
2614 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2615 }
2616
2617 amdgpu_vm_pt_free_root(adev, vm);
2618 amdgpu_bo_unreserve(root);
2619 amdgpu_bo_unref(&root);
2620 WARN_ON(vm->root.bo);
2621
2622 amdgpu_vm_fini_entities(vm);
2623
2624 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2625 dev_err(adev->dev, "still active bo inside vm\n");
2626 }
2627 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2628 &vm->va.rb_root, rb) {
2629 /* Don't remove the mapping here, we don't want to trigger a
2630 * rebalance and the tree is about to be destroyed anyway.
2631 */
2632 list_del(&mapping->list);
2633 kfree(mapping);
2634 }
2635
2636 dma_fence_put(vm->last_update);
2637
2638 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2639 if (vm->reserved_vmid[i]) {
2640 amdgpu_vmid_free_reserved(adev, i);
2641 vm->reserved_vmid[i] = false;
2642 }
2643 }
2644
2645 }
2646
2647 /**
2648 * amdgpu_vm_manager_init - init the VM manager
2649 *
2650 * @adev: amdgpu_device pointer
2651 *
2652 * Initialize the VM manager structures
2653 */
amdgpu_vm_manager_init(struct amdgpu_device * adev)2654 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2655 {
2656 unsigned i;
2657
2658 /* Concurrent flushes are only possible starting with Vega10 and
2659 * are broken on Navi10 and Navi14.
2660 */
2661 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2662 adev->asic_type == CHIP_NAVI10 ||
2663 adev->asic_type == CHIP_NAVI14);
2664 amdgpu_vmid_mgr_init(adev);
2665
2666 adev->vm_manager.fence_context =
2667 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2668 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2669 adev->vm_manager.seqno[i] = 0;
2670
2671 spin_lock_init(&adev->vm_manager.prt_lock);
2672 atomic_set(&adev->vm_manager.num_prt_users, 0);
2673
2674 /* If not overridden by the user, by default, only in large BAR systems
2675 * Compute VM tables will be updated by CPU
2676 */
2677 #ifdef CONFIG_X86_64
2678 if (amdgpu_vm_update_mode == -1) {
2679 /* For asic with VF MMIO access protection
2680 * avoid using CPU for VM table updates
2681 */
2682 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2683 !amdgpu_sriov_vf_mmio_access_protection(adev))
2684 adev->vm_manager.vm_update_mode =
2685 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2686 else
2687 adev->vm_manager.vm_update_mode = 0;
2688 } else
2689 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2690 #else
2691 adev->vm_manager.vm_update_mode = 0;
2692 #endif
2693
2694 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2695 }
2696
2697 /**
2698 * amdgpu_vm_manager_fini - cleanup VM manager
2699 *
2700 * @adev: amdgpu_device pointer
2701 *
2702 * Cleanup the VM manager and free resources.
2703 */
amdgpu_vm_manager_fini(struct amdgpu_device * adev)2704 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2705 {
2706 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2707 xa_destroy(&adev->vm_manager.pasids);
2708
2709 amdgpu_vmid_mgr_fini(adev);
2710 }
2711
2712 /**
2713 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2714 *
2715 * @dev: drm device pointer
2716 * @data: drm_amdgpu_vm
2717 * @filp: drm file pointer
2718 *
2719 * Returns:
2720 * 0 for success, -errno for errors.
2721 */
amdgpu_vm_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)2722 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2723 {
2724 union drm_amdgpu_vm *args = data;
2725 struct amdgpu_device *adev = drm_to_adev(dev);
2726 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2727
2728 /* No valid flags defined yet */
2729 if (args->in.flags)
2730 return -EINVAL;
2731
2732 switch (args->in.op) {
2733 case AMDGPU_VM_OP_RESERVE_VMID:
2734 /* We only have requirement to reserve vmid from gfxhub */
2735 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2736 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2737 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2738 }
2739
2740 break;
2741 case AMDGPU_VM_OP_UNRESERVE_VMID:
2742 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2743 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2744 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2745 }
2746 break;
2747 default:
2748 return -EINVAL;
2749 }
2750
2751 return 0;
2752 }
2753
2754 /**
2755 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2756 * @adev: amdgpu device pointer
2757 * @pasid: PASID of the VM
2758 * @vmid: VMID, only used for GFX 9.4.3.
2759 * @node_id: Node_id received in IH cookie. Only applicable for
2760 * GFX 9.4.3.
2761 * @addr: Address of the fault
2762 * @write_fault: true is write fault, false is read fault
2763 *
2764 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2765 * shouldn't be reported any more.
2766 */
amdgpu_vm_handle_fault(struct amdgpu_device * adev,u32 pasid,u32 vmid,u32 node_id,uint64_t addr,bool write_fault)2767 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2768 u32 vmid, u32 node_id, uint64_t addr,
2769 bool write_fault)
2770 {
2771 bool is_compute_context = false;
2772 struct amdgpu_bo *root;
2773 unsigned long irqflags;
2774 uint64_t value, flags;
2775 struct amdgpu_vm *vm;
2776 int r;
2777
2778 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2779 vm = xa_load(&adev->vm_manager.pasids, pasid);
2780 if (vm) {
2781 root = amdgpu_bo_ref(vm->root.bo);
2782 is_compute_context = vm->is_compute_context;
2783 } else {
2784 root = NULL;
2785 }
2786 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2787
2788 if (!root)
2789 return false;
2790
2791 addr /= AMDGPU_GPU_PAGE_SIZE;
2792
2793 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2794 node_id, addr, write_fault)) {
2795 amdgpu_bo_unref(&root);
2796 return true;
2797 }
2798
2799 r = amdgpu_bo_reserve(root, true);
2800 if (r)
2801 goto error_unref;
2802
2803 /* Double check that the VM still exists */
2804 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2805 vm = xa_load(&adev->vm_manager.pasids, pasid);
2806 if (vm && vm->root.bo != root)
2807 vm = NULL;
2808 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2809 if (!vm)
2810 goto error_unlock;
2811
2812 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2813 AMDGPU_PTE_SYSTEM;
2814
2815 if (is_compute_context) {
2816 /* Intentionally setting invalid PTE flag
2817 * combination to force a no-retry-fault
2818 */
2819 flags = AMDGPU_VM_NORETRY_FLAGS;
2820 value = 0;
2821 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2822 /* Redirect the access to the dummy page */
2823 value = adev->dummy_page_addr;
2824 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2825 AMDGPU_PTE_WRITEABLE;
2826
2827 } else {
2828 /* Let the hw retry silently on the PTE */
2829 value = 0;
2830 }
2831
2832 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2833 if (r) {
2834 pr_debug("failed %d to reserve fence slot\n", r);
2835 goto error_unlock;
2836 }
2837
2838 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2839 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2840 if (r)
2841 goto error_unlock;
2842
2843 r = amdgpu_vm_update_pdes(adev, vm, true);
2844
2845 error_unlock:
2846 amdgpu_bo_unreserve(root);
2847 if (r < 0)
2848 DRM_ERROR("Can't handle page fault (%d)\n", r);
2849
2850 error_unref:
2851 amdgpu_bo_unref(&root);
2852
2853 return false;
2854 }
2855
2856 #if defined(CONFIG_DEBUG_FS)
2857 /**
2858 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2859 *
2860 * @vm: Requested VM for printing BO info
2861 * @m: debugfs file
2862 *
2863 * Print BO information in debugfs file for the VM
2864 */
amdgpu_debugfs_vm_bo_info(struct amdgpu_vm * vm,struct seq_file * m)2865 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2866 {
2867 struct amdgpu_bo_va *bo_va, *tmp;
2868 u64 total_idle = 0;
2869 u64 total_evicted = 0;
2870 u64 total_relocated = 0;
2871 u64 total_moved = 0;
2872 u64 total_invalidated = 0;
2873 u64 total_done = 0;
2874 unsigned int total_idle_objs = 0;
2875 unsigned int total_evicted_objs = 0;
2876 unsigned int total_relocated_objs = 0;
2877 unsigned int total_moved_objs = 0;
2878 unsigned int total_invalidated_objs = 0;
2879 unsigned int total_done_objs = 0;
2880 unsigned int id = 0;
2881
2882 spin_lock(&vm->status_lock);
2883 seq_puts(m, "\tIdle BOs:\n");
2884 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2885 if (!bo_va->base.bo)
2886 continue;
2887 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2888 }
2889 total_idle_objs = id;
2890 id = 0;
2891
2892 seq_puts(m, "\tEvicted BOs:\n");
2893 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2894 if (!bo_va->base.bo)
2895 continue;
2896 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2897 }
2898 total_evicted_objs = id;
2899 id = 0;
2900
2901 seq_puts(m, "\tRelocated BOs:\n");
2902 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2903 if (!bo_va->base.bo)
2904 continue;
2905 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2906 }
2907 total_relocated_objs = id;
2908 id = 0;
2909
2910 seq_puts(m, "\tMoved BOs:\n");
2911 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2912 if (!bo_va->base.bo)
2913 continue;
2914 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2915 }
2916 total_moved_objs = id;
2917 id = 0;
2918
2919 seq_puts(m, "\tInvalidated BOs:\n");
2920 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2921 if (!bo_va->base.bo)
2922 continue;
2923 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2924 }
2925 total_invalidated_objs = id;
2926 id = 0;
2927
2928 seq_puts(m, "\tDone BOs:\n");
2929 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2930 if (!bo_va->base.bo)
2931 continue;
2932 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2933 }
2934 spin_unlock(&vm->status_lock);
2935 total_done_objs = id;
2936
2937 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2938 total_idle_objs);
2939 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2940 total_evicted_objs);
2941 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2942 total_relocated_objs);
2943 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2944 total_moved_objs);
2945 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2946 total_invalidated_objs);
2947 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2948 total_done_objs);
2949 }
2950 #endif
2951
2952 /**
2953 * amdgpu_vm_update_fault_cache - update cached fault into.
2954 * @adev: amdgpu device pointer
2955 * @pasid: PASID of the VM
2956 * @addr: Address of the fault
2957 * @status: GPUVM fault status register
2958 * @vmhub: which vmhub got the fault
2959 *
2960 * Cache the fault info for later use by userspace in debugging.
2961 */
amdgpu_vm_update_fault_cache(struct amdgpu_device * adev,unsigned int pasid,uint64_t addr,uint32_t status,unsigned int vmhub)2962 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2963 unsigned int pasid,
2964 uint64_t addr,
2965 uint32_t status,
2966 unsigned int vmhub)
2967 {
2968 struct amdgpu_vm *vm;
2969 unsigned long flags;
2970
2971 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2972
2973 vm = xa_load(&adev->vm_manager.pasids, pasid);
2974 /* Don't update the fault cache if status is 0. In the multiple
2975 * fault case, subsequent faults will return a 0 status which is
2976 * useless for userspace and replaces the useful fault status, so
2977 * only update if status is non-0.
2978 */
2979 if (vm && status) {
2980 vm->fault_info.addr = addr;
2981 vm->fault_info.status = status;
2982 /*
2983 * Update the fault information globally for later usage
2984 * when vm could be stale or freed.
2985 */
2986 adev->vm_manager.fault_info.addr = addr;
2987 adev->vm_manager.fault_info.vmhub = vmhub;
2988 adev->vm_manager.fault_info.status = status;
2989
2990 if (AMDGPU_IS_GFXHUB(vmhub)) {
2991 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
2992 vm->fault_info.vmhub |=
2993 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
2994 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
2995 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
2996 vm->fault_info.vmhub |=
2997 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
2998 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
2999 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
3000 vm->fault_info.vmhub |=
3001 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
3002 } else {
3003 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
3004 }
3005 }
3006 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
3007 }
3008
3009