1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
31 * southbridges.
32 * Please see the following specifications for the descriptions of the
33 * registers and flags:
34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
36 * - AMD SB700/710/750 Register Reference Guide (RRG)
37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
38 * - AMD SB700/710/750 Register Programming Requirements (RPR)
39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf
42 * Please see the following for Watchdog Resource Table specification:
43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
46 * specifications, but the table hasn't been spotted in the wild yet.
47 */
48
49 #include <sys/cdefs.h>
50 #include "opt_amdsbwd.h"
51
52 #include <sys/param.h>
53 #include <sys/eventhandler.h>
54 #include <sys/kernel.h>
55 #include <sys/module.h>
56 #include <sys/systm.h>
57 #include <sys/sysctl.h>
58 #include <sys/bus.h>
59 #include <machine/bus.h>
60 #include <sys/rman.h>
61 #include <machine/cputypes.h>
62 #include <machine/md_var.h>
63 #include <machine/resource.h>
64 #include <sys/watchdog.h>
65
66 #include <dev/pci/pcivar.h>
67 #include <dev/amdsbwd/amd_chipset.h>
68 #include <isa/isavar.h>
69
70 /*
71 * Registers in the Watchdog IO space.
72 * See SB7xx RRG 2.3.4, WDRT.
73 */
74 #define AMDSB_WD_CTRL 0x00
75 #define AMDSB_WD_RUN 0x01
76 #define AMDSB_WD_FIRED 0x02
77 #define AMDSB_WD_SHUTDOWN 0x04
78 #define AMDSB_WD_DISABLE 0x08
79 #define AMDSB_WD_RESERVED 0x70
80 #define AMDSB_WD_RELOAD 0x80
81 #define AMDSB_WD_COUNT 0x04
82 #define AMDSB_WD_COUNT_MASK 0xffff
83 #define AMDSB_WDIO_REG_WIDTH 4
84
85 #define amdsbwd_verbose_printf(dev, ...) \
86 do { \
87 if (bootverbose) \
88 device_printf(dev, __VA_ARGS__);\
89 } while (0)
90
91 struct amdsbwd_softc {
92 device_t dev;
93 eventhandler_tag ev_tag;
94 struct resource *res_ctrl;
95 struct resource *res_count;
96 int rid_ctrl;
97 int rid_count;
98 int ms_per_tick;
99 int max_ticks;
100 int active;
101 unsigned int timeout;
102 };
103
104 static void amdsbwd_identify(driver_t *driver, device_t parent);
105 static int amdsbwd_probe(device_t dev);
106 static int amdsbwd_attach(device_t dev);
107 static int amdsbwd_detach(device_t dev);
108 static int amdsbwd_suspend(device_t dev);
109 static int amdsbwd_resume(device_t dev);
110
111 static device_method_t amdsbwd_methods[] = {
112 DEVMETHOD(device_identify, amdsbwd_identify),
113 DEVMETHOD(device_probe, amdsbwd_probe),
114 DEVMETHOD(device_attach, amdsbwd_attach),
115 DEVMETHOD(device_detach, amdsbwd_detach),
116 DEVMETHOD(device_suspend, amdsbwd_suspend),
117 DEVMETHOD(device_resume, amdsbwd_resume),
118 #if 0
119 DEVMETHOD(device_shutdown, amdsbwd_detach),
120 #endif
121 DEVMETHOD_END
122 };
123
124 static driver_t amdsbwd_driver = {
125 "amdsbwd",
126 amdsbwd_methods,
127 sizeof(struct amdsbwd_softc)
128 };
129
130 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, NULL, NULL);
131
132 static uint8_t
pmio_read(struct resource * res,uint8_t reg)133 pmio_read(struct resource *res, uint8_t reg)
134 {
135 bus_write_1(res, 0, reg); /* Index */
136 return (bus_read_1(res, 1)); /* Data */
137 }
138
139 static void
pmio_write(struct resource * res,uint8_t reg,uint8_t val)140 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
141 {
142 bus_write_1(res, 0, reg); /* Index */
143 bus_write_1(res, 1, val); /* Data */
144 }
145
146 static uint32_t
wdctrl_read(struct amdsbwd_softc * sc)147 wdctrl_read(struct amdsbwd_softc *sc)
148 {
149 return (bus_read_4(sc->res_ctrl, 0));
150 }
151
152 static void
wdctrl_write(struct amdsbwd_softc * sc,uint32_t val)153 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
154 {
155 bus_write_4(sc->res_ctrl, 0, val);
156 }
157
158 static __unused uint32_t
wdcount_read(struct amdsbwd_softc * sc)159 wdcount_read(struct amdsbwd_softc *sc)
160 {
161 return (bus_read_4(sc->res_count, 0));
162 }
163
164 static void
wdcount_write(struct amdsbwd_softc * sc,uint32_t val)165 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
166 {
167 bus_write_4(sc->res_count, 0, val);
168 }
169
170 static void
amdsbwd_tmr_enable(struct amdsbwd_softc * sc)171 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
172 {
173 uint32_t val;
174
175 val = wdctrl_read(sc);
176 val |= AMDSB_WD_RUN;
177 wdctrl_write(sc, val);
178 sc->active = 1;
179 amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
180 }
181
182 static void
amdsbwd_tmr_disable(struct amdsbwd_softc * sc)183 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
184 {
185 uint32_t val;
186
187 val = wdctrl_read(sc);
188 val &= ~AMDSB_WD_RUN;
189 wdctrl_write(sc, val);
190 sc->active = 0;
191 amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
192 }
193
194 static void
amdsbwd_tmr_reload(struct amdsbwd_softc * sc)195 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
196 {
197 uint32_t val;
198
199 val = wdctrl_read(sc);
200 val |= AMDSB_WD_RELOAD;
201 wdctrl_write(sc, val);
202 }
203
204 static void
amdsbwd_tmr_set(struct amdsbwd_softc * sc,uint16_t timeout)205 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
206 {
207
208 timeout &= AMDSB_WD_COUNT_MASK;
209 wdcount_write(sc, timeout);
210 sc->timeout = timeout;
211 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
212 }
213
214 static void
amdsbwd_event(void * arg,unsigned int cmd,int * error)215 amdsbwd_event(void *arg, unsigned int cmd, int *error)
216 {
217 struct amdsbwd_softc *sc = arg;
218 uint64_t timeout;
219
220 if (cmd != 0) {
221 timeout = 0;
222 cmd &= WD_INTERVAL;
223 if (cmd >= WD_TO_1MS) {
224 timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
225 timeout = timeout / sc->ms_per_tick;
226 }
227 /* For a too short timeout use 1 tick. */
228 if (timeout == 0)
229 timeout = 1;
230 /* For a too long timeout stop the timer. */
231 if (timeout > sc->max_ticks)
232 timeout = 0;
233 } else {
234 timeout = 0;
235 }
236
237 if (timeout != 0) {
238 if (timeout != sc->timeout)
239 amdsbwd_tmr_set(sc, timeout);
240 if (!sc->active)
241 amdsbwd_tmr_enable(sc);
242 amdsbwd_tmr_reload(sc);
243 *error = 0;
244 } else {
245 if (sc->active)
246 amdsbwd_tmr_disable(sc);
247 }
248 }
249
250 static void
amdsbwd_identify(driver_t * driver,device_t parent)251 amdsbwd_identify(driver_t *driver, device_t parent)
252 {
253 device_t child;
254 device_t smb_dev;
255
256 if (resource_disabled("amdsbwd", 0))
257 return;
258 if (device_find_child(parent, "amdsbwd", -1) != NULL)
259 return;
260
261 /*
262 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
263 * that should be present at bus 0, device 20, function 0.
264 */
265 smb_dev = pci_find_bsf(0, 20, 0);
266 if (smb_dev == NULL)
267 return;
268 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
269 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
270 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID &&
271 pci_get_devid(smb_dev) != HYGONCZ_SMBUS_DEVID)
272 return;
273
274 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
275 if (child == NULL)
276 device_printf(parent, "add amdsbwd child failed\n");
277 }
278
279 static void
amdsbwd_probe_sb7xx(device_t dev,struct resource * pmres,uint32_t * addr)280 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
281 {
282 uint8_t val;
283 int i;
284
285 /* Report cause of previous reset for user's convenience. */
286 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
287 if (val != 0)
288 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
289 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
290 if (val != 0)
291 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
292 if ((val & AMDSB_WD_RST_STS) != 0)
293 device_printf(dev, "Previous Reset was caused by Watchdog\n");
294
295 /* Find base address of memory mapped WDT registers. */
296 for (*addr = 0, i = 0; i < 4; i++) {
297 *addr <<= 8;
298 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
299 }
300 *addr &= ~0x07u;
301
302 /* Set watchdog timer tick to 1s. */
303 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
304 val &= ~AMDSB_WDT_RES_MASK;
305 val |= AMDSB_WDT_RES_1S;
306 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
307
308 /* Enable watchdog device (in stopped state). */
309 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
310 val &= ~AMDSB_WDT_DISABLE;
311 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
312
313 /*
314 * XXX TODO: Ensure that watchdog decode is enabled
315 * (register 0x41, bit 3).
316 */
317 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
318 }
319
320 static void
amdsbwd_probe_sb8xx(device_t dev,struct resource * pmres,uint32_t * addr)321 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
322 {
323 uint32_t val;
324 int i;
325
326 /* Report cause of previous reset for user's convenience. */
327
328 val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL);
329 if ((val & AMDSB8_RST_STS_DIS) != 0) {
330 val &= ~AMDSB8_RST_STS_DIS;
331 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val);
332 }
333 val = 0;
334 for (i = 3; i >= 0; i--) {
335 val <<= 8;
336 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i);
337 }
338 if (val != 0)
339 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val);
340 if ((val & AMDSB8_WD_RST_STS) != 0)
341 device_printf(dev, "Previous Reset was caused by Watchdog\n");
342
343 /* Find base address of memory mapped WDT registers. */
344 for (*addr = 0, i = 0; i < 4; i++) {
345 *addr <<= 8;
346 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
347 }
348 *addr &= ~0x07u;
349
350 /* Set watchdog timer tick to 1s. */
351 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
352 val &= ~AMDSB8_WDT_RES_MASK;
353 val |= AMDSB8_WDT_1HZ;
354 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
355 #ifdef AMDSBWD_DEBUG
356 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
357 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
358 #endif
359
360 /*
361 * Enable watchdog device (in stopped state)
362 * and decoding of its address.
363 */
364 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
365 val &= ~AMDSB8_WDT_DISABLE;
366 val |= AMDSB8_WDT_DEC_EN;
367 pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
368 #ifdef AMDSBWD_DEBUG
369 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
370 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
371 #endif
372 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
373 }
374
375 static void
amdsbwd_probe_fch41(device_t dev,struct resource * pmres,uint32_t * addr)376 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
377 {
378 uint8_t val;
379
380 /*
381 * Enable decoding of watchdog MMIO address.
382 */
383 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
384 val |= AMDFCH41_WDT_EN;
385 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
386 #ifdef AMDSBWD_DEBUG
387 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
388 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val);
389 #endif
390
391 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
392 if ((val & AMDFCH41_MMIO_EN) != 0) {
393 /* Fixed offset for the watchdog within ACPI MMIO range. */
394 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
395 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
396 } else {
397 /* Special fixed MMIO range for the watchdog. */
398 *addr = AMDFCH41_WDT_FIXED_ADDR;
399 }
400
401 /*
402 * Set watchdog timer tick to 1s and
403 * enable the watchdog device (in stopped state).
404 */
405 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
406 val &= ~AMDFCH41_WDT_RES_MASK;
407 val |= AMDFCH41_WDT_RES_1S;
408 val &= ~AMDFCH41_WDT_EN_MASK;
409 val |= AMDFCH41_WDT_ENABLE;
410 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
411 #ifdef AMDSBWD_DEBUG
412 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
413 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
414 val);
415 #endif
416 device_set_descf(dev, "%s FCH Rev 41h+ Watchdog Timer",
417 cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD");
418 }
419
420 static int
amdsbwd_probe(device_t dev)421 amdsbwd_probe(device_t dev)
422 {
423 struct resource *res;
424 device_t smb_dev;
425 uint32_t addr;
426 int rid;
427 int rc;
428 uint32_t devid;
429 uint8_t revid;
430
431 /* Do not claim some ISA PnP device by accident. */
432 if (isa_get_logicalid(dev) != 0)
433 return (ENXIO);
434
435 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
436 AMDSB_PMIO_WIDTH);
437 if (rc != 0) {
438 device_printf(dev, "bus_set_resource for IO failed\n");
439 return (ENXIO);
440 }
441 rid = 0;
442 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
443 RF_ACTIVE | RF_SHAREABLE);
444 if (res == NULL) {
445 device_printf(dev, "bus_alloc_resource for IO failed\n");
446 return (ENXIO);
447 }
448
449 smb_dev = pci_find_bsf(0, 20, 0);
450 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
451 devid = pci_get_devid(smb_dev);
452 revid = pci_get_revid(smb_dev);
453 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
454 amdsbwd_probe_sb7xx(dev, res, &addr);
455 else if (devid == AMDSB_SMBUS_DEVID ||
456 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
457 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID))
458 amdsbwd_probe_sb8xx(dev, res, &addr);
459 else
460 amdsbwd_probe_fch41(dev, res, &addr);
461
462 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
463 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
464
465 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
466 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
467 AMDSB_WDIO_REG_WIDTH);
468 if (rc != 0) {
469 device_printf(dev, "bus_set_resource for control failed\n");
470 return (ENXIO);
471 }
472 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
473 AMDSB_WDIO_REG_WIDTH);
474 if (rc != 0) {
475 device_printf(dev, "bus_set_resource for count failed\n");
476 return (ENXIO);
477 }
478
479 return (0);
480 }
481
482 static int
amdsbwd_attach_sb(device_t dev,struct amdsbwd_softc * sc)483 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
484 {
485
486 sc->max_ticks = UINT16_MAX;
487 sc->rid_ctrl = 0;
488 sc->rid_count = 1;
489
490 sc->ms_per_tick = 1000;
491
492 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
493 &sc->rid_ctrl, RF_ACTIVE);
494 if (sc->res_ctrl == NULL) {
495 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
496 return (ENXIO);
497 }
498 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
499 &sc->rid_count, RF_ACTIVE);
500 if (sc->res_count == NULL) {
501 device_printf(dev, "bus_alloc_resource for count failed\n");
502 return (ENXIO);
503 }
504 return (0);
505 }
506
507 static int
amdsbwd_attach(device_t dev)508 amdsbwd_attach(device_t dev)
509 {
510 struct amdsbwd_softc *sc;
511 int rc;
512
513 sc = device_get_softc(dev);
514 sc->dev = dev;
515
516 rc = amdsbwd_attach_sb(dev, sc);
517 if (rc != 0)
518 goto fail;
519
520 #ifdef AMDSBWD_DEBUG
521 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
522 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
523 #endif
524
525 /* Setup initial state of Watchdog Control. */
526 wdctrl_write(sc, AMDSB_WD_FIRED);
527
528 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
529 device_printf(dev, "watchdog hardware is disabled\n");
530 goto fail;
531 }
532
533 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
534 EVENTHANDLER_PRI_ANY);
535
536 return (0);
537
538 fail:
539 amdsbwd_detach(dev);
540 return (ENXIO);
541 }
542
543 static int
amdsbwd_detach(device_t dev)544 amdsbwd_detach(device_t dev)
545 {
546 struct amdsbwd_softc *sc;
547
548 sc = device_get_softc(dev);
549 if (sc->ev_tag != NULL)
550 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
551
552 if (sc->active)
553 amdsbwd_tmr_disable(sc);
554
555 if (sc->res_ctrl != NULL)
556 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
557 sc->res_ctrl);
558
559 if (sc->res_count != NULL)
560 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
561 sc->res_count);
562
563 return (0);
564 }
565
566 static int
amdsbwd_suspend(device_t dev)567 amdsbwd_suspend(device_t dev)
568 {
569 struct amdsbwd_softc *sc;
570 uint32_t val;
571
572 sc = device_get_softc(dev);
573 val = wdctrl_read(sc);
574 val &= ~AMDSB_WD_RUN;
575 wdctrl_write(sc, val);
576 return (0);
577 }
578
579 static int
amdsbwd_resume(device_t dev)580 amdsbwd_resume(device_t dev)
581 {
582 struct amdsbwd_softc *sc;
583
584 sc = device_get_softc(dev);
585 wdctrl_write(sc, AMDSB_WD_FIRED);
586 if (sc->active) {
587 amdsbwd_tmr_set(sc, sc->timeout);
588 amdsbwd_tmr_enable(sc);
589 amdsbwd_tmr_reload(sc);
590 }
591 return (0);
592 }
593