1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the RegisterBankInfo class.
10 //===----------------------------------------------------------------------===//
11
12 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/ADT/iterator_range.h"
17 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetOpcodes.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28
29 #include <algorithm> // For std::max.
30
31 #define DEBUG_TYPE "registerbankinfo"
32
33 using namespace llvm;
34
35 STATISTIC(NumPartialMappingsCreated,
36 "Number of partial mappings dynamically created");
37 STATISTIC(NumPartialMappingsAccessed,
38 "Number of partial mappings dynamically accessed");
39 STATISTIC(NumValueMappingsCreated,
40 "Number of value mappings dynamically created");
41 STATISTIC(NumValueMappingsAccessed,
42 "Number of value mappings dynamically accessed");
43 STATISTIC(NumOperandsMappingsCreated,
44 "Number of operands mappings dynamically created");
45 STATISTIC(NumOperandsMappingsAccessed,
46 "Number of operands mappings dynamically accessed");
47 STATISTIC(NumInstructionMappingsCreated,
48 "Number of instruction mappings dynamically created");
49 STATISTIC(NumInstructionMappingsAccessed,
50 "Number of instruction mappings dynamically accessed");
51
52 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
53 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
54
55 //------------------------------------------------------------------------------
56 // RegisterBankInfo implementation.
57 //------------------------------------------------------------------------------
RegisterBankInfo(RegisterBank ** RegBanks,unsigned NumRegBanks)58 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
59 unsigned NumRegBanks)
60 : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
61 #ifndef NDEBUG
62 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
63 assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
64 assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
65 }
66 #endif // NDEBUG
67 }
68
verify(const TargetRegisterInfo & TRI) const69 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
70 #ifndef NDEBUG
71 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
72 const RegisterBank &RegBank = getRegBank(Idx);
73 assert(Idx == RegBank.getID() &&
74 "ID does not match the index in the array");
75 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n');
76 assert(RegBank.verify(TRI) && "RegBank is invalid");
77 }
78 #endif // NDEBUG
79 return true;
80 }
81
82 const RegisterBank *
getRegBank(Register Reg,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const83 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
84 const TargetRegisterInfo &TRI) const {
85 if (Register::isPhysicalRegister(Reg)) {
86 // FIXME: This was probably a copy to a virtual register that does have a
87 // type we could use.
88 return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT());
89 }
90
91 assert(Reg && "NoRegister does not have a register bank");
92 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
93 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
94 return RB;
95 if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
96 return &getRegBankFromRegClass(*RC, MRI.getType(Reg));
97 return nullptr;
98 }
99
100 const TargetRegisterClass &
getMinimalPhysRegClass(Register Reg,const TargetRegisterInfo & TRI) const101 RegisterBankInfo::getMinimalPhysRegClass(Register Reg,
102 const TargetRegisterInfo &TRI) const {
103 assert(Register::isPhysicalRegister(Reg) && "Reg must be a physreg");
104 const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
105 if (RegRCIt != PhysRegMinimalRCs.end())
106 return *RegRCIt->second;
107 const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
108 PhysRegMinimalRCs[Reg] = PhysRC;
109 return *PhysRC;
110 }
111
getRegBankFromConstraints(const MachineInstr & MI,unsigned OpIdx,const TargetInstrInfo & TII,const MachineRegisterInfo & MRI) const112 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
113 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
114 const MachineRegisterInfo &MRI) const {
115 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
116
117 // The mapping of the registers may be available via the
118 // register class constraints.
119 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI);
120
121 if (!RC)
122 return nullptr;
123
124 Register Reg = MI.getOperand(OpIdx).getReg();
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg));
126 // Sanity check that the target properly implemented getRegBankFromRegClass.
127 assert(RegBank.covers(*RC) &&
128 "The mapping of the register bank does not make sense");
129 return &RegBank;
130 }
131
constrainGenericRegister(Register Reg,const TargetRegisterClass & RC,MachineRegisterInfo & MRI)132 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
133 Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
134
135 // If the register already has a class, fallback to MRI::constrainRegClass.
136 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
137 if (RegClassOrBank.is<const TargetRegisterClass *>())
138 return MRI.constrainRegClass(Reg, &RC);
139
140 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
141 // Otherwise, all we can do is ensure the bank covers the class, and set it.
142 if (RB && !RB->covers(RC))
143 return nullptr;
144
145 // If nothing was set or the class is simply compatible, set it.
146 MRI.setRegClass(Reg, &RC);
147 return &RC;
148 }
149
150 /// Check whether or not \p MI should be treated like a copy
151 /// for the mappings.
152 /// Copy like instruction are special for mapping because
153 /// they don't have actual register constraints. Moreover,
154 /// they sometimes have register classes assigned and we can
155 /// just use that instead of failing to provide a generic mapping.
isCopyLike(const MachineInstr & MI)156 static bool isCopyLike(const MachineInstr &MI) {
157 return MI.isCopy() || MI.isPHI() ||
158 MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
159 }
160
161 const RegisterBankInfo::InstructionMapping &
getInstrMappingImpl(const MachineInstr & MI) const162 RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
163 // For copies we want to walk over the operands and try to find one
164 // that has a register bank since the instruction itself will not get
165 // us any constraint.
166 bool IsCopyLike = isCopyLike(MI);
167 // For copy like instruction, only the mapping of the definition
168 // is important. The rest is not constrained.
169 unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
170
171 const MachineFunction &MF = *MI.getMF();
172 const TargetSubtargetInfo &STI = MF.getSubtarget();
173 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
174 const MachineRegisterInfo &MRI = MF.getRegInfo();
175 // We may need to query the instruction encoding to guess the mapping.
176 const TargetInstrInfo &TII = *STI.getInstrInfo();
177
178 // Before doing anything complicated check if the mapping is not
179 // directly available.
180 bool CompleteMapping = true;
181
182 SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
183 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
184 ++OpIdx) {
185 const MachineOperand &MO = MI.getOperand(OpIdx);
186 if (!MO.isReg())
187 continue;
188 Register Reg = MO.getReg();
189 if (!Reg)
190 continue;
191 // The register bank of Reg is just a side effect of the current
192 // excution and in particular, there is no reason to believe this
193 // is the best default mapping for the current instruction. Keep
194 // it as an alternative register bank if we cannot figure out
195 // something.
196 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
197 // For copy-like instruction, we want to reuse the register bank
198 // that is already set on Reg, if any, since those instructions do
199 // not have any constraints.
200 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
201 if (!CurRegBank) {
202 // If this is a target specific instruction, we can deduce
203 // the register bank from the encoding constraints.
204 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI);
205 if (!CurRegBank) {
206 // All our attempts failed, give up.
207 CompleteMapping = false;
208
209 if (!IsCopyLike)
210 // MI does not carry enough information to guess the mapping.
211 return getInvalidInstructionMapping();
212 continue;
213 }
214 }
215
216 unsigned Size = getSizeInBits(Reg, MRI, TRI);
217 const ValueMapping *ValMapping = &getValueMapping(0, Size, *CurRegBank);
218 if (IsCopyLike) {
219 if (!OperandsMapping[0]) {
220 if (MI.isRegSequence()) {
221 // For reg_sequence, the result size does not match the input.
222 unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),
223 MRI, TRI);
224 OperandsMapping[0] = &getValueMapping(0, ResultSize, *CurRegBank);
225 } else {
226 OperandsMapping[0] = ValMapping;
227 }
228 }
229
230 // The default handling assumes any register bank can be copied to any
231 // other. If this isn't the case, the target should specially deal with
232 // reg_sequence/phi. There may also be unsatisfiable copies.
233 for (; OpIdx != EndIdx; ++OpIdx) {
234 const MachineOperand &MO = MI.getOperand(OpIdx);
235 if (!MO.isReg())
236 continue;
237 Register Reg = MO.getReg();
238 if (!Reg)
239 continue;
240
241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
242 if (AltRegBank &&
243 cannotCopy(*CurRegBank, *AltRegBank, getSizeInBits(Reg, MRI, TRI)))
244 return getInvalidInstructionMapping();
245 }
246
247 CompleteMapping = true;
248 break;
249 }
250
251 OperandsMapping[OpIdx] = ValMapping;
252 }
253
254 if (IsCopyLike && !CompleteMapping) {
255 // No way to deduce the type from what we have.
256 return getInvalidInstructionMapping();
257 }
258
259 assert(CompleteMapping && "Setting an uncomplete mapping");
260 return getInstructionMapping(
261 DefaultMappingID, /*Cost*/ 1,
262 /*OperandsMapping*/ getOperandsMapping(OperandsMapping),
263 NumOperandsForMapping);
264 }
265
266 /// Hashing function for PartialMapping.
hashPartialMapping(unsigned StartIdx,unsigned Length,const RegisterBank * RegBank)267 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
268 const RegisterBank *RegBank) {
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
270 }
271
272 /// Overloaded version of hash_value for a PartialMapping.
273 hash_code
hash_value(const RegisterBankInfo::PartialMapping & PartMapping)274 llvm::hash_value(const RegisterBankInfo::PartialMapping &PartMapping) {
275 return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
276 PartMapping.RegBank);
277 }
278
279 const RegisterBankInfo::PartialMapping &
getPartialMapping(unsigned StartIdx,unsigned Length,const RegisterBank & RegBank) const280 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
281 const RegisterBank &RegBank) const {
282 ++NumPartialMappingsAccessed;
283
284 hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
285 const auto &It = MapOfPartialMappings.find(Hash);
286 if (It != MapOfPartialMappings.end())
287 return *It->second;
288
289 ++NumPartialMappingsCreated;
290
291 auto &PartMapping = MapOfPartialMappings[Hash];
292 PartMapping = std::make_unique<PartialMapping>(StartIdx, Length, RegBank);
293 return *PartMapping;
294 }
295
296 const RegisterBankInfo::ValueMapping &
getValueMapping(unsigned StartIdx,unsigned Length,const RegisterBank & RegBank) const297 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
298 const RegisterBank &RegBank) const {
299 return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
300 }
301
302 static hash_code
hashValueMapping(const RegisterBankInfo::PartialMapping * BreakDown,unsigned NumBreakDowns)303 hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown,
304 unsigned NumBreakDowns) {
305 if (LLVM_LIKELY(NumBreakDowns == 1))
306 return hash_value(*BreakDown);
307 SmallVector<size_t, 8> Hashes(NumBreakDowns);
308 for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
309 Hashes.push_back(hash_value(BreakDown[Idx]));
310 return hash_combine_range(Hashes.begin(), Hashes.end());
311 }
312
313 const RegisterBankInfo::ValueMapping &
getValueMapping(const PartialMapping * BreakDown,unsigned NumBreakDowns) const314 RegisterBankInfo::getValueMapping(const PartialMapping *BreakDown,
315 unsigned NumBreakDowns) const {
316 ++NumValueMappingsAccessed;
317
318 hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
319 const auto &It = MapOfValueMappings.find(Hash);
320 if (It != MapOfValueMappings.end())
321 return *It->second;
322
323 ++NumValueMappingsCreated;
324
325 auto &ValMapping = MapOfValueMappings[Hash];
326 ValMapping = std::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
327 return *ValMapping;
328 }
329
330 template <typename Iterator>
331 const RegisterBankInfo::ValueMapping *
getOperandsMapping(Iterator Begin,Iterator End) const332 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
333
334 ++NumOperandsMappingsAccessed;
335
336 // The addresses of the value mapping are unique.
337 // Therefore, we can use them directly to hash the operand mapping.
338 hash_code Hash = hash_combine_range(Begin, End);
339 auto &Res = MapOfOperandsMappings[Hash];
340 if (Res)
341 return Res.get();
342
343 ++NumOperandsMappingsCreated;
344
345 // Create the array of ValueMapping.
346 // Note: this array will not hash to this instance of operands
347 // mapping, because we use the pointer of the ValueMapping
348 // to hash and we expect them to uniquely identify an instance
349 // of value mapping.
350 Res = std::make_unique<ValueMapping[]>(std::distance(Begin, End));
351 unsigned Idx = 0;
352 for (Iterator It = Begin; It != End; ++It, ++Idx) {
353 const ValueMapping *ValMap = *It;
354 if (!ValMap)
355 continue;
356 Res[Idx] = *ValMap;
357 }
358 return Res.get();
359 }
360
getOperandsMapping(const SmallVectorImpl<const RegisterBankInfo::ValueMapping * > & OpdsMapping) const361 const RegisterBankInfo::ValueMapping *RegisterBankInfo::getOperandsMapping(
362 const SmallVectorImpl<const RegisterBankInfo::ValueMapping *> &OpdsMapping)
363 const {
364 return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
365 }
366
getOperandsMapping(std::initializer_list<const RegisterBankInfo::ValueMapping * > OpdsMapping) const367 const RegisterBankInfo::ValueMapping *RegisterBankInfo::getOperandsMapping(
368 std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
369 const {
370 return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
371 }
372
373 static hash_code
hashInstructionMapping(unsigned ID,unsigned Cost,const RegisterBankInfo::ValueMapping * OperandsMapping,unsigned NumOperands)374 hashInstructionMapping(unsigned ID, unsigned Cost,
375 const RegisterBankInfo::ValueMapping *OperandsMapping,
376 unsigned NumOperands) {
377 return hash_combine(ID, Cost, OperandsMapping, NumOperands);
378 }
379
380 const RegisterBankInfo::InstructionMapping &
getInstructionMappingImpl(bool IsInvalid,unsigned ID,unsigned Cost,const RegisterBankInfo::ValueMapping * OperandsMapping,unsigned NumOperands) const381 RegisterBankInfo::getInstructionMappingImpl(
382 bool IsInvalid, unsigned ID, unsigned Cost,
383 const RegisterBankInfo::ValueMapping *OperandsMapping,
384 unsigned NumOperands) const {
385 assert(((IsInvalid && ID == InvalidMappingID && Cost == 0 &&
386 OperandsMapping == nullptr && NumOperands == 0) ||
387 !IsInvalid) &&
388 "Mismatch argument for invalid input");
389 ++NumInstructionMappingsAccessed;
390
391 hash_code Hash =
392 hashInstructionMapping(ID, Cost, OperandsMapping, NumOperands);
393 const auto &It = MapOfInstructionMappings.find(Hash);
394 if (It != MapOfInstructionMappings.end())
395 return *It->second;
396
397 ++NumInstructionMappingsCreated;
398
399 auto &InstrMapping = MapOfInstructionMappings[Hash];
400 InstrMapping = std::make_unique<InstructionMapping>(
401 ID, Cost, OperandsMapping, NumOperands);
402 return *InstrMapping;
403 }
404
405 const RegisterBankInfo::InstructionMapping &
getInstrMapping(const MachineInstr & MI) const406 RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
407 const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
408 if (Mapping.isValid())
409 return Mapping;
410 llvm_unreachable("The target must implement this");
411 }
412
413 RegisterBankInfo::InstructionMappings
getInstrPossibleMappings(const MachineInstr & MI) const414 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
415 InstructionMappings PossibleMappings;
416 const auto &Mapping = getInstrMapping(MI);
417 if (Mapping.isValid()) {
418 // Put the default mapping first.
419 PossibleMappings.push_back(&Mapping);
420 }
421
422 // Then the alternative mapping, if any.
423 InstructionMappings AltMappings = getInstrAlternativeMappings(MI);
424 append_range(PossibleMappings, AltMappings);
425 #ifndef NDEBUG
426 for (const InstructionMapping *Mapping : PossibleMappings)
427 assert(Mapping->verify(MI) && "Mapping is invalid");
428 #endif
429 return PossibleMappings;
430 }
431
432 RegisterBankInfo::InstructionMappings
getInstrAlternativeMappings(const MachineInstr & MI) const433 RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
434 // No alternative for MI.
435 return InstructionMappings();
436 }
437
applyDefaultMapping(const OperandsMapper & OpdMapper)438 void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
439 MachineInstr &MI = OpdMapper.getMI();
440 MachineRegisterInfo &MRI = OpdMapper.getMRI();
441 LLVM_DEBUG(dbgs() << "Applying default-like mapping\n");
442 for (unsigned OpIdx = 0,
443 EndIdx = OpdMapper.getInstrMapping().getNumOperands();
444 OpIdx != EndIdx; ++OpIdx) {
445 LLVM_DEBUG(dbgs() << "OpIdx " << OpIdx);
446 MachineOperand &MO = MI.getOperand(OpIdx);
447 if (!MO.isReg()) {
448 LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n");
449 continue;
450 }
451 if (!MO.getReg()) {
452 LLVM_DEBUG(dbgs() << " is $noreg, nothing to be done\n");
453 continue;
454 }
455 assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
456 0 &&
457 "Invalid mapping");
458 assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
459 1 &&
460 "This mapping is too complex for this function");
461 iterator_range<SmallVectorImpl<Register>::const_iterator> NewRegs =
462 OpdMapper.getVRegs(OpIdx);
463 if (NewRegs.empty()) {
464 LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
465 continue;
466 }
467 Register OrigReg = MO.getReg();
468 Register NewReg = *NewRegs.begin();
469 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
470 MO.setReg(NewReg);
471 LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
472
473 // The OperandsMapper creates plain scalar, we may have to fix that.
474 // Check if the types match and if not, fix that.
475 LLT OrigTy = MRI.getType(OrigReg);
476 LLT NewTy = MRI.getType(NewReg);
477 if (OrigTy != NewTy) {
478 // The default mapping is not supposed to change the size of
479 // the storage. However, right now we don't necessarily bump all
480 // the types to storage size. For instance, we can consider
481 // s16 G_AND legal whereas the storage size is going to be 32.
482 assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
483 "Types with difference size cannot be handled by the default "
484 "mapping");
485 LLVM_DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
486 << OrigTy);
487 MRI.setType(NewReg, OrigTy);
488 }
489 LLVM_DEBUG(dbgs() << '\n');
490 }
491 }
492
getSizeInBits(Register Reg,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const493 unsigned RegisterBankInfo::getSizeInBits(Register Reg,
494 const MachineRegisterInfo &MRI,
495 const TargetRegisterInfo &TRI) const {
496 if (Register::isPhysicalRegister(Reg)) {
497 // The size is not directly available for physical registers.
498 // Instead, we need to access a register class that contains Reg and
499 // get the size of that register class.
500 // Because this is expensive, we'll cache the register class by calling
501 auto *RC = &getMinimalPhysRegClass(Reg, TRI);
502 assert(RC && "Expecting Register class");
503 return TRI.getRegSizeInBits(*RC);
504 }
505 return TRI.getRegSizeInBits(Reg, MRI);
506 }
507
508 //------------------------------------------------------------------------------
509 // Helper classes implementation.
510 //------------------------------------------------------------------------------
511 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const512 LLVM_DUMP_METHOD void RegisterBankInfo::PartialMapping::dump() const {
513 print(dbgs());
514 dbgs() << '\n';
515 }
516 #endif
517
verify() const518 bool RegisterBankInfo::PartialMapping::verify() const {
519 assert(RegBank && "Register bank not set");
520 assert(Length && "Empty mapping");
521 assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
522 // Check if the minimum width fits into RegBank.
523 assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
524 return true;
525 }
526
print(raw_ostream & OS) const527 void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
528 OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
529 if (RegBank)
530 OS << *RegBank;
531 else
532 OS << "nullptr";
533 }
534
partsAllUniform() const535 bool RegisterBankInfo::ValueMapping::partsAllUniform() const {
536 if (NumBreakDowns < 2)
537 return true;
538
539 const PartialMapping *First = begin();
540 for (const PartialMapping *Part = First + 1; Part != end(); ++Part) {
541 if (Part->Length != First->Length || Part->RegBank != First->RegBank)
542 return false;
543 }
544
545 return true;
546 }
547
verify(unsigned MeaningfulBitWidth) const548 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
549 assert(NumBreakDowns && "Value mapped nowhere?!");
550 unsigned OrigValueBitWidth = 0;
551 for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
552 // Check that each register bank is big enough to hold the partial value:
553 // this check is done by PartialMapping::verify
554 assert(PartMap.verify() && "Partial mapping is invalid");
555 // The original value should completely be mapped.
556 // Thus the maximum accessed index + 1 is the size of the original value.
557 OrigValueBitWidth =
558 std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
559 }
560 assert(OrigValueBitWidth >= MeaningfulBitWidth &&
561 "Meaningful bits not covered by the mapping");
562 APInt ValueMask(OrigValueBitWidth, 0);
563 for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
564 // Check that the union of the partial mappings covers the whole value,
565 // without overlaps.
566 // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
567 APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
568 PartMap.getHighBitIdx() + 1);
569 ValueMask ^= PartMapMask;
570 assert((ValueMask & PartMapMask) == PartMapMask &&
571 "Some partial mappings overlap");
572 }
573 assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
574 return true;
575 }
576
577 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const578 LLVM_DUMP_METHOD void RegisterBankInfo::ValueMapping::dump() const {
579 print(dbgs());
580 dbgs() << '\n';
581 }
582 #endif
583
print(raw_ostream & OS) const584 void RegisterBankInfo::ValueMapping::print(raw_ostream &OS) const {
585 OS << "#BreakDown: " << NumBreakDowns << " ";
586 bool IsFirst = true;
587 for (const PartialMapping &PartMap : *this) {
588 if (!IsFirst)
589 OS << ", ";
590 OS << '[' << PartMap << ']';
591 IsFirst = false;
592 }
593 }
594
verify(const MachineInstr & MI) const595 bool RegisterBankInfo::InstructionMapping::verify(
596 const MachineInstr &MI) const {
597 // Check that all the register operands are properly mapped.
598 // Check the constructor invariant.
599 // For PHI, we only care about mapping the definition.
600 assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
601 "NumOperands must match, see constructor");
602 assert(MI.getParent() && MI.getMF() &&
603 "MI must be connected to a MachineFunction");
604 const MachineFunction &MF = *MI.getMF();
605 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
606 (void)RBI;
607
608 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
609 const MachineOperand &MO = MI.getOperand(Idx);
610 if (!MO.isReg()) {
611 assert(!getOperandMapping(Idx).isValid() &&
612 "We should not care about non-reg mapping");
613 continue;
614 }
615 Register Reg = MO.getReg();
616 if (!Reg)
617 continue;
618 assert(getOperandMapping(Idx).isValid() &&
619 "We must have a mapping for reg operands");
620 const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
621 (void)MOMapping;
622 // Register size in bits.
623 // This size must match what the mapping expects.
624 assert(MOMapping.verify(RBI->getSizeInBits(
625 Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
626 "Value mapping is invalid");
627 }
628 return true;
629 }
630
631 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const632 LLVM_DUMP_METHOD void RegisterBankInfo::InstructionMapping::dump() const {
633 print(dbgs());
634 dbgs() << '\n';
635 }
636 #endif
637
print(raw_ostream & OS) const638 void RegisterBankInfo::InstructionMapping::print(raw_ostream &OS) const {
639 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
640
641 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
642 const ValueMapping &ValMapping = getOperandMapping(OpIdx);
643 if (OpIdx)
644 OS << ", ";
645 OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
646 }
647 }
648
649 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
650
OperandsMapper(MachineInstr & MI,const InstructionMapping & InstrMapping,MachineRegisterInfo & MRI)651 RegisterBankInfo::OperandsMapper::OperandsMapper(
652 MachineInstr &MI, const InstructionMapping &InstrMapping,
653 MachineRegisterInfo &MRI)
654 : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
655 unsigned NumOpds = InstrMapping.getNumOperands();
656 OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
657 assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
658 }
659
660 iterator_range<SmallVectorImpl<Register>::iterator>
getVRegsMem(unsigned OpIdx)661 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
662 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
663 unsigned NumPartialVal =
664 getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
665 int StartIdx = OpToNewVRegIdx[OpIdx];
666
667 if (StartIdx == OperandsMapper::DontKnowIdx) {
668 // This is the first time we try to access OpIdx.
669 // Create the cells that will hold all the partial values at the
670 // end of the list of NewVReg.
671 StartIdx = NewVRegs.size();
672 OpToNewVRegIdx[OpIdx] = StartIdx;
673 for (unsigned i = 0; i < NumPartialVal; ++i)
674 NewVRegs.push_back(0);
675 }
676 SmallVectorImpl<Register>::iterator End =
677 getNewVRegsEnd(StartIdx, NumPartialVal);
678
679 return make_range(&NewVRegs[StartIdx], End);
680 }
681
682 SmallVectorImpl<Register>::const_iterator
getNewVRegsEnd(unsigned StartIdx,unsigned NumVal) const683 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
684 unsigned NumVal) const {
685 return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
686 }
687 SmallVectorImpl<Register>::iterator
getNewVRegsEnd(unsigned StartIdx,unsigned NumVal)688 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
689 unsigned NumVal) {
690 assert((NewVRegs.size() == StartIdx + NumVal ||
691 NewVRegs.size() > StartIdx + NumVal) &&
692 "NewVRegs too small to contain all the partial mapping");
693 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
694 : &NewVRegs[StartIdx + NumVal];
695 }
696
createVRegs(unsigned OpIdx)697 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) {
698 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
699 iterator_range<SmallVectorImpl<Register>::iterator> NewVRegsForOpIdx =
700 getVRegsMem(OpIdx);
701 const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
702 const PartialMapping *PartMap = ValMapping.begin();
703 for (Register &NewVReg : NewVRegsForOpIdx) {
704 assert(PartMap != ValMapping.end() && "Out-of-bound access");
705 assert(NewVReg == 0 && "Register has already been created");
706 // The new registers are always bound to scalar with the right size.
707 // The actual type has to be set when the target does the mapping
708 // of the instruction.
709 // The rationale is that this generic code cannot guess how the
710 // target plans to split the input type.
711 NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
712 MRI.setRegBank(NewVReg, *PartMap->RegBank);
713 ++PartMap;
714 }
715 }
716
setVRegs(unsigned OpIdx,unsigned PartialMapIdx,Register NewVReg)717 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx,
718 unsigned PartialMapIdx,
719 Register NewVReg) {
720 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
721 assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
722 PartialMapIdx &&
723 "Out-of-bound access for partial mapping");
724 // Make sure the memory is initialized for that operand.
725 (void)getVRegsMem(OpIdx);
726 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
727 "This value is already set");
728 NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
729 }
730
731 iterator_range<SmallVectorImpl<Register>::const_iterator>
getVRegs(unsigned OpIdx,bool ForDebug) const732 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx,
733 bool ForDebug) const {
734 (void)ForDebug;
735 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
736 int StartIdx = OpToNewVRegIdx[OpIdx];
737
738 if (StartIdx == OperandsMapper::DontKnowIdx)
739 return make_range(NewVRegs.end(), NewVRegs.end());
740
741 unsigned PartMapSize =
742 getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
743 SmallVectorImpl<Register>::const_iterator End =
744 getNewVRegsEnd(StartIdx, PartMapSize);
745 iterator_range<SmallVectorImpl<Register>::const_iterator> Res =
746 make_range(&NewVRegs[StartIdx], End);
747 #ifndef NDEBUG
748 for (Register VReg : Res)
749 assert((VReg || ForDebug) && "Some registers are uninitialized");
750 #endif
751 return Res;
752 }
753
754 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const755 LLVM_DUMP_METHOD void RegisterBankInfo::OperandsMapper::dump() const {
756 print(dbgs(), true);
757 dbgs() << '\n';
758 }
759 #endif
760
print(raw_ostream & OS,bool ForDebug) const761 void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS,
762 bool ForDebug) const {
763 unsigned NumOpds = getInstrMapping().getNumOperands();
764 if (ForDebug) {
765 OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
766 // Print out the internal state of the index table.
767 OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
768 bool IsFirst = true;
769 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
770 if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
771 if (!IsFirst)
772 OS << ", ";
773 OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
774 IsFirst = false;
775 }
776 }
777 OS << '\n';
778 } else
779 OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
780
781 OS << "Operand Mapping: ";
782 // If we have a function, we can pretty print the name of the registers.
783 // Otherwise we will print the raw numbers.
784 const TargetRegisterInfo *TRI =
785 getMI().getParent() && getMI().getMF()
786 ? getMI().getMF()->getSubtarget().getRegisterInfo()
787 : nullptr;
788 bool IsFirst = true;
789 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
790 if (OpToNewVRegIdx[Idx] == DontKnowIdx)
791 continue;
792 if (!IsFirst)
793 OS << ", ";
794 IsFirst = false;
795 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
796 bool IsFirstNewVReg = true;
797 for (Register VReg : getVRegs(Idx)) {
798 if (!IsFirstNewVReg)
799 OS << ", ";
800 IsFirstNewVReg = false;
801 OS << printReg(VReg, TRI);
802 }
803 OS << "])";
804 }
805 }
806