1 /*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_ah.h"
18
19 #include "ah.h"
20 #include "ah_internal.h"
21 #include "ah_devid.h"
22 #ifdef AH_DEBUG
23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */
24 #endif
25
26 #include "ar9300/ar9300.h"
27 #include "ar9300/ar9300reg.h"
28 #include "ar9300/ar9300phy.h"
29
30
31 void
ar9300_get_hw_hangs(struct ath_hal * ah,hal_hw_hangs_t * hangs)32 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
33 {
34 struct ath_hal_9300 *ahp = AH9300(ah);
35 *hangs = 0;
36
37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) {
38 *hangs |= HAL_RIFS_BB_HANG_WAR;
39 }
40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) {
41 *hangs |= HAL_DFS_BB_HANG_WAR;
42 }
43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL)
44 == HAL_OK)
45 {
46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR;
47 }
48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) {
49 *hangs |= HAL_MAC_HANG_WAR;
50 }
51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58 }
59
60 /*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
64 static u_int
ar9300_mac_to_usec(struct ath_hal * ah,u_int clks)65 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66 {
67 #if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75 #endif
76 return (ath_hal_mac_usec(ah, clks));
77 }
78
79 u_int
ar9300_mac_to_clks(struct ath_hal * ah,u_int usecs)80 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81 {
82 #if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90 #endif
91 return (ath_hal_mac_clks(ah, usecs));
92 }
93
94 void
ar9300_get_mac_address(struct ath_hal * ah,u_int8_t * mac)95 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96 {
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
100 }
101
102 HAL_BOOL
ar9300_set_mac_address(struct ath_hal * ah,const u_int8_t * mac)103 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac)
104 {
105 struct ath_hal_9300 *ahp = AH9300(ah);
106
107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
108 return AH_TRUE;
109 }
110
111 void
ar9300_get_bss_id_mask(struct ath_hal * ah,u_int8_t * mask)112 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask)
113 {
114 struct ath_hal_9300 *ahp = AH9300(ah);
115
116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN);
117 }
118
119 HAL_BOOL
ar9300_set_bss_id_mask(struct ath_hal * ah,const u_int8_t * mask)120 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask)
121 {
122 struct ath_hal_9300 *ahp = AH9300(ah);
123
124 /* save it since it must be rewritten on reset */
125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN);
126
127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
129 return AH_TRUE;
130 }
131
132 /*
133 * Attempt to change the cards operating regulatory domain to the given value
134 * Returns: A_EINVAL for an unsupported regulatory domain.
135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137 HAL_BOOL
ar9300_set_regulatory_domain(struct ath_hal * ah,u_int16_t reg_domain,HAL_STATUS * status)138 ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140 {
141 HAL_STATUS ecode;
142
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
149 #if 0
150 bad:
151 #endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156 }
157
158 /*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165 u_int
ar9300_get_wireless_modes(struct ath_hal * ah)166 ar9300_get_wireless_modes(struct ath_hal *ah)
167 {
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169 }
170
171 /*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176 void
ar9300_enable_rf_kill(struct ath_hal * ah)177 ar9300_enable_rf_kill(struct ath_hal *ah)
178 {
179 /* TODO - can this really be above the hal on the GPIO interface for
180 * TODO - the client only?
181 */
182 struct ath_hal_9300 *ahp = AH9300(ah);
183
184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
185 /* Check RF kill GPIO before set/clear RFSILENT bits. */
186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) {
187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
188 AR_RFSILENT_FORCE);
189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
190 }
191 else {
192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
193 AR_RFSILENT_FORCE);
194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
195 }
196 }
197 else {
198 /* Connect rfsilent_bb_l to baseband */
199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
201
202 /* Set input mux for rfsilent_bb_l to GPIO #0 */
203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for
221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
222 * connection is present.
223 */
224 /*
225 * RFKill uses polling not interrupt,
226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue
227 */
228 if (ath_hal_hasrfkill_int(ah)) {
229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) {
230 /* switch already closed, set to interrupt upon open */
231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit);
232 } else {
233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit);
234 }
235 }
236 }
237
238 /*
239 * Change the LED blinking pattern to correspond to the connectivity
240 */
241 void
ar9300_set_led_state(struct ath_hal * ah,HAL_LED_STATE state)242 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state)
243 {
244 static const u_int32_t ledbits[8] = {
245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */
246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */
247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */
248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */
249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */
250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */
251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
252 AR_CFG_LED_ASSOC_NONE,
253 };
254
255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]);
256 }
257
258 /*
259 * Sets the Power LED on the cardbus without affecting the Network LED.
260 */
261 void
ar9300_set_power_led_state(struct ath_hal * ah,u_int8_t enabled)262 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled)
263 {
264 u_int32_t val;
265
266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
268 }
269
270 /*
271 * Sets the Network LED on the cardbus without affecting the Power LED.
272 */
273 void
ar9300_set_network_led_state(struct ath_hal * ah,u_int8_t enabled)274 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled)
275 {
276 u_int32_t val;
277
278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
280 }
281
282 /*
283 * Change association related fields programmed into the hardware.
284 * Writing a valid BSSID to the hardware effectively enables the hardware
285 * to synchronize its TSF to the correct beacons and receive frames coming
286 * from that BSSID. It is called by the SME JOIN operation.
287 */
288 void
ar9300_write_associd(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)289 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
290 u_int16_t assoc_id)
291 {
292 struct ath_hal_9300 *ahp = AH9300(ah);
293
294 /* save bssid and assoc_id for restore on reset */
295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
296 ahp->ah_assoc_id = assoc_id;
297
298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
301 }
302
303 /*
304 * Get the current hardware tsf for stamlme
305 */
306 u_int64_t
ar9300_get_tsf64(struct ath_hal * ah)307 ar9300_get_tsf64(struct ath_hal *ah)
308 {
309 u_int64_t tsf;
310
311 /* XXX sync multi-word read? */
312 tsf = OS_REG_READ(ah, AR_TSF_U32);
313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
314 return tsf;
315 }
316
317 void
ar9300_set_tsf64(struct ath_hal * ah,u_int64_t tsf)318 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf)
319 {
320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff));
321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff));
322 }
323
324 /*
325 * Get the current hardware tsf for stamlme
326 */
327 u_int32_t
ar9300_get_tsf32(struct ath_hal * ah)328 ar9300_get_tsf32(struct ath_hal *ah)
329 {
330 return OS_REG_READ(ah, AR_TSF_L32);
331 }
332
333 u_int32_t
ar9300_get_tsf2_32(struct ath_hal * ah)334 ar9300_get_tsf2_32(struct ath_hal *ah)
335 {
336 return OS_REG_READ(ah, AR_TSF2_L32);
337 }
338
339 /*
340 * Reset the current hardware tsf for stamlme.
341 */
342 void
ar9300_reset_tsf(struct ath_hal * ah)343 ar9300_reset_tsf(struct ath_hal *ah)
344 {
345 int count;
346
347 count = 0;
348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
349 count++;
350 if (count > 10) {
351 HALDEBUG(ah, HAL_DEBUG_RESET,
352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__);
353 break;
354 }
355 OS_DELAY(10);
356 }
357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
358 }
359
360 /*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365 void
ar9300_set_basic_rate(struct ath_hal * ah,HAL_RATE_SET * rs)366 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367 {
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;
382 }
383 }
384 /*
385 * Set the h/w bit to reflect whether or not the basic
386 * rate is found to be equal or less than 2Mbps.
387 */
388 reg = OS_REG_READ(ah, AR_STA_ID1);
389 if (xset && xset / 2 <= 2) {
390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
391 } else {
392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
393 }
394 }
395
396 /*
397 * Grab a semi-random value from hardware registers - may not
398 * change often
399 */
400 u_int32_t
ar9300_get_random_seed(struct ath_hal * ah)401 ar9300_get_random_seed(struct ath_hal *ah)
402 {
403 u_int32_t nf;
404
405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
406 if (nf & 0x100) {
407 nf = 0 - ((nf ^ 0x1ff) + 1);
408 }
409 return (OS_REG_READ(ah, AR_TSF_U32) ^
410 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
411 }
412
413 /*
414 * Detect if our card is present
415 */
416 HAL_BOOL
ar9300_detect_card_present(struct ath_hal * ah)417 ar9300_detect_card_present(struct ath_hal *ah)
418 {
419 u_int16_t mac_version, mac_rev;
420 u_int32_t v;
421
422 /*
423 * Read the Silicon Revision register and compare that
424 * to what we read at attach time. If the same, we say
425 * a card/device is present.
426 */
427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID;
428 if (v == 0xFF) {
429 /* new SREV format */
430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
431 /*
432 * Include 6-bit Chip Type (masked to 0) to differentiate
433 * from pre-Sowl versions
434 */
435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
436 mac_rev = MS(v, AR_SREV_REVISION2);
437 } else {
438 mac_version = MS(v, AR_SREV_VERSION);
439 mac_rev = v & AR_SREV_REVISION;
440 }
441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version &&
442 AH_PRIVATE(ah)->ah_macRev == mac_rev);
443 }
444
445 /*
446 * Update MIB Counters
447 */
448 void
ar9300_update_mib_mac_stats(struct ath_hal * ah)449 ar9300_update_mib_mac_stats(struct ath_hal *ah)
450 {
451 struct ath_hal_9300 *ahp = AH9300(ah);
452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats;
453
454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
459 }
460
461 void
ar9300_get_mib_mac_stats(struct ath_hal * ah,HAL_MIB_STATS * stats)462 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats)
463 {
464 struct ath_hal_9300 *ahp = AH9300(ah);
465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats;
466
467 stats->ackrcv_bad = istats->ackrcv_bad;
468 stats->rts_bad = istats->rts_bad;
469 stats->fcs_bad = istats->fcs_bad;
470 stats->rts_good = istats->rts_good;
471 stats->beacons = istats->beacons;
472 }
473
474 /*
475 * Detect if the HW supports spreading a CCK signal on channel 14
476 */
477 HAL_BOOL
ar9300_is_japan_channel_spread_supported(struct ath_hal * ah)478 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah)
479 {
480 return AH_TRUE;
481 }
482
483 /*
484 * Get the rssi of frame curently being received.
485 */
486 u_int32_t
ar9300_get_cur_rssi(struct ath_hal * ah)487 ar9300_get_cur_rssi(struct ath_hal *ah)
488 {
489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */
490 /* get combined RSSI */
491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff);
492 }
493
494 #if ATH_GEN_RANDOMNESS
495 /*
496 * Get the rssi value from BB on ctl chain0.
497 */
498 u_int32_t
ar9300_get_rssi_chain0(struct ath_hal * ah)499 ar9300_get_rssi_chain0(struct ath_hal *ah)
500 {
501 /* get ctl chain0 RSSI */
502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff;
503 }
504 #endif
505
506 u_int
ar9300_get_def_antenna(struct ath_hal * ah)507 ar9300_get_def_antenna(struct ath_hal *ah)
508 {
509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
510 }
511
512 /* Setup coverage class */
513 void
ar9300_set_coverage_class(struct ath_hal * ah,u_int8_t coverageclass,int now)514 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now)
515 {
516 }
517
518 void
ar9300_set_def_antenna(struct ath_hal * ah,u_int antenna)519 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520 {
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522 }
523
524 HAL_BOOL
ar9300_set_antenna_switch(struct ath_hal * ah,HAL_ANT_SETTING settings,const struct ieee80211_channel * chan,u_int8_t * tx_chainmask,u_int8_t * rx_chainmask,u_int8_t * antenna_cfgd)525 ar9300_set_antenna_switch(struct ath_hal *ah,
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528 {
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system
536 * to dramatically reduce the TX power on a particular chain.
537 *
538 * Based on the value of (redefined) diversity_control, the
539 * reset code will decrease power on chain 0 or chain 1/2.
540 *
541 * Based on the value of bit 0 of antenna_switch_swap,
542 * the mapping between OID call and chain is defined as:
543 * 0: map A -> 0, B -> 1;
544 * 1: map A -> 1, B -> 0;
545 *
546 * NOTE:
547 * The devices that use this OID should use a tx_chain_mask and
548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is
549 * used in order to ensure an active transmit antenna. This
550 * API will allow the host to turn off the only transmitting
551 * antenna to ensure the antenna closest to the user's body is
552 * powered-down.
553 */
554 /*
555 * Set antenna control for use during reset sequence by
556 * ar9300_decrease_chain_power()
557 */
558 ahp->ah_diversity_control = settings;
559
560 return AH_TRUE;
561 }
562
563 HAL_BOOL
ar9300_is_sleep_after_beacon_broken(struct ath_hal * ah)564 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah)
565 {
566 return AH_TRUE;
567 }
568
569 HAL_BOOL
ar9300_set_slot_time(struct ath_hal * ah,u_int us)570 ar9300_set_slot_time(struct ath_hal *ah, u_int us)
571 {
572 struct ath_hal_9300 *ahp = AH9300(ah);
573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) {
574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us);
575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */
576 return AH_FALSE;
577 } else {
578 /* convert to system clocks */
579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us));
580 ahp->ah_slot_time = us;
581 return AH_TRUE;
582 }
583 }
584
585 HAL_BOOL
ar9300_set_ack_timeout(struct ath_hal * ah,u_int us)586 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us)
587 {
588 struct ath_hal_9300 *ahp = AH9300(ah);
589
590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us);
592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */
593 return AH_FALSE;
594 } else {
595 /* convert to system clocks */
596 OS_REG_RMW_FIELD(ah,
597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us));
598 ahp->ah_ack_timeout = us;
599 return AH_TRUE;
600 }
601 }
602
603 u_int
ar9300_get_ack_timeout(struct ath_hal * ah)604 ar9300_get_ack_timeout(struct ath_hal *ah)
605 {
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608 }
609
610 HAL_STATUS
ar9300_set_quiet(struct ath_hal * ah,u_int32_t period,u_int32_t duration,u_int32_t next_start,HAL_QUIET_FLAG flag)611 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613 {
614 #define TU_TO_USEC(_tu) ((_tu) << 10)
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
626 ah->ah_config.ah_sw_beacon_response_time;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;
635 break;
636 }
637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved "
638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf);
639 /* TSF shouldn't count twice or reg access is taking forever */
640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648 #undef TU_TO_USEC
649 }
650 #ifdef ATH_SUPPORT_DFS
651 void
ar9300_cac_tx_quiet(struct ath_hal * ah,HAL_BOOL enable)652 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653 {
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1));
658 AH9300(ah)->ah_cac_quiet_enabled = enable;
659
660 if (enable) {
661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
662 reg1 | AR_PCU_FORCE_QUIET_COLL);
663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE);
665 } else {
666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
667 reg1 & ~AR_PCU_FORCE_QUIET_COLL);
668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE);
670 }
671 }
672 #endif /* ATH_SUPPORT_DFS */
673
674 void
ar9300_set_pcu_config(struct ath_hal * ah)675 ar9300_set_pcu_config(struct ath_hal *ah)
676 {
677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode);
678 }
679
680 HAL_STATUS
ar9300_get_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t * result)681 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
682 u_int32_t capability, u_int32_t *result)
683 {
684 struct ath_hal_9300 *ahp = AH9300(ah);
685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
686 struct ar9300_ani_state *ani;
687
688 switch (type) {
689 case HAL_CAP_CIPHER: /* cipher handled in hardware */
690 switch (capability) {
691 case HAL_CIPHER_AES_CCM:
692 case HAL_CIPHER_AES_OCB:
693 case HAL_CIPHER_TKIP:
694 case HAL_CIPHER_WEP:
695 case HAL_CIPHER_MIC:
696 case HAL_CIPHER_CLR:
697 return HAL_OK;
698 default:
699 return HAL_ENOTSUPP;
700 }
701 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
702 switch (capability) {
703 case 0: /* hardware capability */
704 return HAL_OK;
705 case 1:
706 return (ahp->ah_sta_id1_defaults &
707 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
708 default:
709 return HAL_ENOTSUPP;
710 }
711 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
712 switch (capability) {
713 case 0: /* hardware capability */
714 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
715 case 1: /* current setting */
716 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
717 HAL_ENXIO : HAL_OK;
718 default:
719 return HAL_ENOTSUPP;
720 }
721 case HAL_CAP_WME_TKIPMIC:
722 /* hardware can do TKIP MIC when WMM is turned on */
723 return HAL_OK;
724 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
725 return HAL_OK;
726 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
727 switch (capability) {
728 case 0: /* hardware capability */
729 return HAL_OK;
730 case 1: /* current setting */
731 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) &
732 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
733 HAL_OK : HAL_ENXIO;
734 }
735 return HAL_EINVAL;
736 case HAL_CAP_TPC:
737 switch (capability) {
738 case 0: /* hardware capability */
739 return HAL_OK;
740 case 1:
741 return ah->ah_config.ath_hal_desc_tpc ?
742 HAL_OK : HAL_ENXIO;
743 }
744 return HAL_OK;
745 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
746 return HAL_OK;
747 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
748 switch (capability) {
749 case 0: /* hardware capability */
750 return HAL_OK;
751 case 1:
752 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
753 /*
754 * Owl and Merlin have problems in mcast key search.
755 * Disable this cap. in Ad-hoc mode. see Bug 25776 and
756 * 26802
757 */
758 return HAL_ENXIO;
759 } else {
760 return (ahp->ah_sta_id1_defaults &
761 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
762 }
763 }
764 return HAL_EINVAL;
765 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
766 switch (capability) {
767 case 0: /* hardware capability */
768 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
769 case 1:
770 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
771 HAL_OK : HAL_ENXIO;
772 }
773 return HAL_EINVAL;
774 case HAL_CAP_RFSILENT: /* rfsilent support */
775 if (capability == 3) { /* rfkill interrupt */
776 /*
777 * XXX: Interrupt-based notification of RF Kill state
778 * changes not working yet. Report that this feature
779 * is not supported so that polling is used instead.
780 */
781 return (HAL_ENOTSUPP);
782 }
783 return ath_hal_getcapability(ah, type, capability, result);
784 case HAL_CAP_4ADDR_AGGR:
785 return HAL_OK;
786 case HAL_CAP_BB_RIFS_HANG:
787 return HAL_ENOTSUPP;
788 case HAL_CAP_BB_DFS_HANG:
789 return HAL_ENOTSUPP;
790 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG:
791 /* Track chips that are known to have BB hangs related
792 * to rx_clear stuck low.
793 */
794 return HAL_ENOTSUPP;
795 case HAL_CAP_MAC_HANG:
796 /* Track chips that are known to have MAC hangs.
797 */
798 return HAL_OK;
799 case HAL_CAP_RIFS_RX_ENABLED:
800 /* Is RIFS RX currently enabled */
801 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
802 #if 0
803 case HAL_CAP_ANT_CFG_2GHZ:
804 *result = p_cap->halNumAntCfg2Ghz;
805 return HAL_OK;
806 case HAL_CAP_ANT_CFG_5GHZ:
807 *result = p_cap->halNumAntCfg5Ghz;
808 return HAL_OK;
809 case HAL_CAP_RX_STBC:
810 *result = p_cap->hal_rx_stbc_support;
811 return HAL_OK;
812 case HAL_CAP_TX_STBC:
813 *result = p_cap->hal_tx_stbc_support;
814 return HAL_OK;
815 #endif
816 case HAL_CAP_LDPC:
817 *result = p_cap->halLDPCSupport;
818 return HAL_OK;
819 case HAL_CAP_DYNAMIC_SMPS:
820 return HAL_OK;
821 case HAL_CAP_DS:
822 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
823 (p_cap->halTxChainMask & 0x3) != 0x3 ||
824 (p_cap->halRxChainMask & 0x3) != 0x3) ?
825 HAL_ENOTSUPP : HAL_OK;
826 case HAL_CAP_TS:
827 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
828 (p_cap->halTxChainMask & 0x7) != 0x7 ||
829 (p_cap->halRxChainMask & 0x7) != 0x7) ?
830 HAL_ENOTSUPP : HAL_OK;
831 case HAL_CAP_OL_PWRCTRL:
832 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
833 HAL_OK : HAL_ENOTSUPP;
834 case HAL_CAP_CRDC:
835 #if ATH_SUPPORT_CRDC
836 return (AR_SREV_WASP(ah) &&
837 ah->ah_config.ath_hal_crdc_enable) ?
838 HAL_OK : HAL_ENOTSUPP;
839 #else
840 return HAL_ENOTSUPP;
841 #endif
842 #if 0
843 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
844 *result = (u_int32_t)(-1);
845 return HAL_OK;
846 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
847 *result = (u_int32_t)(-1);
848 return HAL_OK;
849 #endif
850 case HAL_CAP_BB_PANIC_WATCHDOG:
851 return HAL_OK;
852 case HAL_CAP_PHYRESTART_CLR_WAR:
853 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
854 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
855 {
856 return HAL_OK;
857 }
858 else
859 {
860 return HAL_ENOTSUPP;
861 }
862 case HAL_CAP_ENTERPRISE_MODE:
863 *result = ahp->ah_enterprise_mode >> 16;
864 /*
865 * WAR for EV 77658 - Add delimiters to first sub-frame when using
866 * RTS/CTS with aggregation and non-enterprise Osprey.
867 *
868 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
869 */
870 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
871 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
872 AR_SREV_WASP_10(ah))) {
873 *result |= AH_ENT_RTSCTS_DELIM_WAR;
874 }
875 return HAL_OK;
876 case HAL_CAP_LDPCWAR:
877 /* WAR for RIFS+LDPC issue is required for all chips currently
878 * supported by ar9300 HAL.
879 */
880 return HAL_OK;
881 case HAL_CAP_ENABLE_APM:
882 *result = p_cap->halApmEnable;
883 return HAL_OK;
884 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
885 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
886 case HAL_CAP_PCIE_LCR_OFFSET:
887 *result = p_cap->hal_pcie_lcr_offset;
888 return HAL_OK;
889 case HAL_CAP_SMARTANTENNA:
890 /* FIXME A request is pending with h/w team to add feature bit in
891 * caldata to detect if board has smart antenna or not, once added
892 * we need to fix his piece of code to read and return value without
893 * any compile flags
894 */
895 #if UMAC_SUPPORT_SMARTANTENNA
896 /* enable smart antenna for Peacock, Wasp and scorpion
897 for future chips need to modify */
898 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) {
899 return HAL_OK;
900 } else {
901 return HAL_ENOTSUPP;
902 }
903 #else
904 return HAL_ENOTSUPP;
905 #endif
906
907 #ifdef ATH_TRAFFIC_FAST_RECOVER
908 case HAL_CAP_TRAFFIC_FAST_RECOVER:
909 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) {
910 return HAL_OK;
911 } else {
912 return HAL_ENOTSUPP;
913 }
914 #endif
915
916 /* FreeBSD ANI */
917 case HAL_CAP_INTMIT: /* interference mitigation */
918 switch (capability) {
919 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */
920 return HAL_OK;
921 case HAL_CAP_INTMIT_ENABLE:
922 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ?
923 HAL_OK : HAL_ENXIO;
924 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL:
925 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL:
926 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR:
927 case HAL_CAP_INTMIT_FIRSTEP_LEVEL:
928 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL:
929 ani = ar9300_ani_get_current_state(ah);
930 if (ani == AH_NULL)
931 return HAL_ENXIO;
932 switch (capability) {
933 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */
934 case 2: *result = ani->ofdm_noise_immunity_level; break;
935 case 3: *result = !ani->ofdm_weak_sig_detect_off; break;
936 // case 4: *result = ani->cck_weak_sig_threshold; break;
937 case 5: *result = ani->firstep_level; break;
938 case 6: *result = ani->spur_immunity_level; break;
939 }
940 return HAL_OK;
941 }
942 return HAL_EINVAL;
943 case HAL_CAP_ENFORCE_TXOP:
944 if (capability == 0)
945 return (HAL_OK);
946 if (capability != 1)
947 return (HAL_ENOTSUPP);
948 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA);
949 return (HAL_OK);
950 default:
951 return ath_hal_getcapability(ah, type, capability, result);
952 }
953 }
954
955 HAL_BOOL
ar9300_set_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t setting,HAL_STATUS * status)956 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
957 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
958 {
959 struct ath_hal_9300 *ahp = AH9300(ah);
960 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
961 u_int32_t v;
962
963 switch (type) {
964 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
965 if (! p_cap->halTkipMicTxRxKeySupport)
966 return AH_FALSE;
967
968 if (setting)
969 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
970 else
971 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
972
973 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
974 return AH_TRUE;
975
976 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
977 if (setting) {
978 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
979 } else {
980 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
981 }
982 return AH_TRUE;
983 case HAL_CAP_DIVERSITY:
984 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
985 if (setting) {
986 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
987 } else {
988 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
989 }
990 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
991 return AH_TRUE;
992 case HAL_CAP_DIAG: /* hardware diagnostic support */
993 /*
994 * NB: could split this up into virtual capabilities,
995 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
996 * seems worth the additional complexity.
997 */
998 #ifdef AH_DEBUG
999 AH_PRIVATE(ah)->ah_diagreg = setting;
1000 #else
1001 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
1002 #endif
1003 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
1004 return AH_TRUE;
1005 case HAL_CAP_TPC:
1006 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
1007 return AH_TRUE;
1008 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
1009 if (setting) {
1010 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
1011 } else {
1012 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1013 }
1014 return AH_TRUE;
1015 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
1016 if (p_cap->halTsfAddSupport) {
1017 if (setting) {
1018 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
1019 } else {
1020 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
1021 }
1022 return AH_TRUE;
1023 }
1024 return AH_FALSE;
1025
1026 /* FreeBSD interrupt mitigation / ANI */
1027 case HAL_CAP_INTMIT: { /* interference mitigation */
1028 /* This maps the public ANI commands to the internal ANI commands */
1029 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */
1030 static const HAL_ANI_CMD cmds[] = {
1031 HAL_ANI_PRESENT,
1032 HAL_ANI_MODE,
1033 HAL_ANI_NOISE_IMMUNITY_LEVEL,
1034 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
1035 HAL_ANI_CCK_WEAK_SIGNAL_THR,
1036 HAL_ANI_FIRSTEP_LEVEL,
1037 HAL_ANI_SPUR_IMMUNITY_LEVEL,
1038 };
1039 return capability < nitems(cmds) ?
1040 ar9300_ani_control(ah, cmds[capability], setting) :
1041 AH_FALSE;
1042 }
1043
1044 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */
1045 ahp->rx_buf_size = setting & AR_DATABUF_MASK;
1046 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
1047 return AH_TRUE;
1048
1049 case HAL_CAP_ENFORCE_TXOP:
1050 if (capability != 1)
1051 return AH_FALSE;
1052 if (setting) {
1053 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA;
1054 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1055 } else {
1056 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA;
1057 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1058 }
1059 return AH_TRUE;
1060
1061 /* fall thru... */
1062 default:
1063 return ath_hal_setcapability(ah, type, capability, setting, status);
1064 }
1065 }
1066
1067 #ifdef AH_DEBUG
1068 static void
ar9300_print_reg(struct ath_hal * ah,u_int32_t args)1069 ar9300_print_reg(struct ath_hal *ah, u_int32_t args)
1070 {
1071 u_int32_t i = 0;
1072
1073 /* Read 0x80d0 to trigger pcie analyzer */
1074 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1075 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0));
1076
1077 if (args & HAL_DIAG_PRINT_REG_COUNTER) {
1078 struct ath_hal_9300 *ahp = AH9300(ah);
1079 u_int32_t tf, rf, rc, cc;
1080
1081 tf = OS_REG_READ(ah, AR_TFCNT);
1082 rf = OS_REG_READ(ah, AR_RFCNT);
1083 rc = OS_REG_READ(ah, AR_RCCNT);
1084 cc = OS_REG_READ(ah, AR_CCCNT);
1085
1086 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1087 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf);
1088 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1089 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf);
1090 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1091 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc);
1092 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1093 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc);
1094
1095 ahp->last_tf = tf;
1096 ahp->last_rf = rf;
1097 ahp->last_rc = rc;
1098 ahp->last_cc = cc;
1099
1100 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1101 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0));
1102 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1103 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1));
1104 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1105 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2));
1106 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1107 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3));
1108 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1109 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4));
1110 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1111 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5));
1112 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1113 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6));
1114 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1115 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7));
1116 }
1117
1118 if (args & HAL_DIAG_PRINT_REG_ALL) {
1119 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) {
1120 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1121 i, OS_REG_READ(ah, i));
1122 }
1123
1124 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) {
1125 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1126 i, OS_REG_READ(ah, i));
1127 }
1128
1129 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1130 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i));
1131
1132 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1133 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i));
1134
1135 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) {
1136 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1137 i, OS_REG_READ(ah, i));
1138 }
1139
1140 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) {
1141 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1142 i, OS_REG_READ(ah, i));
1143 }
1144
1145 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) {
1146 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1147 i, OS_REG_READ(ah, i));
1148 }
1149
1150 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) {
1151 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1152 i, OS_REG_READ(ah, i));
1153 }
1154
1155 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) {
1156 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1157 i, OS_REG_READ(ah, i));
1158 }
1159
1160 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) {
1161 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1162 i, OS_REG_READ(ah, i));
1163 }
1164
1165 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) {
1166 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1167 i, OS_REG_READ(ah, i));
1168 }
1169
1170 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) {
1171 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1172 i, OS_REG_READ(ah, i));
1173 }
1174
1175 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) {
1176 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1177 i, OS_REG_READ(ah, i));
1178 }
1179
1180 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) {
1181 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1182 i, OS_REG_READ(ah, i));
1183 }
1184
1185 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) {
1186 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1187 i, OS_REG_READ(ah, i));
1188 }
1189 }
1190 }
1191 #endif
1192
1193 HAL_BOOL
ar9300_get_diag_state(struct ath_hal * ah,int request,const void * args,u_int32_t argsize,void ** result,u_int32_t * resultsize)1194 ar9300_get_diag_state(struct ath_hal *ah, int request,
1195 const void *args, u_int32_t argsize,
1196 void **result, u_int32_t *resultsize)
1197 {
1198 struct ath_hal_9300 *ahp = AH9300(ah);
1199 struct ar9300_ani_state *ani;
1200
1201 (void) ahp;
1202 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) {
1203 return AH_TRUE;
1204 }
1205 switch (request) {
1206 #ifdef AH_PRIVATE_DIAG
1207 case HAL_DIAG_EEPROM:
1208 *result = &ahp->ah_eeprom;
1209 *resultsize = sizeof(ar9300_eeprom_t);
1210 return AH_TRUE;
1211
1212 #if 0 /* XXX - TODO */
1213 case HAL_DIAG_EEPROM_EXP_11A:
1214 case HAL_DIAG_EEPROM_EXP_11B:
1215 case HAL_DIAG_EEPROM_EXP_11G:
1216 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A];
1217 *result = pe->p_channels;
1218 *resultsize = (*result == AH_NULL) ? 0 :
1219 roundup(sizeof(u_int16_t) * pe->num_channels,
1220 sizeof(u_int32_t)) +
1221 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels;
1222 return AH_TRUE;
1223 #endif
1224 case HAL_DIAG_RFGAIN:
1225 *result = &ahp->ah_gain_values;
1226 *resultsize = sizeof(GAIN_VALUES);
1227 return AH_TRUE;
1228 case HAL_DIAG_RFGAIN_CURSTEP:
1229 *result = (void *) ahp->ah_gain_values.curr_step;
1230 *resultsize = (*result == AH_NULL) ?
1231 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1232 return AH_TRUE;
1233 #if 0 /* XXX - TODO */
1234 case HAL_DIAG_PCDAC:
1235 *result = ahp->ah_pcdac_table;
1236 *resultsize = ahp->ah_pcdac_table_size;
1237 return AH_TRUE;
1238 #endif
1239 case HAL_DIAG_ANI_CURRENT:
1240
1241 ani = ar9300_ani_get_current_state(ah);
1242 if (ani == AH_NULL)
1243 return AH_FALSE;
1244 /* Convert ar9300 HAL to FreeBSD HAL ANI state */
1245 /* XXX TODO: add all of these to the HAL ANI state structure */
1246 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state));
1247 /* XXX should this be OFDM or CCK noise immunity level? */
1248 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level;
1249 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level;
1250 ahp->ext_ani_state.firstepLevel = ani->firstep_level;
1251 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off;
1252 /* mrc_cck_off */
1253 /* cck_noise_immunity_level */
1254
1255 ahp->ext_ani_state.listenTime = ani->listen_time;
1256
1257 *result = &ahp->ext_ani_state;
1258 *resultsize = sizeof(ahp->ext_ani_state);
1259 #if 0
1260 *result = ar9300_ani_get_current_state(ah);
1261 *resultsize = (*result == AH_NULL) ?
1262 0 : sizeof(struct ar9300_ani_state);
1263 #endif
1264 return AH_TRUE;
1265 case HAL_DIAG_ANI_STATS:
1266 *result = ar9300_ani_get_current_stats(ah);
1267 *resultsize = (*result == AH_NULL) ?
1268 0 : sizeof(HAL_ANI_STATS);
1269 return AH_TRUE;
1270 case HAL_DIAG_ANI_CMD:
1271 if (argsize != 2*sizeof(u_int32_t)) {
1272 return AH_FALSE;
1273 }
1274 ar9300_ani_control(
1275 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1276 return AH_TRUE;
1277 #if 0
1278 case HAL_DIAG_TXCONT:
1279 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1280 return AH_TRUE;
1281 #endif /* 0 */
1282 #endif /* AH_PRIVATE_DIAG */
1283 case HAL_DIAG_CHANNELS:
1284 #if 0
1285 *result = &(ahp->ah_priv.ah_channels[0]);
1286 *resultsize =
1287 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1288 #endif
1289 return AH_TRUE;
1290 #ifdef AH_DEBUG
1291 case HAL_DIAG_PRINT_REG:
1292 ar9300_print_reg(ah, *((const u_int32_t *)args));
1293 return AH_TRUE;
1294 #endif
1295 default:
1296 break;
1297 }
1298
1299 return AH_FALSE;
1300 }
1301
1302 void
ar9300_dma_reg_dump(struct ath_hal * ah)1303 ar9300_dma_reg_dump(struct ath_hal *ah)
1304 {
1305 #ifdef AH_DEBUG
1306 #define NUM_DMA_DEBUG_REGS 8
1307 #define NUM_QUEUES 10
1308
1309 u_int32_t val[NUM_DMA_DEBUG_REGS];
1310 int qcu_offset = 0, dcu_offset = 0;
1311 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1312 int i, j, k;
1313 int16_t nfarray[HAL_NUM_NF_READINGS];
1314 #ifdef ATH_NF_PER_CHAN
1315 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1316 #endif /* ATH_NF_PER_CHAN */
1317 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1318
1319 /* selecting DMA OBS 8 */
1320 OS_REG_WRITE(ah, AR_MACMISC,
1321 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1322 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1323
1324 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1325 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
1326 if (i % 4 == 0) {
1327 ath_hal_printf(ah, "\n");
1328 }
1329
1330 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1331 ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1332 }
1333
1334 ath_hal_printf(ah, "\n\n");
1335 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1336
1337 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) {
1338 if (i == 8) {
1339 /* only 8 QCU entries in val[0] */
1340 qcu_offset = 0;
1341 qcu_base++;
1342 }
1343
1344 if (i == 6) {
1345 /* only 6 DCU entries in val[4] */
1346 dcu_offset = 0;
1347 dcu_base++;
1348 }
1349
1350 ath_hal_printf(ah,
1351 "%2d %2x %1x %2x %2x\n",
1352 i,
1353 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset,
1354 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3),
1355 val[2] & (0x7 << (i * 3)) >> (i * 3),
1356 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset);
1357 }
1358
1359 ath_hal_printf(ah, "\n");
1360 ath_hal_printf(ah,
1361 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1362 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1363 ath_hal_printf(ah,
1364 "qcu_complete state: %2x dcu_complete state: %2x\n",
1365 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1366 ath_hal_printf(ah,
1367 "dcu_arb state: %2x dcu_fp state: %2x\n",
1368 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1369 ath_hal_printf(ah,
1370 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1371 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1372 ath_hal_printf(ah,
1373 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1374 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1375 ath_hal_printf(ah,
1376 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1377 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1378 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1));
1379 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR));
1380
1381 ar9300_upload_noise_floor(ah, 1, nfarray);
1382 ath_hal_printf(ah, "2G:\n");
1383 ath_hal_printf(ah, "Min CCA Out:\n");
1384 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1385 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1386 nfarray[0], nfarray[1], nfarray[2]);
1387 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1388 nfarray[3], nfarray[4], nfarray[5]);
1389
1390 ar9300_upload_noise_floor(ah, 0, nfarray);
1391 ath_hal_printf(ah, "5G:\n");
1392 ath_hal_printf(ah, "Min CCA Out:\n");
1393 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1394 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1395 nfarray[0], nfarray[1], nfarray[2]);
1396 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1397 nfarray[3], nfarray[4], nfarray[5]);
1398
1399 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1400 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1401 ((i < 3) ? "Control " : "Extension "), i%3);
1402 for (j = 0, k = h->base.curr_index;
1403 j < HAL_NF_CAL_HIST_LEN_FULL;
1404 j++, k++) {
1405 ath_hal_printf(ah, "Element %d: %d\n",
1406 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1407 }
1408 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]);
1409 }
1410
1411 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1412 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n",
1413 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1414 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1415 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ);
1416 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n",
1417 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
1418 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
1419 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n",
1420 MS(reg, AR_PHY_DESIRED_SZ_ADC),
1421 MS(reg, AR_PHY_DESIRED_SZ_ADC));
1422 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG);
1423 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n",
1424 MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
1425 MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
1426 reg = OS_REG_READ(ah, AR_PHY_AGC);
1427 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n",
1428 MS(reg, AR_PHY_AGC_COARSE_HIGH),
1429 MS(reg, AR_PHY_AGC_COARSE_HIGH));
1430 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n",
1431 MS(reg, AR_PHY_AGC_COARSE_LOW),
1432 MS(reg, AR_PHY_AGC_COARSE_LOW));
1433 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n",
1434 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
1435 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
1436 reg = OS_REG_READ(ah, AR_PHY_TIMING5);
1437 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n",
1438 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
1439 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n",
1440 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
1441 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
1442 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
1443 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
1444 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
1445 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK);
1446 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n",
1447 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
1448 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n",
1449 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
1450 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
1451
1452
1453 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
1454 reg = OS_REG_READ(ah, 0xa360);
1455 reg &= ~0x00800000;
1456 OS_REG_WRITE(ah, 0xa360, reg);
1457
1458 /* Step 2a: Set register 0xa364 to 0x1000 */
1459 reg = 0x1000;
1460 OS_REG_WRITE(ah, 0xa364, reg);
1461
1462 /* Step 3a: Read bits 17:0 of register 0x9c20 */
1463 reg = OS_REG_READ(ah, 0x9c20);
1464 reg &= 0x0003ffff;
1465 ath_hal_printf(ah,
1466 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n",
1467 __func__, reg);
1468
1469 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
1470 reg = OS_REG_READ(ah, 0xa360);
1471 reg &= ~0x00800000;
1472 OS_REG_WRITE(ah, 0xa360, reg);
1473
1474 /* Step 2b: Set register 0xa364 to 0x1400 */
1475 reg = 0x1400;
1476 OS_REG_WRITE(ah, 0xa364, reg);
1477
1478 /* Step 3b: Read bits 17:0 of register 0x9c20 */
1479 reg = OS_REG_READ(ah, 0x9c20);
1480 reg &= 0x0003ffff;
1481 ath_hal_printf(ah,
1482 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n",
1483 __func__, reg);
1484
1485 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
1486 reg = OS_REG_READ(ah, 0xa360);
1487 reg &= ~0x00800000;
1488 OS_REG_WRITE(ah, 0xa360, reg);
1489
1490 /* Step 2c: Set register 0xa364 to 0x3C00 */
1491 reg = 0x3c00;
1492 OS_REG_WRITE(ah, 0xa364, reg);
1493
1494 /* Step 3c: Read bits 17:0 of register 0x9c20 */
1495 reg = OS_REG_READ(ah, 0x9c20);
1496 reg &= 0x0003ffff;
1497 ath_hal_printf(ah,
1498 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n",
1499 __func__, reg);
1500
1501 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
1502 reg = OS_REG_READ(ah, 0xa360);
1503 reg &= ~0x001040000;
1504 OS_REG_WRITE(ah, 0xa360, reg);
1505
1506 /* Step 2d: Set register 0xa364 to 0x5005D */
1507 reg = 0x5005D;
1508 OS_REG_WRITE(ah, 0xa364, reg);
1509
1510 /* Step 3d: Read bits 17:0 of register 0xa368 */
1511 reg = OS_REG_READ(ah, 0xa368);
1512 reg &= 0x0003ffff;
1513 ath_hal_printf(ah,
1514 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n",
1515 __func__, reg);
1516
1517 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
1518 reg = OS_REG_READ(ah, 0xa360);
1519 reg &= ~0x001040000;
1520 OS_REG_WRITE(ah, 0xa360, reg);
1521
1522 /* Step 2e: Set register 0xa364 to 0x7005D */
1523 reg = 0x7005D;
1524 OS_REG_WRITE(ah, 0xa364, reg);
1525
1526 /* Step 3e: Read bits 17:0 of register 0xa368 */
1527 reg = OS_REG_READ(ah, 0xa368);
1528 reg &= 0x0003ffff;
1529 ath_hal_printf(ah,
1530 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n",
1531 __func__, reg);
1532
1533 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
1534 reg = OS_REG_READ(ah, 0xa360);
1535 reg &= ~0x001000000;
1536 reg |= 0x40000;
1537 OS_REG_WRITE(ah, 0xa360, reg);
1538
1539 /* Step 2f: Set register 0xa364 to 0x3005D */
1540 reg = 0x3005D;
1541 OS_REG_WRITE(ah, 0xa364, reg);
1542
1543 /* Step 3f: Read bits 17:0 of register 0xa368 */
1544 reg = OS_REG_READ(ah, 0xa368);
1545 reg &= 0x0003ffff;
1546 ath_hal_printf(ah,
1547 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n",
1548 __func__, reg);
1549
1550 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
1551 reg = OS_REG_READ(ah, 0xa360);
1552 reg &= ~0x001000000;
1553 reg |= 0x40000;
1554 OS_REG_WRITE(ah, 0xa360, reg);
1555
1556 /* Step 2g: Set register 0xa364 to 0x6005D */
1557 reg = 0x6005D;
1558 OS_REG_WRITE(ah, 0xa364, reg);
1559
1560 /* Step 3g: Read bits 17:0 of register 0xa368 */
1561 reg = OS_REG_READ(ah, 0xa368);
1562 reg &= 0x0003ffff;
1563 ath_hal_printf(ah,
1564 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n",
1565 __func__, reg);
1566 #endif /* AH_DEBUG */
1567 }
1568
1569 /*
1570 * Return the busy for rx_frame, rx_clear, and tx_frame
1571 */
1572 u_int32_t
ar9300_get_mib_cycle_counts_pct(struct ath_hal * ah,u_int32_t * rxc_pcnt,u_int32_t * rxf_pcnt,u_int32_t * txf_pcnt)1573 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
1574 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt)
1575 {
1576 struct ath_hal_9300 *ahp = AH9300(ah);
1577 u_int32_t good = 1;
1578
1579 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT);
1580 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT);
1581 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT);
1582 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1583
1584 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) {
1585 /*
1586 * Cycle counter wrap (or initial call); it's not possible
1587 * to accurately calculate a value because the registers
1588 * right shift rather than wrap--so punt and return 0.
1589 */
1590 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1591 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1592 good = 0;
1593 } else {
1594 u_int32_t cc_d = cc - ahp->ah_cycles;
1595 u_int32_t rc_d = rc - ahp->ah_rx_clear;
1596 u_int32_t rf_d = rf - ahp->ah_rx_frame;
1597 u_int32_t tf_d = tf - ahp->ah_tx_frame;
1598
1599 if (cc_d != 0) {
1600 *rxc_pcnt = rc_d * 100 / cc_d;
1601 *rxf_pcnt = rf_d * 100 / cc_d;
1602 *txf_pcnt = tf_d * 100 / cc_d;
1603 } else {
1604 good = 0;
1605 }
1606 }
1607
1608 ahp->ah_cycles = cc;
1609 ahp->ah_rx_frame = rf;
1610 ahp->ah_rx_clear = rc;
1611 ahp->ah_tx_frame = tf;
1612
1613 return good;
1614 }
1615
1616 /*
1617 * Return approximation of extension channel busy over an time interval
1618 * 0% (clear) -> 100% (busy)
1619 * -1 for invalid estimate
1620 */
1621 uint32_t
ar9300_get_11n_ext_busy(struct ath_hal * ah)1622 ar9300_get_11n_ext_busy(struct ath_hal *ah)
1623 {
1624 /*
1625 * Overflow condition to check before multiplying to get %
1626 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1627 */
1628 #define OVERFLOW_LIMIT 0x28F5C28
1629 #define ERROR_CODE -1
1630
1631 struct ath_hal_9300 *ahp = AH9300(ah);
1632 u_int32_t busy = 0; /* percentage */
1633 int8_t busyper = 0;
1634 u_int32_t cycle_count, ctl_busy, ext_busy;
1635
1636 /* cycle_count will always be the first to wrap; therefore, read it last
1637 * This sequence of reads is not atomic, and MIB counter wrap
1638 * could happen during it ?
1639 */
1640 ctl_busy = OS_REG_READ(ah, AR_RCCNT);
1641 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT);
1642 cycle_count = OS_REG_READ(ah, AR_CCCNT);
1643
1644 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) ||
1645 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy))
1646 {
1647 /*
1648 * Cycle counter wrap (or initial call); it's not possible
1649 * to accurately calculate a value because the registers
1650 * right shift rather than wrap--so punt and return 0.
1651 */
1652 busyper = ERROR_CODE;
1653 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1654 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1655 } else {
1656 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count;
1657 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy;
1658
1659 /*
1660 * Compute extension channel busy percentage
1661 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100
1662 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0
1663 * Will never happen, since (ext_busy_delta < cycle_delta) always,
1664 * and shift necessitated by large ext_busy_delta.
1665 * Due to timing difference to read the registers and counter overflow,
1666 * it may still happen that cycle_delta >> 7 = 0.
1667 *
1668 */
1669 if (cycle_delta) {
1670 if (ext_busy_delta > OVERFLOW_LIMIT) {
1671 if (cycle_delta >> 7) {
1672 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7);
1673 } else {
1674 busyper = ERROR_CODE;
1675 }
1676 } else {
1677 busy = (ext_busy_delta * 100) / cycle_delta;
1678 }
1679 } else {
1680 busyper = ERROR_CODE;
1681 }
1682
1683 if (busy > 100) {
1684 busy = 100;
1685 }
1686 if ( busyper != ERROR_CODE ) {
1687 busyper = busy;
1688 }
1689 }
1690
1691 ahp->ah_cycle_count = cycle_count;
1692 ahp->ah_ctl_busy = ctl_busy;
1693 ahp->ah_ext_busy = ext_busy;
1694
1695 return busyper;
1696 #undef OVERFLOW_LIMIT
1697 #undef ERROR_CODE
1698 }
1699
1700 /* BB Panic Watchdog declarations */
1701 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1702 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1703
1704 void
ar9300_config_bb_panic_watchdog(struct ath_hal * ah)1705 ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1706 {
1707 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1708 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1709 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1710 u_int32_t val, idle_count;
1711
1712 if (idle_tmo_ms != 0) {
1713 /* enable IRQ, disable chip-reset for BB panic */
1714 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1715 AR_PHY_BB_PANIC_CNTL2_MASK;
1716 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1717 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1718 /* bound limit to 10 secs */
1719 if (idle_tmo_ms > 10000) {
1720 idle_tmo_ms = 10000;
1721 }
1722 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1723 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1724 } else {
1725 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1726 }
1727 /*
1728 * enable panic in non-IDLE mode,
1729 * disable in IDLE mode,
1730 * set idle time-out
1731 */
1732
1733 // EV92527 : Enable IDLE mode panic
1734
1735 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1736 AR_PHY_BB_PANIC_NON_IDLE_ENABLE |
1737 AR_PHY_BB_PANIC_IDLE_ENABLE |
1738 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) |
1739 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2)));
1740 } else {
1741 /* disable IRQ, disable chip-reset for BB panic */
1742 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1743 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1744 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1745 /* disable panic in non-IDLE mode, disable in IDLE mode */
1746 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1747 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1748 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1749 }
1750
1751 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1752 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1753 #undef HAL_BB_PANIC_IDLE_TIME_OUT
1754 }
1755
1756
1757 void
ar9300_handle_bb_panic(struct ath_hal * ah)1758 ar9300_handle_bb_panic(struct ath_hal *ah)
1759 {
1760 u_int32_t status;
1761 /*
1762 * we want to avoid printing in ISR context so we save
1763 * panic watchdog status to be printed later in DPC context
1764 */
1765 AH9300(ah)->ah_bb_panic_last_status = status =
1766 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1767 /*
1768 * panic watchdog timer should reset on status read
1769 * but to make sure we write 0 to the watchdog status bit
1770 */
1771 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1772 }
1773
1774 int
ar9300_get_bb_panic_info(struct ath_hal * ah,struct hal_bb_panic_info * bb_panic)1775 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1776 {
1777 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1778
1779 /*
1780 * For signature 04000539 do not print anything.
1781 * This is a very common occurence as a compromise between
1782 * BB Panic and AH_FALSE detects (EV71009). It indicates
1783 * radar hang, which can be cleared by reprogramming
1784 * radar related register and does not requre a chip reset
1785 */
1786
1787 /* Suppress BB Status mesg following signature */
1788 switch (bb_panic->status) {
1789 case 0x04000539:
1790 case 0x04008009:
1791 case 0x04000b09:
1792 case 0x1300000a:
1793 return -1;
1794 }
1795
1796 bb_panic->tsf = ar9300_get_tsf32(ah);
1797 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1798 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1799 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1800 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1801 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1802 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1803 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1804 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1805 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1806 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1807 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1808 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1809 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1810 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1811 &bb_panic->rxc_pcnt,
1812 &bb_panic->rxf_pcnt,
1813 &bb_panic->txf_pcnt);
1814
1815 if (ah->ah_config.ath_hal_show_bb_panic) {
1816 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1817 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1818 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1819 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1820 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1821 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1822 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1823 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1824 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1825 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n",
1826 bb_panic->phy_gen_ctrl);
1827 if (bb_panic->cycles) {
1828 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, "
1829 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1830 bb_panic->rxf_pcnt, bb_panic->txf_pcnt);
1831 }
1832 ath_hal_printf(ah, "==== BB update: done ====\n\n");
1833 }
1834
1835 return 0; //The returned data will be stored for athstats to retrieve it
1836 }
1837
1838 /* set the reason for HAL reset */
1839 void
ar9300_set_hal_reset_reason(struct ath_hal * ah,u_int8_t resetreason)1840 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1841 {
1842 AH9300(ah)->ah_reset_reason = resetreason;
1843 }
1844
1845 /*
1846 * Configure 20/40 operation
1847 *
1848 * 20/40 = joint rx clear (control and extension)
1849 * 20 = rx clear (control)
1850 *
1851 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1852 * when changing from 20/40 => 20 only
1853 */
1854 void
ar9300_set_11n_mac2040(struct ath_hal * ah,HAL_HT_MACMODE mode)1855 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1856 {
1857 u_int32_t macmode;
1858
1859 /* Configure MAC for 20/40 operation */
1860 if (mode == HAL_HT_MACMODE_2040 &&
1861 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1862 macmode = AR_2040_JOINED_RX_CLEAR;
1863 } else {
1864 macmode = 0;
1865 }
1866 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1867 }
1868
1869 /*
1870 * Get Rx clear (control/extension channel)
1871 *
1872 * Returns active low (busy) for ctrl/ext channel
1873 * Owl 2.0
1874 */
1875 HAL_HT_RXCLEAR
ar9300_get_11n_rx_clear(struct ath_hal * ah)1876 ar9300_get_11n_rx_clear(struct ath_hal *ah)
1877 {
1878 HAL_HT_RXCLEAR rxclear = 0;
1879 u_int32_t val;
1880
1881 val = OS_REG_READ(ah, AR_DIAG_SW);
1882
1883 /* control channel */
1884 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1885 rxclear |= HAL_RX_CLEAR_CTL_LOW;
1886 }
1887 /* extension channel */
1888 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1889 rxclear |= HAL_RX_CLEAR_EXT_LOW;
1890 }
1891 return rxclear;
1892 }
1893
1894 /*
1895 * Set Rx clear (control/extension channel)
1896 *
1897 * Useful for forcing the channel to appear busy for
1898 * debugging/diagnostics
1899 * Owl 2.0
1900 */
1901 void
ar9300_set_11n_rx_clear(struct ath_hal * ah,HAL_HT_RXCLEAR rxclear)1902 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
1903 {
1904 /* control channel */
1905 if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
1906 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1907 } else {
1908 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1909 }
1910 /* extension channel */
1911 if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
1912 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1913 } else {
1914 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1915 }
1916 }
1917
1918
1919 /*
1920 * HAL support code for force ppm tracking workaround.
1921 */
1922
1923 u_int32_t
ar9300_ppm_get_rssi_dump(struct ath_hal * ah)1924 ar9300_ppm_get_rssi_dump(struct ath_hal *ah)
1925 {
1926 u_int32_t retval;
1927 u_int32_t off1;
1928 u_int32_t off2;
1929
1930 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1931 off1 = 0x2000;
1932 off2 = 0x1000;
1933 } else {
1934 off1 = 0x1000;
1935 off2 = 0x2000;
1936 }
1937
1938 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) |
1939 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) |
1940 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16);
1941
1942 return retval;
1943 }
1944
1945 u_int32_t
ar9300_ppm_force(struct ath_hal * ah)1946 ar9300_ppm_force(struct ath_hal *ah)
1947 {
1948 u_int32_t data_fine;
1949 u_int32_t data4;
1950 //u_int32_t off1;
1951 //u_int32_t off2;
1952 HAL_BOOL signed_val = AH_FALSE;
1953
1954 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1955 // off1 = 0x2000;
1956 // off2 = 0x1000;
1957 // } else {
1958 // off1 = 0x1000;
1959 // off2 = 0x2000;
1960 // }
1961 data_fine =
1962 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK &
1963 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF);
1964
1965 /*
1966 * bit [11-0] is new ppm value. bit 11 is the signed bit.
1967 * So check value from bit[10:0].
1968 * Now get the abs val of the ppm value read in bit[0:11].
1969 * After that do bound check on abs value.
1970 * if value is off limit, CAP the value and and restore signed bit.
1971 */
1972 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1973 {
1974 /* get the positive value */
1975 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1976 signed_val = AH_TRUE;
1977 }
1978 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1979 {
1980 HALDEBUG(ah, HAL_DEBUG_REGIO,
1981 "%s Correcting ppm out of range %x\n",
1982 __func__, (data_fine & 0x7ff));
1983 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1984 }
1985 /*
1986 * Restore signed value if changed above.
1987 * Use typecast to avoid compilation errors
1988 */
1989 if (signed_val) {
1990 data_fine = (-(int32_t)data_fine) &
1991 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1992 }
1993
1994 /* write value */
1995 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) &
1996 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1997 OS_REG_WRITE(ah, AR_PHY_TIMING2,
1998 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM);
1999
2000 return data_fine;
2001 }
2002
2003 void
ar9300_ppm_un_force(struct ath_hal * ah)2004 ar9300_ppm_un_force(struct ath_hal *ah)
2005 {
2006 u_int32_t data4;
2007
2008 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM;
2009 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4);
2010 }
2011
2012 u_int32_t
ar9300_ppm_arm_trigger(struct ath_hal * ah)2013 ar9300_ppm_arm_trigger(struct ath_hal *ah)
2014 {
2015 u_int32_t val;
2016 u_int32_t ret;
2017
2018 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
2019 ret = OS_REG_READ(ah, AR_TSF_L32);
2020 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY,
2021 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
2022
2023 /* return low word of TSF at arm time */
2024 return ret;
2025 }
2026
2027 int
ar9300_ppm_get_trigger(struct ath_hal * ah)2028 ar9300_ppm_get_trigger(struct ath_hal *ah)
2029 {
2030 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) &
2031 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK)
2032 {
2033 /* has not triggered yet, return AH_FALSE */
2034 return 0;
2035 }
2036
2037 /* else triggered, return AH_TRUE */
2038 return 1;
2039 }
2040
2041 void
ar9300_mark_phy_inactive(struct ath_hal * ah)2042 ar9300_mark_phy_inactive(struct ath_hal *ah)
2043 {
2044 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2045 }
2046
2047 /* DEBUG */
2048 u_int32_t
ar9300_ppm_get_force_state(struct ath_hal * ah)2049 ar9300_ppm_get_force_state(struct ath_hal *ah)
2050 {
2051 return
2052 OS_REG_READ(ah, AR_PHY_TIMING2) &
2053 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
2054 }
2055
2056 /*
2057 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
2058 */
2059 HAL_BOOL
ar9300_get_mib_cycle_counts(struct ath_hal * ah,HAL_SURVEY_SAMPLE * hs)2060 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
2061 {
2062 /*
2063 * XXX FreeBSD todo: reimplement this
2064 */
2065 #if 0
2066 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2067 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
2068 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
2069 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2070 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
2071 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
2072 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
2073 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
2074 #endif
2075 return AH_FALSE;
2076 }
2077
2078 void
ar9300_clear_mib_counters(struct ath_hal * ah)2079 ar9300_clear_mib_counters(struct ath_hal *ah)
2080 {
2081 u_int32_t reg_val;
2082
2083 reg_val = OS_REG_READ(ah, AR_MIBC);
2084 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
2085 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
2086 }
2087
2088
2089 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
2090 HAL_BOOL
ar9300_set_rifs_delay(struct ath_hal * ah,HAL_BOOL enable)2091 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2092 {
2093 struct ath_hal_9300 *ahp = AH9300(ah);
2094 HAL_CHANNEL_INTERNAL *ichan =
2095 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2096 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2097 u_int32_t tmp = 0;
2098
2099 if (enable) {
2100 if (ahp->ah_rifs_enabled == AH_TRUE) {
2101 return AH_TRUE;
2102 }
2103
2104 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2105 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2106 ahp->ah_rifs_reg[1]);
2107
2108 ahp->ah_rifs_enabled = AH_TRUE;
2109 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg));
2110 } else {
2111 if (ahp->ah_rifs_enabled == AH_TRUE) {
2112 ahp->ah_rifs_reg[0] = OS_REG_READ(ah,
2113 AR_PHY_SEARCH_START_DELAY);
2114 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2115 }
2116 /* Change rifs init delay to 0 */
2117 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2118 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2119 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2120 if (is_chan_2g) {
2121 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2122 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2123 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2124 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2125 }
2126 } else {
2127 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2128 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2129 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2130 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2131 }
2132 }
2133
2134 ahp->ah_rifs_enabled = AH_FALSE;
2135 }
2136 return AH_TRUE;
2137
2138 } /* ar9300_set_rifs_delay () */
2139
2140 /* Set the current RIFS Rx setting */
2141 HAL_BOOL
ar9300_set_11n_rx_rifs(struct ath_hal * ah,HAL_BOOL enable)2142 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable)
2143 {
2144 /* Non-Owl 11n chips */
2145 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) {
2146 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) {
2147 return ar9300_set_rifs_delay(ah, enable);
2148 }
2149 return AH_FALSE;
2150 }
2151
2152 return AH_TRUE;
2153 } /* ar9300_set_11n_rx_rifs () */
2154
2155 static hal_mac_hangs_t
ar9300_compare_dbg_hang(struct ath_hal * ah,mac_dbg_regs_t mac_dbg,hal_mac_hang_check_t hang_check,hal_mac_hangs_t hangs,u_int8_t * dcu_chain)2156 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg,
2157 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain)
2158 {
2159 int i = 0;
2160 hal_mac_hangs_t found_hangs = 0;
2161
2162 if (hangs & dcu_chain_state) {
2163 for (i = 0; i < 6; i++) {
2164 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) ==
2165 hang_check.dcu_chain_state)
2166 {
2167 found_hangs |= dcu_chain_state;
2168 *dcu_chain = i;
2169 }
2170 }
2171 for (i = 0; i < 4; i++) {
2172 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) ==
2173 hang_check.dcu_chain_state)
2174 {
2175 found_hangs |= dcu_chain_state;
2176 *dcu_chain = i + 6;
2177 }
2178 }
2179 }
2180
2181 if (hangs & dcu_complete_state) {
2182 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) {
2183 found_hangs |= dcu_complete_state;
2184 }
2185 }
2186
2187 return found_hangs;
2188
2189 } /* end - ar9300_compare_dbg_hang */
2190
2191 #define NUM_STATUS_READS 50
2192 HAL_BOOL
ar9300_detect_mac_hang(struct ath_hal * ah)2193 ar9300_detect_mac_hang(struct ath_hal *ah)
2194 {
2195 struct ath_hal_9300 *ahp = AH9300(ah);
2196 mac_dbg_regs_t mac_dbg;
2197 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0};
2198 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state);
2199 int i = 0;
2200 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val;
2201
2202 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) {
2203 return AH_FALSE;
2204 }
2205
2206 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg));
2207
2208 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2209 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2210 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2211
2212 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n",
2213 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
2214 mac_dbg.dma_dbg_6);
2215
2216 if (hang_sig1 !=
2217 ar9300_compare_dbg_hang(ah, mac_dbg,
2218 hang_sig1_val, hang_sig1, &dcu_chain))
2219 {
2220 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n");
2221 return AH_FALSE;
2222 }
2223
2224 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain);
2225 shift_val *= 5;
2226
2227 for (i = 1; i <= NUM_STATUS_READS; i++) {
2228 if (dcu_chain < 6) {
2229 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2230 current_dcu_chain_state =
2231 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f);
2232 } else {
2233 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2234 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f);
2235 }
2236 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2237
2238 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state)
2239 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) {
2240 return AH_FALSE;
2241 }
2242 }
2243 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__,
2244 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]);
2245 ahp->ah_hang[MAC_HANG_SIG1]++;
2246 return AH_TRUE;
2247
2248 } /* end - ar9300_detect_mac_hang */
2249
2250 /* Determine if the baseband is hung by reading the Observation Bus Register */
2251 HAL_BOOL
ar9300_detect_bb_hang(struct ath_hal * ah)2252 ar9300_detect_bb_hang(struct ath_hal *ah)
2253 {
2254 struct ath_hal_9300 *ahp = AH9300(ah);
2255 u_int32_t hang_sig = 0;
2256 int i = 0;
2257 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times
2258 *
2259 * 4 known BB hang signatures -
2260 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
2261 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52
2262 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18
2263 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
2264 * Rx State (bits 20-24) is 0x7.
2265 */
2266 hal_hw_hang_check_t hang_list [] =
2267 {
2268 /* Offset Reg Value Reg Mask Hang Offset */
2269 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1},
2270 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2},
2271 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3},
2272 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4}
2273 };
2274
2275 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR |
2276 HAL_DFS_BB_HANG_WAR |
2277 HAL_RX_STUCK_LOW_BB_HANG_WAR))) {
2278 return AH_FALSE;
2279 }
2280
2281 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1);
2282 for (i = 1; i <= NUM_STATUS_READS; i++) {
2283 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) {
2284 return AH_FALSE;
2285 }
2286 }
2287
2288 for (i = 0; i < nitems(hang_list); i++) {
2289 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) {
2290 ahp->ah_hang[hang_list[i].hang_offset]++;
2291 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d "
2292 "sig3count=%d sig4count=%d\n", __func__,
2293 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2],
2294 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]);
2295 return AH_TRUE;
2296 }
2297 }
2298
2299 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! "
2300 "<0x806c>=0x%x\n", __func__, hang_sig);
2301
2302 return AH_FALSE;
2303
2304 } /* end - ar9300_detect_bb_hang () */
2305
2306 #undef NUM_STATUS_READS
2307
2308 HAL_STATUS
ar9300_select_ant_config(struct ath_hal * ah,u_int32_t cfg)2309 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2310 {
2311 struct ath_hal_9300 *ahp = AH9300(ah);
2312 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2313 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2314 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2315 u_int16_t ant_config;
2316 u_int32_t hal_num_ant_config;
2317
2318 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2319 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2320
2321 if (cfg < hal_num_ant_config) {
2322 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2323 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2324 return HAL_OK;
2325 }
2326 }
2327
2328 return HAL_EINVAL;
2329 }
2330
2331 /*
2332 * Functions to get/set DCS mode
2333 */
2334 void
ar9300_set_dcs_mode(struct ath_hal * ah,u_int32_t mode)2335 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2336 {
2337 AH9300(ah)->ah_dcs_enable = mode;
2338 }
2339
2340 u_int32_t
ar9300_get_dcs_mode(struct ath_hal * ah)2341 ar9300_get_dcs_mode(struct ath_hal *ah)
2342 {
2343 return AH9300(ah)->ah_dcs_enable;
2344 }
2345
2346 #if ATH_BT_COEX
2347 void
ar9300_set_bt_coex_info(struct ath_hal * ah,HAL_BT_COEX_INFO * btinfo)2348 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2349 {
2350 struct ath_hal_9300 *ahp = AH9300(ah);
2351
2352 ahp->ah_bt_module = btinfo->bt_module;
2353 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2354 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
2355 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority;
2356 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active;
2357 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity;
2358 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant;
2359 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation;
2360 }
2361
2362 void
ar9300_bt_coex_config(struct ath_hal * ah,HAL_BT_COEX_CONFIG * btconf)2363 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)
2364 {
2365 struct ath_hal_9300 *ahp = AH9300(ah);
2366 HAL_BOOL rx_clear_polarity;
2367
2368 /*
2369 * For Kiwi and Osprey, the polarity of rx_clear is active high.
2370 * The bt_rxclear_polarity flag from ath_dev needs to be inverted.
2371 */
2372 rx_clear_polarity = !btconf->bt_rxclear_polarity;
2373
2374 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) |
2375 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) |
2376 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
2377 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
2378 SM(btconf->bt_mode, AR_BT_MODE) |
2379 SM(btconf->bt_quiet_collision, AR_BT_QUIET) |
2380 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) |
2381 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) |
2382 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME);
2383
2384 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR);
2385
2386 if (ahp->ah_bt_coex_single_ant == AH_FALSE) {
2387 /* Enable ACK to go out even though BT has higher priority. */
2388 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
2389 }
2390 }
2391
2392 void
ar9300_bt_coex_set_qcu_thresh(struct ath_hal * ah,int qnum)2393 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum)
2394 {
2395 struct ath_hal_9300 *ahp = AH9300(ah);
2396
2397 /* clear the old value, then set the new value */
2398 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH;
2399 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
2400 }
2401
2402 void
ar9300_bt_coex_set_weights(struct ath_hal * ah,u_int32_t stomp_type)2403 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
2404 {
2405 struct ath_hal_9300 *ahp = AH9300(ah);
2406
2407 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT;
2408 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT;
2409 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT;
2410 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT;
2411
2412 switch (stomp_type) {
2413 case HAL_BT_COEX_STOMP_ALL:
2414 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
2415 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
2416 break;
2417 case HAL_BT_COEX_STOMP_LOW:
2418 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
2419 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
2420 break;
2421 case HAL_BT_COEX_STOMP_ALL_FORCE:
2422 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0;
2423 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1;
2424 break;
2425 case HAL_BT_COEX_STOMP_LOW_FORCE:
2426 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0;
2427 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1;
2428 break;
2429 case HAL_BT_COEX_STOMP_NONE:
2430 case HAL_BT_COEX_NO_STOMP:
2431 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
2432 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
2433 break;
2434 default:
2435 /* There is a force_weight from registry */
2436 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
2437 ahp->ah_bt_coex_wlan_weight[1] = stomp_type;
2438 break;
2439 }
2440 }
2441
2442 void
ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal * ah,u_int32_t thresh)2443 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh)
2444 {
2445 struct ath_hal_9300 *ahp = AH9300(ah);
2446
2447 /* clear the old value, then set the new value */
2448 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH;
2449 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2450 }
2451
2452 static void
ar9300_bt_coex_antenna_diversity(struct ath_hal * ah,u_int32_t value)2453 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2454 {
2455 struct ath_hal_9300 *ahp = AH9300(ah);
2456 #if ATH_ANT_DIV_COMB
2457 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2458 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2459 #endif
2460
2461 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2462 {
2463 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2464 {
2465 /* Config antenna diversity */
2466 #if ATH_ANT_DIV_COMB
2467 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan);
2468 #endif
2469 }
2470 }
2471 }
2472
2473
2474 void
ar9300_bt_coex_set_parameter(struct ath_hal * ah,u_int32_t type,u_int32_t value)2475 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
2476 u_int32_t value)
2477 {
2478 struct ath_hal_9300 *ahp = AH9300(ah);
2479 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2480
2481 switch (type) {
2482 case HAL_BT_COEX_SET_ACK_PWR:
2483 if (value) {
2484 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2485 } else {
2486 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2487 }
2488 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2489 ahpriv->ah_extraTxPow, 0);
2490 break;
2491
2492 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2493 if (AR_SREV_POSEIDON(ah)) {
2494 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2495 if (value) {
2496 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2497 }
2498 else {
2499 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2500 }
2501 ar9300_bt_coex_antenna_diversity(ah, value);
2502 }
2503 break;
2504 case HAL_BT_COEX_LOWER_TX_PWR:
2505 if (value) {
2506 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2507 }
2508 else {
2509 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2510 }
2511 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2512 ahpriv->ah_extraTxPow, 0);
2513 break;
2514 #if ATH_SUPPORT_MCI
2515 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2516 if ((ah->ah_config.ath_hal_mci_config &
2517 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2518 {
2519 if (value) {
2520 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2521 ahp->ah_mci_concur_tx_en = AH_TRUE;
2522 }
2523 else {
2524 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2525 ahp->ah_mci_concur_tx_en = AH_FALSE;
2526 }
2527 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2528 ahpriv->ah_extraTxPow, 0);
2529 }
2530 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2531 ahp->ah_mci_concur_tx_en);
2532 break;
2533 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2534 if (value) {
2535 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2536 }
2537 else {
2538 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2539 }
2540 break;
2541 #endif
2542 default:
2543 break;
2544 }
2545 }
2546
2547 void
ar9300_bt_coex_disable(struct ath_hal * ah)2548 ar9300_bt_coex_disable(struct ath_hal *ah)
2549 {
2550 struct ath_hal_9300 *ahp = AH9300(ah);
2551
2552 /* Always drive rx_clear_external output as 0 */
2553 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2554 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2555
2556 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2557 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2558 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2559 }
2560
2561 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
2562 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
2563 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
2564 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
2565 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
2566 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
2567 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
2568 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
2569
2570 ahp->ah_bt_coex_enabled = AH_FALSE;
2571 }
2572
2573 int
ar9300_bt_coex_enable(struct ath_hal * ah)2574 ar9300_bt_coex_enable(struct ath_hal *ah)
2575 {
2576 struct ath_hal_9300 *ahp = AH9300(ah);
2577
2578 /* Program coex mode and weight registers to actually enable coex */
2579 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode);
2580 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2);
2581 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
2582 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
2583 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]);
2584 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]);
2585 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]);
2586 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]);
2587
2588 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) {
2589 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
2590 } else {
2591 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);
2592 }
2593
2594 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2595 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2596 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2597 } else {
2598 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2599 }
2600
2601 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2602 /* For 3-wire, configure the desired GPIO port for rx_clear */
2603 ath_hal_gpioCfgOutput(ah,
2604 ahp->ah_wlan_active_gpio_select,
2605 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2606 }
2607 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2608 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2609 {
2610 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2611 ath_hal_gpioCfgOutput(ah,
2612 ahp->ah_wlan_active_gpio_select,
2613 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2614 }
2615
2616 /*
2617 * Enable a weak pull down on BT_ACTIVE.
2618 * When BT device is disabled, BT_ACTIVE might be floating.
2619 */
2620 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU),
2621 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)),
2622 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2)));
2623
2624 ahp->ah_bt_coex_enabled = AH_TRUE;
2625
2626 return 0;
2627 }
2628
ar9300_get_bt_active_gpio(struct ath_hal * ah,u_int32_t reg)2629 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg)
2630 {
2631 return 0;
2632 }
2633
ar9300_get_wlan_active_gpio(struct ath_hal * ah,u_int32_t reg,u_int32_t bOn)2634 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn)
2635 {
2636 return bOn;
2637 }
2638
2639 void
ar9300_init_bt_coex(struct ath_hal * ah)2640 ar9300_init_bt_coex(struct ath_hal *ah)
2641 {
2642 struct ath_hal_9300 *ahp = AH9300(ah);
2643
2644 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2645 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2646 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
2647 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
2648
2649 /*
2650 * Set input mux for bt_prority_async and
2651 * bt_active_async to GPIO pins
2652 */
2653 OS_REG_RMW_FIELD(ah,
2654 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2655 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2656 ahp->ah_bt_active_gpio_select);
2657 OS_REG_RMW_FIELD(ah,
2658 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2659 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2660 ahp->ah_bt_priority_gpio_select);
2661
2662 /* Configure the desired GPIO ports for input */
2663 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2664 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2665
2666 if (ahp->ah_bt_coex_enabled) {
2667 ar9300_bt_coex_enable(ah);
2668 } else {
2669 ar9300_bt_coex_disable(ah);
2670 }
2671 }
2672 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2673 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2674 {
2675 /* 2-wire */
2676 if (ahp->ah_bt_coex_enabled) {
2677 /* Connect bt_active_async to baseband */
2678 OS_REG_CLR_BIT(ah,
2679 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2680 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
2681 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
2682 OS_REG_SET_BIT(ah,
2683 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2684 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
2685
2686 /*
2687 * Set input mux for bt_prority_async and
2688 * bt_active_async to GPIO pins
2689 */
2690 OS_REG_RMW_FIELD(ah,
2691 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2692 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2693 ahp->ah_bt_active_gpio_select);
2694
2695 /* Configure the desired GPIO ports for input */
2696 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2697
2698 /* Enable coexistence on initialization */
2699 ar9300_bt_coex_enable(ah);
2700 }
2701 }
2702 #if ATH_SUPPORT_MCI
2703 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2704 if (ahp->ah_bt_coex_enabled) {
2705 ar9300_mci_bt_coex_enable(ah);
2706 }
2707 else {
2708 ar9300_mci_bt_coex_disable(ah);
2709 }
2710 }
2711 #endif /* ATH_SUPPORT_MCI */
2712 }
2713
2714 #endif /* ATH_BT_COEX */
2715
ar9300_set_proxy_sta(struct ath_hal * ah,HAL_BOOL enable)2716 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
2717 {
2718 u_int32_t val;
2719 int wasp_mm_rev;
2720
2721 #define AR_SOC_RST_REVISION_ID 0xB8060090
2722 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2723 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) &
2724 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >>
2725 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT;
2726 #undef AR_SOC_RST_REVISION_ID
2727 #undef REG_READ
2728
2729 /*
2730 * Azimuth (ProxySTA) Mode is only supported correctly by
2731 * Peacock or WASP 1.3.0.1 or later (hopefully) chips.
2732 *
2733 * Enable this feature for Scorpion at this time. The silicon
2734 * still needs to be validated.
2735 */
2736 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) &&
2737 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) &&
2738 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) &&
2739 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) ||
2740 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 &&
2741 wasp_mm_rev >= 0 /* 1 */))))
2742 {
2743 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, "
2744 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n",
2745 __func__, AH_PRIVATE((ah))->ah_macVersion,
2746 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev);
2747 return HAL_ENOTSUPP;
2748 }
2749
2750 OS_REG_WRITE(ah,
2751 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996);
2752
2753 /* turn on mode bit[24] for proxy sta */
2754 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2755 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA);
2756
2757 val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2758 if (enable) {
2759 val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2760 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2761 AR_AZIMUTH_BA_USES_AD1;
2762 /* turn off filter pass hold (bit 9) */
2763 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2764 } else {
2765 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2766 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2767 AR_AZIMUTH_BA_USES_AD1);
2768 }
2769 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2770
2771 /* enable promiscous mode */
2772 OS_REG_WRITE(ah, AR_RX_FILTER,
2773 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM);
2774 /* enable promiscous in azimuth mode */
2775 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE);
2776 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE);
2777
2778 /* turn on filter pass hold (bit 9) */
2779 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2780 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2781
2782 return HAL_OK;
2783 }
2784
2785 #if 0
2786 void ar9300_mat_enable(struct ath_hal *ah, int enable)
2787 {
2788 /*
2789 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2790 * mitigation and turn on key search always for better performance.
2791 */
2792 struct ath_hal_9300 *ahp = AH9300(ah);
2793 struct ath_hal_private *ap = AH_PRIVATE(ah);
2794
2795 ahp->ah_intr_mitigation_rx = !enable;
2796 if (ahp->ah_intr_mitigation_rx) {
2797 /*
2798 * Enable Interrupt Mitigation for Rx.
2799 * If no build-specific limits for the rx interrupt mitigation
2800 * timer have been specified, use conservative defaults.
2801 */
2802 #ifndef AH_RIMT_VAL_LAST
2803 #define AH_RIMT_LAST_MICROSEC 500
2804 #endif
2805 #ifndef AH_RIMT_VAL_FIRST
2806 #define AH_RIMT_FIRST_MICROSEC 2000
2807 #endif
2808 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2809 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2810 } else {
2811 OS_REG_WRITE(ah, AR_RIMT, 0);
2812 }
2813
2814 ahp->ah_enable_keysearch_always = !!enable;
2815 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2816 }
2817 #endif
2818
ar9300_enable_tpc(struct ath_hal * ah)2819 void ar9300_enable_tpc(struct ath_hal *ah)
2820 {
2821 u_int32_t val = 0;
2822
2823 ah->ah_config.ath_hal_desc_tpc = 1;
2824
2825 /* Enable TPC */
2826 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2827
2828 /*
2829 * Disable per chain power reduction since we are already
2830 * accounting for this in our calculations
2831 */
2832 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2833 if (AR_SREV_WASP(ah)) {
2834 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2835 val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2836 } else {
2837 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2838 val & AR_PHY_POWER_TX_SUB_3_DISABLE);
2839 }
2840 }
2841
2842
2843 /*
2844 * ar9300_force_tsf_sync
2845 * This function forces the TSF sync to the given bssid, this is implemented
2846 * as a temp hack to get the AoW demo, and is primarily used in the WDS client
2847 * mode of operation, where we sync the TSF to RootAP TSF values
2848 */
2849 void
ar9300_force_tsf_sync(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)2850 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
2851 u_int16_t assoc_id)
2852 {
2853 ar9300_set_operating_mode(ah, HAL_M_STA);
2854 ar9300_write_associd(ah, bssid, assoc_id);
2855 }
2856
ar9300_chk_rssi_update_tx_pwr(struct ath_hal * ah,int rssi)2857 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
2858 {
2859 struct ath_hal_9300 *ahp = AH9300(ah);
2860 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val;
2861 u_int32_t temp_powertx_rate9_reg_val;
2862 int8_t olpc_power_offset = 0;
2863 int8_t tmp_olpc_val = 0;
2864 HAL_RSSI_TX_POWER old_greentx_status;
2865 u_int8_t target_power_val_t[ar9300_rate_size];
2866 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2867
2868 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2869 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2870 return;
2871 }
2872
2873 old_greentx_status = AH9300(ah)->green_tx_status;
2874 if (ahp->ah_hw_green_tx_enable) {
2875 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2876 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2877 } else {
2878 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2879 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2880 }
2881
2882 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2883 && (rssi > tmp_rss1_thr1))
2884 {
2885 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2886 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2887 }
2888 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2889 && (rssi > tmp_rss1_thr2))
2890 {
2891 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2892 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2893 }
2894 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2895 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2896 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2897 }
2898 }
2899
2900 /* If status is not change, don't do anything */
2901 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2902 return;
2903 }
2904
2905 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2906 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2907 && AR_SREV_POSEIDON(ah))
2908 {
2909 if (ahp->ah_hw_green_tx_enable) {
2910 switch (AH9300(ah)->green_tx_status) {
2911 case HAL_RSSI_TX_POWER_SHORT:
2912 /* 1. TxPower Config */
2913 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2914 sizeof(target_power_val_t));
2915 /* 1.1 Store OLPC Delta Calibration Offset*/
2916 olpc_power_offset = 0;
2917 /* 2. Store OB/DB */
2918 /* 3. Store TPC settting */
2919 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2920 SM(14, AR_TPC_CTS) |
2921 SM(14, AR_TPC_CHIRP) |
2922 SM(14, AR_TPC_RPT));
2923 /* 4. Store BB_powertx_rate9 value */
2924 temp_powertx_rate9_reg_val =
2925 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE;
2926 break;
2927 case HAL_RSSI_TX_POWER_MIDDLE:
2928 /* 1. TxPower Config */
2929 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle,
2930 sizeof(target_power_val_t));
2931 /* 1.1 Store OLPC Delta Calibration Offset*/
2932 olpc_power_offset = 0;
2933 /* 2. Store OB/DB */
2934 /* 3. Store TPC settting */
2935 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) |
2936 SM(18, AR_TPC_CTS) |
2937 SM(18, AR_TPC_CHIRP) |
2938 SM(18, AR_TPC_RPT));
2939 /* 4. Store BB_powertx_rate9 value */
2940 temp_powertx_rate9_reg_val =
2941 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE;
2942 break;
2943 case HAL_RSSI_TX_POWER_LONG:
2944 default:
2945 /* 1. TxPower Config */
2946 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2947 sizeof(target_power_val_t));
2948 /* 1.1 Store OLPC Delta Calibration Offset*/
2949 olpc_power_offset = 0;
2950 /* 2. Store OB/DB1/DB2 */
2951 /* 3. Store TPC settting */
2952 temp_tcp_reg_val =
2953 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2954 /* 4. Store BB_powertx_rate9 value */
2955 temp_powertx_rate9_reg_val =
2956 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2957 break;
2958 }
2959 } else {
2960 switch (AH9300(ah)->green_tx_status) {
2961 case HAL_RSSI_TX_POWER_SHORT:
2962 /* 1. TxPower Config */
2963 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2964 sizeof(target_power_val_t));
2965 /* 1.1 Store OLPC Delta Calibration Offset*/
2966 olpc_power_offset =
2967 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2968 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2969 /* 2. Store OB/DB */
2970 temp_obdb_reg_val =
2971 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2972 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2973 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2974 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2975 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2976 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2977 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2978 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2979 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2980 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2981 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2982 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2983 /* 3. Store TPC settting */
2984 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) |
2985 SM(6, AR_TPC_CTS) |
2986 SM(6, AR_TPC_CHIRP) |
2987 SM(6, AR_TPC_RPT));
2988 /* 4. Store BB_powertx_rate9 value */
2989 temp_powertx_rate9_reg_val =
2990 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE;
2991 break;
2992 case HAL_RSSI_TX_POWER_MIDDLE:
2993 /* 1. TxPower Config */
2994 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2995 sizeof(target_power_val_t));
2996 /* 1.1 Store OLPC Delta Calibration Offset*/
2997 olpc_power_offset =
2998 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2999 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3000 /* 2. Store OB/DB */
3001 temp_obdb_reg_val =
3002 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3003 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
3004 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
3005 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
3006 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
3007 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
3008 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3009 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
3010 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3011 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
3012 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3013 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
3014 /* 3. Store TPC settting */
3015 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
3016 SM(14, AR_TPC_CTS) |
3017 SM(14, AR_TPC_CHIRP) |
3018 SM(14, AR_TPC_RPT));
3019 /* 4. Store BB_powertx_rate9 value */
3020 temp_powertx_rate9_reg_val =
3021 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE;
3022 break;
3023 case HAL_RSSI_TX_POWER_LONG:
3024 default:
3025 /* 1. TxPower Config */
3026 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
3027 sizeof(target_power_val_t));
3028 /* 1.1 Store OLPC Delta Calibration Offset*/
3029 olpc_power_offset =
3030 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
3031 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3032 /* 2. Store OB/DB1/DB2 */
3033 temp_obdb_reg_val =
3034 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3035 /* 3. Store TPC settting */
3036 temp_tcp_reg_val =
3037 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
3038 /* 4. Store BB_powertx_rate9 value */
3039 temp_powertx_rate9_reg_val =
3040 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
3041 break;
3042 }
3043 }
3044 /* 1.1 Do OLPC Delta Calibration Offset */
3045 tmp_olpc_val =
3046 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
3047 tmp_olpc_val += olpc_power_offset;
3048 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
3049 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3050 AR_PHY_TPC_OLPC_GAIN_DELTA);
3051
3052 /* 1.2 TxPower Config */
3053 ar9300_transmit_power_reg_write(ah, target_power_val_t);
3054 /* 2. Config OB/DB */
3055 if (!ahp->ah_hw_green_tx_enable) {
3056 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
3057 }
3058 /* 3. config TPC settting */
3059 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
3060 /* 4. config BB_powertx_rate9 value */
3061 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
3062 }
3063 }
3064
3065 #if 0
3066 void
3067 ar9300_get_vow_stats(
3068 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
3069 {
3070 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
3071 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
3072 }
3073 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
3074 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
3075 }
3076 if (vow_reg_flags & AR_REG_RX_CLR_CNT) {
3077 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
3078 }
3079 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
3080 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
3081 }
3082 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
3083 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
3084 }
3085 }
3086 #endif
3087
3088 /*
3089 * ar9300_is_skip_paprd_by_greentx
3090 *
3091 * This function check if we need to skip PAPRD tuning
3092 * when GreenTx in specific state.
3093 */
3094 HAL_BOOL
ar9300_is_skip_paprd_by_greentx(struct ath_hal * ah)3095 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3096 {
3097 if (AR_SREV_POSEIDON(ah) &&
3098 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3099 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3100 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3101 {
3102 return AH_TRUE;
3103 }
3104 return AH_FALSE;
3105 }
3106
3107 void
ar9300_control_signals_for_green_tx_mode(struct ath_hal * ah)3108 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
3109 {
3110 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3]
3111 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3]
3112 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3]
3113 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3]
3114 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3]
3115 struct ath_hal_9300 *ahp = AH9300(ah);
3116
3117 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3118 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3119 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0);
3120 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3121 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0);
3122 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3123 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0);
3124 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3125 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0);
3126 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3127 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0);
3128 }
3129 }
3130
ar9300_hwgreentx_set_pal_spare(struct ath_hal * ah,int value)3131 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value)
3132 {
3133 struct ath_hal_9300 *ahp = AH9300(ah);
3134
3135 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3136 if ((value == 0) || (value == 1)) {
3137 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
3138 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value);
3139 }
3140 }
3141 }
3142
ar9300_reset_hw_beacon_proc_crc(struct ath_hal * ah)3143 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah)
3144 {
3145 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC);
3146 }
3147
ar9300_get_hw_beacon_rssi(struct ath_hal * ah)3148 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah)
3149 {
3150 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3151
3152 /* RSSI format is 8.4. Ignore lowest four bits */
3153 val = val >> 4;
3154 return val;
3155 }
3156
ar9300_set_hw_beacon_rssi_threshold(struct ath_hal * ah,u_int32_t rssi_threshold)3157 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
3158 u_int32_t rssi_threshold)
3159 {
3160 struct ath_hal_9300 *ahp = AH9300(ah);
3161
3162 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold);
3163
3164 /* save value for restoring after chip reset */
3165 ahp->ah_beacon_rssi_threshold = rssi_threshold;
3166 }
3167
ar9300_reset_hw_beacon_rssi(struct ath_hal * ah)3168 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah)
3169 {
3170 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST);
3171 }
3172
ar9300_set_hw_beacon_proc(struct ath_hal * ah,HAL_BOOL on)3173 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on)
3174 {
3175 if (on) {
3176 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3177 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3178 }
3179 else {
3180 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3181 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3182 }
3183 }
3184 /*
3185 * Gets the contents of the specified key cache entry.
3186 */
3187 HAL_BOOL
ar9300_print_keycache(struct ath_hal * ah)3188 ar9300_print_keycache(struct ath_hal *ah)
3189 {
3190
3191 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3192 u_int32_t key0, key1, key2, key3, key4;
3193 u_int32_t mac_hi, mac_lo;
3194 u_int16_t entry = 0;
3195 u_int32_t valid = 0;
3196 u_int32_t key_type;
3197
3198 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3199
3200 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3201 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3202 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3203 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3204 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3205 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3206
3207 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3208
3209 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));
3210 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
3211
3212 if (mac_hi & AR_KEYTABLE_VALID) {
3213 valid = 1;
3214 } else {
3215 valid = 0;
3216 }
3217
3218 if ((mac_hi != 0) && (mac_lo != 0)) {
3219 mac_hi &= ~0x8000;
3220 mac_hi <<= 1;
3221 mac_hi |= ((mac_lo & (1 << 31) )) >> 31;
3222 mac_lo <<= 1;
3223 }
3224
3225 ath_hal_printf(ah,
3226 "%03d "
3227 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
3228 " %02d %02d "
3229 "%02x:%02x:%02x:%02x:%02x:%02x \n",
3230 entry,
3231 (key0 << 24) >> 24, (key0 << 16) >> 24,
3232 (key0 << 8) >> 24, key0 >> 24,
3233 (key1 << 24) >> 24, (key1 << 16) >> 24,
3234 //(key1 << 8) >> 24, key1 >> 24,
3235 (key2 << 24) >> 24, (key2 << 16) >> 24,
3236 (key2 << 8) >> 24, key2 >> 24,
3237 (key3 << 24) >> 24, (key3 << 16) >> 24,
3238 //(key3 << 8) >> 24, key3 >> 24,
3239 (key4 << 24) >> 24, (key4 << 16) >> 24,
3240 (key4 << 8) >> 24, key4 >> 24,
3241 valid, key_type,
3242 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3243 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3244 }
3245
3246 return AH_TRUE;
3247 }
3248
3249 /* enable/disable smart antenna mode */
3250 HAL_BOOL
ar9300_set_smart_antenna(struct ath_hal * ah,HAL_BOOL enable)3251 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3252 {
3253 struct ath_hal_9300 *ahp = AH9300(ah);
3254
3255 if (enable) {
3256 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3257 } else {
3258 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3259 }
3260
3261 /* if scropion and smart antenna is enabled, write swcom1 with 0x440
3262 * and swcom2 with 0
3263 * FIXME Ideally these registers need to be made read from caldata.
3264 * Until the calibration team gets them, keep them along with board
3265 * configuration.
3266 */
3267 if (enable && AR_SREV_SCORPION(ah) &&
3268 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) {
3269
3270 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440);
3271 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0);
3272 }
3273
3274 ahp->ah_smartantenna_enable = enable;
3275 return 1;
3276 }
3277
3278 #ifdef ATH_TX99_DIAG
3279 #ifndef ATH_SUPPORT_HTC
3280 void
ar9300_tx99_channel_pwr_update(struct ath_hal * ah,HAL_CHANNEL * c,u_int32_t txpower)3281 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3282 u_int32_t txpower)
3283 {
3284 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3285 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3286 int32_t i;
3287
3288 /* The max power is limited to 63 */
3289 if (txpower <= AR9300_MAX_RATE_POWER) {
3290 for (i = 0; i < ar9300_rate_size; i++) {
3291 p_pwr_array[i] = txpower;
3292 }
3293 } else {
3294 for (i = 0; i < ar9300_rate_size; i++) {
3295 p_pwr_array[i] = AR9300_MAX_RATE_POWER;
3296 }
3297 }
3298
3299 OS_REG_WRITE(ah, 0xa458, 0);
3300
3301 /* Write the OFDM power per rate set */
3302 /* 6 (LSB), 9, 12, 18 (MSB) */
3303 OS_REG_WRITE(ah, 0xa3c0,
3304 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24)
3305 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16)
3306 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8)
3307 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3308 );
3309 /* 24 (LSB), 36, 48, 54 (MSB) */
3310 OS_REG_WRITE(ah, 0xa3c4,
3311 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24)
3312 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16)
3313 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8)
3314 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3315 );
3316
3317 /* Write the CCK power per rate set */
3318 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3319 OS_REG_WRITE(ah, 0xa3c8,
3320 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24)
3321 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16)
3322 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */
3323 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3324 );
3325 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3326 OS_REG_WRITE(ah, 0xa3cc,
3327 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24)
3328 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16)
3329 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8)
3330 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3331 );
3332
3333 /* Write the HT20 power per rate set */
3334 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3335 OS_REG_WRITE(ah, 0xa3d0,
3336 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24)
3337 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16)
3338 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
3339 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)
3340 );
3341
3342 /* 6 (LSB), 7, 12, 13 (MSB) */
3343 OS_REG_WRITE(ah, 0xa3d4,
3344 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24)
3345 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16)
3346 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8)
3347 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0)
3348 );
3349
3350 /* 14 (LSB), 15, 20, 21 */
3351 OS_REG_WRITE(ah, 0xa3e4,
3352 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24)
3353 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16)
3354 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8)
3355 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0)
3356 );
3357
3358 /* Mixed HT20 and HT40 rates */
3359 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3360 OS_REG_WRITE(ah, 0xa3e8,
3361 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24)
3362 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16)
3363 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8)
3364 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0)
3365 );
3366
3367 /* Write the HT40 power per rate set */
3368 /* correct PAR difference between HT40 and HT20/LEGACY */
3369 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3370 OS_REG_WRITE(ah, 0xa3d8,
3371 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24)
3372 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16)
3373 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
3374 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)
3375 );
3376
3377 /* 6 (LSB), 7, 12, 13 (MSB) */
3378 OS_REG_WRITE(ah, 0xa3dc,
3379 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24)
3380 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16)
3381 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8)
3382 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0)
3383 );
3384
3385 /* 14 (LSB), 15, 20, 21 */
3386 OS_REG_WRITE(ah, 0xa3ec,
3387 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24)
3388 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16)
3389 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8)
3390 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0)
3391 );
3392 #undef PWR_MAS
3393 }
3394
3395 void
ar9300_tx99_chainmsk_setup(struct ath_hal * ah,int tx_chainmask)3396 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
3397 {
3398 if (tx_chainmask == 0x5) {
3399 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3400 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3401 }
3402 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
3403 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
3404
3405 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3406 if (tx_chainmask == 0x5) {
3407 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3408 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3409 }
3410 }
3411
3412 void
ar9300_tx99_set_single_carrier(struct ath_hal * ah,int tx_chain_mask,int chtype)3413 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask,
3414 int chtype)
3415 {
3416 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff);
3417 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1));
3418 OS_REG_WRITE(ah, 0xa350,
3419 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13));
3420
3421 /* 11G mode */
3422 if (!chtype) {
3423 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3424 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3425 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3426 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3427 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3428 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3429 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3430 | (0x1 << 26) | (0x7 << 24))
3431 & ~(0x1 << 22));
3432 } else {
3433 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3434 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3435 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3436 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3437 | (0x1 << 26) | (0x7 << 24))
3438 & ~(0x1 << 22));
3439 }
3440
3441 /* chain zero */
3442 if ((tx_chain_mask & 0x01) == 0x01) {
3443 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3444 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3445 | (0x1 << 31) | (0x5 << 15)
3446 | (0x3 << 9)) & ~(0x1 << 27)
3447 & ~(0x1 << 12));
3448 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3449 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3450 | (0x1 << 12) | (0x1 << 10)
3451 | (0x1 << 9) | (0x1 << 8)
3452 | (0x1 << 7)) & ~(0x1 << 11));
3453 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3454 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3455 | (0x1 << 29) | (0x1 << 25)
3456 | (0x1 << 23) | (0x1 << 19)
3457 | (0x1 << 10) | (0x1 << 9)
3458 | (0x1 << 8) | (0x1 << 3))
3459 & ~(0x1 << 28)& ~(0x1 << 24)
3460 & ~(0x1 << 22)& ~(0x1 << 7));
3461 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3462 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3463 | (0x1 << 23))& ~(0x1 << 21));
3464 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3465 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3466 | (0x1 << 12) | (0x1 << 10)
3467 | (0x1 << 9) | (0x1 << 8)
3468 | (0x1 << 6) | (0x1 << 5)
3469 | (0x1 << 4) | (0x1 << 3)
3470 | (0x1 << 2));
3471 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3472 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3473 }
3474 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3475 /* chain one */
3476 if ((tx_chain_mask & 0x02) == 0x02 ) {
3477 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3478 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3479 | (0x1 << 31) | (0x5 << 15)
3480 | (0x3 << 9)) & ~(0x1 << 27)
3481 & ~(0x1 << 12));
3482 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3483 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3484 | (0x1 << 12) | (0x1 << 10)
3485 | (0x1 << 9) | (0x1 << 8)
3486 | (0x1 << 7)) & ~(0x1 << 11));
3487 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3488 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3489 | (0x1 << 29) | (0x1 << 25)
3490 | (0x1 << 23) | (0x1 << 19)
3491 | (0x1 << 10) | (0x1 << 9)
3492 | (0x1 << 8) | (0x1 << 3))
3493 & ~(0x1 << 28)& ~(0x1 << 24)
3494 & ~(0x1 << 22)& ~(0x1 << 7));
3495 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3496 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3497 | (0x1 << 23))& ~(0x1 << 21));
3498 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3499 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3500 | (0x1 << 12) | (0x1 << 10)
3501 | (0x1 << 9) | (0x1 << 8)
3502 | (0x1 << 6) | (0x1 << 5)
3503 | (0x1 << 4) | (0x1 << 3)
3504 | (0x1 << 2));
3505 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3506 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3507 }
3508 }
3509 if (AR_SREV_OSPREY(ah)) {
3510 /* chain two */
3511 if ((tx_chain_mask & 0x04) == 0x04 ) {
3512 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3513 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3514 | (0x1 << 31) | (0x5 << 15)
3515 | (0x3 << 9)) & ~(0x1 << 27)
3516 & ~(0x1 << 12));
3517 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3518 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3519 | (0x1 << 12) | (0x1 << 10)
3520 | (0x1 << 9) | (0x1 << 8)
3521 | (0x1 << 7)) & ~(0x1 << 11));
3522 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3523 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3524 | (0x1 << 29) | (0x1 << 25)
3525 | (0x1 << 23) | (0x1 << 19)
3526 | (0x1 << 10) | (0x1 << 9)
3527 | (0x1 << 8) | (0x1 << 3))
3528 & ~(0x1 << 28)& ~(0x1 << 24)
3529 & ~(0x1 << 22)& ~(0x1 << 7));
3530 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3531 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3532 | (0x1 << 23))& ~(0x1 << 21));
3533 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3534 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3535 | (0x1 << 12) | (0x1 << 10)
3536 | (0x1 << 9) | (0x1 << 8)
3537 | (0x1 << 6) | (0x1 << 5)
3538 | (0x1 << 4) | (0x1 << 3)
3539 | (0x1 << 2));
3540 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3541 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3542 }
3543 }
3544
3545 OS_REG_WRITE(ah, 0xa28c, 0x11111);
3546 OS_REG_WRITE(ah, 0xa288, 0x111);
3547 } else {
3548 /* chain zero */
3549 if ((tx_chain_mask & 0x01) == 0x01) {
3550 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3551 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3552 | (0x1 << 31) | (0x1 << 27)
3553 | (0x3 << 23) | (0x1 << 19)
3554 | (0x1 << 15) | (0x3 << 9))
3555 & ~(0x1 << 12));
3556 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3557 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3558 | (0x1 << 12) | (0x1 << 10)
3559 | (0x1 << 9) | (0x1 << 8)
3560 | (0x1 << 7) | (0x1 << 3)
3561 | (0x1 << 2) | (0x1 << 1))
3562 & ~(0x1 << 11)& ~(0x1 << 0));
3563 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3564 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3565 | (0x1 << 29) | (0x1 << 25)
3566 | (0x1 << 23) | (0x1 << 19)
3567 | (0x1 << 10) | (0x1 << 9)
3568 | (0x1 << 8) | (0x1 << 3))
3569 & ~(0x1 << 28)& ~(0x1 << 24)
3570 & ~(0x1 << 22)& ~(0x1 << 7));
3571 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3572 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3573 | (0x1 << 23))& ~(0x1 << 21));
3574 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2,
3575 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
3576 | (0x3 << 3) | (0x3 << 0));
3577 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3,
3578 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
3579 | (0x3 << 29) | (0x3 << 26)
3580 | (0x2 << 23) | (0x2 << 20)
3581 | (0x2 << 17))& ~(0x1 << 14));
3582 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3583 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3584 | (0x1 << 12) | (0x1 << 10)
3585 | (0x1 << 9) | (0x1 << 8)
3586 | (0x1 << 6) | (0x1 << 5)
3587 | (0x1 << 4) | (0x1 << 3)
3588 | (0x1 << 2));
3589 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3590 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3591 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3592 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3593 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3594 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3595 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3596 | (0x1 << 26) | (0x7 << 24)
3597 | (0x3 << 22));
3598 } else {
3599 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3600 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3601 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3602 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3603 | (0x1 << 26) | (0x7 << 24)
3604 | (0x3 << 22));
3605 }
3606
3607 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3608 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3609 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3610 | (0x1 << 3) | (0x1 << 2)
3611 | (0x1 << 1)) & ~(0x1 << 0));
3612 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3613 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3614 | (0x1 << 19) | (0x1 << 3));
3615 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3616 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3617 }
3618 if (AR_SREV_OSPREY(ah)) {
3619 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3620 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3621 | (0x1 << 3) | (0x1 << 2)
3622 | (0x1 << 1)) & ~(0x1 << 0));
3623 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3624 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3625 | (0x1 << 19) | (0x1 << 3));
3626 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3627 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3628 }
3629 }
3630 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3631 /* chain one */
3632 if ((tx_chain_mask & 0x02) == 0x02 ) {
3633 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3634 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3635 | (0x1 << 3) | (0x1 << 2)
3636 | (0x1 << 1)) & ~(0x1 << 0));
3637 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3638 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3639 | (0x1 << 19) | (0x1 << 3));
3640 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3641 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3642 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3643 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3644 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3645 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3646 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3647 | (0x1 << 26) | (0x7 << 24)
3648 | (0x3 << 22));
3649 } else {
3650 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3651 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3652 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3653 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3654 | (0x1 << 26) | (0x7 << 24)
3655 | (0x3 << 22));
3656 }
3657
3658 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3659 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3660 | (0x1 << 31) | (0x1 << 27)
3661 | (0x3 << 23) | (0x1 << 19)
3662 | (0x1 << 15) | (0x3 << 9))
3663 & ~(0x1 << 12));
3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3665 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3666 | (0x1 << 12) | (0x1 << 10)
3667 | (0x1 << 9) | (0x1 << 8)
3668 | (0x1 << 7) | (0x1 << 3)
3669 | (0x1 << 2) | (0x1 << 1))
3670 & ~(0x1 << 11)& ~(0x1 << 0));
3671 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3672 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3673 | (0x1 << 29) | (0x1 << 25)
3674 | (0x1 << 23) | (0x1 << 19)
3675 | (0x1 << 10) | (0x1 << 9)
3676 | (0x1 << 8) | (0x1 << 3))
3677 & ~(0x1 << 28)& ~(0x1 << 24)
3678 & ~(0x1 << 22)& ~(0x1 << 7));
3679 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3680 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3681 | (0x1 << 23))& ~(0x1 << 21));
3682 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2,
3683 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
3684 | (0x3 << 3) | (0x3 << 0));
3685 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3,
3686 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
3687 | (0x3 << 29) | (0x3 << 26)
3688 | (0x2 << 23) | (0x2 << 20)
3689 | (0x2 << 17))& ~(0x1 << 14));
3690 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3691 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3692 | (0x1 << 12) | (0x1 << 10)
3693 | (0x1 << 9) | (0x1 << 8)
3694 | (0x1 << 6) | (0x1 << 5)
3695 | (0x1 << 4) | (0x1 << 3)
3696 | (0x1 << 2));
3697 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3698 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3699
3700 if (AR_SREV_OSPREY(ah)) {
3701 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3702 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3703 | (0x1 << 3) | (0x1 << 2)
3704 | (0x1 << 1)) & ~(0x1 << 0));
3705 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3706 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3707 | (0x1 << 19) | (0x1 << 3));
3708 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3709 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3710 }
3711 }
3712 }
3713 if (AR_SREV_OSPREY(ah)) {
3714 /* chain two */
3715 if ((tx_chain_mask & 0x04) == 0x04 ) {
3716 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3717 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3718 | (0x1 << 3) | (0x1 << 2)
3719 | (0x1 << 1)) & ~(0x1 << 0));
3720 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3721 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3722 | (0x1 << 19) | (0x1 << 3));
3723 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3724 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3725 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3726 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3727 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3728 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3729 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3730 | (0x1 << 26) | (0x7 << 24)
3731 | (0x3 << 22));
3732 } else {
3733 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3734 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3735 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3736 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3737 | (0x1 << 26) | (0x7 << 24)
3738 | (0x3 << 22));
3739 }
3740
3741 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3742 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3743 | (0x1 << 3) | (0x1 << 2)
3744 | (0x1 << 1)) & ~(0x1 << 0));
3745 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3746 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3747 | (0x1 << 19) | (0x1 << 3));
3748 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3749 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3750
3751 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3752 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3753 | (0x1 << 31) | (0x1 << 27)
3754 | (0x3 << 23) | (0x1 << 19)
3755 | (0x1 << 15) | (0x3 << 9))
3756 & ~(0x1 << 12));
3757 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3758 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3759 | (0x1 << 12) | (0x1 << 10)
3760 | (0x1 << 9) | (0x1 << 8)
3761 | (0x1 << 7) | (0x1 << 3)
3762 | (0x1 << 2) | (0x1 << 1))
3763 & ~(0x1 << 11)& ~(0x1 << 0));
3764 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3765 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3766 | (0x1 << 29) | (0x1 << 25)
3767 | (0x1 << 23) | (0x1 << 19)
3768 | (0x1 << 10) | (0x1 << 9)
3769 | (0x1 << 8) | (0x1 << 3))
3770 & ~(0x1 << 28)& ~(0x1 << 24)
3771 & ~(0x1 << 22)& ~(0x1 << 7));
3772 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3773 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3774 | (0x1 << 23))& ~(0x1 << 21));
3775 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2,
3776 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
3777 | (0x3 << 3) | (0x3 << 0));
3778 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3,
3779 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
3780 | (0x3 << 29) | (0x3 << 26)
3781 | (0x2 << 23) | (0x2 << 20)
3782 | (0x2 << 17))& ~(0x1 << 14));
3783 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3784 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3785 | (0x1 << 12) | (0x1 << 10)
3786 | (0x1 << 9) | (0x1 << 8)
3787 | (0x1 << 6) | (0x1 << 5)
3788 | (0x1 << 4) | (0x1 << 3)
3789 | (0x1 << 2));
3790 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3791 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3792 }
3793 }
3794
3795 OS_REG_WRITE(ah, 0xa28c, 0x22222);
3796 OS_REG_WRITE(ah, 0xa288, 0x222);
3797 }
3798 }
3799
3800 void
ar9300_tx99_start(struct ath_hal * ah,u_int8_t * data)3801 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data)
3802 {
3803 u_int32_t val;
3804 u_int32_t qnum = (u_int32_t)data;
3805
3806 /* Disable AGC to A2 */
3807 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR));
3808 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
3809
3810 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */
3811 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */
3812 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
3813 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
3814 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
3815 /* 200 ok for HT20, 400 ok for HT40 */
3816 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
3817 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
3818
3819 /* set QCU modes to early termination */
3820 val = OS_REG_READ(ah, AR_QMISC(qnum));
3821 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
3822 }
3823
3824 void
ar9300_tx99_stop(struct ath_hal * ah)3825 ar9300_tx99_stop(struct ath_hal *ah)
3826 {
3827 /* this should follow the setting of start */
3828 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR);
3829 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
3830 }
3831 #endif /* ATH_TX99_DIAG */
3832 #endif /* ATH_SUPPORT_HTC */
3833
3834 HAL_BOOL
ar9300Get3StreamSignature(struct ath_hal * ah)3835 ar9300Get3StreamSignature(struct ath_hal *ah)
3836 {
3837 return AH_FALSE;
3838 }
3839
3840 HAL_BOOL
ar9300ForceVCS(struct ath_hal * ah)3841 ar9300ForceVCS(struct ath_hal *ah)
3842 {
3843 return AH_FALSE;
3844 }
3845
3846 HAL_BOOL
ar9300SetDfs3StreamFix(struct ath_hal * ah,u_int32_t val)3847 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3848 {
3849 return AH_FALSE;
3850 }
3851
3852 HAL_BOOL
ar9300_set_ctl_pwr(struct ath_hal * ah,u_int8_t * ctl_array)3853 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array)
3854 {
3855 struct ath_hal_9300 *ahp = AH9300(ah);
3856 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom;
3857 u_int8_t *ctl_index;
3858 u_int32_t offset = 0;
3859
3860 if (!ctl_array)
3861 return AH_FALSE;
3862
3863 /* copy 2G ctl freqbin and power data */
3864 ctl_index = p_eep_data->ctl_index_2g;
3865 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array,
3866 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */
3867 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */
3868 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) +
3869 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G));
3870
3871
3872 /* copy 2G ctl freqbin and power data */
3873 ctl_index = p_eep_data->ctl_index_5g;
3874 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset,
3875 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */
3876 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */
3877
3878 return AH_FALSE;
3879 }
3880
3881 void
ar9300_set_txchainmaskopt(struct ath_hal * ah,u_int8_t mask)3882 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask)
3883 {
3884 struct ath_hal_9300 *ahp = AH9300(ah);
3885
3886 /* optional txchainmask should be subset of primary txchainmask */
3887 if ((mask & ahp->ah_tx_chainmask) != mask) {
3888 ahp->ah_tx_chainmaskopt = 0;
3889 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask);
3890 return;
3891 }
3892
3893 ahp->ah_tx_chainmaskopt = mask;
3894 }
3895