1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
24 #include "qemu/log.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
29 #include "cpu.h"
30 #ifdef CONFIG_TCG
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "cpu-features.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
40 #ifdef CONFIG_TCG
41 #include "hw/intc/armv7m_nvic.h"
42 #endif /* CONFIG_TCG */
43 #endif /* !CONFIG_USER_ONLY */
44 #include "sysemu/tcg.h"
45 #include "sysemu/qtest.h"
46 #include "sysemu/hw_accel.h"
47 #include "kvm_arm.h"
48 #include "disas/capstone.h"
49 #include "fpu/softfloat.h"
50 #include "cpregs.h"
51 #include "target/arm/cpu-qom.h"
52 #include "target/arm/gtimer.h"
53
arm_cpu_set_pc(CPUState * cs,vaddr value)54 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
55 {
56 ARMCPU *cpu = ARM_CPU(cs);
57 CPUARMState *env = &cpu->env;
58
59 if (is_a64(env)) {
60 env->pc = value;
61 env->thumb = false;
62 } else {
63 env->regs[15] = value & ~1;
64 env->thumb = value & 1;
65 }
66 }
67
arm_cpu_get_pc(CPUState * cs)68 static vaddr arm_cpu_get_pc(CPUState *cs)
69 {
70 ARMCPU *cpu = ARM_CPU(cs);
71 CPUARMState *env = &cpu->env;
72
73 if (is_a64(env)) {
74 return env->pc;
75 } else {
76 return env->regs[15];
77 }
78 }
79
80 #ifdef CONFIG_TCG
arm_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)81 void arm_cpu_synchronize_from_tb(CPUState *cs,
82 const TranslationBlock *tb)
83 {
84 /* The program counter is always up to date with CF_PCREL. */
85 if (!(tb_cflags(tb) & CF_PCREL)) {
86 CPUARMState *env = cpu_env(cs);
87 /*
88 * It's OK to look at env for the current mode here, because it's
89 * never possible for an AArch64 TB to chain to an AArch32 TB.
90 */
91 if (is_a64(env)) {
92 env->pc = tb->pc;
93 } else {
94 env->regs[15] = tb->pc;
95 }
96 }
97 }
98
arm_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)99 void arm_restore_state_to_opc(CPUState *cs,
100 const TranslationBlock *tb,
101 const uint64_t *data)
102 {
103 CPUARMState *env = cpu_env(cs);
104
105 if (is_a64(env)) {
106 if (tb_cflags(tb) & CF_PCREL) {
107 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
108 } else {
109 env->pc = data[0];
110 }
111 env->condexec_bits = 0;
112 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
113 } else {
114 if (tb_cflags(tb) & CF_PCREL) {
115 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
116 } else {
117 env->regs[15] = data[0];
118 }
119 env->condexec_bits = data[1];
120 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
121 }
122 }
123 #endif /* CONFIG_TCG */
124
125 /*
126 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with
127 * IRQ without Superpriority. Moreover, if the GIC is configured so that
128 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see
129 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
130 * unconditionally.
131 */
arm_cpu_has_work(CPUState * cs)132 static bool arm_cpu_has_work(CPUState *cs)
133 {
134 ARMCPU *cpu = ARM_CPU(cs);
135
136 return (cpu->power_state != PSCI_OFF)
137 && cs->interrupt_request &
138 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
139 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI
140 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
141 | CPU_INTERRUPT_EXITTB);
142 }
143
arm_cpu_mmu_index(CPUState * cs,bool ifetch)144 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
145 {
146 return arm_env_mmu_index(cpu_env(cs));
147 }
148
arm_register_pre_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)149 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
150 void *opaque)
151 {
152 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
153
154 entry->hook = hook;
155 entry->opaque = opaque;
156
157 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
158 }
159
arm_register_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)160 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
161 void *opaque)
162 {
163 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
164
165 entry->hook = hook;
166 entry->opaque = opaque;
167
168 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
169 }
170
cp_reg_reset(gpointer key,gpointer value,gpointer opaque)171 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
172 {
173 /* Reset a single ARMCPRegInfo register */
174 ARMCPRegInfo *ri = value;
175 ARMCPU *cpu = opaque;
176
177 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
178 return;
179 }
180
181 if (ri->resetfn) {
182 ri->resetfn(&cpu->env, ri);
183 return;
184 }
185
186 /* A zero offset is never possible as it would be regs[0]
187 * so we use it to indicate that reset is being handled elsewhere.
188 * This is basically only used for fields in non-core coprocessors
189 * (like the pxa2xx ones).
190 */
191 if (!ri->fieldoffset) {
192 return;
193 }
194
195 if (cpreg_field_is_64bit(ri)) {
196 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
197 } else {
198 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
199 }
200 }
201
cp_reg_check_reset(gpointer key,gpointer value,gpointer opaque)202 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
203 {
204 /* Purely an assertion check: we've already done reset once,
205 * so now check that running the reset for the cpreg doesn't
206 * change its value. This traps bugs where two different cpregs
207 * both try to reset the same state field but to different values.
208 */
209 ARMCPRegInfo *ri = value;
210 ARMCPU *cpu = opaque;
211 uint64_t oldvalue, newvalue;
212
213 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
214 return;
215 }
216
217 oldvalue = read_raw_cp_reg(&cpu->env, ri);
218 cp_reg_reset(key, value, opaque);
219 newvalue = read_raw_cp_reg(&cpu->env, ri);
220 assert(oldvalue == newvalue);
221 }
222
arm_cpu_reset_hold(Object * obj,ResetType type)223 static void arm_cpu_reset_hold(Object *obj, ResetType type)
224 {
225 CPUState *cs = CPU(obj);
226 ARMCPU *cpu = ARM_CPU(cs);
227 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
228 CPUARMState *env = &cpu->env;
229
230 if (acc->parent_phases.hold) {
231 acc->parent_phases.hold(obj, type);
232 }
233
234 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
235
236 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
237 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
238
239 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
240 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
241 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
242 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
243
244 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;
245
246 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
247 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
248 }
249
250 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
251 /* 64 bit CPUs always start in 64 bit mode */
252 env->aarch64 = true;
253 #if defined(CONFIG_USER_ONLY)
254 env->pstate = PSTATE_MODE_EL0t;
255 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
256 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
257 /* Enable all PAC keys. */
258 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
259 SCTLR_EnDA | SCTLR_EnDB);
260 /* Trap on btype=3 for PACIxSP. */
261 env->cp15.sctlr_el[1] |= SCTLR_BT0;
262 /* Trap on implementation defined registers. */
263 if (cpu_isar_feature(aa64_tidcp1, cpu)) {
264 env->cp15.sctlr_el[1] |= SCTLR_TIDCP;
265 }
266 /* and to the FP/Neon instructions */
267 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
268 CPACR_EL1, FPEN, 3);
269 /* and to the SVE instructions, with default vector length */
270 if (cpu_isar_feature(aa64_sve, cpu)) {
271 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
272 CPACR_EL1, ZEN, 3);
273 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
274 }
275 /* and for SME instructions, with default vector length, and TPIDR2 */
276 if (cpu_isar_feature(aa64_sme, cpu)) {
277 env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
278 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
279 CPACR_EL1, SMEN, 3);
280 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
281 if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
282 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
283 SMCR, FA64, 1);
284 }
285 }
286 /*
287 * Enable 48-bit address space (TODO: take reserved_va into account).
288 * Enable TBI0 but not TBI1.
289 * Note that this must match useronly_clean_ptr.
290 */
291 env->cp15.tcr_el[1] = 5 | (1ULL << 37);
292
293 /* Enable MTE */
294 if (cpu_isar_feature(aa64_mte, cpu)) {
295 /* Enable tag access, but leave TCF0 as No Effect (0). */
296 env->cp15.sctlr_el[1] |= SCTLR_ATA0;
297 /*
298 * Exclude all tags, so that tag 0 is always used.
299 * This corresponds to Linux current->thread.gcr_incl = 0.
300 *
301 * Set RRND, so that helper_irg() will generate a seed later.
302 * Here in cpu_reset(), the crypto subsystem has not yet been
303 * initialized.
304 */
305 env->cp15.gcr_el1 = 0x1ffff;
306 }
307 /*
308 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
309 * This is not yet exposed from the Linux kernel in any way.
310 */
311 env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
312 /* Disable access to Debug Communication Channel (DCC). */
313 env->cp15.mdscr_el1 |= 1 << 12;
314 /* Enable FEAT_MOPS */
315 env->cp15.sctlr_el[1] |= SCTLR_MSCEN;
316 #else
317 /* Reset into the highest available EL */
318 if (arm_feature(env, ARM_FEATURE_EL3)) {
319 env->pstate = PSTATE_MODE_EL3h;
320 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
321 env->pstate = PSTATE_MODE_EL2h;
322 } else {
323 env->pstate = PSTATE_MODE_EL1h;
324 }
325
326 /* Sample rvbar at reset. */
327 env->cp15.rvbar = cpu->rvbar_prop;
328 env->pc = env->cp15.rvbar;
329 #endif
330 } else {
331 #if defined(CONFIG_USER_ONLY)
332 /* Userspace expects access to cp10 and cp11 for FP/Neon */
333 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
334 CPACR, CP10, 3);
335 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
336 CPACR, CP11, 3);
337 #endif
338 if (arm_feature(env, ARM_FEATURE_V8)) {
339 env->cp15.rvbar = cpu->rvbar_prop;
340 env->regs[15] = cpu->rvbar_prop;
341 }
342 }
343
344 #if defined(CONFIG_USER_ONLY)
345 env->uncached_cpsr = ARM_CPU_MODE_USR;
346 /* For user mode we must enable access to coprocessors */
347 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
348 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
349 env->cp15.c15_cpar = 3;
350 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
351 env->cp15.c15_cpar = 1;
352 }
353 #else
354
355 /*
356 * If the highest available EL is EL2, AArch32 will start in Hyp
357 * mode; otherwise it starts in SVC. Note that if we start in
358 * AArch64 then these values in the uncached_cpsr will be ignored.
359 */
360 if (arm_feature(env, ARM_FEATURE_EL2) &&
361 !arm_feature(env, ARM_FEATURE_EL3)) {
362 env->uncached_cpsr = ARM_CPU_MODE_HYP;
363 } else {
364 env->uncached_cpsr = ARM_CPU_MODE_SVC;
365 }
366 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
367
368 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
369 * executing as AArch32 then check if highvecs are enabled and
370 * adjust the PC accordingly.
371 */
372 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
373 env->regs[15] = 0xFFFF0000;
374 }
375
376 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
377 #endif
378
379 if (arm_feature(env, ARM_FEATURE_M)) {
380 #ifndef CONFIG_USER_ONLY
381 uint32_t initial_msp; /* Loaded from 0x0 */
382 uint32_t initial_pc; /* Loaded from 0x4 */
383 uint8_t *rom;
384 uint32_t vecbase;
385 #endif
386
387 if (cpu_isar_feature(aa32_lob, cpu)) {
388 /*
389 * LTPSIZE is constant 4 if MVE not implemented, and resets
390 * to an UNKNOWN value if MVE is implemented. We choose to
391 * always reset to 4.
392 */
393 env->v7m.ltpsize = 4;
394 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
395 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
396 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
397 }
398
399 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
400 env->v7m.secure = true;
401 } else {
402 /* This bit resets to 0 if security is supported, but 1 if
403 * it is not. The bit is not present in v7M, but we set it
404 * here so we can avoid having to make checks on it conditional
405 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
406 */
407 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
408 /*
409 * Set NSACR to indicate "NS access permitted to everything";
410 * this avoids having to have all the tests of it being
411 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
412 * v8.1M the guest-visible value of NSACR in a CPU without the
413 * Security Extension is 0xcff.
414 */
415 env->v7m.nsacr = 0xcff;
416 }
417
418 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
419 * that it resets to 1, so QEMU always does that rather than making
420 * it dependent on CPU model. In v8M it is RES1.
421 */
422 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
423 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
424 if (arm_feature(env, ARM_FEATURE_V8)) {
425 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
426 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
427 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
428 }
429 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
430 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
431 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
432 }
433
434 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
435 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
436 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
437 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
438 }
439
440 #ifndef CONFIG_USER_ONLY
441 /* Unlike A/R profile, M profile defines the reset LR value */
442 env->regs[14] = 0xffffffff;
443
444 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
445 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
446
447 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
448 vecbase = env->v7m.vecbase[env->v7m.secure];
449 rom = rom_ptr_for_as(cs->as, vecbase, 8);
450 if (rom) {
451 /* Address zero is covered by ROM which hasn't yet been
452 * copied into physical memory.
453 */
454 initial_msp = ldl_p(rom);
455 initial_pc = ldl_p(rom + 4);
456 } else {
457 /* Address zero not covered by a ROM blob, or the ROM blob
458 * is in non-modifiable memory and this is a second reset after
459 * it got copied into memory. In the latter case, rom_ptr
460 * will return a NULL pointer and we should use ldl_phys instead.
461 */
462 initial_msp = ldl_phys(cs->as, vecbase);
463 initial_pc = ldl_phys(cs->as, vecbase + 4);
464 }
465
466 qemu_log_mask(CPU_LOG_INT,
467 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
468 initial_msp, initial_pc);
469
470 env->regs[13] = initial_msp & 0xFFFFFFFC;
471 env->regs[15] = initial_pc & ~1;
472 env->thumb = initial_pc & 1;
473 #else
474 /*
475 * For user mode we run non-secure and with access to the FPU.
476 * The FPU context is active (ie does not need further setup)
477 * and is owned by non-secure.
478 */
479 env->v7m.secure = false;
480 env->v7m.nsacr = 0xcff;
481 env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
482 env->v7m.fpccr[M_REG_S] &=
483 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
484 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
485 #endif
486 }
487
488 /* M profile requires that reset clears the exclusive monitor;
489 * A profile does not, but clearing it makes more sense than having it
490 * set with an exclusive access on address zero.
491 */
492 arm_clear_exclusive(env);
493
494 if (arm_feature(env, ARM_FEATURE_PMSA)) {
495 if (cpu->pmsav7_dregion > 0) {
496 if (arm_feature(env, ARM_FEATURE_V8)) {
497 memset(env->pmsav8.rbar[M_REG_NS], 0,
498 sizeof(*env->pmsav8.rbar[M_REG_NS])
499 * cpu->pmsav7_dregion);
500 memset(env->pmsav8.rlar[M_REG_NS], 0,
501 sizeof(*env->pmsav8.rlar[M_REG_NS])
502 * cpu->pmsav7_dregion);
503 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
504 memset(env->pmsav8.rbar[M_REG_S], 0,
505 sizeof(*env->pmsav8.rbar[M_REG_S])
506 * cpu->pmsav7_dregion);
507 memset(env->pmsav8.rlar[M_REG_S], 0,
508 sizeof(*env->pmsav8.rlar[M_REG_S])
509 * cpu->pmsav7_dregion);
510 }
511 } else if (arm_feature(env, ARM_FEATURE_V7)) {
512 memset(env->pmsav7.drbar, 0,
513 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
514 memset(env->pmsav7.drsr, 0,
515 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
516 memset(env->pmsav7.dracr, 0,
517 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
518 }
519 }
520
521 if (cpu->pmsav8r_hdregion > 0) {
522 memset(env->pmsav8.hprbar, 0,
523 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
524 memset(env->pmsav8.hprlar, 0,
525 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
526 }
527
528 env->pmsav7.rnr[M_REG_NS] = 0;
529 env->pmsav7.rnr[M_REG_S] = 0;
530 env->pmsav8.mair0[M_REG_NS] = 0;
531 env->pmsav8.mair0[M_REG_S] = 0;
532 env->pmsav8.mair1[M_REG_NS] = 0;
533 env->pmsav8.mair1[M_REG_S] = 0;
534 }
535
536 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
537 if (cpu->sau_sregion > 0) {
538 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
539 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
540 }
541 env->sau.rnr = 0;
542 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
543 * the Cortex-M33 does.
544 */
545 env->sau.ctrl = 0;
546 }
547
548 set_flush_to_zero(1, &env->vfp.standard_fp_status);
549 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
550 set_default_nan_mode(1, &env->vfp.standard_fp_status);
551 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
552 set_float_detect_tininess(float_tininess_before_rounding,
553 &env->vfp.fp_status);
554 set_float_detect_tininess(float_tininess_before_rounding,
555 &env->vfp.standard_fp_status);
556 set_float_detect_tininess(float_tininess_before_rounding,
557 &env->vfp.fp_status_f16);
558 set_float_detect_tininess(float_tininess_before_rounding,
559 &env->vfp.standard_fp_status_f16);
560 #ifndef CONFIG_USER_ONLY
561 if (kvm_enabled()) {
562 kvm_arm_reset_vcpu(cpu);
563 }
564 #endif
565
566 if (tcg_enabled()) {
567 hw_breakpoint_update_all(cpu);
568 hw_watchpoint_update_all(cpu);
569
570 arm_rebuild_hflags(env);
571 }
572 }
573
arm_emulate_firmware_reset(CPUState * cpustate,int target_el)574 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
575 {
576 ARMCPU *cpu = ARM_CPU(cpustate);
577 CPUARMState *env = &cpu->env;
578 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
579 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
580
581 /*
582 * Check we have the EL we're aiming for. If that is the
583 * highest implemented EL, then cpu_reset has already done
584 * all the work.
585 */
586 switch (target_el) {
587 case 3:
588 assert(have_el3);
589 return;
590 case 2:
591 assert(have_el2);
592 if (!have_el3) {
593 return;
594 }
595 break;
596 case 1:
597 if (!have_el3 && !have_el2) {
598 return;
599 }
600 break;
601 default:
602 g_assert_not_reached();
603 }
604
605 if (have_el3) {
606 /*
607 * Set the EL3 state so code can run at EL2. This should match
608 * the requirements set by Linux in its booting spec.
609 */
610 if (env->aarch64) {
611 env->cp15.scr_el3 |= SCR_RW;
612 if (cpu_isar_feature(aa64_pauth, cpu)) {
613 env->cp15.scr_el3 |= SCR_API | SCR_APK;
614 }
615 if (cpu_isar_feature(aa64_mte, cpu)) {
616 env->cp15.scr_el3 |= SCR_ATA;
617 }
618 if (cpu_isar_feature(aa64_sve, cpu)) {
619 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
620 env->vfp.zcr_el[3] = 0xf;
621 }
622 if (cpu_isar_feature(aa64_sme, cpu)) {
623 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
624 env->cp15.scr_el3 |= SCR_ENTP2;
625 env->vfp.smcr_el[3] = 0xf;
626 }
627 if (cpu_isar_feature(aa64_hcx, cpu)) {
628 env->cp15.scr_el3 |= SCR_HXEN;
629 }
630 if (cpu_isar_feature(aa64_fgt, cpu)) {
631 env->cp15.scr_el3 |= SCR_FGTEN;
632 }
633 }
634
635 if (target_el == 2) {
636 /* If the guest is at EL2 then Linux expects the HVC insn to work */
637 env->cp15.scr_el3 |= SCR_HCE;
638 }
639
640 /* Put CPU into non-secure state */
641 env->cp15.scr_el3 |= SCR_NS;
642 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
643 env->cp15.nsacr |= 3 << 10;
644 }
645
646 if (have_el2 && target_el < 2) {
647 /* Set EL2 state so code can run at EL1. */
648 if (env->aarch64) {
649 env->cp15.hcr_el2 |= HCR_RW;
650 }
651 }
652
653 /* Set the CPU to the desired state */
654 if (env->aarch64) {
655 env->pstate = aarch64_pstate_mode(target_el, true);
656 } else {
657 static const uint32_t mode_for_el[] = {
658 0,
659 ARM_CPU_MODE_SVC,
660 ARM_CPU_MODE_HYP,
661 ARM_CPU_MODE_SVC,
662 };
663
664 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
665 }
666 }
667
668
669 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
670
arm_excp_unmasked(CPUState * cs,unsigned int excp_idx,unsigned int target_el,unsigned int cur_el,bool secure,uint64_t hcr_el2)671 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
672 unsigned int target_el,
673 unsigned int cur_el, bool secure,
674 uint64_t hcr_el2)
675 {
676 CPUARMState *env = cpu_env(cs);
677 bool pstate_unmasked;
678 bool unmasked = false;
679 bool allIntMask = false;
680
681 /*
682 * Don't take exceptions if they target a lower EL.
683 * This check should catch any exceptions that would not be taken
684 * but left pending.
685 */
686 if (cur_el > target_el) {
687 return false;
688 }
689
690 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
691 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) {
692 allIntMask = env->pstate & PSTATE_ALLINT ||
693 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) &&
694 (env->pstate & PSTATE_SP));
695 }
696
697 switch (excp_idx) {
698 case EXCP_NMI:
699 pstate_unmasked = !allIntMask;
700 break;
701
702 case EXCP_VINMI:
703 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
704 /* VINMIs are only taken when hypervized. */
705 return false;
706 }
707 return !allIntMask;
708 case EXCP_VFNMI:
709 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
710 /* VFNMIs are only taken when hypervized. */
711 return false;
712 }
713 return !allIntMask;
714 case EXCP_FIQ:
715 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask);
716 break;
717
718 case EXCP_IRQ:
719 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask);
720 break;
721
722 case EXCP_VFIQ:
723 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
724 /* VFIQs are only taken when hypervized. */
725 return false;
726 }
727 return !(env->daif & PSTATE_F) && (!allIntMask);
728 case EXCP_VIRQ:
729 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
730 /* VIRQs are only taken when hypervized. */
731 return false;
732 }
733 return !(env->daif & PSTATE_I) && (!allIntMask);
734 case EXCP_VSERR:
735 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
736 /* VIRQs are only taken when hypervized. */
737 return false;
738 }
739 return !(env->daif & PSTATE_A);
740 default:
741 g_assert_not_reached();
742 }
743
744 /*
745 * Use the target EL, current execution state and SCR/HCR settings to
746 * determine whether the corresponding CPSR bit is used to mask the
747 * interrupt.
748 */
749 if ((target_el > cur_el) && (target_el != 1)) {
750 /* Exceptions targeting a higher EL may not be maskable */
751 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
752 switch (target_el) {
753 case 2:
754 /*
755 * According to ARM DDI 0487H.a, an interrupt can be masked
756 * when HCR_E2H and HCR_TGE are both set regardless of the
757 * current Security state. Note that we need to revisit this
758 * part again once we need to support NMI.
759 */
760 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
761 unmasked = true;
762 }
763 break;
764 case 3:
765 /* Interrupt cannot be masked when the target EL is 3 */
766 unmasked = true;
767 break;
768 default:
769 g_assert_not_reached();
770 }
771 } else {
772 /*
773 * The old 32-bit-only environment has a more complicated
774 * masking setup. HCR and SCR bits not only affect interrupt
775 * routing but also change the behaviour of masking.
776 */
777 bool hcr, scr;
778
779 switch (excp_idx) {
780 case EXCP_FIQ:
781 /*
782 * If FIQs are routed to EL3 or EL2 then there are cases where
783 * we override the CPSR.F in determining if the exception is
784 * masked or not. If neither of these are set then we fall back
785 * to the CPSR.F setting otherwise we further assess the state
786 * below.
787 */
788 hcr = hcr_el2 & HCR_FMO;
789 scr = (env->cp15.scr_el3 & SCR_FIQ);
790
791 /*
792 * When EL3 is 32-bit, the SCR.FW bit controls whether the
793 * CPSR.F bit masks FIQ interrupts when taken in non-secure
794 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
795 * when non-secure but only when FIQs are only routed to EL3.
796 */
797 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
798 break;
799 case EXCP_IRQ:
800 /*
801 * When EL3 execution state is 32-bit, if HCR.IMO is set then
802 * we may override the CPSR.I masking when in non-secure state.
803 * The SCR.IRQ setting has already been taken into consideration
804 * when setting the target EL, so it does not have a further
805 * affect here.
806 */
807 hcr = hcr_el2 & HCR_IMO;
808 scr = false;
809 break;
810 default:
811 g_assert_not_reached();
812 }
813
814 if ((scr || hcr) && !secure) {
815 unmasked = true;
816 }
817 }
818 }
819
820 /*
821 * The PSTATE bits only mask the interrupt if we have not overridden the
822 * ability above.
823 */
824 return unmasked || pstate_unmasked;
825 }
826
arm_cpu_exec_interrupt(CPUState * cs,int interrupt_request)827 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
828 {
829 CPUClass *cc = CPU_GET_CLASS(cs);
830 CPUARMState *env = cpu_env(cs);
831 uint32_t cur_el = arm_current_el(env);
832 bool secure = arm_is_secure(env);
833 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
834 uint32_t target_el;
835 uint32_t excp_idx;
836
837 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
838
839 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
840 (arm_sctlr(env, cur_el) & SCTLR_NMI)) {
841 if (interrupt_request & CPU_INTERRUPT_NMI) {
842 excp_idx = EXCP_NMI;
843 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
844 if (arm_excp_unmasked(cs, excp_idx, target_el,
845 cur_el, secure, hcr_el2)) {
846 goto found;
847 }
848 }
849 if (interrupt_request & CPU_INTERRUPT_VINMI) {
850 excp_idx = EXCP_VINMI;
851 target_el = 1;
852 if (arm_excp_unmasked(cs, excp_idx, target_el,
853 cur_el, secure, hcr_el2)) {
854 goto found;
855 }
856 }
857 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
858 excp_idx = EXCP_VFNMI;
859 target_el = 1;
860 if (arm_excp_unmasked(cs, excp_idx, target_el,
861 cur_el, secure, hcr_el2)) {
862 goto found;
863 }
864 }
865 } else {
866 /*
867 * NMI disabled: interrupts with superpriority are handled
868 * as if they didn't have it
869 */
870 if (interrupt_request & CPU_INTERRUPT_NMI) {
871 interrupt_request |= CPU_INTERRUPT_HARD;
872 }
873 if (interrupt_request & CPU_INTERRUPT_VINMI) {
874 interrupt_request |= CPU_INTERRUPT_VIRQ;
875 }
876 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
877 interrupt_request |= CPU_INTERRUPT_VFIQ;
878 }
879 }
880
881 if (interrupt_request & CPU_INTERRUPT_FIQ) {
882 excp_idx = EXCP_FIQ;
883 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
884 if (arm_excp_unmasked(cs, excp_idx, target_el,
885 cur_el, secure, hcr_el2)) {
886 goto found;
887 }
888 }
889 if (interrupt_request & CPU_INTERRUPT_HARD) {
890 excp_idx = EXCP_IRQ;
891 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
892 if (arm_excp_unmasked(cs, excp_idx, target_el,
893 cur_el, secure, hcr_el2)) {
894 goto found;
895 }
896 }
897 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
898 excp_idx = EXCP_VIRQ;
899 target_el = 1;
900 if (arm_excp_unmasked(cs, excp_idx, target_el,
901 cur_el, secure, hcr_el2)) {
902 goto found;
903 }
904 }
905 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
906 excp_idx = EXCP_VFIQ;
907 target_el = 1;
908 if (arm_excp_unmasked(cs, excp_idx, target_el,
909 cur_el, secure, hcr_el2)) {
910 goto found;
911 }
912 }
913 if (interrupt_request & CPU_INTERRUPT_VSERR) {
914 excp_idx = EXCP_VSERR;
915 target_el = 1;
916 if (arm_excp_unmasked(cs, excp_idx, target_el,
917 cur_el, secure, hcr_el2)) {
918 /* Taking a virtual abort clears HCR_EL2.VSE */
919 env->cp15.hcr_el2 &= ~HCR_VSE;
920 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
921 goto found;
922 }
923 }
924 return false;
925
926 found:
927 cs->exception_index = excp_idx;
928 env->exception.target_el = target_el;
929 cc->tcg_ops->do_interrupt(cs);
930 return true;
931 }
932
933 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
934
arm_cpu_update_virq(ARMCPU * cpu)935 void arm_cpu_update_virq(ARMCPU *cpu)
936 {
937 /*
938 * Update the interrupt level for VIRQ, which is the logical OR of
939 * the HCR_EL2.VI bit and the input line level from the GIC.
940 */
941 CPUARMState *env = &cpu->env;
942 CPUState *cs = CPU(cpu);
943
944 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
945 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
946 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
947
948 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
949 if (new_state) {
950 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
951 } else {
952 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
953 }
954 }
955 }
956
arm_cpu_update_vfiq(ARMCPU * cpu)957 void arm_cpu_update_vfiq(ARMCPU *cpu)
958 {
959 /*
960 * Update the interrupt level for VFIQ, which is the logical OR of
961 * the HCR_EL2.VF bit and the input line level from the GIC.
962 */
963 CPUARMState *env = &cpu->env;
964 CPUState *cs = CPU(cpu);
965
966 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) &&
967 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) ||
968 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
969
970 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
971 if (new_state) {
972 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
973 } else {
974 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
975 }
976 }
977 }
978
arm_cpu_update_vinmi(ARMCPU * cpu)979 void arm_cpu_update_vinmi(ARMCPU *cpu)
980 {
981 /*
982 * Update the interrupt level for VINMI, which is the logical OR of
983 * the HCRX_EL2.VINMI bit and the input line level from the GIC.
984 */
985 CPUARMState *env = &cpu->env;
986 CPUState *cs = CPU(cpu);
987
988 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
989 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
990 (env->irq_line_state & CPU_INTERRUPT_VINMI);
991
992 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) {
993 if (new_state) {
994 cpu_interrupt(cs, CPU_INTERRUPT_VINMI);
995 } else {
996 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI);
997 }
998 }
999 }
1000
arm_cpu_update_vfnmi(ARMCPU * cpu)1001 void arm_cpu_update_vfnmi(ARMCPU *cpu)
1002 {
1003 /*
1004 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit.
1005 */
1006 CPUARMState *env = &cpu->env;
1007 CPUState *cs = CPU(cpu);
1008
1009 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) &&
1010 (arm_hcrx_el2_eff(env) & HCRX_VFNMI);
1011
1012 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) {
1013 if (new_state) {
1014 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI);
1015 } else {
1016 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI);
1017 }
1018 }
1019 }
1020
arm_cpu_update_vserr(ARMCPU * cpu)1021 void arm_cpu_update_vserr(ARMCPU *cpu)
1022 {
1023 /*
1024 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
1025 */
1026 CPUARMState *env = &cpu->env;
1027 CPUState *cs = CPU(cpu);
1028
1029 bool new_state = env->cp15.hcr_el2 & HCR_VSE;
1030
1031 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
1032 if (new_state) {
1033 cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
1034 } else {
1035 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
1036 }
1037 }
1038 }
1039
1040 #ifndef CONFIG_USER_ONLY
arm_cpu_set_irq(void * opaque,int irq,int level)1041 static void arm_cpu_set_irq(void *opaque, int irq, int level)
1042 {
1043 ARMCPU *cpu = opaque;
1044 CPUARMState *env = &cpu->env;
1045 CPUState *cs = CPU(cpu);
1046 static const int mask[] = {
1047 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
1048 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
1049 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
1050 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
1051 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI,
1052 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI,
1053 };
1054
1055 if (!arm_feature(env, ARM_FEATURE_EL2) &&
1056 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) {
1057 /*
1058 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
1059 * have EL2 support we don't care. (Unless the guest is doing something
1060 * silly this will only be calls saying "level is still 0".)
1061 */
1062 return;
1063 }
1064
1065 if (level) {
1066 env->irq_line_state |= mask[irq];
1067 } else {
1068 env->irq_line_state &= ~mask[irq];
1069 }
1070
1071 switch (irq) {
1072 case ARM_CPU_VIRQ:
1073 arm_cpu_update_virq(cpu);
1074 break;
1075 case ARM_CPU_VFIQ:
1076 arm_cpu_update_vfiq(cpu);
1077 break;
1078 case ARM_CPU_VINMI:
1079 arm_cpu_update_vinmi(cpu);
1080 break;
1081 case ARM_CPU_IRQ:
1082 case ARM_CPU_FIQ:
1083 case ARM_CPU_NMI:
1084 if (level) {
1085 cpu_interrupt(cs, mask[irq]);
1086 } else {
1087 cpu_reset_interrupt(cs, mask[irq]);
1088 }
1089 break;
1090 default:
1091 g_assert_not_reached();
1092 }
1093 }
1094
arm_cpu_kvm_set_irq(void * opaque,int irq,int level)1095 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
1096 {
1097 #ifdef CONFIG_KVM
1098 ARMCPU *cpu = opaque;
1099 CPUARMState *env = &cpu->env;
1100 CPUState *cs = CPU(cpu);
1101 uint32_t linestate_bit;
1102 int irq_id;
1103
1104 switch (irq) {
1105 case ARM_CPU_IRQ:
1106 irq_id = KVM_ARM_IRQ_CPU_IRQ;
1107 linestate_bit = CPU_INTERRUPT_HARD;
1108 break;
1109 case ARM_CPU_FIQ:
1110 irq_id = KVM_ARM_IRQ_CPU_FIQ;
1111 linestate_bit = CPU_INTERRUPT_FIQ;
1112 break;
1113 default:
1114 g_assert_not_reached();
1115 }
1116
1117 if (level) {
1118 env->irq_line_state |= linestate_bit;
1119 } else {
1120 env->irq_line_state &= ~linestate_bit;
1121 }
1122 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
1123 #endif
1124 }
1125
arm_cpu_virtio_is_big_endian(CPUState * cs)1126 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
1127 {
1128 ARMCPU *cpu = ARM_CPU(cs);
1129 CPUARMState *env = &cpu->env;
1130
1131 cpu_synchronize_state(cs);
1132 return arm_cpu_data_is_big_endian(env);
1133 }
1134
1135 #ifdef CONFIG_TCG
arm_cpu_exec_halt(CPUState * cs)1136 bool arm_cpu_exec_halt(CPUState *cs)
1137 {
1138 bool leave_halt = cpu_has_work(cs);
1139
1140 if (leave_halt) {
1141 /* We're about to come out of WFI/WFE: disable the WFxT timer */
1142 ARMCPU *cpu = ARM_CPU(cs);
1143 if (cpu->wfxt_timer) {
1144 timer_del(cpu->wfxt_timer);
1145 }
1146 }
1147 return leave_halt;
1148 }
1149 #endif
1150
arm_wfxt_timer_cb(void * opaque)1151 static void arm_wfxt_timer_cb(void *opaque)
1152 {
1153 ARMCPU *cpu = opaque;
1154 CPUState *cs = CPU(cpu);
1155
1156 /*
1157 * We expect the CPU to be halted; this will cause arm_cpu_is_work()
1158 * to return true (so we will come out of halt even with no other
1159 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt()
1160 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us.
1161 */
1162 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
1163 }
1164 #endif
1165
arm_disas_set_info(CPUState * cpu,disassemble_info * info)1166 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
1167 {
1168 ARMCPU *ac = ARM_CPU(cpu);
1169 CPUARMState *env = &ac->env;
1170 bool sctlr_b;
1171
1172 if (is_a64(env)) {
1173 info->cap_arch = CS_ARCH_ARM64;
1174 info->cap_insn_unit = 4;
1175 info->cap_insn_split = 4;
1176 } else {
1177 int cap_mode;
1178 if (env->thumb) {
1179 info->cap_insn_unit = 2;
1180 info->cap_insn_split = 4;
1181 cap_mode = CS_MODE_THUMB;
1182 } else {
1183 info->cap_insn_unit = 4;
1184 info->cap_insn_split = 4;
1185 cap_mode = CS_MODE_ARM;
1186 }
1187 if (arm_feature(env, ARM_FEATURE_V8)) {
1188 cap_mode |= CS_MODE_V8;
1189 }
1190 if (arm_feature(env, ARM_FEATURE_M)) {
1191 cap_mode |= CS_MODE_MCLASS;
1192 }
1193 info->cap_arch = CS_ARCH_ARM;
1194 info->cap_mode = cap_mode;
1195 }
1196
1197 sctlr_b = arm_sctlr_b(env);
1198 if (bswap_code(sctlr_b)) {
1199 #if TARGET_BIG_ENDIAN
1200 info->endian = BFD_ENDIAN_LITTLE;
1201 #else
1202 info->endian = BFD_ENDIAN_BIG;
1203 #endif
1204 }
1205 info->flags &= ~INSN_ARM_BE32;
1206 #ifndef CONFIG_USER_ONLY
1207 if (sctlr_b) {
1208 info->flags |= INSN_ARM_BE32;
1209 }
1210 #endif
1211 }
1212
1213 #ifdef TARGET_AARCH64
1214
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1215 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1216 {
1217 ARMCPU *cpu = ARM_CPU(cs);
1218 CPUARMState *env = &cpu->env;
1219 uint32_t psr = pstate_read(env);
1220 int i, j;
1221 int el = arm_current_el(env);
1222 uint64_t hcr = arm_hcr_el2_eff(env);
1223 const char *ns_status;
1224 bool sve;
1225
1226 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
1227 for (i = 0; i < 32; i++) {
1228 if (i == 31) {
1229 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
1230 } else {
1231 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
1232 (i + 2) % 3 ? " " : "\n");
1233 }
1234 }
1235
1236 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
1237 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1238 } else {
1239 ns_status = "";
1240 }
1241 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1242 psr,
1243 psr & PSTATE_N ? 'N' : '-',
1244 psr & PSTATE_Z ? 'Z' : '-',
1245 psr & PSTATE_C ? 'C' : '-',
1246 psr & PSTATE_V ? 'V' : '-',
1247 ns_status,
1248 el,
1249 psr & PSTATE_SP ? 'h' : 't');
1250
1251 if (cpu_isar_feature(aa64_sme, cpu)) {
1252 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
1253 env->svcr,
1254 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
1255 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
1256 }
1257 if (cpu_isar_feature(aa64_bti, cpu)) {
1258 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
1259 }
1260 qemu_fprintf(f, "%s%s%s",
1261 (hcr & HCR_NV) ? " NV" : "",
1262 (hcr & HCR_NV1) ? " NV1" : "",
1263 (hcr & HCR_NV2) ? " NV2" : "");
1264 if (!(flags & CPU_DUMP_FPU)) {
1265 qemu_fprintf(f, "\n");
1266 return;
1267 }
1268 if (fp_exception_el(env, el) != 0) {
1269 qemu_fprintf(f, " FPU disabled\n");
1270 return;
1271 }
1272 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
1273 vfp_get_fpcr(env), vfp_get_fpsr(env));
1274
1275 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
1276 sve = sme_exception_el(env, el) == 0;
1277 } else if (cpu_isar_feature(aa64_sve, cpu)) {
1278 sve = sve_exception_el(env, el) == 0;
1279 } else {
1280 sve = false;
1281 }
1282
1283 if (sve) {
1284 int zcr_len = sve_vqm1_for_el(env, el);
1285
1286 for (i = 0; i <= FFR_PRED_NUM; i++) {
1287 bool eol;
1288 if (i == FFR_PRED_NUM) {
1289 qemu_fprintf(f, "FFR=");
1290 /* It's last, so end the line. */
1291 eol = true;
1292 } else {
1293 qemu_fprintf(f, "P%02d=", i);
1294 switch (zcr_len) {
1295 case 0:
1296 eol = i % 8 == 7;
1297 break;
1298 case 1:
1299 eol = i % 6 == 5;
1300 break;
1301 case 2:
1302 case 3:
1303 eol = i % 3 == 2;
1304 break;
1305 default:
1306 /* More than one quadword per predicate. */
1307 eol = true;
1308 break;
1309 }
1310 }
1311 for (j = zcr_len / 4; j >= 0; j--) {
1312 int digits;
1313 if (j * 4 + 4 <= zcr_len + 1) {
1314 digits = 16;
1315 } else {
1316 digits = (zcr_len % 4 + 1) * 4;
1317 }
1318 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
1319 env->vfp.pregs[i].p[j],
1320 j ? ":" : eol ? "\n" : " ");
1321 }
1322 }
1323
1324 if (zcr_len == 0) {
1325 /*
1326 * With vl=16, there are only 37 columns per register,
1327 * so output two registers per line.
1328 */
1329 for (i = 0; i < 32; i++) {
1330 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1331 i, env->vfp.zregs[i].d[1],
1332 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
1333 }
1334 } else {
1335 for (i = 0; i < 32; i++) {
1336 qemu_fprintf(f, "Z%02d=", i);
1337 for (j = zcr_len; j >= 0; j--) {
1338 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
1339 env->vfp.zregs[i].d[j * 2 + 1],
1340 env->vfp.zregs[i].d[j * 2 + 0],
1341 j ? ":" : "\n");
1342 }
1343 }
1344 }
1345 } else {
1346 for (i = 0; i < 32; i++) {
1347 uint64_t *q = aa64_vfp_qreg(env, i);
1348 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1349 i, q[1], q[0], (i & 1 ? "\n" : " "));
1350 }
1351 }
1352
1353 if (cpu_isar_feature(aa64_sme, cpu) &&
1354 FIELD_EX64(env->svcr, SVCR, ZA) &&
1355 sme_exception_el(env, el) == 0) {
1356 int zcr_len = sve_vqm1_for_el_sm(env, el, true);
1357 int svl = (zcr_len + 1) * 16;
1358 int svl_lg10 = svl < 100 ? 2 : 3;
1359
1360 for (i = 0; i < svl; i++) {
1361 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
1362 for (j = zcr_len; j >= 0; --j) {
1363 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
1364 env->zarray[i].d[2 * j + 1],
1365 env->zarray[i].d[2 * j],
1366 j ? ':' : '\n');
1367 }
1368 }
1369 }
1370 }
1371
1372 #else
1373
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1374 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1375 {
1376 g_assert_not_reached();
1377 }
1378
1379 #endif
1380
arm_cpu_dump_state(CPUState * cs,FILE * f,int flags)1381 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1382 {
1383 ARMCPU *cpu = ARM_CPU(cs);
1384 CPUARMState *env = &cpu->env;
1385 int i;
1386
1387 if (is_a64(env)) {
1388 aarch64_cpu_dump_state(cs, f, flags);
1389 return;
1390 }
1391
1392 for (i = 0; i < 16; i++) {
1393 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
1394 if ((i % 4) == 3) {
1395 qemu_fprintf(f, "\n");
1396 } else {
1397 qemu_fprintf(f, " ");
1398 }
1399 }
1400
1401 if (arm_feature(env, ARM_FEATURE_M)) {
1402 uint32_t xpsr = xpsr_read(env);
1403 const char *mode;
1404 const char *ns_status = "";
1405
1406 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1407 ns_status = env->v7m.secure ? "S " : "NS ";
1408 }
1409
1410 if (xpsr & XPSR_EXCP) {
1411 mode = "handler";
1412 } else {
1413 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
1414 mode = "unpriv-thread";
1415 } else {
1416 mode = "priv-thread";
1417 }
1418 }
1419
1420 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
1421 xpsr,
1422 xpsr & XPSR_N ? 'N' : '-',
1423 xpsr & XPSR_Z ? 'Z' : '-',
1424 xpsr & XPSR_C ? 'C' : '-',
1425 xpsr & XPSR_V ? 'V' : '-',
1426 xpsr & XPSR_T ? 'T' : 'A',
1427 ns_status,
1428 mode);
1429 } else {
1430 uint32_t psr = cpsr_read(env);
1431 const char *ns_status = "";
1432
1433 if (arm_feature(env, ARM_FEATURE_EL3) &&
1434 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1435 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1436 }
1437
1438 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1439 psr,
1440 psr & CPSR_N ? 'N' : '-',
1441 psr & CPSR_Z ? 'Z' : '-',
1442 psr & CPSR_C ? 'C' : '-',
1443 psr & CPSR_V ? 'V' : '-',
1444 psr & CPSR_T ? 'T' : 'A',
1445 ns_status,
1446 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1447 }
1448
1449 if (flags & CPU_DUMP_FPU) {
1450 int numvfpregs = 0;
1451 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1452 numvfpregs = 32;
1453 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1454 numvfpregs = 16;
1455 }
1456 for (i = 0; i < numvfpregs; i++) {
1457 uint64_t v = *aa32_vfp_dreg(env, i);
1458 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1459 i * 2, (uint32_t)v,
1460 i * 2 + 1, (uint32_t)(v >> 32),
1461 i, v);
1462 }
1463 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1464 if (cpu_isar_feature(aa32_mve, cpu)) {
1465 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1466 }
1467 }
1468 }
1469
arm_build_mp_affinity(int idx,uint8_t clustersz)1470 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
1471 {
1472 uint32_t Aff1 = idx / clustersz;
1473 uint32_t Aff0 = idx % clustersz;
1474 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1475 }
1476
arm_cpu_mp_affinity(ARMCPU * cpu)1477 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
1478 {
1479 return cpu->mp_affinity;
1480 }
1481
arm_cpu_initfn(Object * obj)1482 static void arm_cpu_initfn(Object *obj)
1483 {
1484 ARMCPU *cpu = ARM_CPU(obj);
1485
1486 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
1487 NULL, g_free);
1488
1489 QLIST_INIT(&cpu->pre_el_change_hooks);
1490 QLIST_INIT(&cpu->el_change_hooks);
1491
1492 #ifdef CONFIG_USER_ONLY
1493 # ifdef TARGET_AARCH64
1494 /*
1495 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1496 * These values were chosen to fit within the default signal frame.
1497 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1498 * and our corresponding cpu property.
1499 */
1500 cpu->sve_default_vq = 4;
1501 cpu->sme_default_vq = 2;
1502 # endif
1503 #else
1504 /* Our inbound IRQ and FIQ lines */
1505 if (kvm_enabled()) {
1506 /*
1507 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add
1508 * them to maintain the same interface as non-KVM CPUs.
1509 */
1510 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6);
1511 } else {
1512 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6);
1513 }
1514
1515 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1516 ARRAY_SIZE(cpu->gt_timer_outputs));
1517
1518 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1519 "gicv3-maintenance-interrupt", 1);
1520 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1521 "pmu-interrupt", 1);
1522 #endif
1523
1524 /* DTB consumers generally don't in fact care what the 'compatible'
1525 * string is, so always provide some string and trust that a hypothetical
1526 * picky DTB consumer will also provide a helpful error message.
1527 */
1528 cpu->dtb_compatible = "qemu,unknown";
1529 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
1530 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1531
1532 if (tcg_enabled() || hvf_enabled()) {
1533 /* TCG and HVF implement PSCI 1.1 */
1534 cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1535 }
1536 }
1537
1538 /*
1539 * 0 means "unset, use the default value". That default might vary depending
1540 * on the CPU type, and is set in the realize fn.
1541 */
1542 static Property arm_cpu_gt_cntfrq_property =
1543 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
1544
1545 static Property arm_cpu_reset_cbar_property =
1546 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1547
1548 static Property arm_cpu_reset_hivecs_property =
1549 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1550
1551 #ifndef CONFIG_USER_ONLY
1552 static Property arm_cpu_has_el2_property =
1553 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1554
1555 static Property arm_cpu_has_el3_property =
1556 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1557 #endif
1558
1559 static Property arm_cpu_cfgend_property =
1560 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1561
1562 static Property arm_cpu_has_vfp_property =
1563 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1564
1565 static Property arm_cpu_has_vfp_d32_property =
1566 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1567
1568 static Property arm_cpu_has_neon_property =
1569 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1570
1571 static Property arm_cpu_has_dsp_property =
1572 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1573
1574 static Property arm_cpu_has_mpu_property =
1575 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1576
1577 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1578 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1579 * the right value for that particular CPU type, and we don't want
1580 * to override that with an incorrect constant value.
1581 */
1582 static Property arm_cpu_pmsav7_dregion_property =
1583 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1584 pmsav7_dregion,
1585 qdev_prop_uint32, uint32_t);
1586
arm_get_pmu(Object * obj,Error ** errp)1587 static bool arm_get_pmu(Object *obj, Error **errp)
1588 {
1589 ARMCPU *cpu = ARM_CPU(obj);
1590
1591 return cpu->has_pmu;
1592 }
1593
arm_set_pmu(Object * obj,bool value,Error ** errp)1594 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1595 {
1596 ARMCPU *cpu = ARM_CPU(obj);
1597
1598 if (value) {
1599 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1600 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1601 return;
1602 }
1603 set_feature(&cpu->env, ARM_FEATURE_PMU);
1604 } else {
1605 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1606 }
1607 cpu->has_pmu = value;
1608 }
1609
gt_cntfrq_period_ns(ARMCPU * cpu)1610 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1611 {
1612 /*
1613 * The exact approach to calculating guest ticks is:
1614 *
1615 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1616 * NANOSECONDS_PER_SECOND);
1617 *
1618 * We don't do that. Rather we intentionally use integer division
1619 * truncation below and in the caller for the conversion of host monotonic
1620 * time to guest ticks to provide the exact inverse for the semantics of
1621 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1622 * it loses precision when representing frequencies where
1623 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1624 * provide an exact inverse leads to scheduling timers with negative
1625 * periods, which in turn leads to sticky behaviour in the guest.
1626 *
1627 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1628 * cannot become zero.
1629 */
1630 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1631 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1632 }
1633
arm_cpu_propagate_feature_implications(ARMCPU * cpu)1634 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
1635 {
1636 CPUARMState *env = &cpu->env;
1637 bool no_aa32 = false;
1638
1639 /*
1640 * Some features automatically imply others: set the feature
1641 * bits explicitly for these cases.
1642 */
1643
1644 if (arm_feature(env, ARM_FEATURE_M)) {
1645 set_feature(env, ARM_FEATURE_PMSA);
1646 }
1647
1648 if (arm_feature(env, ARM_FEATURE_V8)) {
1649 if (arm_feature(env, ARM_FEATURE_M)) {
1650 set_feature(env, ARM_FEATURE_V7);
1651 } else {
1652 set_feature(env, ARM_FEATURE_V7VE);
1653 }
1654 }
1655
1656 /*
1657 * There exist AArch64 cpus without AArch32 support. When KVM
1658 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1659 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1660 * As a general principle, we also do not make ID register
1661 * consistency checks anywhere unless using TCG, because only
1662 * for TCG would a consistency-check failure be a QEMU bug.
1663 */
1664 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1665 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1666 }
1667
1668 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1669 /*
1670 * v7 Virtualization Extensions. In real hardware this implies
1671 * EL2 and also the presence of the Security Extensions.
1672 * For QEMU, for backwards-compatibility we implement some
1673 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1674 * include the various other features that V7VE implies.
1675 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1676 * Security Extensions is ARM_FEATURE_EL3.
1677 */
1678 assert(!tcg_enabled() || no_aa32 ||
1679 cpu_isar_feature(aa32_arm_div, cpu));
1680 set_feature(env, ARM_FEATURE_LPAE);
1681 set_feature(env, ARM_FEATURE_V7);
1682 }
1683 if (arm_feature(env, ARM_FEATURE_V7)) {
1684 set_feature(env, ARM_FEATURE_VAPA);
1685 set_feature(env, ARM_FEATURE_THUMB2);
1686 set_feature(env, ARM_FEATURE_MPIDR);
1687 if (!arm_feature(env, ARM_FEATURE_M)) {
1688 set_feature(env, ARM_FEATURE_V6K);
1689 } else {
1690 set_feature(env, ARM_FEATURE_V6);
1691 }
1692
1693 /*
1694 * Always define VBAR for V7 CPUs even if it doesn't exist in
1695 * non-EL3 configs. This is needed by some legacy boards.
1696 */
1697 set_feature(env, ARM_FEATURE_VBAR);
1698 }
1699 if (arm_feature(env, ARM_FEATURE_V6K)) {
1700 set_feature(env, ARM_FEATURE_V6);
1701 set_feature(env, ARM_FEATURE_MVFR);
1702 }
1703 if (arm_feature(env, ARM_FEATURE_V6)) {
1704 set_feature(env, ARM_FEATURE_V5);
1705 if (!arm_feature(env, ARM_FEATURE_M)) {
1706 assert(!tcg_enabled() || no_aa32 ||
1707 cpu_isar_feature(aa32_jazelle, cpu));
1708 set_feature(env, ARM_FEATURE_AUXCR);
1709 }
1710 }
1711 if (arm_feature(env, ARM_FEATURE_V5)) {
1712 set_feature(env, ARM_FEATURE_V4T);
1713 }
1714 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1715 set_feature(env, ARM_FEATURE_V7MP);
1716 }
1717 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1718 set_feature(env, ARM_FEATURE_CBAR);
1719 }
1720 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1721 !arm_feature(env, ARM_FEATURE_M)) {
1722 set_feature(env, ARM_FEATURE_THUMB_DSP);
1723 }
1724 }
1725
arm_cpu_post_init(Object * obj)1726 void arm_cpu_post_init(Object *obj)
1727 {
1728 ARMCPU *cpu = ARM_CPU(obj);
1729
1730 /*
1731 * Some features imply others. Figure this out now, because we
1732 * are going to look at the feature bits in deciding which
1733 * properties to add.
1734 */
1735 arm_cpu_propagate_feature_implications(cpu);
1736
1737 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1738 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1739 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1740 }
1741
1742 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1743 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1744 }
1745
1746 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1747 object_property_add_uint64_ptr(obj, "rvbar",
1748 &cpu->rvbar_prop,
1749 OBJ_PROP_FLAG_READWRITE);
1750 }
1751
1752 #ifndef CONFIG_USER_ONLY
1753 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1754 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1755 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1756 */
1757 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1758
1759 object_property_add_link(obj, "secure-memory",
1760 TYPE_MEMORY_REGION,
1761 (Object **)&cpu->secure_memory,
1762 qdev_prop_allow_set_link_before_realize,
1763 OBJ_PROP_LINK_STRONG);
1764 }
1765
1766 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1767 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1768 }
1769 #endif
1770
1771 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1772 cpu->has_pmu = true;
1773 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1774 }
1775
1776 /*
1777 * Allow user to turn off VFP and Neon support, but only for TCG --
1778 * KVM does not currently allow us to lie to the guest about its
1779 * ID/feature registers, so the guest always sees what the host has.
1780 */
1781 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1782 if (cpu_isar_feature(aa64_fp_simd, cpu)) {
1783 cpu->has_vfp = true;
1784 cpu->has_vfp_d32 = true;
1785 if (tcg_enabled() || qtest_enabled()) {
1786 qdev_property_add_static(DEVICE(obj),
1787 &arm_cpu_has_vfp_property);
1788 }
1789 }
1790 } else if (cpu_isar_feature(aa32_vfp, cpu)) {
1791 cpu->has_vfp = true;
1792 if (tcg_enabled() || qtest_enabled()) {
1793 qdev_property_add_static(DEVICE(obj),
1794 &arm_cpu_has_vfp_property);
1795 }
1796 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1797 cpu->has_vfp_d32 = true;
1798 /*
1799 * The permitted values of the SIMDReg bits [3:0] on
1800 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1801 * make sure that has_vfp_d32 can not be set to false.
1802 */
1803 if ((tcg_enabled() || qtest_enabled())
1804 && !(arm_feature(&cpu->env, ARM_FEATURE_V8)
1805 && !arm_feature(&cpu->env, ARM_FEATURE_M))) {
1806 qdev_property_add_static(DEVICE(obj),
1807 &arm_cpu_has_vfp_d32_property);
1808 }
1809 }
1810 }
1811
1812 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1813 cpu->has_neon = true;
1814 if (!kvm_enabled()) {
1815 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1816 }
1817 }
1818
1819 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1820 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1821 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1822 }
1823
1824 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1825 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1826 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1827 qdev_property_add_static(DEVICE(obj),
1828 &arm_cpu_pmsav7_dregion_property);
1829 }
1830 }
1831
1832 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1833 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1834 qdev_prop_allow_set_link_before_realize,
1835 OBJ_PROP_LINK_STRONG);
1836 /*
1837 * M profile: initial value of the Secure VTOR. We can't just use
1838 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1839 * the property to be set after realize.
1840 */
1841 object_property_add_uint32_ptr(obj, "init-svtor",
1842 &cpu->init_svtor,
1843 OBJ_PROP_FLAG_READWRITE);
1844 }
1845 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1846 /*
1847 * Initial value of the NS VTOR (for cores without the Security
1848 * extension, this is the only VTOR)
1849 */
1850 object_property_add_uint32_ptr(obj, "init-nsvtor",
1851 &cpu->init_nsvtor,
1852 OBJ_PROP_FLAG_READWRITE);
1853 }
1854
1855 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1856 object_property_add_uint32_ptr(obj, "psci-conduit",
1857 &cpu->psci_conduit,
1858 OBJ_PROP_FLAG_READWRITE);
1859
1860 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1861
1862 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1863 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1864 }
1865
1866 if (kvm_enabled()) {
1867 kvm_arm_add_vcpu_properties(cpu);
1868 }
1869
1870 #ifndef CONFIG_USER_ONLY
1871 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1872 cpu_isar_feature(aa64_mte, cpu)) {
1873 object_property_add_link(obj, "tag-memory",
1874 TYPE_MEMORY_REGION,
1875 (Object **)&cpu->tag_memory,
1876 qdev_prop_allow_set_link_before_realize,
1877 OBJ_PROP_LINK_STRONG);
1878
1879 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1880 object_property_add_link(obj, "secure-tag-memory",
1881 TYPE_MEMORY_REGION,
1882 (Object **)&cpu->secure_tag_memory,
1883 qdev_prop_allow_set_link_before_realize,
1884 OBJ_PROP_LINK_STRONG);
1885 }
1886 }
1887 #endif
1888 }
1889
arm_cpu_finalizefn(Object * obj)1890 static void arm_cpu_finalizefn(Object *obj)
1891 {
1892 ARMCPU *cpu = ARM_CPU(obj);
1893 ARMELChangeHook *hook, *next;
1894
1895 g_hash_table_destroy(cpu->cp_regs);
1896
1897 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1898 QLIST_REMOVE(hook, node);
1899 g_free(hook);
1900 }
1901 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1902 QLIST_REMOVE(hook, node);
1903 g_free(hook);
1904 }
1905 #ifndef CONFIG_USER_ONLY
1906 if (cpu->pmu_timer) {
1907 timer_free(cpu->pmu_timer);
1908 }
1909 if (cpu->wfxt_timer) {
1910 timer_free(cpu->wfxt_timer);
1911 }
1912 #endif
1913 }
1914
arm_cpu_finalize_features(ARMCPU * cpu,Error ** errp)1915 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1916 {
1917 Error *local_err = NULL;
1918
1919 #ifdef TARGET_AARCH64
1920 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1921 arm_cpu_sve_finalize(cpu, &local_err);
1922 if (local_err != NULL) {
1923 error_propagate(errp, local_err);
1924 return;
1925 }
1926
1927 /*
1928 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1929 * FEAT_SME_FA64 is present). However our implementation currently
1930 * assumes it, so if the user asked for sve=off then turn off SME also.
1931 * (KVM doesn't currently support SME at all.)
1932 */
1933 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) {
1934 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort);
1935 }
1936
1937 arm_cpu_sme_finalize(cpu, &local_err);
1938 if (local_err != NULL) {
1939 error_propagate(errp, local_err);
1940 return;
1941 }
1942
1943 arm_cpu_pauth_finalize(cpu, &local_err);
1944 if (local_err != NULL) {
1945 error_propagate(errp, local_err);
1946 return;
1947 }
1948
1949 arm_cpu_lpa2_finalize(cpu, &local_err);
1950 if (local_err != NULL) {
1951 error_propagate(errp, local_err);
1952 return;
1953 }
1954 }
1955 #endif
1956
1957 if (kvm_enabled()) {
1958 kvm_arm_steal_time_finalize(cpu, &local_err);
1959 if (local_err != NULL) {
1960 error_propagate(errp, local_err);
1961 return;
1962 }
1963 }
1964 }
1965
arm_cpu_realizefn(DeviceState * dev,Error ** errp)1966 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1967 {
1968 CPUState *cs = CPU(dev);
1969 ARMCPU *cpu = ARM_CPU(dev);
1970 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1971 CPUARMState *env = &cpu->env;
1972 Error *local_err = NULL;
1973
1974 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1975 /* Use pc-relative instructions in system-mode */
1976 tcg_cflags_set(cs, CF_PCREL);
1977 #endif
1978
1979 /* If we needed to query the host kernel for the CPU features
1980 * then it's possible that might have failed in the initfn, but
1981 * this is the first point where we can report it.
1982 */
1983 if (cpu->host_cpu_probe_failed) {
1984 if (!kvm_enabled() && !hvf_enabled()) {
1985 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
1986 } else {
1987 error_setg(errp, "Failed to retrieve host CPU features");
1988 }
1989 return;
1990 }
1991
1992 if (!cpu->gt_cntfrq_hz) {
1993 /*
1994 * 0 means "the board didn't set a value, use the default". (We also
1995 * get here for the CONFIG_USER_ONLY case.)
1996 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
1997 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
1998 * which gives a 16ns tick period.
1999 *
2000 * We will use the back-compat value:
2001 * - for QEMU CPU types added before we standardized on 1GHz
2002 * - for versioned machine types with a version of 9.0 or earlier
2003 */
2004 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
2005 cpu->backcompat_cntfrq) {
2006 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
2007 } else {
2008 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
2009 }
2010 }
2011
2012 #ifndef CONFIG_USER_ONLY
2013 /* The NVIC and M-profile CPU are two halves of a single piece of
2014 * hardware; trying to use one without the other is a command line
2015 * error and will result in segfaults if not caught here.
2016 */
2017 if (arm_feature(env, ARM_FEATURE_M)) {
2018 if (!env->nvic) {
2019 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
2020 return;
2021 }
2022 } else {
2023 if (env->nvic) {
2024 error_setg(errp, "This board can only be used with Cortex-M CPUs");
2025 return;
2026 }
2027 }
2028
2029 if (!tcg_enabled() && !qtest_enabled()) {
2030 /*
2031 * We assume that no accelerator except TCG (and the "not really an
2032 * accelerator" qtest) can handle these features, because Arm hardware
2033 * virtualization can't virtualize them.
2034 *
2035 * Catch all the cases which might cause us to create more than one
2036 * address space for the CPU (otherwise we will assert() later in
2037 * cpu_address_space_init()).
2038 */
2039 if (arm_feature(env, ARM_FEATURE_M)) {
2040 error_setg(errp,
2041 "Cannot enable %s when using an M-profile guest CPU",
2042 current_accel_name());
2043 return;
2044 }
2045 if (cpu->has_el3) {
2046 error_setg(errp,
2047 "Cannot enable %s when guest CPU has EL3 enabled",
2048 current_accel_name());
2049 return;
2050 }
2051 if (cpu->tag_memory) {
2052 error_setg(errp,
2053 "Cannot enable %s when guest CPUs has MTE enabled",
2054 current_accel_name());
2055 return;
2056 }
2057 }
2058
2059 {
2060 uint64_t scale = gt_cntfrq_period_ns(cpu);
2061
2062 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2063 arm_gt_ptimer_cb, cpu);
2064 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2065 arm_gt_vtimer_cb, cpu);
2066 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2067 arm_gt_htimer_cb, cpu);
2068 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2069 arm_gt_stimer_cb, cpu);
2070 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2071 arm_gt_hvtimer_cb, cpu);
2072 }
2073 #endif
2074
2075 cpu_exec_realizefn(cs, &local_err);
2076 if (local_err != NULL) {
2077 error_propagate(errp, local_err);
2078 return;
2079 }
2080
2081 arm_cpu_finalize_features(cpu, &local_err);
2082 if (local_err != NULL) {
2083 error_propagate(errp, local_err);
2084 return;
2085 }
2086
2087 #ifdef CONFIG_USER_ONLY
2088 /*
2089 * User mode relies on IC IVAU instructions to catch modification of
2090 * dual-mapped code.
2091 *
2092 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
2093 * IC IVAU even if the emulated processor does not normally require it.
2094 */
2095 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
2096 #endif
2097
2098 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
2099 cpu->has_vfp != cpu->has_neon) {
2100 /*
2101 * This is an architectural requirement for AArch64; AArch32 is
2102 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
2103 */
2104 error_setg(errp,
2105 "AArch64 CPUs must have both VFP and Neon or neither");
2106 return;
2107 }
2108
2109 if (cpu->has_vfp_d32 != cpu->has_neon) {
2110 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
2111 return;
2112 }
2113
2114 if (!cpu->has_vfp_d32) {
2115 uint32_t u;
2116
2117 u = cpu->isar.mvfr0;
2118 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
2119 cpu->isar.mvfr0 = u;
2120 }
2121
2122 if (!cpu->has_vfp) {
2123 uint64_t t;
2124 uint32_t u;
2125
2126 t = cpu->isar.id_aa64isar1;
2127 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
2128 cpu->isar.id_aa64isar1 = t;
2129
2130 t = cpu->isar.id_aa64pfr0;
2131 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
2132 cpu->isar.id_aa64pfr0 = t;
2133
2134 u = cpu->isar.id_isar6;
2135 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
2136 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2137 cpu->isar.id_isar6 = u;
2138
2139 u = cpu->isar.mvfr0;
2140 u = FIELD_DP32(u, MVFR0, FPSP, 0);
2141 u = FIELD_DP32(u, MVFR0, FPDP, 0);
2142 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
2143 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
2144 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
2145 if (!arm_feature(env, ARM_FEATURE_M)) {
2146 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
2147 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
2148 }
2149 cpu->isar.mvfr0 = u;
2150
2151 u = cpu->isar.mvfr1;
2152 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
2153 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
2154 u = FIELD_DP32(u, MVFR1, FPHP, 0);
2155 if (arm_feature(env, ARM_FEATURE_M)) {
2156 u = FIELD_DP32(u, MVFR1, FP16, 0);
2157 }
2158 cpu->isar.mvfr1 = u;
2159
2160 u = cpu->isar.mvfr2;
2161 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
2162 cpu->isar.mvfr2 = u;
2163 }
2164
2165 if (!cpu->has_neon) {
2166 uint64_t t;
2167 uint32_t u;
2168
2169 unset_feature(env, ARM_FEATURE_NEON);
2170
2171 t = cpu->isar.id_aa64isar0;
2172 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
2173 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
2174 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
2175 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
2176 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
2177 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
2178 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
2179 cpu->isar.id_aa64isar0 = t;
2180
2181 t = cpu->isar.id_aa64isar1;
2182 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
2183 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
2184 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
2185 cpu->isar.id_aa64isar1 = t;
2186
2187 t = cpu->isar.id_aa64pfr0;
2188 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
2189 cpu->isar.id_aa64pfr0 = t;
2190
2191 u = cpu->isar.id_isar5;
2192 u = FIELD_DP32(u, ID_ISAR5, AES, 0);
2193 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
2194 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
2195 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
2196 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
2197 cpu->isar.id_isar5 = u;
2198
2199 u = cpu->isar.id_isar6;
2200 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
2201 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
2202 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2203 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
2204 cpu->isar.id_isar6 = u;
2205
2206 if (!arm_feature(env, ARM_FEATURE_M)) {
2207 u = cpu->isar.mvfr1;
2208 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
2209 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
2210 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
2211 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
2212 cpu->isar.mvfr1 = u;
2213
2214 u = cpu->isar.mvfr2;
2215 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
2216 cpu->isar.mvfr2 = u;
2217 }
2218 }
2219
2220 if (!cpu->has_neon && !cpu->has_vfp) {
2221 uint64_t t;
2222 uint32_t u;
2223
2224 t = cpu->isar.id_aa64isar0;
2225 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
2226 cpu->isar.id_aa64isar0 = t;
2227
2228 t = cpu->isar.id_aa64isar1;
2229 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
2230 cpu->isar.id_aa64isar1 = t;
2231
2232 u = cpu->isar.mvfr0;
2233 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
2234 cpu->isar.mvfr0 = u;
2235
2236 /* Despite the name, this field covers both VFP and Neon */
2237 u = cpu->isar.mvfr1;
2238 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
2239 cpu->isar.mvfr1 = u;
2240 }
2241
2242 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
2243 uint32_t u;
2244
2245 unset_feature(env, ARM_FEATURE_THUMB_DSP);
2246
2247 u = cpu->isar.id_isar1;
2248 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
2249 cpu->isar.id_isar1 = u;
2250
2251 u = cpu->isar.id_isar2;
2252 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
2253 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
2254 cpu->isar.id_isar2 = u;
2255
2256 u = cpu->isar.id_isar3;
2257 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
2258 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
2259 cpu->isar.id_isar3 = u;
2260 }
2261
2262
2263 /*
2264 * We rely on no XScale CPU having VFP so we can use the same bits in the
2265 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2266 */
2267 assert(arm_feature(env, ARM_FEATURE_AARCH64) ||
2268 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
2269 !arm_feature(env, ARM_FEATURE_XSCALE));
2270
2271 #ifndef CONFIG_USER_ONLY
2272 {
2273 int pagebits;
2274 if (arm_feature(env, ARM_FEATURE_V7) &&
2275 !arm_feature(env, ARM_FEATURE_M) &&
2276 !arm_feature(env, ARM_FEATURE_PMSA)) {
2277 /*
2278 * v7VMSA drops support for the old ARMv5 tiny pages,
2279 * so we can use 4K pages.
2280 */
2281 pagebits = 12;
2282 } else {
2283 /*
2284 * For CPUs which might have tiny 1K pages, or which have an
2285 * MPU and might have small region sizes, stick with 1K pages.
2286 */
2287 pagebits = 10;
2288 }
2289 if (!set_preferred_target_page_bits(pagebits)) {
2290 /*
2291 * This can only ever happen for hotplugging a CPU, or if
2292 * the board code incorrectly creates a CPU which it has
2293 * promised via minimum_page_size that it will not.
2294 */
2295 error_setg(errp, "This CPU requires a smaller page size "
2296 "than the system is using");
2297 return;
2298 }
2299 }
2300 #endif
2301
2302 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2303 * We don't support setting cluster ID ([16..23]) (known as Aff2
2304 * in later ARM ARM versions), or any of the higher affinity level fields,
2305 * so these bits always RAZ.
2306 */
2307 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
2308 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
2309 ARM_DEFAULT_CPUS_PER_CLUSTER);
2310 }
2311
2312 if (cpu->reset_hivecs) {
2313 cpu->reset_sctlr |= (1 << 13);
2314 }
2315
2316 if (cpu->cfgend) {
2317 if (arm_feature(env, ARM_FEATURE_V7)) {
2318 cpu->reset_sctlr |= SCTLR_EE;
2319 } else {
2320 cpu->reset_sctlr |= SCTLR_B;
2321 }
2322 }
2323
2324 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
2325 /* If the has_el3 CPU property is disabled then we need to disable the
2326 * feature.
2327 */
2328 unset_feature(env, ARM_FEATURE_EL3);
2329
2330 /*
2331 * Disable the security extension feature bits in the processor
2332 * feature registers as well.
2333 */
2334 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
2335 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
2336 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2337 ID_AA64PFR0, EL3, 0);
2338
2339 /* Disable the realm management extension, which requires EL3. */
2340 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2341 ID_AA64PFR0, RME, 0);
2342 }
2343
2344 if (!cpu->has_el2) {
2345 unset_feature(env, ARM_FEATURE_EL2);
2346 }
2347
2348 if (!cpu->has_pmu) {
2349 unset_feature(env, ARM_FEATURE_PMU);
2350 }
2351 if (arm_feature(env, ARM_FEATURE_PMU)) {
2352 pmu_init(cpu);
2353
2354 if (!kvm_enabled()) {
2355 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
2356 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
2357 }
2358
2359 #ifndef CONFIG_USER_ONLY
2360 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
2361 cpu);
2362 #endif
2363 } else {
2364 cpu->isar.id_aa64dfr0 =
2365 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
2366 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
2367 cpu->pmceid0 = 0;
2368 cpu->pmceid1 = 0;
2369 }
2370
2371 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2372 /*
2373 * Disable the hypervisor feature bits in the processor feature
2374 * registers if we don't have EL2.
2375 */
2376 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2377 ID_AA64PFR0, EL2, 0);
2378 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
2379 ID_PFR1, VIRTUALIZATION, 0);
2380 }
2381
2382 if (cpu_isar_feature(aa64_mte, cpu)) {
2383 /*
2384 * The architectural range of GM blocksize is 2-6, however qemu
2385 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2386 */
2387 if (tcg_enabled()) {
2388 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
2389 }
2390
2391 #ifndef CONFIG_USER_ONLY
2392 /*
2393 * If we do not have tag-memory provided by the machine,
2394 * reduce MTE support to instructions enabled at EL0.
2395 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2396 */
2397 if (cpu->tag_memory == NULL) {
2398 cpu->isar.id_aa64pfr1 =
2399 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
2400 }
2401 #endif
2402 }
2403
2404 #ifndef CONFIG_USER_ONLY
2405 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) {
2406 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2407 arm_wfxt_timer_cb, cpu);
2408 }
2409 #endif
2410
2411 if (tcg_enabled()) {
2412 /*
2413 * Don't report some architectural features in the ID registers
2414 * where TCG does not yet implement it (not even a minimal
2415 * stub version). This avoids guests falling over when they
2416 * try to access the non-existent system registers for them.
2417 */
2418 /* FEAT_SPE (Statistical Profiling Extension) */
2419 cpu->isar.id_aa64dfr0 =
2420 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
2421 /* FEAT_TRBE (Trace Buffer Extension) */
2422 cpu->isar.id_aa64dfr0 =
2423 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
2424 /* FEAT_TRF (Self-hosted Trace Extension) */
2425 cpu->isar.id_aa64dfr0 =
2426 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
2427 cpu->isar.id_dfr0 =
2428 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
2429 /* Trace Macrocell system register access */
2430 cpu->isar.id_aa64dfr0 =
2431 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
2432 cpu->isar.id_dfr0 =
2433 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
2434 /* Memory mapped trace */
2435 cpu->isar.id_dfr0 =
2436 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
2437 /* FEAT_AMU (Activity Monitors Extension) */
2438 cpu->isar.id_aa64pfr0 =
2439 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
2440 cpu->isar.id_pfr0 =
2441 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
2442 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2443 cpu->isar.id_aa64pfr0 =
2444 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
2445 }
2446
2447 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2448 * to false or by setting pmsav7-dregion to 0.
2449 */
2450 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
2451 cpu->has_mpu = false;
2452 cpu->pmsav7_dregion = 0;
2453 cpu->pmsav8r_hdregion = 0;
2454 }
2455
2456 if (arm_feature(env, ARM_FEATURE_PMSA) &&
2457 arm_feature(env, ARM_FEATURE_V7)) {
2458 uint32_t nr = cpu->pmsav7_dregion;
2459
2460 if (nr > 0xff) {
2461 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2462 return;
2463 }
2464
2465 if (nr) {
2466 if (arm_feature(env, ARM_FEATURE_V8)) {
2467 /* PMSAv8 */
2468 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
2469 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
2470 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2471 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
2472 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2473 }
2474 } else {
2475 env->pmsav7.drbar = g_new0(uint32_t, nr);
2476 env->pmsav7.drsr = g_new0(uint32_t, nr);
2477 env->pmsav7.dracr = g_new0(uint32_t, nr);
2478 }
2479 }
2480
2481 if (cpu->pmsav8r_hdregion > 0xff) {
2482 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
2483 cpu->pmsav8r_hdregion);
2484 return;
2485 }
2486
2487 if (cpu->pmsav8r_hdregion) {
2488 env->pmsav8.hprbar = g_new0(uint32_t,
2489 cpu->pmsav8r_hdregion);
2490 env->pmsav8.hprlar = g_new0(uint32_t,
2491 cpu->pmsav8r_hdregion);
2492 }
2493 }
2494
2495 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2496 uint32_t nr = cpu->sau_sregion;
2497
2498 if (nr > 0xff) {
2499 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2500 return;
2501 }
2502
2503 if (nr) {
2504 env->sau.rbar = g_new0(uint32_t, nr);
2505 env->sau.rlar = g_new0(uint32_t, nr);
2506 }
2507 }
2508
2509 if (arm_feature(env, ARM_FEATURE_EL3)) {
2510 set_feature(env, ARM_FEATURE_VBAR);
2511 }
2512
2513 #ifndef CONFIG_USER_ONLY
2514 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) {
2515 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0);
2516 }
2517 #endif
2518
2519 register_cp_regs_for_features(cpu);
2520 arm_cpu_register_gdb_regs_for_features(cpu);
2521 arm_cpu_register_gdb_commands(cpu);
2522
2523 init_cpreg_list(cpu);
2524
2525 #ifndef CONFIG_USER_ONLY
2526 MachineState *ms = MACHINE(qdev_get_machine());
2527 unsigned int smp_cpus = ms->smp.cpus;
2528 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
2529
2530 /*
2531 * We must set cs->num_ases to the final value before
2532 * the first call to cpu_address_space_init.
2533 */
2534 if (cpu->tag_memory != NULL) {
2535 cs->num_ases = 3 + has_secure;
2536 } else {
2537 cs->num_ases = 1 + has_secure;
2538 }
2539
2540 if (has_secure) {
2541 if (!cpu->secure_memory) {
2542 cpu->secure_memory = cs->memory;
2543 }
2544 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
2545 cpu->secure_memory);
2546 }
2547
2548 if (cpu->tag_memory != NULL) {
2549 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
2550 cpu->tag_memory);
2551 if (has_secure) {
2552 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
2553 cpu->secure_tag_memory);
2554 }
2555 }
2556
2557 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
2558
2559 /* No core_count specified, default to smp_cpus. */
2560 if (cpu->core_count == -1) {
2561 cpu->core_count = smp_cpus;
2562 }
2563 #endif
2564
2565 if (tcg_enabled()) {
2566 int dcz_blocklen = 4 << cpu->dcz_blocksize;
2567
2568 /*
2569 * We only support DCZ blocklen that fits on one page.
2570 *
2571 * Architectually this is always true. However TARGET_PAGE_SIZE
2572 * is variable and, for compatibility with -machine virt-2.7,
2573 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2574 * But even then, while the largest architectural DCZ blocklen
2575 * is 2KiB, no cpu actually uses such a large blocklen.
2576 */
2577 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
2578
2579 /*
2580 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2581 * both nibbles of each byte storing tag data may be written at once.
2582 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2583 */
2584 if (cpu_isar_feature(aa64_mte, cpu)) {
2585 assert(dcz_blocklen >= 2 * TAG_GRANULE);
2586 }
2587 }
2588
2589 qemu_init_vcpu(cs);
2590 cpu_reset(cs);
2591
2592 acc->parent_realize(dev, errp);
2593 }
2594
arm_cpu_class_by_name(const char * cpu_model)2595 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
2596 {
2597 ObjectClass *oc;
2598 char *typename;
2599 char **cpuname;
2600 const char *cpunamestr;
2601
2602 cpuname = g_strsplit(cpu_model, ",", 1);
2603 cpunamestr = cpuname[0];
2604 #ifdef CONFIG_USER_ONLY
2605 /* For backwards compatibility usermode emulation allows "-cpu any",
2606 * which has the same semantics as "-cpu max".
2607 */
2608 if (!strcmp(cpunamestr, "any")) {
2609 cpunamestr = "max";
2610 }
2611 #endif
2612 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
2613 oc = object_class_by_name(typename);
2614 g_strfreev(cpuname);
2615 g_free(typename);
2616
2617 return oc;
2618 }
2619
2620 static Property arm_cpu_properties[] = {
2621 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2622 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2623 mp_affinity, ARM64_AFFINITY_INVALID),
2624 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2625 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2626 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
2627 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
2628 DEFINE_PROP_END_OF_LIST()
2629 };
2630
arm_gdb_arch_name(CPUState * cs)2631 static const gchar *arm_gdb_arch_name(CPUState *cs)
2632 {
2633 ARMCPU *cpu = ARM_CPU(cs);
2634 CPUARMState *env = &cpu->env;
2635
2636 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2637 return "iwmmxt";
2638 }
2639 return "arm";
2640 }
2641
2642 #ifndef CONFIG_USER_ONLY
2643 #include "hw/core/sysemu-cpu-ops.h"
2644
2645 static const struct SysemuCPUOps arm_sysemu_ops = {
2646 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
2647 .asidx_from_attrs = arm_asidx_from_attrs,
2648 .write_elf32_note = arm_cpu_write_elf32_note,
2649 .write_elf64_note = arm_cpu_write_elf64_note,
2650 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
2651 .legacy_vmsd = &vmstate_arm_cpu,
2652 };
2653 #endif
2654
2655 #ifdef CONFIG_TCG
2656 static const TCGCPUOps arm_tcg_ops = {
2657 .initialize = arm_translate_init,
2658 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2659 .debug_excp_handler = arm_debug_excp_handler,
2660 .restore_state_to_opc = arm_restore_state_to_opc,
2661
2662 #ifdef CONFIG_USER_ONLY
2663 .record_sigsegv = arm_cpu_record_sigsegv,
2664 .record_sigbus = arm_cpu_record_sigbus,
2665 #else
2666 .tlb_fill = arm_cpu_tlb_fill,
2667 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2668 .cpu_exec_halt = arm_cpu_exec_halt,
2669 .do_interrupt = arm_cpu_do_interrupt,
2670 .do_transaction_failed = arm_cpu_do_transaction_failed,
2671 .do_unaligned_access = arm_cpu_do_unaligned_access,
2672 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2673 .debug_check_watchpoint = arm_debug_check_watchpoint,
2674 .debug_check_breakpoint = arm_debug_check_breakpoint,
2675 #endif /* !CONFIG_USER_ONLY */
2676 };
2677 #endif /* CONFIG_TCG */
2678
arm_cpu_class_init(ObjectClass * oc,void * data)2679 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2680 {
2681 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2682 CPUClass *cc = CPU_CLASS(acc);
2683 DeviceClass *dc = DEVICE_CLASS(oc);
2684 ResettableClass *rc = RESETTABLE_CLASS(oc);
2685
2686 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2687 &acc->parent_realize);
2688
2689 device_class_set_props(dc, arm_cpu_properties);
2690
2691 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
2692 &acc->parent_phases);
2693
2694 cc->class_by_name = arm_cpu_class_by_name;
2695 cc->has_work = arm_cpu_has_work;
2696 cc->mmu_index = arm_cpu_mmu_index;
2697 cc->dump_state = arm_cpu_dump_state;
2698 cc->set_pc = arm_cpu_set_pc;
2699 cc->get_pc = arm_cpu_get_pc;
2700 cc->gdb_read_register = arm_cpu_gdb_read_register;
2701 cc->gdb_write_register = arm_cpu_gdb_write_register;
2702 #ifndef CONFIG_USER_ONLY
2703 cc->sysemu_ops = &arm_sysemu_ops;
2704 #endif
2705 cc->gdb_arch_name = arm_gdb_arch_name;
2706 cc->gdb_stop_before_watchpoint = true;
2707 cc->disas_set_info = arm_disas_set_info;
2708
2709 #ifdef CONFIG_TCG
2710 cc->tcg_ops = &arm_tcg_ops;
2711 #endif /* CONFIG_TCG */
2712 }
2713
arm_cpu_instance_init(Object * obj)2714 static void arm_cpu_instance_init(Object *obj)
2715 {
2716 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2717
2718 acc->info->initfn(obj);
2719 arm_cpu_post_init(obj);
2720 }
2721
cpu_register_class_init(ObjectClass * oc,void * data)2722 static void cpu_register_class_init(ObjectClass *oc, void *data)
2723 {
2724 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2725 CPUClass *cc = CPU_CLASS(acc);
2726
2727 acc->info = data;
2728 cc->gdb_core_xml_file = "arm-core.xml";
2729 }
2730
arm_cpu_register(const ARMCPUInfo * info)2731 void arm_cpu_register(const ARMCPUInfo *info)
2732 {
2733 TypeInfo type_info = {
2734 .parent = TYPE_ARM_CPU,
2735 .instance_init = arm_cpu_instance_init,
2736 .class_init = info->class_init ?: cpu_register_class_init,
2737 .class_data = (void *)info,
2738 };
2739
2740 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2741 type_register(&type_info);
2742 g_free((void *)type_info.name);
2743 }
2744
2745 static const TypeInfo arm_cpu_type_info = {
2746 .name = TYPE_ARM_CPU,
2747 .parent = TYPE_CPU,
2748 .instance_size = sizeof(ARMCPU),
2749 .instance_align = __alignof__(ARMCPU),
2750 .instance_init = arm_cpu_initfn,
2751 .instance_finalize = arm_cpu_finalizefn,
2752 .abstract = true,
2753 .class_size = sizeof(ARMCPUClass),
2754 .class_init = arm_cpu_class_init,
2755 };
2756
arm_cpu_register_types(void)2757 static void arm_cpu_register_types(void)
2758 {
2759 type_register_static(&arm_cpu_type_info);
2760 }
2761
2762 type_init(arm_cpu_register_types)
2763