1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
24 #include "qemu/log.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
29 #include "cpu.h"
30 #ifdef CONFIG_TCG
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "cpu-features.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
40 #ifdef CONFIG_TCG
41 #include "hw/intc/armv7m_nvic.h"
42 #endif /* CONFIG_TCG */
43 #endif /* !CONFIG_USER_ONLY */
44 #include "sysemu/tcg.h"
45 #include "sysemu/qtest.h"
46 #include "sysemu/hw_accel.h"
47 #include "kvm_arm.h"
48 #include "disas/capstone.h"
49 #include "fpu/softfloat.h"
50 #include "cpregs.h"
51 #include "target/arm/cpu-qom.h"
52 #include "target/arm/gtimer.h"
53
arm_cpu_set_pc(CPUState * cs,vaddr value)54 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
55 {
56 ARMCPU *cpu = ARM_CPU(cs);
57 CPUARMState *env = &cpu->env;
58
59 if (is_a64(env)) {
60 env->pc = value;
61 env->thumb = false;
62 } else {
63 env->regs[15] = value & ~1;
64 env->thumb = value & 1;
65 }
66 }
67
arm_cpu_get_pc(CPUState * cs)68 static vaddr arm_cpu_get_pc(CPUState *cs)
69 {
70 ARMCPU *cpu = ARM_CPU(cs);
71 CPUARMState *env = &cpu->env;
72
73 if (is_a64(env)) {
74 return env->pc;
75 } else {
76 return env->regs[15];
77 }
78 }
79
80 #ifdef CONFIG_TCG
arm_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)81 void arm_cpu_synchronize_from_tb(CPUState *cs,
82 const TranslationBlock *tb)
83 {
84 /* The program counter is always up to date with CF_PCREL. */
85 if (!(tb_cflags(tb) & CF_PCREL)) {
86 CPUARMState *env = cpu_env(cs);
87 /*
88 * It's OK to look at env for the current mode here, because it's
89 * never possible for an AArch64 TB to chain to an AArch32 TB.
90 */
91 if (is_a64(env)) {
92 env->pc = tb->pc;
93 } else {
94 env->regs[15] = tb->pc;
95 }
96 }
97 }
98
arm_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)99 void arm_restore_state_to_opc(CPUState *cs,
100 const TranslationBlock *tb,
101 const uint64_t *data)
102 {
103 CPUARMState *env = cpu_env(cs);
104
105 if (is_a64(env)) {
106 if (tb_cflags(tb) & CF_PCREL) {
107 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
108 } else {
109 env->pc = data[0];
110 }
111 env->condexec_bits = 0;
112 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
113 } else {
114 if (tb_cflags(tb) & CF_PCREL) {
115 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
116 } else {
117 env->regs[15] = data[0];
118 }
119 env->condexec_bits = data[1];
120 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
121 }
122 }
123 #endif /* CONFIG_TCG */
124
125 /*
126 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with
127 * IRQ without Superpriority. Moreover, if the GIC is configured so that
128 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see
129 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
130 * unconditionally.
131 */
arm_cpu_has_work(CPUState * cs)132 static bool arm_cpu_has_work(CPUState *cs)
133 {
134 ARMCPU *cpu = ARM_CPU(cs);
135
136 return (cpu->power_state != PSCI_OFF)
137 && cs->interrupt_request &
138 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
139 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI
140 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
141 | CPU_INTERRUPT_EXITTB);
142 }
143
arm_cpu_mmu_index(CPUState * cs,bool ifetch)144 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
145 {
146 return arm_env_mmu_index(cpu_env(cs));
147 }
148
arm_register_pre_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)149 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
150 void *opaque)
151 {
152 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
153
154 entry->hook = hook;
155 entry->opaque = opaque;
156
157 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
158 }
159
arm_register_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)160 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
161 void *opaque)
162 {
163 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
164
165 entry->hook = hook;
166 entry->opaque = opaque;
167
168 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
169 }
170
cp_reg_reset(gpointer key,gpointer value,gpointer opaque)171 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
172 {
173 /* Reset a single ARMCPRegInfo register */
174 ARMCPRegInfo *ri = value;
175 ARMCPU *cpu = opaque;
176
177 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
178 return;
179 }
180
181 if (ri->resetfn) {
182 ri->resetfn(&cpu->env, ri);
183 return;
184 }
185
186 /* A zero offset is never possible as it would be regs[0]
187 * so we use it to indicate that reset is being handled elsewhere.
188 * This is basically only used for fields in non-core coprocessors
189 * (like the pxa2xx ones).
190 */
191 if (!ri->fieldoffset) {
192 return;
193 }
194
195 if (cpreg_field_is_64bit(ri)) {
196 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
197 } else {
198 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
199 }
200 }
201
cp_reg_check_reset(gpointer key,gpointer value,gpointer opaque)202 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
203 {
204 /* Purely an assertion check: we've already done reset once,
205 * so now check that running the reset for the cpreg doesn't
206 * change its value. This traps bugs where two different cpregs
207 * both try to reset the same state field but to different values.
208 */
209 ARMCPRegInfo *ri = value;
210 ARMCPU *cpu = opaque;
211 uint64_t oldvalue, newvalue;
212
213 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
214 return;
215 }
216
217 oldvalue = read_raw_cp_reg(&cpu->env, ri);
218 cp_reg_reset(key, value, opaque);
219 newvalue = read_raw_cp_reg(&cpu->env, ri);
220 assert(oldvalue == newvalue);
221 }
222
arm_cpu_reset_hold(Object * obj,ResetType type)223 static void arm_cpu_reset_hold(Object *obj, ResetType type)
224 {
225 CPUState *cs = CPU(obj);
226 ARMCPU *cpu = ARM_CPU(cs);
227 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
228 CPUARMState *env = &cpu->env;
229
230 if (acc->parent_phases.hold) {
231 acc->parent_phases.hold(obj, type);
232 }
233
234 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
235
236 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
237 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
238
239 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
240 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
241 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
242 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
243
244 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;
245
246 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
247 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
248 }
249
250 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
251 /* 64 bit CPUs always start in 64 bit mode */
252 env->aarch64 = true;
253 #if defined(CONFIG_USER_ONLY)
254 env->pstate = PSTATE_MODE_EL0t;
255 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
256 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
257 /* Enable all PAC keys. */
258 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
259 SCTLR_EnDA | SCTLR_EnDB);
260 /* Trap on btype=3 for PACIxSP. */
261 env->cp15.sctlr_el[1] |= SCTLR_BT0;
262 /* Trap on implementation defined registers. */
263 if (cpu_isar_feature(aa64_tidcp1, cpu)) {
264 env->cp15.sctlr_el[1] |= SCTLR_TIDCP;
265 }
266 /* and to the FP/Neon instructions */
267 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
268 CPACR_EL1, FPEN, 3);
269 /* and to the SVE instructions, with default vector length */
270 if (cpu_isar_feature(aa64_sve, cpu)) {
271 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
272 CPACR_EL1, ZEN, 3);
273 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
274 }
275 /* and for SME instructions, with default vector length, and TPIDR2 */
276 if (cpu_isar_feature(aa64_sme, cpu)) {
277 env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
278 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
279 CPACR_EL1, SMEN, 3);
280 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
281 if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
282 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
283 SMCR, FA64, 1);
284 }
285 }
286 /*
287 * Enable 48-bit address space (TODO: take reserved_va into account).
288 * Enable TBI0 but not TBI1.
289 * Note that this must match useronly_clean_ptr.
290 */
291 env->cp15.tcr_el[1] = 5 | (1ULL << 37);
292
293 /* Enable MTE */
294 if (cpu_isar_feature(aa64_mte, cpu)) {
295 /* Enable tag access, but leave TCF0 as No Effect (0). */
296 env->cp15.sctlr_el[1] |= SCTLR_ATA0;
297 /*
298 * Exclude all tags, so that tag 0 is always used.
299 * This corresponds to Linux current->thread.gcr_incl = 0.
300 *
301 * Set RRND, so that helper_irg() will generate a seed later.
302 * Here in cpu_reset(), the crypto subsystem has not yet been
303 * initialized.
304 */
305 env->cp15.gcr_el1 = 0x1ffff;
306 }
307 /*
308 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
309 * This is not yet exposed from the Linux kernel in any way.
310 */
311 env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
312 /* Disable access to Debug Communication Channel (DCC). */
313 env->cp15.mdscr_el1 |= 1 << 12;
314 /* Enable FEAT_MOPS */
315 env->cp15.sctlr_el[1] |= SCTLR_MSCEN;
316 #else
317 /* Reset into the highest available EL */
318 if (arm_feature(env, ARM_FEATURE_EL3)) {
319 env->pstate = PSTATE_MODE_EL3h;
320 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
321 env->pstate = PSTATE_MODE_EL2h;
322 } else {
323 env->pstate = PSTATE_MODE_EL1h;
324 }
325
326 /* Sample rvbar at reset. */
327 env->cp15.rvbar = cpu->rvbar_prop;
328 env->pc = env->cp15.rvbar;
329 #endif
330 } else {
331 #if defined(CONFIG_USER_ONLY)
332 /* Userspace expects access to cp10 and cp11 for FP/Neon */
333 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
334 CPACR, CP10, 3);
335 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
336 CPACR, CP11, 3);
337 #endif
338 if (arm_feature(env, ARM_FEATURE_V8)) {
339 env->cp15.rvbar = cpu->rvbar_prop;
340 env->regs[15] = cpu->rvbar_prop;
341 }
342 }
343
344 #if defined(CONFIG_USER_ONLY)
345 env->uncached_cpsr = ARM_CPU_MODE_USR;
346 /* For user mode we must enable access to coprocessors */
347 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
348 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
349 env->cp15.c15_cpar = 3;
350 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
351 env->cp15.c15_cpar = 1;
352 }
353 #else
354
355 /*
356 * If the highest available EL is EL2, AArch32 will start in Hyp
357 * mode; otherwise it starts in SVC. Note that if we start in
358 * AArch64 then these values in the uncached_cpsr will be ignored.
359 */
360 if (arm_feature(env, ARM_FEATURE_EL2) &&
361 !arm_feature(env, ARM_FEATURE_EL3)) {
362 env->uncached_cpsr = ARM_CPU_MODE_HYP;
363 } else {
364 env->uncached_cpsr = ARM_CPU_MODE_SVC;
365 }
366 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
367
368 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
369 * executing as AArch32 then check if highvecs are enabled and
370 * adjust the PC accordingly.
371 */
372 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
373 env->regs[15] = 0xFFFF0000;
374 }
375
376 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
377 #endif
378
379 if (arm_feature(env, ARM_FEATURE_M)) {
380 #ifndef CONFIG_USER_ONLY
381 uint32_t initial_msp; /* Loaded from 0x0 */
382 uint32_t initial_pc; /* Loaded from 0x4 */
383 uint8_t *rom;
384 uint32_t vecbase;
385 #endif
386
387 if (cpu_isar_feature(aa32_lob, cpu)) {
388 /*
389 * LTPSIZE is constant 4 if MVE not implemented, and resets
390 * to an UNKNOWN value if MVE is implemented. We choose to
391 * always reset to 4.
392 */
393 env->v7m.ltpsize = 4;
394 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
395 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
396 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
397 }
398
399 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
400 env->v7m.secure = true;
401 } else {
402 /* This bit resets to 0 if security is supported, but 1 if
403 * it is not. The bit is not present in v7M, but we set it
404 * here so we can avoid having to make checks on it conditional
405 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
406 */
407 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
408 /*
409 * Set NSACR to indicate "NS access permitted to everything";
410 * this avoids having to have all the tests of it being
411 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
412 * v8.1M the guest-visible value of NSACR in a CPU without the
413 * Security Extension is 0xcff.
414 */
415 env->v7m.nsacr = 0xcff;
416 }
417
418 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
419 * that it resets to 1, so QEMU always does that rather than making
420 * it dependent on CPU model. In v8M it is RES1.
421 */
422 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
423 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
424 if (arm_feature(env, ARM_FEATURE_V8)) {
425 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
426 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
427 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
428 }
429 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
430 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
431 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
432 }
433
434 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
435 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
436 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
437 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
438 }
439
440 #ifndef CONFIG_USER_ONLY
441 /* Unlike A/R profile, M profile defines the reset LR value */
442 env->regs[14] = 0xffffffff;
443
444 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
445 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
446
447 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
448 vecbase = env->v7m.vecbase[env->v7m.secure];
449 rom = rom_ptr_for_as(cs->as, vecbase, 8);
450 if (rom) {
451 /* Address zero is covered by ROM which hasn't yet been
452 * copied into physical memory.
453 */
454 initial_msp = ldl_p(rom);
455 initial_pc = ldl_p(rom + 4);
456 } else {
457 /* Address zero not covered by a ROM blob, or the ROM blob
458 * is in non-modifiable memory and this is a second reset after
459 * it got copied into memory. In the latter case, rom_ptr
460 * will return a NULL pointer and we should use ldl_phys instead.
461 */
462 initial_msp = ldl_phys(cs->as, vecbase);
463 initial_pc = ldl_phys(cs->as, vecbase + 4);
464 }
465
466 qemu_log_mask(CPU_LOG_INT,
467 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
468 initial_msp, initial_pc);
469
470 env->regs[13] = initial_msp & 0xFFFFFFFC;
471 env->regs[15] = initial_pc & ~1;
472 env->thumb = initial_pc & 1;
473 #else
474 /*
475 * For user mode we run non-secure and with access to the FPU.
476 * The FPU context is active (ie does not need further setup)
477 * and is owned by non-secure.
478 */
479 env->v7m.secure = false;
480 env->v7m.nsacr = 0xcff;
481 env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
482 env->v7m.fpccr[M_REG_S] &=
483 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
484 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
485 #endif
486 }
487
488 /* M profile requires that reset clears the exclusive monitor;
489 * A profile does not, but clearing it makes more sense than having it
490 * set with an exclusive access on address zero.
491 */
492 arm_clear_exclusive(env);
493
494 if (arm_feature(env, ARM_FEATURE_PMSA)) {
495 if (cpu->pmsav7_dregion > 0) {
496 if (arm_feature(env, ARM_FEATURE_V8)) {
497 memset(env->pmsav8.rbar[M_REG_NS], 0,
498 sizeof(*env->pmsav8.rbar[M_REG_NS])
499 * cpu->pmsav7_dregion);
500 memset(env->pmsav8.rlar[M_REG_NS], 0,
501 sizeof(*env->pmsav8.rlar[M_REG_NS])
502 * cpu->pmsav7_dregion);
503 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
504 memset(env->pmsav8.rbar[M_REG_S], 0,
505 sizeof(*env->pmsav8.rbar[M_REG_S])
506 * cpu->pmsav7_dregion);
507 memset(env->pmsav8.rlar[M_REG_S], 0,
508 sizeof(*env->pmsav8.rlar[M_REG_S])
509 * cpu->pmsav7_dregion);
510 }
511 } else if (arm_feature(env, ARM_FEATURE_V7)) {
512 memset(env->pmsav7.drbar, 0,
513 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
514 memset(env->pmsav7.drsr, 0,
515 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
516 memset(env->pmsav7.dracr, 0,
517 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
518 }
519 }
520
521 if (cpu->pmsav8r_hdregion > 0) {
522 memset(env->pmsav8.hprbar, 0,
523 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
524 memset(env->pmsav8.hprlar, 0,
525 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
526 }
527
528 env->pmsav7.rnr[M_REG_NS] = 0;
529 env->pmsav7.rnr[M_REG_S] = 0;
530 env->pmsav8.mair0[M_REG_NS] = 0;
531 env->pmsav8.mair0[M_REG_S] = 0;
532 env->pmsav8.mair1[M_REG_NS] = 0;
533 env->pmsav8.mair1[M_REG_S] = 0;
534 }
535
536 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
537 if (cpu->sau_sregion > 0) {
538 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
539 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
540 }
541 env->sau.rnr = 0;
542 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
543 * the Cortex-M33 does.
544 */
545 env->sau.ctrl = 0;
546 }
547
548 set_flush_to_zero(1, &env->vfp.standard_fp_status);
549 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
550 set_default_nan_mode(1, &env->vfp.standard_fp_status);
551 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
552 set_float_detect_tininess(float_tininess_before_rounding,
553 &env->vfp.fp_status);
554 set_float_detect_tininess(float_tininess_before_rounding,
555 &env->vfp.standard_fp_status);
556 set_float_detect_tininess(float_tininess_before_rounding,
557 &env->vfp.fp_status_f16);
558 set_float_detect_tininess(float_tininess_before_rounding,
559 &env->vfp.standard_fp_status_f16);
560 #ifndef CONFIG_USER_ONLY
561 if (kvm_enabled()) {
562 kvm_arm_reset_vcpu(cpu);
563 }
564 #endif
565
566 if (tcg_enabled()) {
567 hw_breakpoint_update_all(cpu);
568 hw_watchpoint_update_all(cpu);
569
570 arm_rebuild_hflags(env);
571 }
572 }
573
arm_emulate_firmware_reset(CPUState * cpustate,int target_el)574 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
575 {
576 ARMCPU *cpu = ARM_CPU(cpustate);
577 CPUARMState *env = &cpu->env;
578 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
579 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
580
581 /*
582 * Check we have the EL we're aiming for. If that is the
583 * highest implemented EL, then cpu_reset has already done
584 * all the work.
585 */
586 switch (target_el) {
587 case 3:
588 assert(have_el3);
589 return;
590 case 2:
591 assert(have_el2);
592 if (!have_el3) {
593 return;
594 }
595 break;
596 case 1:
597 if (!have_el3 && !have_el2) {
598 return;
599 }
600 break;
601 default:
602 g_assert_not_reached();
603 }
604
605 if (have_el3) {
606 /*
607 * Set the EL3 state so code can run at EL2. This should match
608 * the requirements set by Linux in its booting spec.
609 */
610 if (env->aarch64) {
611 env->cp15.scr_el3 |= SCR_RW;
612 if (cpu_isar_feature(aa64_pauth, cpu)) {
613 env->cp15.scr_el3 |= SCR_API | SCR_APK;
614 }
615 if (cpu_isar_feature(aa64_mte, cpu)) {
616 env->cp15.scr_el3 |= SCR_ATA;
617 }
618 if (cpu_isar_feature(aa64_sve, cpu)) {
619 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
620 env->vfp.zcr_el[3] = 0xf;
621 }
622 if (cpu_isar_feature(aa64_sme, cpu)) {
623 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
624 env->cp15.scr_el3 |= SCR_ENTP2;
625 env->vfp.smcr_el[3] = 0xf;
626 }
627 if (cpu_isar_feature(aa64_hcx, cpu)) {
628 env->cp15.scr_el3 |= SCR_HXEN;
629 }
630 if (cpu_isar_feature(aa64_fgt, cpu)) {
631 env->cp15.scr_el3 |= SCR_FGTEN;
632 }
633 }
634
635 if (target_el == 2) {
636 /* If the guest is at EL2 then Linux expects the HVC insn to work */
637 env->cp15.scr_el3 |= SCR_HCE;
638 }
639
640 /* Put CPU into non-secure state */
641 env->cp15.scr_el3 |= SCR_NS;
642 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
643 env->cp15.nsacr |= 3 << 10;
644 }
645
646 if (have_el2 && target_el < 2) {
647 /* Set EL2 state so code can run at EL1. */
648 if (env->aarch64) {
649 env->cp15.hcr_el2 |= HCR_RW;
650 }
651 }
652
653 /* Set the CPU to the desired state */
654 if (env->aarch64) {
655 env->pstate = aarch64_pstate_mode(target_el, true);
656 } else {
657 static const uint32_t mode_for_el[] = {
658 0,
659 ARM_CPU_MODE_SVC,
660 ARM_CPU_MODE_HYP,
661 ARM_CPU_MODE_SVC,
662 };
663
664 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
665 }
666 }
667
668
669 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
670
arm_excp_unmasked(CPUState * cs,unsigned int excp_idx,unsigned int target_el,unsigned int cur_el,bool secure,uint64_t hcr_el2)671 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
672 unsigned int target_el,
673 unsigned int cur_el, bool secure,
674 uint64_t hcr_el2)
675 {
676 CPUARMState *env = cpu_env(cs);
677 bool pstate_unmasked;
678 bool unmasked = false;
679 bool allIntMask = false;
680
681 /*
682 * Don't take exceptions if they target a lower EL.
683 * This check should catch any exceptions that would not be taken
684 * but left pending.
685 */
686 if (cur_el > target_el) {
687 return false;
688 }
689
690 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
691 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) {
692 allIntMask = env->pstate & PSTATE_ALLINT ||
693 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) &&
694 (env->pstate & PSTATE_SP));
695 }
696
697 switch (excp_idx) {
698 case EXCP_NMI:
699 pstate_unmasked = !allIntMask;
700 break;
701
702 case EXCP_VINMI:
703 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
704 /* VINMIs are only taken when hypervized. */
705 return false;
706 }
707 return !allIntMask;
708 case EXCP_VFNMI:
709 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
710 /* VFNMIs are only taken when hypervized. */
711 return false;
712 }
713 return !allIntMask;
714 case EXCP_FIQ:
715 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask);
716 break;
717
718 case EXCP_IRQ:
719 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask);
720 break;
721
722 case EXCP_VFIQ:
723 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
724 /* VFIQs are only taken when hypervized. */
725 return false;
726 }
727 return !(env->daif & PSTATE_F) && (!allIntMask);
728 case EXCP_VIRQ:
729 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
730 /* VIRQs are only taken when hypervized. */
731 return false;
732 }
733 return !(env->daif & PSTATE_I) && (!allIntMask);
734 case EXCP_VSERR:
735 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
736 /* VIRQs are only taken when hypervized. */
737 return false;
738 }
739 return !(env->daif & PSTATE_A);
740 default:
741 g_assert_not_reached();
742 }
743
744 /*
745 * Use the target EL, current execution state and SCR/HCR settings to
746 * determine whether the corresponding CPSR bit is used to mask the
747 * interrupt.
748 */
749 if ((target_el > cur_el) && (target_el != 1)) {
750 /* Exceptions targeting a higher EL may not be maskable */
751 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
752 switch (target_el) {
753 case 2:
754 /*
755 * According to ARM DDI 0487H.a, an interrupt can be masked
756 * when HCR_E2H and HCR_TGE are both set regardless of the
757 * current Security state. Note that we need to revisit this
758 * part again once we need to support NMI.
759 */
760 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
761 unmasked = true;
762 }
763 break;
764 case 3:
765 /* Interrupt cannot be masked when the target EL is 3 */
766 unmasked = true;
767 break;
768 default:
769 g_assert_not_reached();
770 }
771 } else {
772 /*
773 * The old 32-bit-only environment has a more complicated
774 * masking setup. HCR and SCR bits not only affect interrupt
775 * routing but also change the behaviour of masking.
776 */
777 bool hcr, scr;
778
779 switch (excp_idx) {
780 case EXCP_FIQ:
781 /*
782 * If FIQs are routed to EL3 or EL2 then there are cases where
783 * we override the CPSR.F in determining if the exception is
784 * masked or not. If neither of these are set then we fall back
785 * to the CPSR.F setting otherwise we further assess the state
786 * below.
787 */
788 hcr = hcr_el2 & HCR_FMO;
789 scr = (env->cp15.scr_el3 & SCR_FIQ);
790
791 /*
792 * When EL3 is 32-bit, the SCR.FW bit controls whether the
793 * CPSR.F bit masks FIQ interrupts when taken in non-secure
794 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
795 * when non-secure but only when FIQs are only routed to EL3.
796 */
797 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
798 break;
799 case EXCP_IRQ:
800 /*
801 * When EL3 execution state is 32-bit, if HCR.IMO is set then
802 * we may override the CPSR.I masking when in non-secure state.
803 * The SCR.IRQ setting has already been taken into consideration
804 * when setting the target EL, so it does not have a further
805 * affect here.
806 */
807 hcr = hcr_el2 & HCR_IMO;
808 scr = false;
809 break;
810 default:
811 g_assert_not_reached();
812 }
813
814 if ((scr || hcr) && !secure) {
815 unmasked = true;
816 }
817 }
818 }
819
820 /*
821 * The PSTATE bits only mask the interrupt if we have not overridden the
822 * ability above.
823 */
824 return unmasked || pstate_unmasked;
825 }
826
arm_cpu_exec_interrupt(CPUState * cs,int interrupt_request)827 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
828 {
829 CPUClass *cc = CPU_GET_CLASS(cs);
830 CPUARMState *env = cpu_env(cs);
831 uint32_t cur_el = arm_current_el(env);
832 bool secure = arm_is_secure(env);
833 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
834 uint32_t target_el;
835 uint32_t excp_idx;
836
837 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
838
839 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
840 (arm_sctlr(env, cur_el) & SCTLR_NMI)) {
841 if (interrupt_request & CPU_INTERRUPT_NMI) {
842 excp_idx = EXCP_NMI;
843 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
844 if (arm_excp_unmasked(cs, excp_idx, target_el,
845 cur_el, secure, hcr_el2)) {
846 goto found;
847 }
848 }
849 if (interrupt_request & CPU_INTERRUPT_VINMI) {
850 excp_idx = EXCP_VINMI;
851 target_el = 1;
852 if (arm_excp_unmasked(cs, excp_idx, target_el,
853 cur_el, secure, hcr_el2)) {
854 goto found;
855 }
856 }
857 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
858 excp_idx = EXCP_VFNMI;
859 target_el = 1;
860 if (arm_excp_unmasked(cs, excp_idx, target_el,
861 cur_el, secure, hcr_el2)) {
862 goto found;
863 }
864 }
865 } else {
866 /*
867 * NMI disabled: interrupts with superpriority are handled
868 * as if they didn't have it
869 */
870 if (interrupt_request & CPU_INTERRUPT_NMI) {
871 interrupt_request |= CPU_INTERRUPT_HARD;
872 }
873 if (interrupt_request & CPU_INTERRUPT_VINMI) {
874 interrupt_request |= CPU_INTERRUPT_VIRQ;
875 }
876 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
877 interrupt_request |= CPU_INTERRUPT_VFIQ;
878 }
879 }
880
881 if (interrupt_request & CPU_INTERRUPT_FIQ) {
882 excp_idx = EXCP_FIQ;
883 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
884 if (arm_excp_unmasked(cs, excp_idx, target_el,
885 cur_el, secure, hcr_el2)) {
886 goto found;
887 }
888 }
889 if (interrupt_request & CPU_INTERRUPT_HARD) {
890 excp_idx = EXCP_IRQ;
891 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
892 if (arm_excp_unmasked(cs, excp_idx, target_el,
893 cur_el, secure, hcr_el2)) {
894 goto found;
895 }
896 }
897 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
898 excp_idx = EXCP_VIRQ;
899 target_el = 1;
900 if (arm_excp_unmasked(cs, excp_idx, target_el,
901 cur_el, secure, hcr_el2)) {
902 goto found;
903 }
904 }
905 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
906 excp_idx = EXCP_VFIQ;
907 target_el = 1;
908 if (arm_excp_unmasked(cs, excp_idx, target_el,
909 cur_el, secure, hcr_el2)) {
910 goto found;
911 }
912 }
913 if (interrupt_request & CPU_INTERRUPT_VSERR) {
914 excp_idx = EXCP_VSERR;
915 target_el = 1;
916 if (arm_excp_unmasked(cs, excp_idx, target_el,
917 cur_el, secure, hcr_el2)) {
918 /* Taking a virtual abort clears HCR_EL2.VSE */
919 env->cp15.hcr_el2 &= ~HCR_VSE;
920 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
921 goto found;
922 }
923 }
924 return false;
925
926 found:
927 cs->exception_index = excp_idx;
928 env->exception.target_el = target_el;
929 cc->tcg_ops->do_interrupt(cs);
930 return true;
931 }
932
933 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
934
arm_cpu_update_virq(ARMCPU * cpu)935 void arm_cpu_update_virq(ARMCPU *cpu)
936 {
937 /*
938 * Update the interrupt level for VIRQ, which is the logical OR of
939 * the HCR_EL2.VI bit and the input line level from the GIC.
940 */
941 CPUARMState *env = &cpu->env;
942 CPUState *cs = CPU(cpu);
943
944 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
945 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
946 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
947
948 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
949 if (new_state) {
950 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
951 } else {
952 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
953 }
954 }
955 }
956
arm_cpu_update_vfiq(ARMCPU * cpu)957 void arm_cpu_update_vfiq(ARMCPU *cpu)
958 {
959 /*
960 * Update the interrupt level for VFIQ, which is the logical OR of
961 * the HCR_EL2.VF bit and the input line level from the GIC.
962 */
963 CPUARMState *env = &cpu->env;
964 CPUState *cs = CPU(cpu);
965
966 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) &&
967 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) ||
968 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
969
970 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
971 if (new_state) {
972 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
973 } else {
974 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
975 }
976 }
977 }
978
arm_cpu_update_vinmi(ARMCPU * cpu)979 void arm_cpu_update_vinmi(ARMCPU *cpu)
980 {
981 /*
982 * Update the interrupt level for VINMI, which is the logical OR of
983 * the HCRX_EL2.VINMI bit and the input line level from the GIC.
984 */
985 CPUARMState *env = &cpu->env;
986 CPUState *cs = CPU(cpu);
987
988 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
989 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
990 (env->irq_line_state & CPU_INTERRUPT_VINMI);
991
992 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) {
993 if (new_state) {
994 cpu_interrupt(cs, CPU_INTERRUPT_VINMI);
995 } else {
996 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI);
997 }
998 }
999 }
1000
arm_cpu_update_vfnmi(ARMCPU * cpu)1001 void arm_cpu_update_vfnmi(ARMCPU *cpu)
1002 {
1003 /*
1004 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit.
1005 */
1006 CPUARMState *env = &cpu->env;
1007 CPUState *cs = CPU(cpu);
1008
1009 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) &&
1010 (arm_hcrx_el2_eff(env) & HCRX_VFNMI);
1011
1012 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) {
1013 if (new_state) {
1014 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI);
1015 } else {
1016 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI);
1017 }
1018 }
1019 }
1020
arm_cpu_update_vserr(ARMCPU * cpu)1021 void arm_cpu_update_vserr(ARMCPU *cpu)
1022 {
1023 /*
1024 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
1025 */
1026 CPUARMState *env = &cpu->env;
1027 CPUState *cs = CPU(cpu);
1028
1029 bool new_state = env->cp15.hcr_el2 & HCR_VSE;
1030
1031 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
1032 if (new_state) {
1033 cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
1034 } else {
1035 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
1036 }
1037 }
1038 }
1039
1040 #ifndef CONFIG_USER_ONLY
arm_cpu_set_irq(void * opaque,int irq,int level)1041 static void arm_cpu_set_irq(void *opaque, int irq, int level)
1042 {
1043 ARMCPU *cpu = opaque;
1044 CPUARMState *env = &cpu->env;
1045 CPUState *cs = CPU(cpu);
1046 static const int mask[] = {
1047 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
1048 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
1049 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
1050 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
1051 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI,
1052 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI,
1053 };
1054
1055 if (!arm_feature(env, ARM_FEATURE_EL2) &&
1056 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) {
1057 /*
1058 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
1059 * have EL2 support we don't care. (Unless the guest is doing something
1060 * silly this will only be calls saying "level is still 0".)
1061 */
1062 return;
1063 }
1064
1065 if (level) {
1066 env->irq_line_state |= mask[irq];
1067 } else {
1068 env->irq_line_state &= ~mask[irq];
1069 }
1070
1071 switch (irq) {
1072 case ARM_CPU_VIRQ:
1073 arm_cpu_update_virq(cpu);
1074 break;
1075 case ARM_CPU_VFIQ:
1076 arm_cpu_update_vfiq(cpu);
1077 break;
1078 case ARM_CPU_VINMI:
1079 arm_cpu_update_vinmi(cpu);
1080 break;
1081 case ARM_CPU_IRQ:
1082 case ARM_CPU_FIQ:
1083 case ARM_CPU_NMI:
1084 if (level) {
1085 cpu_interrupt(cs, mask[irq]);
1086 } else {
1087 cpu_reset_interrupt(cs, mask[irq]);
1088 }
1089 break;
1090 default:
1091 g_assert_not_reached();
1092 }
1093 }
1094
arm_cpu_kvm_set_irq(void * opaque,int irq,int level)1095 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
1096 {
1097 #ifdef CONFIG_KVM
1098 ARMCPU *cpu = opaque;
1099 CPUARMState *env = &cpu->env;
1100 CPUState *cs = CPU(cpu);
1101 uint32_t linestate_bit;
1102 int irq_id;
1103
1104 switch (irq) {
1105 case ARM_CPU_IRQ:
1106 irq_id = KVM_ARM_IRQ_CPU_IRQ;
1107 linestate_bit = CPU_INTERRUPT_HARD;
1108 break;
1109 case ARM_CPU_FIQ:
1110 irq_id = KVM_ARM_IRQ_CPU_FIQ;
1111 linestate_bit = CPU_INTERRUPT_FIQ;
1112 break;
1113 default:
1114 g_assert_not_reached();
1115 }
1116
1117 if (level) {
1118 env->irq_line_state |= linestate_bit;
1119 } else {
1120 env->irq_line_state &= ~linestate_bit;
1121 }
1122 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
1123 #endif
1124 }
1125
arm_cpu_virtio_is_big_endian(CPUState * cs)1126 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
1127 {
1128 ARMCPU *cpu = ARM_CPU(cs);
1129 CPUARMState *env = &cpu->env;
1130
1131 cpu_synchronize_state(cs);
1132 return arm_cpu_data_is_big_endian(env);
1133 }
1134
1135 #endif
1136
arm_disas_set_info(CPUState * cpu,disassemble_info * info)1137 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
1138 {
1139 ARMCPU *ac = ARM_CPU(cpu);
1140 CPUARMState *env = &ac->env;
1141 bool sctlr_b;
1142
1143 if (is_a64(env)) {
1144 info->cap_arch = CS_ARCH_ARM64;
1145 info->cap_insn_unit = 4;
1146 info->cap_insn_split = 4;
1147 } else {
1148 int cap_mode;
1149 if (env->thumb) {
1150 info->cap_insn_unit = 2;
1151 info->cap_insn_split = 4;
1152 cap_mode = CS_MODE_THUMB;
1153 } else {
1154 info->cap_insn_unit = 4;
1155 info->cap_insn_split = 4;
1156 cap_mode = CS_MODE_ARM;
1157 }
1158 if (arm_feature(env, ARM_FEATURE_V8)) {
1159 cap_mode |= CS_MODE_V8;
1160 }
1161 if (arm_feature(env, ARM_FEATURE_M)) {
1162 cap_mode |= CS_MODE_MCLASS;
1163 }
1164 info->cap_arch = CS_ARCH_ARM;
1165 info->cap_mode = cap_mode;
1166 }
1167
1168 sctlr_b = arm_sctlr_b(env);
1169 if (bswap_code(sctlr_b)) {
1170 #if TARGET_BIG_ENDIAN
1171 info->endian = BFD_ENDIAN_LITTLE;
1172 #else
1173 info->endian = BFD_ENDIAN_BIG;
1174 #endif
1175 }
1176 info->flags &= ~INSN_ARM_BE32;
1177 #ifndef CONFIG_USER_ONLY
1178 if (sctlr_b) {
1179 info->flags |= INSN_ARM_BE32;
1180 }
1181 #endif
1182 }
1183
1184 #ifdef TARGET_AARCH64
1185
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1186 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1187 {
1188 ARMCPU *cpu = ARM_CPU(cs);
1189 CPUARMState *env = &cpu->env;
1190 uint32_t psr = pstate_read(env);
1191 int i, j;
1192 int el = arm_current_el(env);
1193 uint64_t hcr = arm_hcr_el2_eff(env);
1194 const char *ns_status;
1195 bool sve;
1196
1197 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
1198 for (i = 0; i < 32; i++) {
1199 if (i == 31) {
1200 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
1201 } else {
1202 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
1203 (i + 2) % 3 ? " " : "\n");
1204 }
1205 }
1206
1207 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
1208 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1209 } else {
1210 ns_status = "";
1211 }
1212 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1213 psr,
1214 psr & PSTATE_N ? 'N' : '-',
1215 psr & PSTATE_Z ? 'Z' : '-',
1216 psr & PSTATE_C ? 'C' : '-',
1217 psr & PSTATE_V ? 'V' : '-',
1218 ns_status,
1219 el,
1220 psr & PSTATE_SP ? 'h' : 't');
1221
1222 if (cpu_isar_feature(aa64_sme, cpu)) {
1223 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
1224 env->svcr,
1225 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
1226 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
1227 }
1228 if (cpu_isar_feature(aa64_bti, cpu)) {
1229 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
1230 }
1231 qemu_fprintf(f, "%s%s%s",
1232 (hcr & HCR_NV) ? " NV" : "",
1233 (hcr & HCR_NV1) ? " NV1" : "",
1234 (hcr & HCR_NV2) ? " NV2" : "");
1235 if (!(flags & CPU_DUMP_FPU)) {
1236 qemu_fprintf(f, "\n");
1237 return;
1238 }
1239 if (fp_exception_el(env, el) != 0) {
1240 qemu_fprintf(f, " FPU disabled\n");
1241 return;
1242 }
1243 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
1244 vfp_get_fpcr(env), vfp_get_fpsr(env));
1245
1246 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
1247 sve = sme_exception_el(env, el) == 0;
1248 } else if (cpu_isar_feature(aa64_sve, cpu)) {
1249 sve = sve_exception_el(env, el) == 0;
1250 } else {
1251 sve = false;
1252 }
1253
1254 if (sve) {
1255 int zcr_len = sve_vqm1_for_el(env, el);
1256
1257 for (i = 0; i <= FFR_PRED_NUM; i++) {
1258 bool eol;
1259 if (i == FFR_PRED_NUM) {
1260 qemu_fprintf(f, "FFR=");
1261 /* It's last, so end the line. */
1262 eol = true;
1263 } else {
1264 qemu_fprintf(f, "P%02d=", i);
1265 switch (zcr_len) {
1266 case 0:
1267 eol = i % 8 == 7;
1268 break;
1269 case 1:
1270 eol = i % 6 == 5;
1271 break;
1272 case 2:
1273 case 3:
1274 eol = i % 3 == 2;
1275 break;
1276 default:
1277 /* More than one quadword per predicate. */
1278 eol = true;
1279 break;
1280 }
1281 }
1282 for (j = zcr_len / 4; j >= 0; j--) {
1283 int digits;
1284 if (j * 4 + 4 <= zcr_len + 1) {
1285 digits = 16;
1286 } else {
1287 digits = (zcr_len % 4 + 1) * 4;
1288 }
1289 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
1290 env->vfp.pregs[i].p[j],
1291 j ? ":" : eol ? "\n" : " ");
1292 }
1293 }
1294
1295 if (zcr_len == 0) {
1296 /*
1297 * With vl=16, there are only 37 columns per register,
1298 * so output two registers per line.
1299 */
1300 for (i = 0; i < 32; i++) {
1301 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1302 i, env->vfp.zregs[i].d[1],
1303 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
1304 }
1305 } else {
1306 for (i = 0; i < 32; i++) {
1307 qemu_fprintf(f, "Z%02d=", i);
1308 for (j = zcr_len; j >= 0; j--) {
1309 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
1310 env->vfp.zregs[i].d[j * 2 + 1],
1311 env->vfp.zregs[i].d[j * 2 + 0],
1312 j ? ":" : "\n");
1313 }
1314 }
1315 }
1316 } else {
1317 for (i = 0; i < 32; i++) {
1318 uint64_t *q = aa64_vfp_qreg(env, i);
1319 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1320 i, q[1], q[0], (i & 1 ? "\n" : " "));
1321 }
1322 }
1323
1324 if (cpu_isar_feature(aa64_sme, cpu) &&
1325 FIELD_EX64(env->svcr, SVCR, ZA) &&
1326 sme_exception_el(env, el) == 0) {
1327 int zcr_len = sve_vqm1_for_el_sm(env, el, true);
1328 int svl = (zcr_len + 1) * 16;
1329 int svl_lg10 = svl < 100 ? 2 : 3;
1330
1331 for (i = 0; i < svl; i++) {
1332 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
1333 for (j = zcr_len; j >= 0; --j) {
1334 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
1335 env->zarray[i].d[2 * j + 1],
1336 env->zarray[i].d[2 * j],
1337 j ? ':' : '\n');
1338 }
1339 }
1340 }
1341 }
1342
1343 #else
1344
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1345 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1346 {
1347 g_assert_not_reached();
1348 }
1349
1350 #endif
1351
arm_cpu_dump_state(CPUState * cs,FILE * f,int flags)1352 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1353 {
1354 ARMCPU *cpu = ARM_CPU(cs);
1355 CPUARMState *env = &cpu->env;
1356 int i;
1357
1358 if (is_a64(env)) {
1359 aarch64_cpu_dump_state(cs, f, flags);
1360 return;
1361 }
1362
1363 for (i = 0; i < 16; i++) {
1364 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
1365 if ((i % 4) == 3) {
1366 qemu_fprintf(f, "\n");
1367 } else {
1368 qemu_fprintf(f, " ");
1369 }
1370 }
1371
1372 if (arm_feature(env, ARM_FEATURE_M)) {
1373 uint32_t xpsr = xpsr_read(env);
1374 const char *mode;
1375 const char *ns_status = "";
1376
1377 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1378 ns_status = env->v7m.secure ? "S " : "NS ";
1379 }
1380
1381 if (xpsr & XPSR_EXCP) {
1382 mode = "handler";
1383 } else {
1384 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
1385 mode = "unpriv-thread";
1386 } else {
1387 mode = "priv-thread";
1388 }
1389 }
1390
1391 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
1392 xpsr,
1393 xpsr & XPSR_N ? 'N' : '-',
1394 xpsr & XPSR_Z ? 'Z' : '-',
1395 xpsr & XPSR_C ? 'C' : '-',
1396 xpsr & XPSR_V ? 'V' : '-',
1397 xpsr & XPSR_T ? 'T' : 'A',
1398 ns_status,
1399 mode);
1400 } else {
1401 uint32_t psr = cpsr_read(env);
1402 const char *ns_status = "";
1403
1404 if (arm_feature(env, ARM_FEATURE_EL3) &&
1405 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1406 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1407 }
1408
1409 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1410 psr,
1411 psr & CPSR_N ? 'N' : '-',
1412 psr & CPSR_Z ? 'Z' : '-',
1413 psr & CPSR_C ? 'C' : '-',
1414 psr & CPSR_V ? 'V' : '-',
1415 psr & CPSR_T ? 'T' : 'A',
1416 ns_status,
1417 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1418 }
1419
1420 if (flags & CPU_DUMP_FPU) {
1421 int numvfpregs = 0;
1422 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1423 numvfpregs = 32;
1424 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1425 numvfpregs = 16;
1426 }
1427 for (i = 0; i < numvfpregs; i++) {
1428 uint64_t v = *aa32_vfp_dreg(env, i);
1429 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1430 i * 2, (uint32_t)v,
1431 i * 2 + 1, (uint32_t)(v >> 32),
1432 i, v);
1433 }
1434 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1435 if (cpu_isar_feature(aa32_mve, cpu)) {
1436 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1437 }
1438 }
1439 }
1440
arm_build_mp_affinity(int idx,uint8_t clustersz)1441 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
1442 {
1443 uint32_t Aff1 = idx / clustersz;
1444 uint32_t Aff0 = idx % clustersz;
1445 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1446 }
1447
arm_cpu_mp_affinity(ARMCPU * cpu)1448 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
1449 {
1450 return cpu->mp_affinity;
1451 }
1452
arm_cpu_initfn(Object * obj)1453 static void arm_cpu_initfn(Object *obj)
1454 {
1455 ARMCPU *cpu = ARM_CPU(obj);
1456
1457 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
1458 NULL, g_free);
1459
1460 QLIST_INIT(&cpu->pre_el_change_hooks);
1461 QLIST_INIT(&cpu->el_change_hooks);
1462
1463 #ifdef CONFIG_USER_ONLY
1464 # ifdef TARGET_AARCH64
1465 /*
1466 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1467 * These values were chosen to fit within the default signal frame.
1468 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1469 * and our corresponding cpu property.
1470 */
1471 cpu->sve_default_vq = 4;
1472 cpu->sme_default_vq = 2;
1473 # endif
1474 #else
1475 /* Our inbound IRQ and FIQ lines */
1476 if (kvm_enabled()) {
1477 /*
1478 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add
1479 * them to maintain the same interface as non-KVM CPUs.
1480 */
1481 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6);
1482 } else {
1483 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6);
1484 }
1485
1486 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1487 ARRAY_SIZE(cpu->gt_timer_outputs));
1488
1489 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1490 "gicv3-maintenance-interrupt", 1);
1491 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1492 "pmu-interrupt", 1);
1493 #endif
1494
1495 /* DTB consumers generally don't in fact care what the 'compatible'
1496 * string is, so always provide some string and trust that a hypothetical
1497 * picky DTB consumer will also provide a helpful error message.
1498 */
1499 cpu->dtb_compatible = "qemu,unknown";
1500 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
1501 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1502
1503 if (tcg_enabled() || hvf_enabled()) {
1504 /* TCG and HVF implement PSCI 1.1 */
1505 cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1506 }
1507 }
1508
1509 /*
1510 * 0 means "unset, use the default value". That default might vary depending
1511 * on the CPU type, and is set in the realize fn.
1512 */
1513 static Property arm_cpu_gt_cntfrq_property =
1514 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
1515
1516 static Property arm_cpu_reset_cbar_property =
1517 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1518
1519 static Property arm_cpu_reset_hivecs_property =
1520 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1521
1522 #ifndef CONFIG_USER_ONLY
1523 static Property arm_cpu_has_el2_property =
1524 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1525
1526 static Property arm_cpu_has_el3_property =
1527 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1528 #endif
1529
1530 static Property arm_cpu_cfgend_property =
1531 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1532
1533 static Property arm_cpu_has_vfp_property =
1534 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1535
1536 static Property arm_cpu_has_vfp_d32_property =
1537 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1538
1539 static Property arm_cpu_has_neon_property =
1540 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1541
1542 static Property arm_cpu_has_dsp_property =
1543 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1544
1545 static Property arm_cpu_has_mpu_property =
1546 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1547
1548 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1549 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1550 * the right value for that particular CPU type, and we don't want
1551 * to override that with an incorrect constant value.
1552 */
1553 static Property arm_cpu_pmsav7_dregion_property =
1554 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1555 pmsav7_dregion,
1556 qdev_prop_uint32, uint32_t);
1557
arm_get_pmu(Object * obj,Error ** errp)1558 static bool arm_get_pmu(Object *obj, Error **errp)
1559 {
1560 ARMCPU *cpu = ARM_CPU(obj);
1561
1562 return cpu->has_pmu;
1563 }
1564
arm_set_pmu(Object * obj,bool value,Error ** errp)1565 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1566 {
1567 ARMCPU *cpu = ARM_CPU(obj);
1568
1569 if (value) {
1570 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1571 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1572 return;
1573 }
1574 set_feature(&cpu->env, ARM_FEATURE_PMU);
1575 } else {
1576 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1577 }
1578 cpu->has_pmu = value;
1579 }
1580
gt_cntfrq_period_ns(ARMCPU * cpu)1581 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1582 {
1583 /*
1584 * The exact approach to calculating guest ticks is:
1585 *
1586 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1587 * NANOSECONDS_PER_SECOND);
1588 *
1589 * We don't do that. Rather we intentionally use integer division
1590 * truncation below and in the caller for the conversion of host monotonic
1591 * time to guest ticks to provide the exact inverse for the semantics of
1592 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1593 * it loses precision when representing frequencies where
1594 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1595 * provide an exact inverse leads to scheduling timers with negative
1596 * periods, which in turn leads to sticky behaviour in the guest.
1597 *
1598 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1599 * cannot become zero.
1600 */
1601 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1602 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1603 }
1604
arm_cpu_propagate_feature_implications(ARMCPU * cpu)1605 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
1606 {
1607 CPUARMState *env = &cpu->env;
1608 bool no_aa32 = false;
1609
1610 /*
1611 * Some features automatically imply others: set the feature
1612 * bits explicitly for these cases.
1613 */
1614
1615 if (arm_feature(env, ARM_FEATURE_M)) {
1616 set_feature(env, ARM_FEATURE_PMSA);
1617 }
1618
1619 if (arm_feature(env, ARM_FEATURE_V8)) {
1620 if (arm_feature(env, ARM_FEATURE_M)) {
1621 set_feature(env, ARM_FEATURE_V7);
1622 } else {
1623 set_feature(env, ARM_FEATURE_V7VE);
1624 }
1625 }
1626
1627 /*
1628 * There exist AArch64 cpus without AArch32 support. When KVM
1629 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1630 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1631 * As a general principle, we also do not make ID register
1632 * consistency checks anywhere unless using TCG, because only
1633 * for TCG would a consistency-check failure be a QEMU bug.
1634 */
1635 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1636 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1637 }
1638
1639 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1640 /*
1641 * v7 Virtualization Extensions. In real hardware this implies
1642 * EL2 and also the presence of the Security Extensions.
1643 * For QEMU, for backwards-compatibility we implement some
1644 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1645 * include the various other features that V7VE implies.
1646 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1647 * Security Extensions is ARM_FEATURE_EL3.
1648 */
1649 assert(!tcg_enabled() || no_aa32 ||
1650 cpu_isar_feature(aa32_arm_div, cpu));
1651 set_feature(env, ARM_FEATURE_LPAE);
1652 set_feature(env, ARM_FEATURE_V7);
1653 }
1654 if (arm_feature(env, ARM_FEATURE_V7)) {
1655 set_feature(env, ARM_FEATURE_VAPA);
1656 set_feature(env, ARM_FEATURE_THUMB2);
1657 set_feature(env, ARM_FEATURE_MPIDR);
1658 if (!arm_feature(env, ARM_FEATURE_M)) {
1659 set_feature(env, ARM_FEATURE_V6K);
1660 } else {
1661 set_feature(env, ARM_FEATURE_V6);
1662 }
1663
1664 /*
1665 * Always define VBAR for V7 CPUs even if it doesn't exist in
1666 * non-EL3 configs. This is needed by some legacy boards.
1667 */
1668 set_feature(env, ARM_FEATURE_VBAR);
1669 }
1670 if (arm_feature(env, ARM_FEATURE_V6K)) {
1671 set_feature(env, ARM_FEATURE_V6);
1672 set_feature(env, ARM_FEATURE_MVFR);
1673 }
1674 if (arm_feature(env, ARM_FEATURE_V6)) {
1675 set_feature(env, ARM_FEATURE_V5);
1676 if (!arm_feature(env, ARM_FEATURE_M)) {
1677 assert(!tcg_enabled() || no_aa32 ||
1678 cpu_isar_feature(aa32_jazelle, cpu));
1679 set_feature(env, ARM_FEATURE_AUXCR);
1680 }
1681 }
1682 if (arm_feature(env, ARM_FEATURE_V5)) {
1683 set_feature(env, ARM_FEATURE_V4T);
1684 }
1685 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1686 set_feature(env, ARM_FEATURE_V7MP);
1687 }
1688 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1689 set_feature(env, ARM_FEATURE_CBAR);
1690 }
1691 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1692 !arm_feature(env, ARM_FEATURE_M)) {
1693 set_feature(env, ARM_FEATURE_THUMB_DSP);
1694 }
1695 }
1696
arm_cpu_post_init(Object * obj)1697 void arm_cpu_post_init(Object *obj)
1698 {
1699 ARMCPU *cpu = ARM_CPU(obj);
1700
1701 /*
1702 * Some features imply others. Figure this out now, because we
1703 * are going to look at the feature bits in deciding which
1704 * properties to add.
1705 */
1706 arm_cpu_propagate_feature_implications(cpu);
1707
1708 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1709 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1710 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1711 }
1712
1713 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1714 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1715 }
1716
1717 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1718 object_property_add_uint64_ptr(obj, "rvbar",
1719 &cpu->rvbar_prop,
1720 OBJ_PROP_FLAG_READWRITE);
1721 }
1722
1723 #ifndef CONFIG_USER_ONLY
1724 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1725 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1726 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1727 */
1728 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1729
1730 object_property_add_link(obj, "secure-memory",
1731 TYPE_MEMORY_REGION,
1732 (Object **)&cpu->secure_memory,
1733 qdev_prop_allow_set_link_before_realize,
1734 OBJ_PROP_LINK_STRONG);
1735 }
1736
1737 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1738 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1739 }
1740 #endif
1741
1742 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1743 cpu->has_pmu = true;
1744 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1745 }
1746
1747 /*
1748 * Allow user to turn off VFP and Neon support, but only for TCG --
1749 * KVM does not currently allow us to lie to the guest about its
1750 * ID/feature registers, so the guest always sees what the host has.
1751 */
1752 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1753 if (cpu_isar_feature(aa64_fp_simd, cpu)) {
1754 cpu->has_vfp = true;
1755 cpu->has_vfp_d32 = true;
1756 if (tcg_enabled() || qtest_enabled()) {
1757 qdev_property_add_static(DEVICE(obj),
1758 &arm_cpu_has_vfp_property);
1759 }
1760 }
1761 } else if (cpu_isar_feature(aa32_vfp, cpu)) {
1762 cpu->has_vfp = true;
1763 if (tcg_enabled() || qtest_enabled()) {
1764 qdev_property_add_static(DEVICE(obj),
1765 &arm_cpu_has_vfp_property);
1766 }
1767 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1768 cpu->has_vfp_d32 = true;
1769 /*
1770 * The permitted values of the SIMDReg bits [3:0] on
1771 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1772 * make sure that has_vfp_d32 can not be set to false.
1773 */
1774 if ((tcg_enabled() || qtest_enabled())
1775 && !(arm_feature(&cpu->env, ARM_FEATURE_V8)
1776 && !arm_feature(&cpu->env, ARM_FEATURE_M))) {
1777 qdev_property_add_static(DEVICE(obj),
1778 &arm_cpu_has_vfp_d32_property);
1779 }
1780 }
1781 }
1782
1783 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1784 cpu->has_neon = true;
1785 if (!kvm_enabled()) {
1786 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1787 }
1788 }
1789
1790 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1791 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1792 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1793 }
1794
1795 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1796 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1797 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1798 qdev_property_add_static(DEVICE(obj),
1799 &arm_cpu_pmsav7_dregion_property);
1800 }
1801 }
1802
1803 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1804 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1805 qdev_prop_allow_set_link_before_realize,
1806 OBJ_PROP_LINK_STRONG);
1807 /*
1808 * M profile: initial value of the Secure VTOR. We can't just use
1809 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1810 * the property to be set after realize.
1811 */
1812 object_property_add_uint32_ptr(obj, "init-svtor",
1813 &cpu->init_svtor,
1814 OBJ_PROP_FLAG_READWRITE);
1815 }
1816 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1817 /*
1818 * Initial value of the NS VTOR (for cores without the Security
1819 * extension, this is the only VTOR)
1820 */
1821 object_property_add_uint32_ptr(obj, "init-nsvtor",
1822 &cpu->init_nsvtor,
1823 OBJ_PROP_FLAG_READWRITE);
1824 }
1825
1826 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1827 object_property_add_uint32_ptr(obj, "psci-conduit",
1828 &cpu->psci_conduit,
1829 OBJ_PROP_FLAG_READWRITE);
1830
1831 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1832
1833 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1834 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1835 }
1836
1837 if (kvm_enabled()) {
1838 kvm_arm_add_vcpu_properties(cpu);
1839 }
1840
1841 #ifndef CONFIG_USER_ONLY
1842 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1843 cpu_isar_feature(aa64_mte, cpu)) {
1844 object_property_add_link(obj, "tag-memory",
1845 TYPE_MEMORY_REGION,
1846 (Object **)&cpu->tag_memory,
1847 qdev_prop_allow_set_link_before_realize,
1848 OBJ_PROP_LINK_STRONG);
1849
1850 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1851 object_property_add_link(obj, "secure-tag-memory",
1852 TYPE_MEMORY_REGION,
1853 (Object **)&cpu->secure_tag_memory,
1854 qdev_prop_allow_set_link_before_realize,
1855 OBJ_PROP_LINK_STRONG);
1856 }
1857 }
1858 #endif
1859 }
1860
arm_cpu_finalizefn(Object * obj)1861 static void arm_cpu_finalizefn(Object *obj)
1862 {
1863 ARMCPU *cpu = ARM_CPU(obj);
1864 ARMELChangeHook *hook, *next;
1865
1866 g_hash_table_destroy(cpu->cp_regs);
1867
1868 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1869 QLIST_REMOVE(hook, node);
1870 g_free(hook);
1871 }
1872 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1873 QLIST_REMOVE(hook, node);
1874 g_free(hook);
1875 }
1876 #ifndef CONFIG_USER_ONLY
1877 if (cpu->pmu_timer) {
1878 timer_free(cpu->pmu_timer);
1879 }
1880 #endif
1881 }
1882
arm_cpu_finalize_features(ARMCPU * cpu,Error ** errp)1883 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1884 {
1885 Error *local_err = NULL;
1886
1887 #ifdef TARGET_AARCH64
1888 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1889 arm_cpu_sve_finalize(cpu, &local_err);
1890 if (local_err != NULL) {
1891 error_propagate(errp, local_err);
1892 return;
1893 }
1894
1895 /*
1896 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1897 * FEAT_SME_FA64 is present). However our implementation currently
1898 * assumes it, so if the user asked for sve=off then turn off SME also.
1899 * (KVM doesn't currently support SME at all.)
1900 */
1901 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) {
1902 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort);
1903 }
1904
1905 arm_cpu_sme_finalize(cpu, &local_err);
1906 if (local_err != NULL) {
1907 error_propagate(errp, local_err);
1908 return;
1909 }
1910
1911 arm_cpu_pauth_finalize(cpu, &local_err);
1912 if (local_err != NULL) {
1913 error_propagate(errp, local_err);
1914 return;
1915 }
1916
1917 arm_cpu_lpa2_finalize(cpu, &local_err);
1918 if (local_err != NULL) {
1919 error_propagate(errp, local_err);
1920 return;
1921 }
1922 }
1923 #endif
1924
1925 if (kvm_enabled()) {
1926 kvm_arm_steal_time_finalize(cpu, &local_err);
1927 if (local_err != NULL) {
1928 error_propagate(errp, local_err);
1929 return;
1930 }
1931 }
1932 }
1933
arm_cpu_realizefn(DeviceState * dev,Error ** errp)1934 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1935 {
1936 CPUState *cs = CPU(dev);
1937 ARMCPU *cpu = ARM_CPU(dev);
1938 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1939 CPUARMState *env = &cpu->env;
1940 Error *local_err = NULL;
1941
1942 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1943 /* Use pc-relative instructions in system-mode */
1944 tcg_cflags_set(cs, CF_PCREL);
1945 #endif
1946
1947 /* If we needed to query the host kernel for the CPU features
1948 * then it's possible that might have failed in the initfn, but
1949 * this is the first point where we can report it.
1950 */
1951 if (cpu->host_cpu_probe_failed) {
1952 if (!kvm_enabled() && !hvf_enabled()) {
1953 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
1954 } else {
1955 error_setg(errp, "Failed to retrieve host CPU features");
1956 }
1957 return;
1958 }
1959
1960 if (!cpu->gt_cntfrq_hz) {
1961 /*
1962 * 0 means "the board didn't set a value, use the default". (We also
1963 * get here for the CONFIG_USER_ONLY case.)
1964 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
1965 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
1966 * which gives a 16ns tick period.
1967 *
1968 * We will use the back-compat value:
1969 * - for QEMU CPU types added before we standardized on 1GHz
1970 * - for versioned machine types with a version of 9.0 or earlier
1971 */
1972 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
1973 cpu->backcompat_cntfrq) {
1974 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
1975 } else {
1976 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
1977 }
1978 }
1979
1980 #ifndef CONFIG_USER_ONLY
1981 /* The NVIC and M-profile CPU are two halves of a single piece of
1982 * hardware; trying to use one without the other is a command line
1983 * error and will result in segfaults if not caught here.
1984 */
1985 if (arm_feature(env, ARM_FEATURE_M)) {
1986 if (!env->nvic) {
1987 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1988 return;
1989 }
1990 } else {
1991 if (env->nvic) {
1992 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1993 return;
1994 }
1995 }
1996
1997 if (!tcg_enabled() && !qtest_enabled()) {
1998 /*
1999 * We assume that no accelerator except TCG (and the "not really an
2000 * accelerator" qtest) can handle these features, because Arm hardware
2001 * virtualization can't virtualize them.
2002 *
2003 * Catch all the cases which might cause us to create more than one
2004 * address space for the CPU (otherwise we will assert() later in
2005 * cpu_address_space_init()).
2006 */
2007 if (arm_feature(env, ARM_FEATURE_M)) {
2008 error_setg(errp,
2009 "Cannot enable %s when using an M-profile guest CPU",
2010 current_accel_name());
2011 return;
2012 }
2013 if (cpu->has_el3) {
2014 error_setg(errp,
2015 "Cannot enable %s when guest CPU has EL3 enabled",
2016 current_accel_name());
2017 return;
2018 }
2019 if (cpu->tag_memory) {
2020 error_setg(errp,
2021 "Cannot enable %s when guest CPUs has MTE enabled",
2022 current_accel_name());
2023 return;
2024 }
2025 }
2026
2027 {
2028 uint64_t scale = gt_cntfrq_period_ns(cpu);
2029
2030 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2031 arm_gt_ptimer_cb, cpu);
2032 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2033 arm_gt_vtimer_cb, cpu);
2034 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2035 arm_gt_htimer_cb, cpu);
2036 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2037 arm_gt_stimer_cb, cpu);
2038 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2039 arm_gt_hvtimer_cb, cpu);
2040 }
2041 #endif
2042
2043 cpu_exec_realizefn(cs, &local_err);
2044 if (local_err != NULL) {
2045 error_propagate(errp, local_err);
2046 return;
2047 }
2048
2049 arm_cpu_finalize_features(cpu, &local_err);
2050 if (local_err != NULL) {
2051 error_propagate(errp, local_err);
2052 return;
2053 }
2054
2055 #ifdef CONFIG_USER_ONLY
2056 /*
2057 * User mode relies on IC IVAU instructions to catch modification of
2058 * dual-mapped code.
2059 *
2060 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
2061 * IC IVAU even if the emulated processor does not normally require it.
2062 */
2063 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
2064 #endif
2065
2066 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
2067 cpu->has_vfp != cpu->has_neon) {
2068 /*
2069 * This is an architectural requirement for AArch64; AArch32 is
2070 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
2071 */
2072 error_setg(errp,
2073 "AArch64 CPUs must have both VFP and Neon or neither");
2074 return;
2075 }
2076
2077 if (cpu->has_vfp_d32 != cpu->has_neon) {
2078 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
2079 return;
2080 }
2081
2082 if (!cpu->has_vfp_d32) {
2083 uint32_t u;
2084
2085 u = cpu->isar.mvfr0;
2086 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
2087 cpu->isar.mvfr0 = u;
2088 }
2089
2090 if (!cpu->has_vfp) {
2091 uint64_t t;
2092 uint32_t u;
2093
2094 t = cpu->isar.id_aa64isar1;
2095 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
2096 cpu->isar.id_aa64isar1 = t;
2097
2098 t = cpu->isar.id_aa64pfr0;
2099 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
2100 cpu->isar.id_aa64pfr0 = t;
2101
2102 u = cpu->isar.id_isar6;
2103 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
2104 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2105 cpu->isar.id_isar6 = u;
2106
2107 u = cpu->isar.mvfr0;
2108 u = FIELD_DP32(u, MVFR0, FPSP, 0);
2109 u = FIELD_DP32(u, MVFR0, FPDP, 0);
2110 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
2111 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
2112 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
2113 if (!arm_feature(env, ARM_FEATURE_M)) {
2114 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
2115 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
2116 }
2117 cpu->isar.mvfr0 = u;
2118
2119 u = cpu->isar.mvfr1;
2120 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
2121 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
2122 u = FIELD_DP32(u, MVFR1, FPHP, 0);
2123 if (arm_feature(env, ARM_FEATURE_M)) {
2124 u = FIELD_DP32(u, MVFR1, FP16, 0);
2125 }
2126 cpu->isar.mvfr1 = u;
2127
2128 u = cpu->isar.mvfr2;
2129 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
2130 cpu->isar.mvfr2 = u;
2131 }
2132
2133 if (!cpu->has_neon) {
2134 uint64_t t;
2135 uint32_t u;
2136
2137 unset_feature(env, ARM_FEATURE_NEON);
2138
2139 t = cpu->isar.id_aa64isar0;
2140 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
2141 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
2142 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
2143 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
2144 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
2145 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
2146 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
2147 cpu->isar.id_aa64isar0 = t;
2148
2149 t = cpu->isar.id_aa64isar1;
2150 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
2151 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
2152 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
2153 cpu->isar.id_aa64isar1 = t;
2154
2155 t = cpu->isar.id_aa64pfr0;
2156 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
2157 cpu->isar.id_aa64pfr0 = t;
2158
2159 u = cpu->isar.id_isar5;
2160 u = FIELD_DP32(u, ID_ISAR5, AES, 0);
2161 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
2162 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
2163 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
2164 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
2165 cpu->isar.id_isar5 = u;
2166
2167 u = cpu->isar.id_isar6;
2168 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
2169 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
2170 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2171 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
2172 cpu->isar.id_isar6 = u;
2173
2174 if (!arm_feature(env, ARM_FEATURE_M)) {
2175 u = cpu->isar.mvfr1;
2176 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
2177 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
2178 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
2179 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
2180 cpu->isar.mvfr1 = u;
2181
2182 u = cpu->isar.mvfr2;
2183 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
2184 cpu->isar.mvfr2 = u;
2185 }
2186 }
2187
2188 if (!cpu->has_neon && !cpu->has_vfp) {
2189 uint64_t t;
2190 uint32_t u;
2191
2192 t = cpu->isar.id_aa64isar0;
2193 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
2194 cpu->isar.id_aa64isar0 = t;
2195
2196 t = cpu->isar.id_aa64isar1;
2197 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
2198 cpu->isar.id_aa64isar1 = t;
2199
2200 u = cpu->isar.mvfr0;
2201 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
2202 cpu->isar.mvfr0 = u;
2203
2204 /* Despite the name, this field covers both VFP and Neon */
2205 u = cpu->isar.mvfr1;
2206 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
2207 cpu->isar.mvfr1 = u;
2208 }
2209
2210 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
2211 uint32_t u;
2212
2213 unset_feature(env, ARM_FEATURE_THUMB_DSP);
2214
2215 u = cpu->isar.id_isar1;
2216 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
2217 cpu->isar.id_isar1 = u;
2218
2219 u = cpu->isar.id_isar2;
2220 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
2221 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
2222 cpu->isar.id_isar2 = u;
2223
2224 u = cpu->isar.id_isar3;
2225 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
2226 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
2227 cpu->isar.id_isar3 = u;
2228 }
2229
2230
2231 /*
2232 * We rely on no XScale CPU having VFP so we can use the same bits in the
2233 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2234 */
2235 assert(arm_feature(env, ARM_FEATURE_AARCH64) ||
2236 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
2237 !arm_feature(env, ARM_FEATURE_XSCALE));
2238
2239 #ifndef CONFIG_USER_ONLY
2240 {
2241 int pagebits;
2242 if (arm_feature(env, ARM_FEATURE_V7) &&
2243 !arm_feature(env, ARM_FEATURE_M) &&
2244 !arm_feature(env, ARM_FEATURE_PMSA)) {
2245 /*
2246 * v7VMSA drops support for the old ARMv5 tiny pages,
2247 * so we can use 4K pages.
2248 */
2249 pagebits = 12;
2250 } else {
2251 /*
2252 * For CPUs which might have tiny 1K pages, or which have an
2253 * MPU and might have small region sizes, stick with 1K pages.
2254 */
2255 pagebits = 10;
2256 }
2257 if (!set_preferred_target_page_bits(pagebits)) {
2258 /*
2259 * This can only ever happen for hotplugging a CPU, or if
2260 * the board code incorrectly creates a CPU which it has
2261 * promised via minimum_page_size that it will not.
2262 */
2263 error_setg(errp, "This CPU requires a smaller page size "
2264 "than the system is using");
2265 return;
2266 }
2267 }
2268 #endif
2269
2270 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2271 * We don't support setting cluster ID ([16..23]) (known as Aff2
2272 * in later ARM ARM versions), or any of the higher affinity level fields,
2273 * so these bits always RAZ.
2274 */
2275 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
2276 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
2277 ARM_DEFAULT_CPUS_PER_CLUSTER);
2278 }
2279
2280 if (cpu->reset_hivecs) {
2281 cpu->reset_sctlr |= (1 << 13);
2282 }
2283
2284 if (cpu->cfgend) {
2285 if (arm_feature(env, ARM_FEATURE_V7)) {
2286 cpu->reset_sctlr |= SCTLR_EE;
2287 } else {
2288 cpu->reset_sctlr |= SCTLR_B;
2289 }
2290 }
2291
2292 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
2293 /* If the has_el3 CPU property is disabled then we need to disable the
2294 * feature.
2295 */
2296 unset_feature(env, ARM_FEATURE_EL3);
2297
2298 /*
2299 * Disable the security extension feature bits in the processor
2300 * feature registers as well.
2301 */
2302 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
2303 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
2304 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2305 ID_AA64PFR0, EL3, 0);
2306
2307 /* Disable the realm management extension, which requires EL3. */
2308 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2309 ID_AA64PFR0, RME, 0);
2310 }
2311
2312 if (!cpu->has_el2) {
2313 unset_feature(env, ARM_FEATURE_EL2);
2314 }
2315
2316 if (!cpu->has_pmu) {
2317 unset_feature(env, ARM_FEATURE_PMU);
2318 }
2319 if (arm_feature(env, ARM_FEATURE_PMU)) {
2320 pmu_init(cpu);
2321
2322 if (!kvm_enabled()) {
2323 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
2324 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
2325 }
2326
2327 #ifndef CONFIG_USER_ONLY
2328 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
2329 cpu);
2330 #endif
2331 } else {
2332 cpu->isar.id_aa64dfr0 =
2333 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
2334 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
2335 cpu->pmceid0 = 0;
2336 cpu->pmceid1 = 0;
2337 }
2338
2339 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2340 /*
2341 * Disable the hypervisor feature bits in the processor feature
2342 * registers if we don't have EL2.
2343 */
2344 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2345 ID_AA64PFR0, EL2, 0);
2346 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
2347 ID_PFR1, VIRTUALIZATION, 0);
2348 }
2349
2350 if (cpu_isar_feature(aa64_mte, cpu)) {
2351 /*
2352 * The architectural range of GM blocksize is 2-6, however qemu
2353 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2354 */
2355 if (tcg_enabled()) {
2356 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
2357 }
2358
2359 #ifndef CONFIG_USER_ONLY
2360 /*
2361 * If we do not have tag-memory provided by the machine,
2362 * reduce MTE support to instructions enabled at EL0.
2363 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2364 */
2365 if (cpu->tag_memory == NULL) {
2366 cpu->isar.id_aa64pfr1 =
2367 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
2368 }
2369 #endif
2370 }
2371
2372 if (tcg_enabled()) {
2373 /*
2374 * Don't report some architectural features in the ID registers
2375 * where TCG does not yet implement it (not even a minimal
2376 * stub version). This avoids guests falling over when they
2377 * try to access the non-existent system registers for them.
2378 */
2379 /* FEAT_SPE (Statistical Profiling Extension) */
2380 cpu->isar.id_aa64dfr0 =
2381 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
2382 /* FEAT_TRBE (Trace Buffer Extension) */
2383 cpu->isar.id_aa64dfr0 =
2384 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
2385 /* FEAT_TRF (Self-hosted Trace Extension) */
2386 cpu->isar.id_aa64dfr0 =
2387 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
2388 cpu->isar.id_dfr0 =
2389 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
2390 /* Trace Macrocell system register access */
2391 cpu->isar.id_aa64dfr0 =
2392 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
2393 cpu->isar.id_dfr0 =
2394 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
2395 /* Memory mapped trace */
2396 cpu->isar.id_dfr0 =
2397 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
2398 /* FEAT_AMU (Activity Monitors Extension) */
2399 cpu->isar.id_aa64pfr0 =
2400 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
2401 cpu->isar.id_pfr0 =
2402 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
2403 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2404 cpu->isar.id_aa64pfr0 =
2405 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
2406 }
2407
2408 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2409 * to false or by setting pmsav7-dregion to 0.
2410 */
2411 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
2412 cpu->has_mpu = false;
2413 cpu->pmsav7_dregion = 0;
2414 cpu->pmsav8r_hdregion = 0;
2415 }
2416
2417 if (arm_feature(env, ARM_FEATURE_PMSA) &&
2418 arm_feature(env, ARM_FEATURE_V7)) {
2419 uint32_t nr = cpu->pmsav7_dregion;
2420
2421 if (nr > 0xff) {
2422 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2423 return;
2424 }
2425
2426 if (nr) {
2427 if (arm_feature(env, ARM_FEATURE_V8)) {
2428 /* PMSAv8 */
2429 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
2430 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
2431 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2432 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
2433 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2434 }
2435 } else {
2436 env->pmsav7.drbar = g_new0(uint32_t, nr);
2437 env->pmsav7.drsr = g_new0(uint32_t, nr);
2438 env->pmsav7.dracr = g_new0(uint32_t, nr);
2439 }
2440 }
2441
2442 if (cpu->pmsav8r_hdregion > 0xff) {
2443 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
2444 cpu->pmsav8r_hdregion);
2445 return;
2446 }
2447
2448 if (cpu->pmsav8r_hdregion) {
2449 env->pmsav8.hprbar = g_new0(uint32_t,
2450 cpu->pmsav8r_hdregion);
2451 env->pmsav8.hprlar = g_new0(uint32_t,
2452 cpu->pmsav8r_hdregion);
2453 }
2454 }
2455
2456 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2457 uint32_t nr = cpu->sau_sregion;
2458
2459 if (nr > 0xff) {
2460 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2461 return;
2462 }
2463
2464 if (nr) {
2465 env->sau.rbar = g_new0(uint32_t, nr);
2466 env->sau.rlar = g_new0(uint32_t, nr);
2467 }
2468 }
2469
2470 if (arm_feature(env, ARM_FEATURE_EL3)) {
2471 set_feature(env, ARM_FEATURE_VBAR);
2472 }
2473
2474 #ifndef CONFIG_USER_ONLY
2475 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) {
2476 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0);
2477 }
2478 #endif
2479
2480 register_cp_regs_for_features(cpu);
2481 arm_cpu_register_gdb_regs_for_features(cpu);
2482
2483 init_cpreg_list(cpu);
2484
2485 #ifndef CONFIG_USER_ONLY
2486 MachineState *ms = MACHINE(qdev_get_machine());
2487 unsigned int smp_cpus = ms->smp.cpus;
2488 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
2489
2490 /*
2491 * We must set cs->num_ases to the final value before
2492 * the first call to cpu_address_space_init.
2493 */
2494 if (cpu->tag_memory != NULL) {
2495 cs->num_ases = 3 + has_secure;
2496 } else {
2497 cs->num_ases = 1 + has_secure;
2498 }
2499
2500 if (has_secure) {
2501 if (!cpu->secure_memory) {
2502 cpu->secure_memory = cs->memory;
2503 }
2504 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
2505 cpu->secure_memory);
2506 }
2507
2508 if (cpu->tag_memory != NULL) {
2509 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
2510 cpu->tag_memory);
2511 if (has_secure) {
2512 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
2513 cpu->secure_tag_memory);
2514 }
2515 }
2516
2517 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
2518
2519 /* No core_count specified, default to smp_cpus. */
2520 if (cpu->core_count == -1) {
2521 cpu->core_count = smp_cpus;
2522 }
2523 #endif
2524
2525 if (tcg_enabled()) {
2526 int dcz_blocklen = 4 << cpu->dcz_blocksize;
2527
2528 /*
2529 * We only support DCZ blocklen that fits on one page.
2530 *
2531 * Architectually this is always true. However TARGET_PAGE_SIZE
2532 * is variable and, for compatibility with -machine virt-2.7,
2533 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2534 * But even then, while the largest architectural DCZ blocklen
2535 * is 2KiB, no cpu actually uses such a large blocklen.
2536 */
2537 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
2538
2539 /*
2540 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2541 * both nibbles of each byte storing tag data may be written at once.
2542 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2543 */
2544 if (cpu_isar_feature(aa64_mte, cpu)) {
2545 assert(dcz_blocklen >= 2 * TAG_GRANULE);
2546 }
2547 }
2548
2549 qemu_init_vcpu(cs);
2550 cpu_reset(cs);
2551
2552 acc->parent_realize(dev, errp);
2553 }
2554
arm_cpu_class_by_name(const char * cpu_model)2555 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
2556 {
2557 ObjectClass *oc;
2558 char *typename;
2559 char **cpuname;
2560 const char *cpunamestr;
2561
2562 cpuname = g_strsplit(cpu_model, ",", 1);
2563 cpunamestr = cpuname[0];
2564 #ifdef CONFIG_USER_ONLY
2565 /* For backwards compatibility usermode emulation allows "-cpu any",
2566 * which has the same semantics as "-cpu max".
2567 */
2568 if (!strcmp(cpunamestr, "any")) {
2569 cpunamestr = "max";
2570 }
2571 #endif
2572 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
2573 oc = object_class_by_name(typename);
2574 g_strfreev(cpuname);
2575 g_free(typename);
2576
2577 return oc;
2578 }
2579
2580 static Property arm_cpu_properties[] = {
2581 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2582 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2583 mp_affinity, ARM64_AFFINITY_INVALID),
2584 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2585 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2586 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
2587 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
2588 DEFINE_PROP_END_OF_LIST()
2589 };
2590
arm_gdb_arch_name(CPUState * cs)2591 static const gchar *arm_gdb_arch_name(CPUState *cs)
2592 {
2593 ARMCPU *cpu = ARM_CPU(cs);
2594 CPUARMState *env = &cpu->env;
2595
2596 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2597 return "iwmmxt";
2598 }
2599 return "arm";
2600 }
2601
2602 #ifndef CONFIG_USER_ONLY
2603 #include "hw/core/sysemu-cpu-ops.h"
2604
2605 static const struct SysemuCPUOps arm_sysemu_ops = {
2606 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
2607 .asidx_from_attrs = arm_asidx_from_attrs,
2608 .write_elf32_note = arm_cpu_write_elf32_note,
2609 .write_elf64_note = arm_cpu_write_elf64_note,
2610 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
2611 .legacy_vmsd = &vmstate_arm_cpu,
2612 };
2613 #endif
2614
2615 #ifdef CONFIG_TCG
2616 static const TCGCPUOps arm_tcg_ops = {
2617 .initialize = arm_translate_init,
2618 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2619 .debug_excp_handler = arm_debug_excp_handler,
2620 .restore_state_to_opc = arm_restore_state_to_opc,
2621
2622 #ifdef CONFIG_USER_ONLY
2623 .record_sigsegv = arm_cpu_record_sigsegv,
2624 .record_sigbus = arm_cpu_record_sigbus,
2625 #else
2626 .tlb_fill = arm_cpu_tlb_fill,
2627 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2628 .do_interrupt = arm_cpu_do_interrupt,
2629 .do_transaction_failed = arm_cpu_do_transaction_failed,
2630 .do_unaligned_access = arm_cpu_do_unaligned_access,
2631 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2632 .debug_check_watchpoint = arm_debug_check_watchpoint,
2633 .debug_check_breakpoint = arm_debug_check_breakpoint,
2634 #endif /* !CONFIG_USER_ONLY */
2635 };
2636 #endif /* CONFIG_TCG */
2637
arm_cpu_class_init(ObjectClass * oc,void * data)2638 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2639 {
2640 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2641 CPUClass *cc = CPU_CLASS(acc);
2642 DeviceClass *dc = DEVICE_CLASS(oc);
2643 ResettableClass *rc = RESETTABLE_CLASS(oc);
2644
2645 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2646 &acc->parent_realize);
2647
2648 device_class_set_props(dc, arm_cpu_properties);
2649
2650 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
2651 &acc->parent_phases);
2652
2653 cc->class_by_name = arm_cpu_class_by_name;
2654 cc->has_work = arm_cpu_has_work;
2655 cc->mmu_index = arm_cpu_mmu_index;
2656 cc->dump_state = arm_cpu_dump_state;
2657 cc->set_pc = arm_cpu_set_pc;
2658 cc->get_pc = arm_cpu_get_pc;
2659 cc->gdb_read_register = arm_cpu_gdb_read_register;
2660 cc->gdb_write_register = arm_cpu_gdb_write_register;
2661 #ifndef CONFIG_USER_ONLY
2662 cc->sysemu_ops = &arm_sysemu_ops;
2663 #endif
2664 cc->gdb_arch_name = arm_gdb_arch_name;
2665 cc->gdb_stop_before_watchpoint = true;
2666 cc->disas_set_info = arm_disas_set_info;
2667
2668 #ifdef CONFIG_TCG
2669 cc->tcg_ops = &arm_tcg_ops;
2670 #endif /* CONFIG_TCG */
2671 }
2672
arm_cpu_instance_init(Object * obj)2673 static void arm_cpu_instance_init(Object *obj)
2674 {
2675 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2676
2677 acc->info->initfn(obj);
2678 arm_cpu_post_init(obj);
2679 }
2680
cpu_register_class_init(ObjectClass * oc,void * data)2681 static void cpu_register_class_init(ObjectClass *oc, void *data)
2682 {
2683 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2684 CPUClass *cc = CPU_CLASS(acc);
2685
2686 acc->info = data;
2687 cc->gdb_core_xml_file = "arm-core.xml";
2688 }
2689
arm_cpu_register(const ARMCPUInfo * info)2690 void arm_cpu_register(const ARMCPUInfo *info)
2691 {
2692 TypeInfo type_info = {
2693 .parent = TYPE_ARM_CPU,
2694 .instance_init = arm_cpu_instance_init,
2695 .class_init = info->class_init ?: cpu_register_class_init,
2696 .class_data = (void *)info,
2697 };
2698
2699 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2700 type_register(&type_info);
2701 g_free((void *)type_info.name);
2702 }
2703
2704 static const TypeInfo arm_cpu_type_info = {
2705 .name = TYPE_ARM_CPU,
2706 .parent = TYPE_CPU,
2707 .instance_size = sizeof(ARMCPU),
2708 .instance_align = __alignof__(ARMCPU),
2709 .instance_init = arm_cpu_initfn,
2710 .instance_finalize = arm_cpu_finalizefn,
2711 .abstract = true,
2712 .class_size = sizeof(ARMCPUClass),
2713 .class_init = arm_cpu_class_init,
2714 };
2715
arm_cpu_register_types(void)2716 static void arm_cpu_register_types(void)
2717 {
2718 type_register_static(&arm_cpu_type_info);
2719 }
2720
2721 type_init(arm_cpu_register_types)
2722