1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #if defined(__i386__) || defined(__x86_64__)
18
19 #include <stdlib.h>
20 #include <string.h>
21 #include "flash.h"
22 #include "programmer.h"
23 #include "hwaccess.h"
24
25 #define BIOS_ROM_ADDR 0x90
26 #define BIOS_ROM_DATA 0x94
27
28 #define REG_FLASH_ACCESS 0x58
29
30 #define PCI_VENDOR_ID_HPT 0x1103
31
32 static uint32_t io_base_addr = 0;
33
34 const struct dev_entry ata_hpt[] = {
35 {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
36 {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
37 {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
38
39 {0},
40 };
41
42 static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
43 chipaddr addr);
44 static uint8_t atahpt_chip_readb(const struct flashctx *flash,
45 const chipaddr addr);
46 static const struct par_master par_master_atahpt = {
47 .chip_readb = atahpt_chip_readb,
48 .chip_readw = fallback_chip_readw,
49 .chip_readl = fallback_chip_readl,
50 .chip_readn = fallback_chip_readn,
51 .chip_writeb = atahpt_chip_writeb,
52 .chip_writew = fallback_chip_writew,
53 .chip_writel = fallback_chip_writel,
54 .chip_writen = fallback_chip_writen,
55 };
56
atahpt_init(void)57 int atahpt_init(void)
58 {
59 struct pci_dev *dev = NULL;
60 uint32_t reg32;
61
62 if (rget_io_perms())
63 return 1;
64
65 dev = pcidev_init(ata_hpt, PCI_BASE_ADDRESS_4);
66 if (!dev)
67 return 1;
68
69 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4);
70 if (!io_base_addr)
71 return 1;
72
73 /* Enable flash access. */
74 reg32 = pci_read_long(dev, REG_FLASH_ACCESS);
75 reg32 |= (1 << 24);
76 rpci_write_long(dev, REG_FLASH_ACCESS, reg32);
77
78 register_par_master(&par_master_atahpt, BUS_PARALLEL);
79
80 return 0;
81 }
82
atahpt_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)83 static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
84 chipaddr addr)
85 {
86 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
87 OUTB(val, io_base_addr + BIOS_ROM_DATA);
88 }
89
atahpt_chip_readb(const struct flashctx * flash,const chipaddr addr)90 static uint8_t atahpt_chip_readb(const struct flashctx *flash,
91 const chipaddr addr)
92 {
93 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
94 return INB(io_base_addr + BIOS_ROM_DATA);
95 }
96
97 #else
98 #error PCI port I/O access is not supported on this architecture yet.
99 #endif
100