atom_DCN_dpphy_dvihdmi_tuningset (definition) in projects: dports

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Searched defs:atom_DCN_dpphy_dvihdmi_tuningset (Results 1 – 3 of 3) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/
H A D	atomfirmware.h	1213 struct atom_DCN_dpphy_dvihdmi_tuningset struct 1215 uint32_t max_symclk_in10khz; 1216 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1217 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1218 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1219 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1220 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1221 uint8_t reserved1; 1222 …uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1223 uint8_t reserved2;
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/
H A D	atomfirmware.h	1213 struct atom_DCN_dpphy_dvihdmi_tuningset struct 1215 uint32_t max_symclk_in10khz; 1216 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1217 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1218 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1219 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1220 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1221 uint8_t reserved1; 1222 …uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1223 uint8_t reserved2;
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/
H A D	atomfirmware.h	1213 struct atom_DCN_dpphy_dvihdmi_tuningset struct 1215 uint32_t max_symclk_in10khz; 1216 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1217 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1218 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1219 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1220 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1221 uint8_t reserved1; 1222 …uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1223 uint8_t reserved2;