1 /* $NetBSD: au_icu.c,v 1.31 2021/01/04 17:35:12 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2006 Itronix Inc.
5 * All rights reserved.
6 *
7 * Written by Garrett D'Amore for Itronix Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of Itronix Inc. may not be used to endorse
18 * or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*-
35 * Copyright (c) 2001 The NetBSD Foundation, Inc.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to The NetBSD Foundation
39 * by Jason R. Thorpe.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 */
62
63 /*
64 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs.
65 *
66 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal
67 * interrupt controllers.
68 */
69
70 #include <sys/cdefs.h>
71 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.31 2021/01/04 17:35:12 thorpej Exp $");
72
73 #include "opt_ddb.h"
74 #define __INTR_PRIVATE
75
76 #include <sys/param.h>
77 #include <sys/bus.h>
78 #include <sys/device.h>
79 #include <sys/intr.h>
80 #include <sys/kernel.h>
81 #include <sys/kmem.h>
82 #include <sys/systm.h>
83
84 #include <mips/locore.h>
85 #include <mips/alchemy/include/aureg.h>
86 #include <mips/alchemy/include/auvar.h>
87
88 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
89
90 /*
91 * This is a mask of bits to clear in the SR when we go to a
92 * given hardware interrupt priority level.
93 */
94
95 static const struct ipl_sr_map alchemy_ipl_sr_map = {
96 .sr_bits = {
97 [IPL_NONE] = 0,
98 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
99 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
100 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
101 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
102 [IPL_VM] = MIPS_SOFT_INT_MASK |
103 MIPS_INT_MASK_0 |
104 MIPS_INT_MASK_1 |
105 MIPS_INT_MASK_2 |
106 MIPS_INT_MASK_3,
107 [IPL_SCHED] = MIPS_INT_MASK,
108 [IPL_DDB] = MIPS_INT_MASK,
109 [IPL_HIGH] = MIPS_INT_MASK,
110 },
111 };
112
113 #define NIRQS 64
114
115 struct au_icu_intrhead {
116 struct evcnt intr_count;
117 int intr_refcnt;
118 };
119 struct au_icu_intrhead au_icu_intrtab[NIRQS];
120
121 #define NINTRS 4 /* MIPS INT0 - INT3 */
122
123 struct au_intrhand {
124 LIST_ENTRY(au_intrhand) ih_q;
125 int (*ih_func)(void *);
126 void *ih_arg;
127 int ih_irq;
128 int ih_mask;
129 };
130
131 struct au_cpuintr {
132 LIST_HEAD(, au_intrhand) cintr_list;
133 struct evcnt cintr_count;
134 };
135
136 struct au_cpuintr au_cpuintrs[NINTRS];
137 const char * const au_cpuintrnames[NINTRS] = {
138 "icu 0, req 0",
139 "icu 0, req 1",
140 "icu 1, req 0",
141 "icu 1, req 1",
142 };
143
144 static bus_addr_t ic0_base, ic1_base;
145
146 void
au_intr_init(void)147 au_intr_init(void)
148 {
149 ipl_sr_map = alchemy_ipl_sr_map;
150
151 for (size_t i = 0; i < NINTRS; i++) {
152 LIST_INIT(&au_cpuintrs[i].cintr_list);
153 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count,
154 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]);
155 }
156
157 struct au_chipdep * const chip = au_chipdep();
158 KASSERT(chip != NULL);
159
160 ic0_base = chip->icus[0];
161 ic1_base = chip->icus[1];
162
163 for (size_t i = 0; i < NIRQS; i++) {
164 au_icu_intrtab[i].intr_refcnt = 0;
165 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count,
166 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]);
167 }
168
169 /* start with all interrupts masked */
170 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff;
171 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff;
172 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff;
173 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff;
174 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff;
175 REGVAL(ic0_base + IC_TEST_BIT) = 0;
176
177 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff;
178 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff;
179 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff;
180 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff;
181 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff;
182 REGVAL(ic1_base + IC_TEST_BIT) = 0;
183 }
184
185 void *
au_intr_establish(int irq,int req,int level,int type,int (* func)(void *),void * arg)186 au_intr_establish(int irq, int req, int level, int type,
187 int (*func)(void *), void *arg)
188 {
189 struct au_intrhand *ih;
190 uint32_t icu_base;
191 int cpu_int, s;
192 struct au_chipdep *chip;
193
194 chip = au_chipdep();
195 KASSERT(chip != NULL);
196
197 if (irq >= NIRQS)
198 panic("au_intr_establish: bogus IRQ %d", irq);
199 if (req > 1)
200 panic("au_intr_establish: bogus request %d", req);
201
202 ih = kmem_alloc(sizeof(*ih), KM_SLEEP);
203 ih->ih_func = func;
204 ih->ih_arg = arg;
205 ih->ih_irq = irq;
206 ih->ih_mask = (1 << (irq & 31));
207
208 s = splhigh();
209
210 /*
211 * First, link it into the tables.
212 * XXX do we want a separate list (really, should only be one item, not
213 * a list anyway) per irq, not per CPU interrupt?
214 */
215 cpu_int = (irq < 32 ? 0 : 2) + req;
216 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q);
217
218 /*
219 * Now enable it.
220 */
221 if (au_icu_intrtab[irq].intr_refcnt++ == 0) {
222 icu_base = (irq < 32) ? ic0_base : ic1_base;
223
224 irq &= 31; /* throw away high bit if set */
225 irq = 1 << irq; /* only used as a mask from here on */
226
227 /* XXX Only level interrupts for now */
228 switch (type) {
229 case IST_NONE:
230 case IST_PULSE:
231 case IST_EDGE:
232 panic("unsupported irq type %d", type);
233 /* NOTREACHED */
234 case IST_LEVEL:
235 case IST_LEVEL_HIGH:
236 REGVAL(icu_base + IC_CONFIG2_SET) = irq;
237 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
238 REGVAL(icu_base + IC_CONFIG0_SET) = irq;
239 break;
240 case IST_LEVEL_LOW:
241 REGVAL(icu_base + IC_CONFIG2_SET) = irq;
242 REGVAL(icu_base + IC_CONFIG1_SET) = irq;
243 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
244 break;
245 }
246 wbflush();
247
248 /* XXX handle GPIO interrupts - not done at all yet */
249 if (cpu_int & 0x1)
250 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq;
251 else
252 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq;
253
254 /* Associate interrupt with peripheral */
255 REGVAL(icu_base + IC_SOURCE_SET) = irq;
256
257 /* Actually enable the interrupt */
258 REGVAL(icu_base + IC_MASK_SET) = irq;
259
260 /* And allow the interrupt to interrupt idle */
261 REGVAL(icu_base + IC_WAKEUP_SET) = irq;
262
263 wbflush();
264 }
265 splx(s);
266
267 return (ih);
268 }
269
270 void
au_intr_disestablish(void * cookie)271 au_intr_disestablish(void *cookie)
272 {
273 struct au_intrhand *ih = cookie;
274 uint32_t icu_base;
275 int irq, s;
276
277 irq = ih->ih_irq;
278
279 s = splhigh();
280
281 /*
282 * First, remove it from the table.
283 */
284 LIST_REMOVE(ih, ih_q);
285
286 /*
287 * Now, disable it, if there is nothing remaining on the
288 * list.
289 */
290 if (au_icu_intrtab[irq].intr_refcnt-- == 1) {
291 icu_base = (irq < 32) ? ic0_base : ic1_base;
292
293 irq &= 31; /* throw away high bit if set */
294 irq = 1 << irq; /* only used as a mask from here on */
295
296 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq;
297 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
298 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
299
300 /* disable with MASK_CLEAR and WAKEUP_CLEAR */
301 REGVAL(icu_base + IC_MASK_CLEAR) = irq;
302 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq;
303 wbflush();
304 }
305
306 splx(s);
307
308 kmem_free(ih, sizeof(*ih));
309 }
310
311 void
au_iointr(int ipl,vaddr_t pc,uint32_t ipending)312 au_iointr(int ipl, vaddr_t pc, uint32_t ipending)
313 {
314 struct au_intrhand *ih;
315 int level;
316 uint32_t icu_base, irqstat, irqmask;
317
318 icu_base = irqstat = 0;
319
320 for (level = 3; level >= 0; level--) {
321 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
322 continue;
323
324 /*
325 * XXX the following may well be slow to execute.
326 * investigate and possibly speed up.
327 *
328 * is something like:
329 *
330 * irqstat = REGVAL(
331 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE +
332 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT);
333 *
334 * be any better?
335 *
336 */
337 switch (level) {
338 case 0:
339 icu_base = ic0_base;
340 irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
341 break;
342 case 1:
343 icu_base = ic0_base;
344 irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
345 break;
346 case 2:
347 icu_base = ic1_base;
348 irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
349 break;
350 case 3:
351 icu_base = ic1_base;
352 irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
353 break;
354 }
355 irqmask = REGVAL(icu_base + IC_MASK_READ);
356 au_cpuintrs[level].cintr_count.ev_count++;
357 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) {
358 int mask = ih->ih_mask;
359
360 if (mask & irqmask & irqstat) {
361 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++;
362 (*ih->ih_func)(ih->ih_arg);
363
364 if (REGVAL(icu_base + IC_MASK_READ) & mask) {
365 REGVAL(icu_base + IC_MASK_CLEAR) = mask;
366 REGVAL(icu_base + IC_MASK_SET) = mask;
367 wbflush();
368 }
369 }
370 }
371 }
372 }
373
374 /*
375 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at
376 * the ICU, and leave them masked off until some later time
377 * (e.g. reenabled by a soft interrupt).
378 */
379
380 void
au_intr_enable(int irq)381 au_intr_enable(int irq)
382 {
383 int s;
384 uint32_t icu_base, mask;
385
386 if (irq >= NIRQS)
387 panic("au_intr_enable: bogus IRQ %d", irq);
388
389 icu_base = (irq < 32) ? ic0_base : ic1_base;
390 mask = irq & 31;
391 mask = 1 << mask;
392
393 s = splhigh();
394 /* only enable the interrupt if we have a handler */
395 if (au_icu_intrtab[irq].intr_refcnt) {
396 REGVAL(icu_base + IC_MASK_SET) = mask;
397 REGVAL(icu_base + IC_WAKEUP_SET) = mask;
398 wbflush();
399 }
400 splx(s);
401 }
402
403 void
au_intr_disable(int irq)404 au_intr_disable(int irq)
405 {
406 int s;
407 uint32_t icu_base, mask;
408
409 if (irq >= NIRQS)
410 panic("au_intr_disable: bogus IRQ %d", irq);
411
412 icu_base = (irq < 32) ? ic0_base : ic1_base;
413 mask = irq & 31;
414 mask = 1 << mask;
415
416 s = splhigh();
417 REGVAL(icu_base + IC_MASK_CLEAR) = mask;
418 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask;
419 wbflush();
420 splx(s);
421 }
422