1 /* $NetBSD: radeon_rs600.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30 /* RS600 / Radeon X1250/X1270 integrated GPU
31 *
32 * This file gather function specific to RS600 which is the IGP of
33 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
34 * is the X1250/X1270 supporting AMD CPU). The display engine are
35 * the avivo one, bios is an atombios, 3D block are the one of the
36 * R4XX family. The GART is different from the RS400 one and is very
37 * close to the one of the R600 family (R600 likely being an evolution
38 * of the RS600 GART block).
39 */
40
41 #include <sys/cdefs.h>
42 __KERNEL_RCSID(0, "$NetBSD: radeon_rs600.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
43
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <linux/pci.h>
46
47 #include <drm/drm_device.h>
48 #include <drm/drm_vblank.h>
49
50 #include "atom.h"
51 #include "radeon.h"
52 #include "radeon_asic.h"
53 #include "radeon_audio.h"
54 #include "rs600_reg_safe.h"
55 #include "rs600d.h"
56
57 static void rs600_gpu_init(struct radeon_device *rdev);
58 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
59
60 static const u32 crtc_offsets[2] =
61 {
62 0,
63 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
64 };
65
avivo_is_in_vblank(struct radeon_device * rdev,int crtc)66 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
67 {
68 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
69 return true;
70 else
71 return false;
72 }
73
avivo_is_counter_moving(struct radeon_device * rdev,int crtc)74 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
75 {
76 u32 pos1, pos2;
77
78 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
79 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
80
81 if (pos1 != pos2)
82 return true;
83 else
84 return false;
85 }
86
87 /**
88 * avivo_wait_for_vblank - vblank wait asic callback.
89 *
90 * @rdev: radeon_device pointer
91 * @crtc: crtc to wait for vblank on
92 *
93 * Wait for vblank on the requested crtc (r5xx-r7xx).
94 */
avivo_wait_for_vblank(struct radeon_device * rdev,int crtc)95 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
96 {
97 unsigned i = 0;
98
99 if (crtc >= rdev->num_crtc)
100 return;
101
102 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
103 return;
104
105 /* depending on when we hit vblank, we may be close to active; if so,
106 * wait for another frame.
107 */
108 while (avivo_is_in_vblank(rdev, crtc)) {
109 if (i++ % 100 == 0) {
110 if (!avivo_is_counter_moving(rdev, crtc))
111 break;
112 }
113 }
114
115 while (!avivo_is_in_vblank(rdev, crtc)) {
116 if (i++ % 100 == 0) {
117 if (!avivo_is_counter_moving(rdev, crtc))
118 break;
119 }
120 }
121 }
122
rs600_page_flip(struct radeon_device * rdev,int crtc_id,u64 crtc_base,bool async)123 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
124 {
125 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
126 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
127 int i;
128
129 /* Lock the graphics update lock */
130 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
131 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
132
133 /* update the scanout addresses */
134 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
135 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
136 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
137 (u32)crtc_base);
138 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
139 (u32)crtc_base);
140
141 /* Wait for update_pending to go high. */
142 for (i = 0; i < rdev->usec_timeout; i++) {
143 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
144 break;
145 udelay(1);
146 }
147 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
148
149 /* Unlock the lock, so double-buffering can take place inside vblank */
150 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
151 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
152 }
153
rs600_page_flip_pending(struct radeon_device * rdev,int crtc_id)154 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
155 {
156 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
157
158 /* Return current update_pending status: */
159 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
160 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
161 }
162
avivo_program_fmt(struct drm_encoder * encoder)163 void avivo_program_fmt(struct drm_encoder *encoder)
164 {
165 struct drm_device *dev = encoder->dev;
166 struct radeon_device *rdev = dev->dev_private;
167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
168 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
169 int bpc = 0;
170 u32 tmp = 0;
171 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
172
173 if (connector) {
174 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
175 bpc = radeon_get_monitor_bpc(connector);
176 dither = radeon_connector->dither;
177 }
178
179 /* LVDS FMT is set up by atom */
180 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
181 return;
182
183 if (bpc == 0)
184 return;
185
186 switch (bpc) {
187 case 6:
188 if (dither == RADEON_FMT_DITHER_ENABLE)
189 /* XXX sort out optimal dither settings */
190 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
191 else
192 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
193 break;
194 case 8:
195 if (dither == RADEON_FMT_DITHER_ENABLE)
196 /* XXX sort out optimal dither settings */
197 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
198 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
199 else
200 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
201 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
202 break;
203 case 10:
204 default:
205 /* not needed */
206 break;
207 }
208
209 switch (radeon_encoder->encoder_id) {
210 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
211 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
212 break;
213 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
214 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
215 break;
216 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
217 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
218 break;
219 case ENCODER_OBJECT_ID_INTERNAL_DDI:
220 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
221 break;
222 default:
223 break;
224 }
225 }
226
rs600_pm_misc(struct radeon_device * rdev)227 void rs600_pm_misc(struct radeon_device *rdev)
228 {
229 int requested_index = rdev->pm.requested_power_state_index;
230 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
231 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
232 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
233 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
234
235 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
236 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
237 tmp = RREG32(voltage->gpio.reg);
238 if (voltage->active_high)
239 tmp |= voltage->gpio.mask;
240 else
241 tmp &= ~(voltage->gpio.mask);
242 WREG32(voltage->gpio.reg, tmp);
243 if (voltage->delay)
244 udelay(voltage->delay);
245 } else {
246 tmp = RREG32(voltage->gpio.reg);
247 if (voltage->active_high)
248 tmp &= ~voltage->gpio.mask;
249 else
250 tmp |= voltage->gpio.mask;
251 WREG32(voltage->gpio.reg, tmp);
252 if (voltage->delay)
253 udelay(voltage->delay);
254 }
255 } else if (voltage->type == VOLTAGE_VDDC)
256 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
257
258 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
259 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
260 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
261 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
262 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
263 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
264 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
265 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
266 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
267 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
268 }
269 } else {
270 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
271 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
272 }
273 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
274
275 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
276 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
277 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
278 if (voltage->delay) {
279 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
280 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
281 } else
282 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
283 } else
284 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
285 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
286
287 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
288 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
289 hdp_dyn_cntl &= ~HDP_FORCEON;
290 else
291 hdp_dyn_cntl |= HDP_FORCEON;
292 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
293 #if 0
294 /* mc_host_dyn seems to cause hangs from time to time */
295 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
296 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
297 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
298 else
299 mc_host_dyn_cntl |= MC_HOST_FORCEON;
300 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
301 #endif
302 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
303 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
304 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
305 else
306 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
307 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
308
309 /* set pcie lanes */
310 if ((rdev->flags & RADEON_IS_PCIE) &&
311 !(rdev->flags & RADEON_IS_IGP) &&
312 rdev->asic->pm.set_pcie_lanes &&
313 (ps->pcie_lanes !=
314 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
315 radeon_set_pcie_lanes(rdev,
316 ps->pcie_lanes);
317 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
318 }
319 }
320
rs600_pm_prepare(struct radeon_device * rdev)321 void rs600_pm_prepare(struct radeon_device *rdev)
322 {
323 struct drm_device *ddev = rdev->ddev;
324 struct drm_crtc *crtc;
325 struct radeon_crtc *radeon_crtc;
326 u32 tmp;
327
328 /* disable any active CRTCs */
329 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
330 radeon_crtc = to_radeon_crtc(crtc);
331 if (radeon_crtc->enabled) {
332 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
333 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
334 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
335 }
336 }
337 }
338
rs600_pm_finish(struct radeon_device * rdev)339 void rs600_pm_finish(struct radeon_device *rdev)
340 {
341 struct drm_device *ddev = rdev->ddev;
342 struct drm_crtc *crtc;
343 struct radeon_crtc *radeon_crtc;
344 u32 tmp;
345
346 /* enable any active CRTCs */
347 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
348 radeon_crtc = to_radeon_crtc(crtc);
349 if (radeon_crtc->enabled) {
350 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
351 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
352 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
353 }
354 }
355 }
356
357 /* hpd for digital panel detect/disconnect */
rs600_hpd_sense(struct radeon_device * rdev,enum radeon_hpd_id hpd)358 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
359 {
360 u32 tmp;
361 bool connected = false;
362
363 switch (hpd) {
364 case RADEON_HPD_1:
365 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
366 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
367 connected = true;
368 break;
369 case RADEON_HPD_2:
370 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
371 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
372 connected = true;
373 break;
374 default:
375 break;
376 }
377 return connected;
378 }
379
rs600_hpd_set_polarity(struct radeon_device * rdev,enum radeon_hpd_id hpd)380 void rs600_hpd_set_polarity(struct radeon_device *rdev,
381 enum radeon_hpd_id hpd)
382 {
383 u32 tmp;
384 bool connected = rs600_hpd_sense(rdev, hpd);
385
386 switch (hpd) {
387 case RADEON_HPD_1:
388 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
389 if (connected)
390 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
391 else
392 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
393 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
394 break;
395 case RADEON_HPD_2:
396 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
397 if (connected)
398 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
399 else
400 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
401 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
402 break;
403 default:
404 break;
405 }
406 }
407
rs600_hpd_init(struct radeon_device * rdev)408 void rs600_hpd_init(struct radeon_device *rdev)
409 {
410 struct drm_device *dev = rdev->ddev;
411 struct drm_connector *connector;
412 unsigned enable = 0;
413
414 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
415 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
416 switch (radeon_connector->hpd.hpd) {
417 case RADEON_HPD_1:
418 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
419 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
420 break;
421 case RADEON_HPD_2:
422 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
423 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
424 break;
425 default:
426 break;
427 }
428 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
429 enable |= 1 << radeon_connector->hpd.hpd;
430 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
431 }
432 radeon_irq_kms_enable_hpd(rdev, enable);
433 }
434
rs600_hpd_fini(struct radeon_device * rdev)435 void rs600_hpd_fini(struct radeon_device *rdev)
436 {
437 struct drm_device *dev = rdev->ddev;
438 struct drm_connector *connector;
439 unsigned disable = 0;
440
441 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
442 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
443 switch (radeon_connector->hpd.hpd) {
444 case RADEON_HPD_1:
445 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
446 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
447 break;
448 case RADEON_HPD_2:
449 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
450 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
451 break;
452 default:
453 break;
454 }
455 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
456 disable |= 1 << radeon_connector->hpd.hpd;
457 }
458 radeon_irq_kms_disable_hpd(rdev, disable);
459 }
460
rs600_asic_reset(struct radeon_device * rdev,bool hard)461 int rs600_asic_reset(struct radeon_device *rdev, bool hard)
462 {
463 struct rv515_mc_save save;
464 u32 status, tmp;
465 int ret = 0;
466
467 status = RREG32(R_000E40_RBBM_STATUS);
468 if (!G_000E40_GUI_ACTIVE(status)) {
469 return 0;
470 }
471 /* Stops all mc clients */
472 rv515_mc_stop(rdev, &save);
473 status = RREG32(R_000E40_RBBM_STATUS);
474 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
475 /* stop CP */
476 WREG32(RADEON_CP_CSQ_CNTL, 0);
477 tmp = RREG32(RADEON_CP_RB_CNTL);
478 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
479 WREG32(RADEON_CP_RB_RPTR_WR, 0);
480 WREG32(RADEON_CP_RB_WPTR, 0);
481 WREG32(RADEON_CP_RB_CNTL, tmp);
482 pci_save_state(rdev->pdev);
483 /* disable bus mastering */
484 pci_clear_master(rdev->pdev);
485 mdelay(1);
486 /* reset GA+VAP */
487 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
488 S_0000F0_SOFT_RESET_GA(1));
489 RREG32(R_0000F0_RBBM_SOFT_RESET);
490 mdelay(500);
491 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
492 mdelay(1);
493 status = RREG32(R_000E40_RBBM_STATUS);
494 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
495 /* reset CP */
496 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
497 RREG32(R_0000F0_RBBM_SOFT_RESET);
498 mdelay(500);
499 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
500 mdelay(1);
501 status = RREG32(R_000E40_RBBM_STATUS);
502 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
503 /* reset MC */
504 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
505 RREG32(R_0000F0_RBBM_SOFT_RESET);
506 mdelay(500);
507 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
508 mdelay(1);
509 status = RREG32(R_000E40_RBBM_STATUS);
510 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
511 /* restore PCI & busmastering */
512 pci_restore_state(rdev->pdev);
513 /* Check if GPU is idle */
514 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
515 dev_err(rdev->dev, "failed to reset GPU\n");
516 ret = -1;
517 } else
518 dev_info(rdev->dev, "GPU reset succeed\n");
519 rv515_mc_resume(rdev, &save);
520 return ret;
521 }
522
523 /*
524 * GART.
525 */
rs600_gart_tlb_flush(struct radeon_device * rdev)526 void rs600_gart_tlb_flush(struct radeon_device *rdev)
527 {
528 uint32_t tmp;
529
530 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
531 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
532 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
533
534 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
535 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
536 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
537
538 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
539 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
540 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
541 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
542 }
543
rs600_gart_init(struct radeon_device * rdev)544 static int rs600_gart_init(struct radeon_device *rdev)
545 {
546 int r;
547
548 if (rdev->gart.robj) {
549 WARN(1, "RS600 GART already initialized\n");
550 return 0;
551 }
552 /* Initialize common gart structure */
553 r = radeon_gart_init(rdev);
554 if (r) {
555 return r;
556 }
557 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
558 return radeon_gart_table_vram_alloc(rdev);
559 }
560
rs600_gart_enable(struct radeon_device * rdev)561 static int rs600_gart_enable(struct radeon_device *rdev)
562 {
563 u32 tmp;
564 int r, i;
565
566 if (rdev->gart.robj == NULL) {
567 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
568 return -EINVAL;
569 }
570 r = radeon_gart_table_vram_pin(rdev);
571 if (r)
572 return r;
573 /* Enable bus master */
574 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
575 WREG32(RADEON_BUS_CNTL, tmp);
576 /* FIXME: setup default page */
577 WREG32_MC(R_000100_MC_PT0_CNTL,
578 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
579 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
580
581 for (i = 0; i < 19; i++) {
582 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
583 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
584 S_00016C_SYSTEM_ACCESS_MODE_MASK(
585 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
586 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
587 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
588 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
589 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
590 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
591 }
592 /* enable first context */
593 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
594 S_000102_ENABLE_PAGE_TABLE(1) |
595 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
596
597 /* disable all other contexts */
598 for (i = 1; i < 8; i++)
599 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
600
601 /* setup the page table */
602 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
603 rdev->gart.table_addr);
604 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
605 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
606 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
607
608 /* System context maps to VRAM space */
609 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
610 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
611
612 /* enable page tables */
613 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
614 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
615 tmp = RREG32_MC(R_000009_MC_CNTL1);
616 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
617 rs600_gart_tlb_flush(rdev);
618 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
619 (unsigned)(rdev->mc.gtt_size >> 20),
620 (unsigned long long)rdev->gart.table_addr);
621 rdev->gart.ready = true;
622 return 0;
623 }
624
rs600_gart_disable(struct radeon_device * rdev)625 static void rs600_gart_disable(struct radeon_device *rdev)
626 {
627 u32 tmp;
628
629 /* FIXME: disable out of gart access */
630 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
631 tmp = RREG32_MC(R_000009_MC_CNTL1);
632 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
633 radeon_gart_table_vram_unpin(rdev);
634 }
635
rs600_gart_fini(struct radeon_device * rdev)636 static void rs600_gart_fini(struct radeon_device *rdev)
637 {
638 radeon_gart_fini(rdev);
639 rs600_gart_disable(rdev);
640 radeon_gart_table_vram_free(rdev);
641 }
642
rs600_gart_get_page_entry(uint64_t addr,uint32_t flags)643 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
644 {
645 addr = addr & 0xFFFFFFFFFFFFF000ULL;
646 addr |= R600_PTE_SYSTEM;
647 if (flags & RADEON_GART_PAGE_VALID)
648 addr |= R600_PTE_VALID;
649 if (flags & RADEON_GART_PAGE_READ)
650 addr |= R600_PTE_READABLE;
651 if (flags & RADEON_GART_PAGE_WRITE)
652 addr |= R600_PTE_WRITEABLE;
653 if (flags & RADEON_GART_PAGE_SNOOP)
654 addr |= R600_PTE_SNOOPED;
655 return addr;
656 }
657
658 #ifdef __NetBSD__
659 # define __iomem volatile
660 # define writeq fake_writeq
661
662 static inline void
fake_writeq(uint64_t v,void __iomem * ptr)663 fake_writeq(uint64_t v, void __iomem *ptr)
664 {
665
666 membar_producer();
667 *(uint64_t __iomem *)ptr = v;
668 }
669 #endif
670
rs600_gart_set_page(struct radeon_device * rdev,unsigned i,uint64_t entry)671 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
672 uint64_t entry)
673 {
674 void __iomem *ptr = (void *)rdev->gart.ptr;
675 writeq(entry, (char __iomem *)ptr + (i * 8));
676 }
677
678 #ifdef __NetBSD__
679 # undef writeq
680 # undef __iomem
681 #endif
682
rs600_irq_set(struct radeon_device * rdev)683 int rs600_irq_set(struct radeon_device *rdev)
684 {
685 uint32_t tmp = 0;
686 uint32_t mode_int = 0;
687 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
688 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
689 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
690 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
691 u32 hdmi0;
692 if (ASIC_IS_DCE2(rdev))
693 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
694 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
695 else
696 hdmi0 = 0;
697
698 if (!rdev->irq.installed) {
699 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
700 WREG32(R_000040_GEN_INT_CNTL, 0);
701 return -EINVAL;
702 }
703 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
704 tmp |= S_000040_SW_INT_EN(1);
705 }
706 if (rdev->irq.crtc_vblank_int[0] ||
707 atomic_read(&rdev->irq.pflip[0])) {
708 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
709 }
710 if (rdev->irq.crtc_vblank_int[1] ||
711 atomic_read(&rdev->irq.pflip[1])) {
712 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
713 }
714 if (rdev->irq.hpd[0]) {
715 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
716 }
717 if (rdev->irq.hpd[1]) {
718 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
719 }
720 if (rdev->irq.afmt[0]) {
721 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
722 }
723 WREG32(R_000040_GEN_INT_CNTL, tmp);
724 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
725 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
726 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
727 if (ASIC_IS_DCE2(rdev))
728 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
729
730 /* posting read */
731 RREG32(R_000040_GEN_INT_CNTL);
732
733 return 0;
734 }
735
rs600_irq_ack(struct radeon_device * rdev)736 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
737 {
738 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
739 uint32_t irq_mask = S_000044_SW_INT(1);
740 u32 tmp;
741
742 if (G_000044_DISPLAY_INT_STAT(irqs)) {
743 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
744 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
745 WREG32(R_006534_D1MODE_VBLANK_STATUS,
746 S_006534_D1MODE_VBLANK_ACK(1));
747 }
748 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
749 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
750 S_006D34_D2MODE_VBLANK_ACK(1));
751 }
752 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
753 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
754 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
755 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
756 }
757 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
758 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
759 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
760 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
761 }
762 } else {
763 rdev->irq.stat_regs.r500.disp_int = 0;
764 }
765
766 if (ASIC_IS_DCE2(rdev)) {
767 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
768 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
769 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
770 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
771 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
772 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
773 }
774 } else
775 rdev->irq.stat_regs.r500.hdmi0_status = 0;
776
777 if (irqs) {
778 WREG32(R_000044_GEN_INT_STATUS, irqs);
779 }
780 return irqs & irq_mask;
781 }
782
rs600_irq_disable(struct radeon_device * rdev)783 void rs600_irq_disable(struct radeon_device *rdev)
784 {
785 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
786 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
787 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
788 WREG32(R_000040_GEN_INT_CNTL, 0);
789 WREG32(R_006540_DxMODE_INT_MASK, 0);
790 /* Wait and acknowledge irq */
791 mdelay(1);
792 rs600_irq_ack(rdev);
793 }
794
rs600_irq_process(struct radeon_device * rdev)795 int rs600_irq_process(struct radeon_device *rdev)
796 {
797 u32 status, msi_rearm;
798 bool queue_hotplug = false;
799 bool queue_hdmi = false;
800
801 status = rs600_irq_ack(rdev);
802 if (!status &&
803 !rdev->irq.stat_regs.r500.disp_int &&
804 !rdev->irq.stat_regs.r500.hdmi0_status) {
805 return IRQ_NONE;
806 }
807 while (status ||
808 rdev->irq.stat_regs.r500.disp_int ||
809 rdev->irq.stat_regs.r500.hdmi0_status) {
810 /* SW interrupt */
811 if (G_000044_SW_INT(status)) {
812 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
813 }
814 /* Vertical blank interrupts */
815 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
816 if (rdev->irq.crtc_vblank_int[0]) {
817 drm_handle_vblank(rdev->ddev, 0);
818 #ifdef __NetBSD__
819 spin_lock(&rdev->irq.vblank_lock);
820 rdev->pm.vblank_sync = true;
821 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
822 spin_unlock(&rdev->irq.vblank_lock);
823 #else
824 rdev->pm.vblank_sync = true;
825 wake_up(&rdev->irq.vblank_queue);
826 #endif
827 }
828 if (atomic_read(&rdev->irq.pflip[0]))
829 radeon_crtc_handle_vblank(rdev, 0);
830 }
831 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
832 if (rdev->irq.crtc_vblank_int[1]) {
833 drm_handle_vblank(rdev->ddev, 1);
834 #ifdef __NetBSD__
835 spin_lock(&rdev->irq.vblank_lock);
836 rdev->pm.vblank_sync = true;
837 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
838 spin_unlock(&rdev->irq.vblank_lock);
839 #else
840 rdev->pm.vblank_sync = true;
841 wake_up(&rdev->irq.vblank_queue);
842 #endif
843 }
844 if (atomic_read(&rdev->irq.pflip[1]))
845 radeon_crtc_handle_vblank(rdev, 1);
846 }
847 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
848 queue_hotplug = true;
849 DRM_DEBUG("HPD1\n");
850 }
851 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
852 queue_hotplug = true;
853 DRM_DEBUG("HPD2\n");
854 }
855 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
856 queue_hdmi = true;
857 DRM_DEBUG("HDMI0\n");
858 }
859 status = rs600_irq_ack(rdev);
860 }
861 if (queue_hotplug)
862 schedule_delayed_work(&rdev->hotplug_work, 0);
863 if (queue_hdmi)
864 schedule_work(&rdev->audio_work);
865 if (rdev->msi_enabled) {
866 switch (rdev->family) {
867 case CHIP_RS600:
868 case CHIP_RS690:
869 case CHIP_RS740:
870 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
871 WREG32(RADEON_BUS_CNTL, msi_rearm);
872 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
873 break;
874 default:
875 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
876 break;
877 }
878 }
879 return IRQ_HANDLED;
880 }
881
rs600_get_vblank_counter(struct radeon_device * rdev,int crtc)882 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
883 {
884 if (crtc == 0)
885 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
886 else
887 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
888 }
889
rs600_mc_wait_for_idle(struct radeon_device * rdev)890 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
891 {
892 unsigned i;
893
894 for (i = 0; i < rdev->usec_timeout; i++) {
895 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
896 return 0;
897 udelay(1);
898 }
899 return -1;
900 }
901
rs600_gpu_init(struct radeon_device * rdev)902 static void rs600_gpu_init(struct radeon_device *rdev)
903 {
904 r420_pipes_init(rdev);
905 /* Wait for mc idle */
906 if (rs600_mc_wait_for_idle(rdev))
907 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
908 }
909
rs600_mc_init(struct radeon_device * rdev)910 static void rs600_mc_init(struct radeon_device *rdev)
911 {
912 u64 base;
913
914 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
915 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
916 rdev->mc.vram_is_ddr = true;
917 rdev->mc.vram_width = 128;
918 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
919 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
920 rdev->mc.visible_vram_size = rdev->mc.aper_size;
921 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
922 base = RREG32_MC(R_000004_MC_FB_LOCATION);
923 base = G_000004_MC_FB_START(base) << 16;
924 radeon_vram_location(rdev, &rdev->mc, base);
925 rdev->mc.gtt_base_align = 0;
926 radeon_gtt_location(rdev, &rdev->mc);
927 radeon_update_bandwidth_info(rdev);
928 }
929
rs600_bandwidth_update(struct radeon_device * rdev)930 void rs600_bandwidth_update(struct radeon_device *rdev)
931 {
932 struct drm_display_mode *mode0 = NULL;
933 struct drm_display_mode *mode1 = NULL;
934 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
935 /* FIXME: implement full support */
936
937 if (!rdev->mode_info.mode_config_initialized)
938 return;
939
940 radeon_update_display_priority(rdev);
941
942 if (rdev->mode_info.crtcs[0]->base.enabled)
943 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
944 if (rdev->mode_info.crtcs[1]->base.enabled)
945 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
946
947 rs690_line_buffer_adjust(rdev, mode0, mode1);
948
949 if (rdev->disp_priority == 2) {
950 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
951 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
952 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
953 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
954 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
955 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
956 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
957 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
958 }
959 }
960
rs600_mc_rreg(struct radeon_device * rdev,uint32_t reg)961 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
962 {
963 unsigned long flags;
964 u32 r;
965
966 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
967 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
968 S_000070_MC_IND_CITF_ARB0(1));
969 r = RREG32(R_000074_MC_IND_DATA);
970 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
971 return r;
972 }
973
rs600_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)974 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
975 {
976 unsigned long flags;
977
978 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
979 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
980 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
981 WREG32(R_000074_MC_IND_DATA, v);
982 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
983 }
984
rs600_debugfs(struct radeon_device * rdev)985 static void rs600_debugfs(struct radeon_device *rdev)
986 {
987 if (r100_debugfs_rbbm_init(rdev))
988 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
989 }
990
rs600_set_safe_registers(struct radeon_device * rdev)991 void rs600_set_safe_registers(struct radeon_device *rdev)
992 {
993 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
994 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
995 }
996
rs600_mc_program(struct radeon_device * rdev)997 static void rs600_mc_program(struct radeon_device *rdev)
998 {
999 struct rv515_mc_save save;
1000
1001 /* Stops all mc clients */
1002 rv515_mc_stop(rdev, &save);
1003
1004 /* Wait for mc idle */
1005 if (rs600_mc_wait_for_idle(rdev))
1006 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
1007
1008 /* FIXME: What does AGP means for such chipset ? */
1009 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
1010 WREG32_MC(R_000006_AGP_BASE, 0);
1011 WREG32_MC(R_000007_AGP_BASE_2, 0);
1012 /* Program MC */
1013 WREG32_MC(R_000004_MC_FB_LOCATION,
1014 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
1015 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
1016 WREG32(R_000134_HDP_FB_LOCATION,
1017 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
1018
1019 rv515_mc_resume(rdev, &save);
1020 }
1021
rs600_startup(struct radeon_device * rdev)1022 static int rs600_startup(struct radeon_device *rdev)
1023 {
1024 int r;
1025
1026 rs600_mc_program(rdev);
1027 /* Resume clock */
1028 rv515_clock_startup(rdev);
1029 /* Initialize GPU configuration (# pipes, ...) */
1030 rs600_gpu_init(rdev);
1031 /* Initialize GART (initialize after TTM so we can allocate
1032 * memory through TTM but finalize after TTM) */
1033 r = rs600_gart_enable(rdev);
1034 if (r)
1035 return r;
1036
1037 /* allocate wb buffer */
1038 r = radeon_wb_init(rdev);
1039 if (r)
1040 return r;
1041
1042 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1043 if (r) {
1044 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1045 return r;
1046 }
1047
1048 /* Enable IRQ */
1049 if (!rdev->irq.installed) {
1050 r = radeon_irq_kms_init(rdev);
1051 if (r)
1052 return r;
1053 }
1054
1055 rs600_irq_set(rdev);
1056 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1057 /* 1M ring buffer */
1058 r = r100_cp_init(rdev, 1024 * 1024);
1059 if (r) {
1060 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1061 return r;
1062 }
1063
1064 r = radeon_ib_pool_init(rdev);
1065 if (r) {
1066 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1067 return r;
1068 }
1069
1070 r = radeon_audio_init(rdev);
1071 if (r) {
1072 dev_err(rdev->dev, "failed initializing audio\n");
1073 return r;
1074 }
1075
1076 return 0;
1077 }
1078
rs600_resume(struct radeon_device * rdev)1079 int rs600_resume(struct radeon_device *rdev)
1080 {
1081 int r;
1082
1083 /* Make sur GART are not working */
1084 rs600_gart_disable(rdev);
1085 /* Resume clock before doing reset */
1086 rv515_clock_startup(rdev);
1087 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1088 if (radeon_asic_reset(rdev)) {
1089 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1090 RREG32(R_000E40_RBBM_STATUS),
1091 RREG32(R_0007C0_CP_STAT));
1092 }
1093 /* post */
1094 atom_asic_init(rdev->mode_info.atom_context);
1095 /* Resume clock after posting */
1096 rv515_clock_startup(rdev);
1097 /* Initialize surface registers */
1098 radeon_surface_init(rdev);
1099
1100 rdev->accel_working = true;
1101 r = rs600_startup(rdev);
1102 if (r) {
1103 rdev->accel_working = false;
1104 }
1105 return r;
1106 }
1107
rs600_suspend(struct radeon_device * rdev)1108 int rs600_suspend(struct radeon_device *rdev)
1109 {
1110 radeon_pm_suspend(rdev);
1111 radeon_audio_fini(rdev);
1112 r100_cp_disable(rdev);
1113 radeon_wb_disable(rdev);
1114 rs600_irq_disable(rdev);
1115 rs600_gart_disable(rdev);
1116 return 0;
1117 }
1118
rs600_fini(struct radeon_device * rdev)1119 void rs600_fini(struct radeon_device *rdev)
1120 {
1121 radeon_pm_fini(rdev);
1122 radeon_audio_fini(rdev);
1123 r100_cp_fini(rdev);
1124 radeon_wb_fini(rdev);
1125 radeon_ib_pool_fini(rdev);
1126 radeon_gem_fini(rdev);
1127 rs600_gart_fini(rdev);
1128 radeon_irq_kms_fini(rdev);
1129 radeon_fence_driver_fini(rdev);
1130 radeon_bo_fini(rdev);
1131 radeon_atombios_fini(rdev);
1132 kfree(rdev->bios);
1133 rdev->bios = NULL;
1134 }
1135
rs600_init(struct radeon_device * rdev)1136 int rs600_init(struct radeon_device *rdev)
1137 {
1138 int r;
1139
1140 /* Disable VGA */
1141 rv515_vga_render_disable(rdev);
1142 /* Initialize scratch registers */
1143 radeon_scratch_init(rdev);
1144 /* Initialize surface registers */
1145 radeon_surface_init(rdev);
1146 /* restore some register to sane defaults */
1147 r100_restore_sanity(rdev);
1148 /* BIOS */
1149 if (!radeon_get_bios(rdev)) {
1150 if (ASIC_IS_AVIVO(rdev))
1151 return -EINVAL;
1152 }
1153 if (rdev->is_atom_bios) {
1154 r = radeon_atombios_init(rdev);
1155 if (r)
1156 return r;
1157 } else {
1158 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1159 return -EINVAL;
1160 }
1161 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1162 if (radeon_asic_reset(rdev)) {
1163 dev_warn(rdev->dev,
1164 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1165 RREG32(R_000E40_RBBM_STATUS),
1166 RREG32(R_0007C0_CP_STAT));
1167 }
1168 /* check if cards are posted or not */
1169 if (radeon_boot_test_post_card(rdev) == false)
1170 return -EINVAL;
1171
1172 /* Initialize clocks */
1173 radeon_get_clock_info(rdev->ddev);
1174 /* initialize memory controller */
1175 rs600_mc_init(rdev);
1176 rs600_debugfs(rdev);
1177 /* Fence driver */
1178 r = radeon_fence_driver_init(rdev);
1179 if (r)
1180 return r;
1181 /* Memory manager */
1182 r = radeon_bo_init(rdev);
1183 if (r)
1184 return r;
1185 r = rs600_gart_init(rdev);
1186 if (r)
1187 return r;
1188 rs600_set_safe_registers(rdev);
1189
1190 /* Initialize power management */
1191 radeon_pm_init(rdev);
1192
1193 rdev->accel_working = true;
1194 r = rs600_startup(rdev);
1195 if (r) {
1196 /* Somethings want wront with the accel init stop accel */
1197 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1198 r100_cp_fini(rdev);
1199 radeon_wb_fini(rdev);
1200 radeon_ib_pool_fini(rdev);
1201 rs600_gart_fini(rdev);
1202 radeon_irq_kms_fini(rdev);
1203 rdev->accel_working = false;
1204 }
1205 return 0;
1206 }
1207