1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2005 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 reg a; initial a = 1'b1; 15 reg b_fc; initial b_fc = 1'b0; 16 reg b_pc; initial b_pc = 1'b0; 17 reg b_oh; initial b_oh = 1'b0; 18 reg b_oc; initial b_oc = 1'b0; 19 wire a_l = ~a; 20 wire b_oc_l = ~b_oc; 21 22 // Note we must ensure that full, parallel, etc, only fire during 23 // edges (not mid-cycle), and must provide a way to turn them off. 24 // SystemVerilog provides: $asserton and $assertoff. 25 26 // verilator lint_off CASEINCOMPLETE 27 28 always @* begin 29 // Note not all tools support directives on casez's 30`ifdef ATTRIBUTES 31 case ({a,b_fc}) // synopsys full_case 32`else 33 case ({a,b_fc}) 34`endif 35 2'b0_0: ; 36 2'b0_1: ; 37 2'b1_0: ; 38 // Note no default 39 endcase 40 priority case ({a,b_fc}) 41 2'b0_0: ; 42 2'b0_1: ; 43 2'b1_0: ; 44 // Note no default 45 endcase 46 end 47 48 always @* begin 49`ifdef ATTRIBUTES 50 case (1'b1) // synopsys full_case parallel_case 51`else 52 `ifdef FAILING_FULL 53 case (1'b1) // synopsys parallel_case 54 `else 55 case (1'b1) // synopsys parallel_full 56 `endif 57`endif 58 a: ; 59 b_pc: ; 60 endcase 61 end 62 63`ifdef NOT_YET_VERILATOR // Unsupported 64 // ambit synthesis one_hot "a, b_oh" 65 // cadence one_cold "a_l, b_oc_l" 66`endif 67 68 integer cyc; initial cyc=1; 69 always @ (posedge clk) begin 70 if (cyc!=0) begin 71 cyc <= cyc + 1; 72 if (cyc==1) begin 73 a <= 1'b1; 74 b_fc <= 1'b0; 75 b_pc <= 1'b0; 76 b_oh <= 1'b0; 77 b_oc <= 1'b0; 78 end 79 if (cyc==2) begin 80 a <= 1'b0; 81 b_fc <= 1'b1; 82 b_pc <= 1'b1; 83 b_oh <= 1'b1; 84 b_oc <= 1'b1; 85 end 86 if (cyc==3) begin 87 a <= 1'b1; 88 b_fc <= 1'b0; 89 b_pc <= 1'b0; 90 b_oh <= 1'b0; 91 b_oc <= 1'b0; 92 end 93 if (cyc==4) begin 94`ifdef FAILING_FULL 95 b_fc <= 1'b1; 96`endif 97`ifdef FAILING_PARALLEL 98 b_pc <= 1'b1; 99`endif 100`ifdef FAILING_OH 101 b_oh <= 1'b1; 102`endif 103`ifdef FAILING_OC 104 b_oc <= 1'b1; 105`endif 106 end 107 if (cyc==10) begin 108 $write("*-* All Finished *-*\n"); 109 $finish; 110 end 111 end 112 end 113 114endmodule 115