1 /*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29 #ifndef __ECORE_H
30 #define __ECORE_H
31
32 #include "ecore_status.h"
33 #include "ecore_hsi_common.h"
34 #include "ecore_hsi_debug_tools.h"
35 #include "ecore_hsi_init_func.h"
36 #include "ecore_hsi_init_tool.h"
37 #include "ecore_proto_if.h"
38 #include "mcp_public.h"
39
40 #define ECORE_MAJOR_VERSION 8
41 #define ECORE_MINOR_VERSION 33
42 #define ECORE_REVISION_VERSION 5
43 #define ECORE_ENGINEERING_VERSION 0
44
45 #define ECORE_VERSION \
46 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
47 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
48
49 #define STORM_FW_VERSION \
50 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
51 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
52
53 #define MAX_HWFNS_PER_DEVICE 2
54 #define NAME_SIZE 16
55 #define ARRAY_DECL static const
56 #define ECORE_WFQ_UNIT 100
57
58 /* Constants */
59 #define ECORE_WID_SIZE (1024)
60 #define ECORE_MIN_WIDS (4)
61
62 /* Configurable */
63 #define ECORE_PF_DEMS_SIZE (4)
64
65 /* cau states */
66 enum ecore_coalescing_mode {
67 ECORE_COAL_MODE_DISABLE,
68 ECORE_COAL_MODE_ENABLE
69 };
70
71 enum ecore_nvm_cmd {
72 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
73 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
74 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
75 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
76 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
77 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
78 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
79 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
80 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
81 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
82 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
83 ECORE_ENCRYPT_PASSWORD = DRV_MSG_CODE_ENCRYPT_PASSWORD,
84 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
85 };
86
87 #ifndef LINUX_REMOVE
88 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \
89 !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI) && \
90 !defined(CONFIG_ECORE_IWARP)
91 #define CONFIG_ECORE_L2
92 #define CONFIG_ECORE_SRIOV
93 #define CONFIG_ECORE_ROCE
94 #define CONFIG_ECORE_IWARP
95 #define CONFIG_ECORE_LL2
96 #define CONFIG_ECORE_RDMA
97 #define ECORE_CONFIG_DIRECT_HWFN
98 #define QLNX_ENABLE_IWARP
99 #endif
100 #endif
101
102 /* helpers */
103 #ifndef __EXTRACT__LINUX__IF__
104 #define MASK_FIELD(_name, _value) \
105 ((_value) &= (_name##_MASK))
106
107 #define FIELD_VALUE(_name, _value) \
108 ((_value & _name##_MASK) << _name##_SHIFT)
109
110 #define SET_FIELD(value, name, flag) \
111 do { \
112 (value) &= ~(name##_MASK << name##_SHIFT); \
113 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
114 } while (0)
115
116 #define GET_FIELD(value, name) \
117 (((value) >> (name##_SHIFT)) & name##_MASK)
118
119 #define GET_MFW_FIELD(name, field) \
120 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
121
122 #define SET_MFW_FIELD(name, field, value) \
123 do { \
124 (name) &= ~(field ## _MASK); \
125 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
126 } while (0)
127 #endif
128
DB_ADDR(u32 cid,u32 DEMS)129 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
130 {
131 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
132 (cid * ECORE_PF_DEMS_SIZE);
133
134 return db_addr;
135 }
136
DB_ADDR_VF(u32 cid,u32 DEMS)137 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
138 {
139 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
140 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
141
142 return db_addr;
143 }
144
145 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
146 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \
147 ~((1<<(p_hwfn->p_dev->cache_shift))-1))
148
149 #ifndef LINUX_REMOVE
150 #ifndef U64_HI
151 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
152 #endif
153
154 #ifndef U64_LO
155 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
156 #endif
157 #endif
158
159 #ifndef __EXTRACT__LINUX__IF__
160 #ifndef UEFI
161 /* Debug print definitions */
162 #define DP_ERR(p_dev, fmt, ...) \
163 do { \
164 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
165 __func__, __LINE__, \
166 (p_dev)->name ? (p_dev)->name : "", \
167 ##__VA_ARGS__); \
168 } while (0)
169
170 #define DP_NOTICE(p_dev, is_assert, fmt, ...) \
171 do { \
172 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \
173 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
174 __func__, __LINE__, \
175 (p_dev)->name ? (p_dev)->name : "", \
176 ##__VA_ARGS__); \
177 OSAL_ASSERT(!is_assert); \
178 } \
179 } while (0)
180
181 #define DP_INFO(p_dev, fmt, ...) \
182 do { \
183 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \
184 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
185 __func__, __LINE__, \
186 (p_dev)->name ? (p_dev)->name : "", \
187 ##__VA_ARGS__); \
188 } \
189 } while (0)
190
191 #define DP_VERBOSE(p_dev, module, fmt, ...) \
192 do { \
193 if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \
194 ((p_dev)->dp_module & module))) { \
195 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
196 __func__, __LINE__, \
197 (p_dev)->name ? (p_dev)->name : "", \
198 ##__VA_ARGS__); \
199 } \
200 } while (0)
201 #endif
202
203 enum DP_LEVEL {
204 ECORE_LEVEL_VERBOSE = 0x0,
205 ECORE_LEVEL_INFO = 0x1,
206 ECORE_LEVEL_NOTICE = 0x2,
207 ECORE_LEVEL_ERR = 0x3,
208 };
209
210 #define ECORE_LOG_LEVEL_SHIFT (30)
211 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
212 #define ECORE_LOG_INFO_MASK (0x40000000)
213 #define ECORE_LOG_NOTICE_MASK (0x80000000)
214
215 enum DP_MODULE {
216 #ifndef LINUX_REMOVE
217 ECORE_MSG_DRV = 0x0001,
218 ECORE_MSG_PROBE = 0x0002,
219 ECORE_MSG_LINK = 0x0004,
220 ECORE_MSG_TIMER = 0x0008,
221 ECORE_MSG_IFDOWN = 0x0010,
222 ECORE_MSG_IFUP = 0x0020,
223 ECORE_MSG_RX_ERR = 0x0040,
224 ECORE_MSG_TX_ERR = 0x0080,
225 ECORE_MSG_TX_QUEUED = 0x0100,
226 ECORE_MSG_INTR = 0x0200,
227 ECORE_MSG_TX_DONE = 0x0400,
228 ECORE_MSG_RX_STATUS = 0x0800,
229 ECORE_MSG_PKTDATA = 0x1000,
230 ECORE_MSG_HW = 0x2000,
231 ECORE_MSG_WOL = 0x4000,
232 #endif
233 ECORE_MSG_SPQ = 0x10000,
234 ECORE_MSG_STATS = 0x20000,
235 ECORE_MSG_DCB = 0x40000,
236 ECORE_MSG_IOV = 0x80000,
237 ECORE_MSG_SP = 0x100000,
238 ECORE_MSG_STORAGE = 0x200000,
239 ECORE_MSG_OOO = 0x200000,
240 ECORE_MSG_CXT = 0x800000,
241 ECORE_MSG_LL2 = 0x1000000,
242 ECORE_MSG_ILT = 0x2000000,
243 ECORE_MSG_RDMA = 0x4000000,
244 ECORE_MSG_DEBUG = 0x8000000,
245 /* to be added...up to 0x8000000 */
246 };
247 #endif
248
249 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
250
251 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
252 (val == (cond1) ? true1 : \
253 (val == (cond2) ? true2 : def))
254
255 /* forward */
256 struct ecore_ptt_pool;
257 struct ecore_spq;
258 struct ecore_sb_info;
259 struct ecore_sb_attn_info;
260 struct ecore_cxt_mngr;
261 struct ecore_dma_mem;
262 struct ecore_sb_sp_info;
263 struct ecore_ll2_info;
264 struct ecore_l2_info;
265 struct ecore_igu_info;
266 struct ecore_mcp_info;
267 struct ecore_dcbx_info;
268 struct ecore_llh_info;
269
270 struct ecore_rt_data {
271 u32 *init_val;
272 bool *b_valid;
273 };
274
275 enum ecore_tunn_mode {
276 ECORE_MODE_L2GENEVE_TUNN,
277 ECORE_MODE_IPGENEVE_TUNN,
278 ECORE_MODE_L2GRE_TUNN,
279 ECORE_MODE_IPGRE_TUNN,
280 ECORE_MODE_VXLAN_TUNN,
281 };
282
283 enum ecore_tunn_clss {
284 ECORE_TUNN_CLSS_MAC_VLAN,
285 ECORE_TUNN_CLSS_MAC_VNI,
286 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
287 ECORE_TUNN_CLSS_INNER_MAC_VNI,
288 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
289 MAX_ECORE_TUNN_CLSS,
290 };
291
292 struct ecore_tunn_update_type {
293 bool b_update_mode;
294 bool b_mode_enabled;
295 enum ecore_tunn_clss tun_cls;
296 };
297
298 struct ecore_tunn_update_udp_port {
299 bool b_update_port;
300 u16 port;
301 };
302
303 struct ecore_tunnel_info {
304 struct ecore_tunn_update_type vxlan;
305 struct ecore_tunn_update_type l2_geneve;
306 struct ecore_tunn_update_type ip_geneve;
307 struct ecore_tunn_update_type l2_gre;
308 struct ecore_tunn_update_type ip_gre;
309
310 struct ecore_tunn_update_udp_port vxlan_port;
311 struct ecore_tunn_update_udp_port geneve_port;
312
313 bool b_update_rx_cls;
314 bool b_update_tx_cls;
315 };
316
317 /* The PCI personality is not quite synonymous to protocol ID:
318 * 1. All personalities need CORE connections
319 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
320 */
321 enum ecore_pci_personality {
322 ECORE_PCI_ETH,
323 ECORE_PCI_FCOE,
324 ECORE_PCI_ISCSI,
325 ECORE_PCI_ETH_ROCE,
326 ECORE_PCI_ETH_IWARP,
327 ECORE_PCI_ETH_RDMA,
328 ECORE_PCI_DEFAULT /* default in shmem */
329 };
330
331 /* All VFs are symetric, all counters are PF + all VFs */
332 struct ecore_qm_iids {
333 u32 cids;
334 u32 vf_cids;
335 u32 tids;
336 };
337
338 /* The PCI relax ordering is either taken care by management FW or can be
339 * enable/disable by ecore client.
340 */
341 enum ecore_pci_rlx_odr {
342 ECORE_DEFAULT_RLX_ODR,
343 ECORE_ENABLE_RLX_ODR,
344 ECORE_DISABLE_RLX_ODR
345 };
346
347 #define MAX_PF_PER_PORT 8
348
349 /* HW / FW resources, output of features supported below, most information
350 * is received from MFW.
351 */
352 enum ecore_resources {
353 ECORE_L2_QUEUE,
354 ECORE_VPORT,
355 ECORE_RSS_ENG,
356 ECORE_PQ,
357 ECORE_RL,
358 ECORE_MAC,
359 ECORE_VLAN,
360 ECORE_RDMA_CNQ_RAM,
361 ECORE_ILT,
362 ECORE_LL2_QUEUE,
363 ECORE_CMDQS_CQS,
364 ECORE_RDMA_STATS_QUEUE,
365 ECORE_BDQ,
366
367 /* This is needed only internally for matching against the IGU.
368 * In case of legacy MFW, would be set to `0'.
369 */
370 ECORE_SB,
371
372 ECORE_MAX_RESC,
373 };
374
375 /* Features that require resources, given as input to the resource management
376 * algorithm, the output are the resources above
377 */
378 enum ecore_feature {
379 ECORE_PF_L2_QUE,
380 ECORE_PF_TC,
381 ECORE_VF,
382 ECORE_EXTRA_VF_QUE,
383 ECORE_VMQ,
384 ECORE_RDMA_CNQ,
385 ECORE_ISCSI_CQ,
386 ECORE_FCOE_CQ,
387 ECORE_VF_L2_QUE,
388 ECORE_MAX_FEATURES,
389 };
390
391 enum ecore_port_mode {
392 ECORE_PORT_MODE_DE_2X40G,
393 ECORE_PORT_MODE_DE_2X50G,
394 ECORE_PORT_MODE_DE_1X100G,
395 ECORE_PORT_MODE_DE_4X10G_F,
396 ECORE_PORT_MODE_DE_4X10G_E,
397 ECORE_PORT_MODE_DE_4X20G,
398 ECORE_PORT_MODE_DE_1X40G,
399 ECORE_PORT_MODE_DE_2X25G,
400 ECORE_PORT_MODE_DE_1X25G,
401 ECORE_PORT_MODE_DE_4X25G,
402 ECORE_PORT_MODE_DE_2X10G,
403 };
404
405 enum ecore_dev_cap {
406 ECORE_DEV_CAP_ETH,
407 ECORE_DEV_CAP_FCOE,
408 ECORE_DEV_CAP_ISCSI,
409 ECORE_DEV_CAP_ROCE,
410 ECORE_DEV_CAP_IWARP
411 };
412
413 #ifndef __EXTRACT__LINUX__IF__
414 enum ecore_hw_err_type {
415 ECORE_HW_ERR_FAN_FAIL,
416 ECORE_HW_ERR_MFW_RESP_FAIL,
417 ECORE_HW_ERR_HW_ATTN,
418 ECORE_HW_ERR_DMAE_FAIL,
419 ECORE_HW_ERR_RAMROD_FAIL,
420 ECORE_HW_ERR_FW_ASSERT,
421 };
422 #endif
423
424 enum ecore_wol_support {
425 ECORE_WOL_SUPPORT_NONE,
426 ECORE_WOL_SUPPORT_PME,
427 };
428
429 enum ecore_db_rec_exec {
430 DB_REC_DRY_RUN,
431 DB_REC_REAL_DEAL,
432 DB_REC_ONCE,
433 };
434
435 struct ecore_hw_info {
436 /* PCI personality */
437 enum ecore_pci_personality personality;
438 #define ECORE_IS_RDMA_PERSONALITY(dev) \
439 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
440 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
441 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
442 #define ECORE_IS_ROCE_PERSONALITY(dev) \
443 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
444 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
445 #define ECORE_IS_IWARP_PERSONALITY(dev) \
446 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
447 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
448 #define ECORE_IS_L2_PERSONALITY(dev) \
449 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
450 ECORE_IS_RDMA_PERSONALITY(dev))
451 #define ECORE_IS_FCOE_PERSONALITY(dev) \
452 ((dev)->hw_info.personality == ECORE_PCI_FCOE)
453 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
454 ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
455
456 /* Resource Allocation scheme results */
457 u32 resc_start[ECORE_MAX_RESC];
458 u32 resc_num[ECORE_MAX_RESC];
459 u32 feat_num[ECORE_MAX_FEATURES];
460
461 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
462 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
463 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
464 RESC_NUM(_p_hwfn, resc))
465 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
466
467 /* Amount of traffic classes HW supports */
468 u8 num_hw_tc;
469
470 /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */
471 u8 num_active_tc;
472
473 /* The traffic class used by PF for it's offloaded protocol */
474 u8 offload_tc;
475
476 u32 concrete_fid;
477 u16 opaque_fid;
478 u16 ovlan;
479 u32 part_num[4];
480
481 #ifndef ETH_ALEN
482 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */
483 #endif
484 unsigned char hw_mac_addr[ETH_ALEN];
485
486 u16 num_iscsi_conns;
487 u16 num_fcoe_conns;
488
489 struct ecore_igu_info *p_igu_info;
490 /* Sriov */
491 u8 max_chains_per_vf;
492
493 u32 port_mode;
494 u32 hw_mode;
495 unsigned long device_capabilities;
496
497 #ifndef __EXTRACT__LINUX__THROW__
498 /* Default DCBX mode */
499 u8 dcbx_mode;
500 #endif
501
502 u16 mtu;
503
504 enum ecore_wol_support b_wol_support;
505 };
506
507 /* maximun size of read/write commands (HW limit) */
508 #define DMAE_MAX_RW_SIZE 0x2000
509
510 struct ecore_dmae_info {
511 /* Spinlock for synchronizing access to functions */
512 osal_spinlock_t lock;
513
514 bool b_mem_ready;
515
516 u8 channel;
517
518 dma_addr_t completion_word_phys_addr;
519
520 /* The memory location where the DMAE writes the completion
521 * value when an operation is finished on this context.
522 */
523 u32 *p_completion_word;
524
525 dma_addr_t intermediate_buffer_phys_addr;
526
527 /* An intermediate buffer for DMAE operations that use virtual
528 * addresses - data is DMA'd to/from this buffer and then
529 * memcpy'd to/from the virtual address
530 */
531 u32 *p_intermediate_buffer;
532
533 dma_addr_t dmae_cmd_phys_addr;
534 struct dmae_cmd *p_dmae_cmd;
535 };
536
537 struct ecore_wfq_data {
538 u32 default_min_speed; /* When wfq feature is not configured */
539 u32 min_speed; /* when feature is configured for any 1 vport */
540 bool configured;
541 };
542
543 struct ecore_qm_info {
544 struct init_qm_pq_params *qm_pq_params;
545 struct init_qm_vport_params *qm_vport_params;
546 struct init_qm_port_params *qm_port_params;
547 u16 start_pq;
548 u8 start_vport;
549 u16 pure_lb_pq;
550 u16 offload_pq;
551 u16 low_latency_pq;
552 u16 pure_ack_pq;
553 u16 ooo_pq;
554 u16 first_vf_pq;
555 u16 first_mcos_pq;
556 u16 first_rl_pq;
557 u16 num_pqs;
558 u16 num_vf_pqs;
559 u8 num_vports;
560 u8 max_phys_tcs_per_port;
561 u8 ooo_tc;
562 bool pf_rl_en;
563 bool pf_wfq_en;
564 bool vport_rl_en;
565 bool vport_wfq_en;
566 u8 pf_wfq;
567 u32 pf_rl;
568 struct ecore_wfq_data *wfq_data;
569 u8 num_pf_rls;
570 };
571
572 struct ecore_db_recovery_info {
573 osal_list_t list;
574 osal_spinlock_t lock;
575 u32 db_recovery_counter;
576 };
577
578 struct storm_stats {
579 u32 address;
580 u32 len;
581 };
582
583 struct ecore_fw_data {
584 #ifdef CONFIG_ECORE_BINARY_FW
585 struct fw_ver_info *fw_ver_info;
586 #endif
587 const u8 *modes_tree_buf;
588 const union init_op *init_ops;
589 const u32 *arr_data;
590 u32 init_ops_size;
591 };
592
593 enum ecore_mf_mode_bit {
594 /* Supports PF-classification based on tag */
595 ECORE_MF_OVLAN_CLSS,
596
597 /* Supports PF-classification based on MAC */
598 ECORE_MF_LLH_MAC_CLSS,
599
600 /* Supports PF-classification based on protocol type */
601 ECORE_MF_LLH_PROTO_CLSS,
602
603 /* Requires a default PF to be set */
604 ECORE_MF_NEED_DEF_PF,
605
606 /* Allow LL2 to multicast/broadcast */
607 ECORE_MF_LL2_NON_UNICAST,
608
609 /* Allow Cross-PF [& child VFs] Tx-switching */
610 ECORE_MF_INTER_PF_SWITCH,
611
612 /* TODO - if we ever re-utilize any of this logic, we can rename */
613 ECORE_MF_UFP_SPECIFIC,
614
615 ECORE_MF_DISABLE_ARFS,
616
617 /* Use vlan for steering */
618 ECORE_MF_8021Q_TAGGING,
619
620 /* Use stag for steering */
621 ECORE_MF_8021AD_TAGGING,
622 };
623
624 enum ecore_ufp_mode {
625 ECORE_UFP_MODE_ETS,
626 ECORE_UFP_MODE_VNIC_BW,
627 ECORE_UFP_MODE_UNKNOWN
628 };
629
630 enum ecore_ufp_pri_type {
631 ECORE_UFP_PRI_OS,
632 ECORE_UFP_PRI_VNIC,
633 ECORE_UFP_PRI_UNKNOWN
634 };
635
636 struct ecore_ufp_info {
637 enum ecore_ufp_pri_type pri_type;
638 enum ecore_ufp_mode mode;
639 u8 tc;
640 };
641
642 enum BAR_ID {
643 BAR_ID_0, /* used for GRC */
644 BAR_ID_1 /* Used for doorbells */
645 };
646
647 struct ecore_hwfn {
648 struct ecore_dev *p_dev;
649 u8 my_id; /* ID inside the PF */
650 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
651 u8 rel_pf_id; /* Relative to engine*/
652 u8 abs_pf_id;
653 #define ECORE_PATH_ID(_p_hwfn) \
654 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
655 u8 port_id;
656 bool b_active;
657
658 u32 dp_module;
659 u8 dp_level;
660 char name[NAME_SIZE];
661 void *dp_ctx;
662
663 bool hw_init_done;
664
665 u8 num_funcs_on_engine;
666 u8 enabled_func_idx;
667
668 /* BAR access */
669 void OSAL_IOMEM *regview;
670 void OSAL_IOMEM *doorbells;
671 u64 db_phys_addr;
672 unsigned long db_size;
673
674 #ifndef LINUX_REMOVE
675 u64 reg_offset;
676 u64 db_offset;
677 #endif
678
679 /* PTT pool */
680 struct ecore_ptt_pool *p_ptt_pool;
681
682 /* HW info */
683 struct ecore_hw_info hw_info;
684
685 /* rt_array (for init-tool) */
686 struct ecore_rt_data rt_data;
687
688 /* SPQ */
689 struct ecore_spq *p_spq;
690
691 /* EQ */
692 struct ecore_eq *p_eq;
693
694 /* Consolidate Q*/
695 struct ecore_consq *p_consq;
696
697 /* Slow-Path definitions */
698 osal_dpc_t sp_dpc;
699 bool b_sp_dpc_enabled;
700
701 struct ecore_ptt *p_main_ptt;
702 struct ecore_ptt *p_dpc_ptt;
703
704 /* PTP will be used only by the leading function.
705 * Usage of all PTP-apis should be synchronized as result.
706 */
707 struct ecore_ptt *p_ptp_ptt;
708
709 struct ecore_sb_sp_info *p_sp_sb;
710 struct ecore_sb_attn_info *p_sb_attn;
711
712 /* Protocol related */
713 bool using_ll2;
714 struct ecore_ll2_info *p_ll2_info;
715 struct ecore_ooo_info *p_ooo_info;
716 struct ecore_iscsi_info *p_iscsi_info;
717 struct ecore_fcoe_info *p_fcoe_info;
718 struct ecore_rdma_info *p_rdma_info;
719 struct ecore_pf_params pf_params;
720
721 bool b_rdma_enabled_in_prs;
722 u32 rdma_prs_search_reg;
723
724 struct ecore_cxt_mngr *p_cxt_mngr;
725
726 /* Flag indicating whether interrupts are enabled or not*/
727 bool b_int_enabled;
728 bool b_int_requested;
729
730 /* True if the driver requests for the link */
731 bool b_drv_link_init;
732
733 struct ecore_vf_iov *vf_iov_info;
734 struct ecore_pf_iov *pf_iov_info;
735 struct ecore_mcp_info *mcp_info;
736 struct ecore_dcbx_info *p_dcbx_info;
737 struct ecore_ufp_info ufp_info;
738
739 struct ecore_dmae_info dmae_info;
740
741 /* QM init */
742 struct ecore_qm_info qm_info;
743
744 /* Buffer for unzipping firmware data */
745 #ifdef CONFIG_ECORE_ZIPPED_FW
746 void *unzip_buf;
747 #endif
748
749 struct dbg_tools_data dbg_info;
750
751 /* PWM region specific data */
752 u16 wid_count;
753 u32 dpi_size;
754 u32 dpi_count;
755 u32 dpi_start_offset; /* this is used to
756 * calculate th
757 * doorbell address
758 */
759
760 /* If one of the following is set then EDPM shouldn't be used */
761 u8 dcbx_no_edpm;
762 u8 db_bar_no_edpm;
763
764 /* L2-related */
765 struct ecore_l2_info *p_l2_info;
766
767 /* Mechanism for recovering from doorbell drop */
768 struct ecore_db_recovery_info db_recovery_info;
769 };
770
771 #ifndef __EXTRACT__LINUX__THROW__
772 enum ecore_mf_mode {
773 ECORE_MF_DEFAULT,
774 ECORE_MF_OVLAN,
775 ECORE_MF_NPAR,
776 ECORE_MF_UFP,
777 };
778 #endif
779
780 #ifndef __EXTRACT__LINUX__IF__
781 enum ecore_dev_type {
782 ECORE_DEV_TYPE_BB,
783 ECORE_DEV_TYPE_AH,
784 ECORE_DEV_TYPE_E5,
785 };
786 #endif
787
788 struct ecore_dev {
789 u32 dp_module;
790 u8 dp_level;
791 char name[NAME_SIZE];
792 void *dp_ctx;
793
794 enum ecore_dev_type type;
795 /* Translate type/revision combo into the proper conditions */
796 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
797 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
798 #ifndef ASIC_ONLY
799 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
800 (CHIP_REV_IS_TEDIBEAR(dev)))
801 #else
802 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
803 #endif
804 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
805 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
806 #define ECORE_IS_E4(dev) (ECORE_IS_BB(dev) || ECORE_IS_AH(dev))
807 #define ECORE_IS_E5(dev) ((dev)->type == ECORE_DEV_TYPE_E5)
808
809 #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false)
810
811 u16 vendor_id;
812 u16 device_id;
813 #define ECORE_DEV_ID_MASK 0xff00
814 #define ECORE_DEV_ID_MASK_BB 0x1600
815 #define ECORE_DEV_ID_MASK_AH 0x8000
816 #define ECORE_DEV_ID_MASK_E5 0x8100
817
818 u16 chip_num;
819 #define CHIP_NUM_MASK 0xffff
820 #define CHIP_NUM_SHIFT 0
821
822 u8 chip_rev;
823 #define CHIP_REV_MASK 0xf
824 #define CHIP_REV_SHIFT 0
825 #ifndef ASIC_ONLY
826 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
827 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
828 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
829 #define CHIP_REV_IS_EMUL(_p_dev) \
830 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
831 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
832 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
833 #define CHIP_REV_IS_FPGA(_p_dev) \
834 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
835 #define CHIP_REV_IS_SLOW(_p_dev) \
836 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
837 #define CHIP_REV_IS_A0(_p_dev) \
838 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
839 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
840 #define CHIP_REV_IS_B0(_p_dev) \
841 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
842 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
843 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
844 #else
845 #define CHIP_REV_IS_A0(_p_dev) \
846 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
847 #define CHIP_REV_IS_B0(_p_dev) \
848 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
849 #endif
850
851 u8 chip_metal;
852 #define CHIP_METAL_MASK 0xff
853 #define CHIP_METAL_SHIFT 0
854
855 u8 chip_bond_id;
856 #define CHIP_BOND_ID_MASK 0xff
857 #define CHIP_BOND_ID_SHIFT 0
858
859 u8 num_engines;
860 u8 num_ports;
861 u8 num_ports_in_engine;
862 u8 num_funcs_in_port;
863
864 u8 path_id;
865
866 unsigned long mf_bits;
867 #ifndef __EXTRACT__LINUX__THROW__
868 enum ecore_mf_mode mf_mode;
869 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
870 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
871 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
872 #endif
873
874 int pcie_width;
875 int pcie_speed;
876
877 /* Add MF related configuration */
878 u8 mcp_rev;
879 u8 boot_mode;
880
881 /* WoL related configurations */
882 u8 wol_config;
883 u8 wol_mac[ETH_ALEN];
884
885 u32 int_mode;
886 enum ecore_coalescing_mode int_coalescing_mode;
887 u16 rx_coalesce_usecs;
888 u16 tx_coalesce_usecs;
889
890 /* Start Bar offset of first hwfn */
891 void OSAL_IOMEM *regview;
892 void OSAL_IOMEM *doorbells;
893 u64 db_phys_addr;
894 unsigned long db_size;
895
896 /* PCI */
897 u8 cache_shift;
898
899 /* Init */
900 const struct iro *iro_arr;
901 #define IRO (p_hwfn->p_dev->iro_arr)
902
903 /* HW functions */
904 u8 num_hwfns;
905 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
906 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
907 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
908
909 /* Engine affinity */
910 u8 l2_affin_hint;
911 u8 fir_affin;
912 u8 iwarp_affin;
913 /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
914 #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin])
915 /* Macro for getting the engine-affinitized hwfn for iWARP */
916 #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin])
917 /* Generic macro for getting the engine-affinitized hwfn */
918 #define ECORE_AFFIN_HWFN(dev) \
919 (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
920 ECORE_IWARP_AFFIN_HWFN(dev) : \
921 ECORE_FIR_AFFIN_HWFN(dev))
922 /* Macro for getting the index (0/1) of the engine-affinitized hwfn */
923 #define ECORE_AFFIN_HWFN_IDX(dev) \
924 (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
925
926 /* SRIOV */
927 struct ecore_hw_sriov_info *p_iov_info;
928 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
929 struct ecore_tunnel_info tunnel;
930 bool b_is_vf;
931 bool b_dont_override_vf_msix;
932
933 u32 drv_type;
934
935 u32 rdma_max_sge;
936 u32 rdma_max_inline;
937 u32 rdma_max_srq_sge;
938 u8 ilt_page_size;
939
940 struct ecore_eth_stats *reset_stats;
941 struct ecore_fw_data *fw_data;
942
943 u32 mcp_nvm_resp;
944
945 /* Recovery */
946 bool recov_in_prog;
947
948 /* Indicates whether should prevent attentions from being reasserted */
949 bool attn_clr_en;
950
951 /* Indicates whether allowing the MFW to collect a crash dump */
952 bool allow_mdump;
953
954 /* Indicates if the reg_fifo is checked after any register access */
955 bool chk_reg_fifo;
956
957 #ifndef ASIC_ONLY
958 bool b_is_emul_full;
959 #endif
960 /* LLH info */
961 u8 ppfid_bitmap;
962 struct ecore_llh_info *p_llh_info;
963 };
964
965 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
966 : MAX_NUM_VFS_K2)
967 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
968 : MAX_NUM_L2_QUEUES_K2)
969 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
970 : MAX_NUM_PORTS_K2)
971 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
972 : MAX_SB_PER_PATH_K2)
973 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
974 : MAX_NUM_PFS_K2)
975
976 #ifndef LINUX_REMOVE
977 #define CRC8_TABLE_SIZE 256
978 #endif
979
980 /**
981 * @brief ecore_concrete_to_sw_fid - get the sw function id from
982 * the concrete value.
983 *
984 * @param concrete_fid
985 *
986 * @return OSAL_INLINE u8
987 */
ecore_concrete_to_sw_fid(u32 concrete_fid)988 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
989 {
990 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
991 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
992 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
993 u8 sw_fid;
994
995 if (vf_valid)
996 sw_fid = vfid + MAX_NUM_PFS;
997 else
998 sw_fid = pfid;
999
1000 return sw_fid;
1001 }
1002
1003 #define PKT_LB_TC 9
1004 #define MAX_NUM_VOQS_E4 20
1005
1006 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
1007 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
1008 struct ecore_ptt *p_ptt,
1009 u32 min_pf_rate);
1010
1011 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
1012 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
1013 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
1014 int ecore_device_num_engines(struct ecore_dev *p_dev);
1015 int ecore_device_num_ports(struct ecore_dev *p_dev);
1016 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
1017 u8 *mac);
1018
1019 /* Flags for indication of required queues */
1020 #define PQ_FLAGS_RLS (1 << 0)
1021 #define PQ_FLAGS_MCOS (1 << 1)
1022 #define PQ_FLAGS_LB (1 << 2)
1023 #define PQ_FLAGS_OOO (1 << 3)
1024 #define PQ_FLAGS_ACK (1 << 4)
1025 #define PQ_FLAGS_OFLD (1 << 5)
1026 #define PQ_FLAGS_VFS (1 << 6)
1027 #define PQ_FLAGS_LLT (1 << 7)
1028
1029 /* physical queue index for cm context intialization */
1030 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
1031 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
1032 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
1033 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
1034
1035 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
1036
1037 /* doorbell recovery mechanism */
1038 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
1039 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
1040 enum ecore_db_rec_exec db_exec);
1041
1042 /* amount of resources used in qm init */
1043 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
1044 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
1045 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
1046 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
1047 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
1048
1049 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
1050 ecore_device_num_ports((_p_hwfn)->p_dev))
1051
1052 /* The PFID<->PPFID calculation is based on the relative index of a PF on its
1053 * port. In BB there is a bug in the LLH in which the PPFID is actually engine
1054 * based, and thus it equals the PFID.
1055 */
1056 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
1057 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1058 (abs_ppfid) : \
1059 (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
1060 MFW_PORT(_p_hwfn))
1061 #define ECORE_PPFID_BY_PFID(_p_hwfn) \
1062 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1063 (_p_hwfn)->rel_pf_id : \
1064 (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
1065
1066 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1067 struct ecore_ptt *p_ptt, u32 addr,
1068 u32 val);
1069
1070 /* Utility functions for dumping the content of the NIG LLH filters */
1071 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
1072 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
1073
1074 #endif /* __ECORE_H */
1075