1 /* $OpenBSD: pchb.c,v 1.94 2023/01/30 10:49:05 jsg Exp $ */
2 /* $NetBSD: pchb.c,v 1.65 2007/08/15 02:26:13 markd Exp $ */
3
4 /*
5 * Copyright (c) 2000 Michael Shalayeff
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 */
29 /*-
30 * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
31 * All rights reserved.
32 *
33 * This code is derived from software contributed to The NetBSD Foundation
34 * by Jason R. Thorpe.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
46 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
47 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
48 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
49 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
50 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
51 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
52 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
53 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
54 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
55 * POSSIBILITY OF SUCH DAMAGE.
56 */
57
58 #include <sys/param.h>
59 #include <sys/systm.h>
60 #include <sys/device.h>
61 #include <sys/timeout.h>
62
63 #include <machine/bus.h>
64
65 #include <dev/pci/pcivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcidevs.h>
68
69 #include <dev/pci/agpvar.h>
70 #include <dev/pci/ppbreg.h>
71
72 #include <dev/ic/i82802reg.h>
73
74 #include "agp.h"
75
76 #define PCISET_INTEL_BRIDGETYPE_MASK 0x3
77 #define PCISET_INTEL_TYPE_COMPAT 0x1
78 #define PCISET_INTEL_TYPE_AUX 0x2
79
80 #define PCISET_INTEL_BUSCONFIG_REG 0x48
81 #define PCISET_INTEL_BRIDGE_NUMBER(reg) (((reg) >> 8) & 0xff)
82 #define PCISET_INTEL_PCI_BUS_NUMBER(reg) (((reg) >> 16) & 0xff)
83
84 #define PCISET_INTEL_SDRAMC_REG 0x74
85 #define PCISET_INTEL_SDRAMC_IPDLT (1 << 24)
86
87 /* XXX should be in dev/ic/i82424{reg.var}.h */
88 #define I82424_CPU_BCTL_REG 0x53
89 #define I82424_PCI_BCTL_REG 0x54
90
91 #define I82424_BCTL_CPUMEM_POSTEN 0x01
92 #define I82424_BCTL_CPUPCI_POSTEN 0x02
93 #define I82424_BCTL_PCIMEM_BURSTEN 0x01
94 #define I82424_BCTL_PCI_BURSTEN 0x02
95
96 /* XXX should be in dev/ic/amd64htreg.h */
97 #define AMD64HT_LDT0_BUS 0x94
98 #define AMD64HT_LDT0_TYPE 0x98
99 #define AMD64HT_LDT1_BUS 0xb4
100 #define AMD64HT_LDT1_TYPE 0xb8
101 #define AMD64HT_LDT2_BUS 0xd4
102 #define AMD64HT_LDT2_TYPE 0xd8
103 #define AMD64HT_LDT3_BUS 0xf4
104 #define AMD64HT_LDT3_TYPE 0xf8
105
106 #define AMD64HT_NUM_LDT 4
107
108 #define AMD64HT_LDT_TYPE_MASK 0x0000001f
109 #define AMD64HT_LDT_INIT_COMPLETE 0x00000002
110 #define AMD64HT_LDT_NC 0x00000004
111
112 #define AMD64HT_LDT_SEC_BUS_NUM(reg) (((reg) >> 8) & 0xff)
113
114 struct pchb_softc {
115 struct device sc_dev;
116
117 bus_space_tag_t sc_bt;
118 bus_space_handle_t sc_bh;
119
120 /* rng stuff */
121 int sc_rng_active;
122 int sc_rng_ax;
123 int sc_rng_i;
124 struct timeout sc_rng_to;
125 };
126
127 int pchbmatch(struct device *, void *, void *);
128 void pchbattach(struct device *, struct device *, void *);
129 int pchbactivate(struct device *, int);
130
131 const struct cfattach pchb_ca = {
132 sizeof(struct pchb_softc), pchbmatch, pchbattach, NULL,
133 pchbactivate
134 };
135
136 struct cfdriver pchb_cd = {
137 NULL, "pchb", DV_DULL
138 };
139
140 int pchb_print(void *, const char *);
141 void pchb_rnd(void *);
142 void pchb_amd64ht_attach(struct device *, struct pci_attach_args *, int);
143
144 int
pchbmatch(struct device * parent,void * match,void * aux)145 pchbmatch(struct device *parent, void *match, void *aux)
146 {
147 struct pci_attach_args *pa = aux;
148
149 #ifdef __i386__
150 /* XXX work around broken via82x866 chipsets */
151 const struct pci_matchid via_devices[] = {
152 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_PWR },
153 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596 },
154 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596B_PM },
155 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_SMB }
156 };
157 if (pci_matchbyid(pa, via_devices,
158 sizeof(via_devices) / sizeof(via_devices[0])))
159 return (0);
160 #endif /* __i386__ */
161
162 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
163 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST)
164 return (1);
165
166 return (0);
167 }
168
169 void
pchbattach(struct device * parent,struct device * self,void * aux)170 pchbattach(struct device *parent, struct device *self, void *aux)
171 {
172 struct pchb_softc *sc = (struct pchb_softc *)self;
173 struct pci_attach_args *pa = aux;
174 struct pcibus_attach_args pba;
175 pcireg_t bcreg, bir;
176 u_char bdnum, pbnum;
177 pcitag_t tag;
178 int i, r;
179 int doattach = 0;
180
181 switch (PCI_VENDOR(pa->pa_id)) {
182 case PCI_VENDOR_AMD:
183 printf("\n");
184 switch (PCI_PRODUCT(pa->pa_id)) {
185 case PCI_PRODUCT_AMD_0F_HT:
186 case PCI_PRODUCT_AMD_10_HT:
187 for (i = 0; i < AMD64HT_NUM_LDT; i++)
188 pchb_amd64ht_attach(self, pa, i);
189 break;
190 }
191 break;
192 #ifdef __i386__
193 case PCI_VENDOR_RCC:
194 {
195 /*
196 * The variable below is a bit vector representing the
197 * Serverworks busses that have already been attached.
198 * Bit 0 represents bus 0 and so forth. The initial
199 * value is 1 because we never actually want to
200 * attach bus 0 since bus 0 is the mainbus.
201 */
202 static u_int32_t rcc_bus_visited = 1;
203
204 printf("\n");
205 bdnum = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x44);
206 if (bdnum >= (sizeof(rcc_bus_visited) * 8) ||
207 (rcc_bus_visited & (1 << bdnum)))
208 break;
209
210 rcc_bus_visited |= 1 << bdnum;
211
212 /*
213 * This host bridge has a second PCI bus.
214 * Configure it.
215 */
216 pbnum = bdnum;
217 doattach = 1;
218 break;
219 }
220 #endif
221 case PCI_VENDOR_INTEL:
222 switch (PCI_PRODUCT(pa->pa_id)) {
223 #ifdef __i386__
224 case PCI_PRODUCT_INTEL_82452_HB:
225 bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);
226 pbnum = PCISET_INTEL_BRIDGE_NUMBER(bcreg);
227 if (pbnum != 0xff) {
228 pbnum++;
229 doattach = 1;
230 }
231 break;
232 case PCI_PRODUCT_INTEL_82443BX_AGP: /* 82443BX AGP (PAC) */
233 case PCI_PRODUCT_INTEL_82443BX_NOAGP: /* 82443BX Host-PCI (no AGP) */
234 /*
235 * An incorrect address may be driven on the
236 * DRAM bus, resulting in memory data being
237 * fetched from the wrong location. This is
238 * the workaround.
239 */
240 if (PCI_REVISION(pa->pa_class) < 0x3) {
241 bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
242 PCISET_INTEL_SDRAMC_REG);
243 bcreg |= PCISET_INTEL_SDRAMC_IPDLT;
244 pci_conf_write(pa->pa_pc, pa->pa_tag,
245 PCISET_INTEL_SDRAMC_REG, bcreg);
246 }
247 break;
248 case PCI_PRODUCT_INTEL_PCI450_PB:
249 bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
250 PCISET_INTEL_BUSCONFIG_REG);
251 bdnum = PCISET_INTEL_BRIDGE_NUMBER(bcreg);
252 pbnum = PCISET_INTEL_PCI_BUS_NUMBER(bcreg);
253 switch (bdnum & PCISET_INTEL_BRIDGETYPE_MASK) {
254 default:
255 printf(": bdnum=%x (reserved)", bdnum);
256 break;
257 case PCISET_INTEL_TYPE_COMPAT:
258 printf(": Compatibility PB (bus %d)", pbnum);
259 break;
260 case PCISET_INTEL_TYPE_AUX:
261 printf(": Auxiliary PB (bus %d)", pbnum);
262 doattach = 1;
263 }
264 break;
265 case PCI_PRODUCT_INTEL_CDC:
266 bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
267 I82424_CPU_BCTL_REG);
268 if (bcreg & I82424_BCTL_CPUPCI_POSTEN) {
269 bcreg &= ~I82424_BCTL_CPUPCI_POSTEN;
270 pci_conf_write(pa->pa_pc, pa->pa_tag,
271 I82424_CPU_BCTL_REG, bcreg);
272 printf(": disabled CPU-PCI write posting");
273 }
274 break;
275 case PCI_PRODUCT_INTEL_82454NX:
276 pbnum = 0;
277 switch (pa->pa_device) {
278 case 18: /* PXB 0 bus A - primary bus */
279 break;
280 case 19: /* PXB 0 bus B */
281 /* read SUBA0 from MIOC */
282 tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
283 bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
284 pbnum = ((bcreg & 0x0000ff00) >> 8) + 1;
285 break;
286 case 20: /* PXB 1 bus A */
287 /* read BUSNO1 from MIOC */
288 tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
289 bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
290 pbnum = (bcreg & 0xff000000) >> 24;
291 break;
292 case 21: /* PXB 1 bus B */
293 /* read SUBA1 from MIOC */
294 tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
295 bcreg = pci_conf_read(pa->pa_pc, tag, 0xd4);
296 pbnum = (bcreg & 0x000000ff) + 1;
297 break;
298 }
299 if (pbnum != 0)
300 doattach = 1;
301 break;
302 /* RNG */
303 case PCI_PRODUCT_INTEL_82810_HB:
304 case PCI_PRODUCT_INTEL_82810_DC100_HB:
305 case PCI_PRODUCT_INTEL_82810E_HB:
306 case PCI_PRODUCT_INTEL_82815_HB:
307 case PCI_PRODUCT_INTEL_82820_HB:
308 case PCI_PRODUCT_INTEL_82840_HB:
309 case PCI_PRODUCT_INTEL_82850_HB:
310 case PCI_PRODUCT_INTEL_82860_HB:
311 #endif /* __i386__ */
312 case PCI_PRODUCT_INTEL_82915G_HB:
313 case PCI_PRODUCT_INTEL_82945G_HB:
314 case PCI_PRODUCT_INTEL_82925X_HB:
315 case PCI_PRODUCT_INTEL_82955X_HB:
316 sc->sc_bt = pa->pa_memt;
317 if (bus_space_map(sc->sc_bt, I82802_IOBASE,
318 I82802_IOSIZE, 0, &sc->sc_bh))
319 break;
320
321 /* probe and init rng */
322 if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
323 I82802_RNG_HWST) & I82802_RNG_HWST_PRESENT))
324 break;
325
326 /* enable RNG */
327 bus_space_write_1(sc->sc_bt, sc->sc_bh,
328 I82802_RNG_HWST,
329 bus_space_read_1(sc->sc_bt, sc->sc_bh,
330 I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE);
331
332 /* see if we can read anything */
333 for (i = 1000; i-- &&
334 !(bus_space_read_1(sc->sc_bt, sc->sc_bh,
335 I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV); )
336 DELAY(10);
337
338 if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
339 I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV))
340 break;
341
342 r = bus_space_read_1(sc->sc_bt, sc->sc_bh,
343 I82802_RNG_DATA);
344
345 timeout_set(&sc->sc_rng_to, pchb_rnd, sc);
346 sc->sc_rng_i = 4;
347 pchb_rnd(sc);
348 sc->sc_rng_active = 1;
349 break;
350 }
351 printf("\n");
352 break;
353 case PCI_VENDOR_VIATECH:
354 switch (PCI_PRODUCT(pa->pa_id)) {
355 case PCI_PRODUCT_VIATECH_VT8251_PCIE_0:
356 /*
357 * Bump the host bridge into PCI-PCI bridge
358 * mode by clearing magic bit on the VLINK
359 * device. This allows us to read the bus
360 * number for the PCI bus attached to this
361 * host bridge.
362 */
363 tag = pci_make_tag(pa->pa_pc, 0, 17, 7);
364 bcreg = pci_conf_read(pa->pa_pc, tag, 0xfc);
365 bcreg &= ~0x00000004; /* XXX Magic */
366 pci_conf_write(pa->pa_pc, tag, 0xfc, bcreg);
367
368 bir = pci_conf_read(pa->pa_pc,
369 pa->pa_tag, PPB_REG_BUSINFO);
370 pbnum = PPB_BUSINFO_PRIMARY(bir);
371 if (pbnum > 0)
372 doattach = 1;
373
374 /* Switch back to host bridge mode. */
375 bcreg |= 0x00000004; /* XXX Magic */
376 pci_conf_write(pa->pa_pc, tag, 0xfc, bcreg);
377 break;
378 }
379 printf("\n");
380 break;
381 default:
382 printf("\n");
383 break;
384 }
385
386 #if NAGP > 0
387 /*
388 * Intel IGD have an odd interface and attach at vga, however,
389 * in that mode they don't have the AGP cap bit, so this
390 * test should be sufficient
391 */
392 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
393 NULL, NULL) != 0) {
394 struct agp_attach_args aa;
395 aa.aa_busname = "agp";
396 aa.aa_pa = pa;
397
398 config_found(self, &aa, agpdev_print);
399 }
400 #endif /* NAGP > 0 */
401
402 if (doattach == 0)
403 return;
404
405 bzero(&pba, sizeof(pba));
406 pba.pba_busname = "pci";
407 pba.pba_iot = pa->pa_iot;
408 pba.pba_memt = pa->pa_memt;
409 pba.pba_dmat = pa->pa_dmat;
410 pba.pba_busex = pa->pa_busex;
411 pba.pba_domain = pa->pa_domain;
412 pba.pba_bus = pbnum;
413 pba.pba_pc = pa->pa_pc;
414 config_found(self, &pba, pchb_print);
415 }
416
417 int
pchbactivate(struct device * self,int act)418 pchbactivate(struct device *self, int act)
419 {
420 struct pchb_softc *sc = (struct pchb_softc *)self;
421 int rv = 0;
422
423 switch (act) {
424 case DVACT_RESUME:
425 /* re-enable RNG, if we have it */
426 if (sc->sc_rng_active)
427 bus_space_write_1(sc->sc_bt, sc->sc_bh,
428 I82802_RNG_HWST,
429 bus_space_read_1(sc->sc_bt, sc->sc_bh,
430 I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE);
431 rv = config_activate_children(self, act);
432 break;
433 default:
434 rv = config_activate_children(self, act);
435 break;
436 }
437 return (rv);
438 }
439
440
441 int
pchb_print(void * aux,const char * pnp)442 pchb_print(void *aux, const char *pnp)
443 {
444 struct pcibus_attach_args *pba = aux;
445
446 if (pnp)
447 printf("%s at %s", pba->pba_busname, pnp);
448 printf(" bus %d", pba->pba_bus);
449 return (UNCONF);
450 }
451
452 /*
453 * Should do FIPS testing as per:
454 * http://csrc.nist.gov/publications/fips/fips140-1/fips1401.pdf
455 */
456 void
pchb_rnd(void * v)457 pchb_rnd(void *v)
458 {
459 struct pchb_softc *sc = v;
460
461 /*
462 * Don't wait for data to be ready. If it's not there, we'll check
463 * next time.
464 */
465 if ((bus_space_read_1(sc->sc_bt, sc->sc_bh, I82802_RNG_RNGST) &
466 I82802_RNG_RNGST_DATAV)) {
467
468 sc->sc_rng_ax = (sc->sc_rng_ax << 8) |
469 bus_space_read_1(sc->sc_bt, sc->sc_bh, I82802_RNG_DATA);
470
471 if (!sc->sc_rng_i--) {
472 sc->sc_rng_i = 4;
473 enqueue_randomness(sc->sc_rng_ax);
474 }
475 }
476
477 timeout_add(&sc->sc_rng_to, 1);
478 }
479
480 void
pchb_amd64ht_attach(struct device * self,struct pci_attach_args * pa,int i)481 pchb_amd64ht_attach(struct device *self, struct pci_attach_args *pa, int i)
482 {
483 struct pcibus_attach_args pba;
484 pcireg_t type, bus;
485 int reg;
486
487 reg = AMD64HT_LDT0_TYPE + i * 0x20;
488 type = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
489 if ((type & AMD64HT_LDT_INIT_COMPLETE) == 0 ||
490 (type & AMD64HT_LDT_NC) == 0)
491 return;
492
493 reg = AMD64HT_LDT0_BUS + i * 0x20;
494 bus = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
495 if (AMD64HT_LDT_SEC_BUS_NUM(bus) > 0) {
496 bzero(&pba, sizeof(pba));
497 pba.pba_busname = "pci";
498 pba.pba_iot = pa->pa_iot;
499 pba.pba_memt = pa->pa_memt;
500 pba.pba_dmat = pa->pa_dmat;
501 pba.pba_busex = pa->pa_busex;
502 pba.pba_domain = pa->pa_domain;
503 pba.pba_bus = AMD64HT_LDT_SEC_BUS_NUM(bus);
504 pba.pba_pc = pa->pa_pc;
505 config_found(self, &pba, pchb_print);
506 }
507 }
508