1 /* $OpenBSD: be.c,v 1.45 2024/05/13 01:15:53 jsg Exp $ */
2 /* $NetBSD: be.c,v 1.26 2001/03/20 15:39:20 pk Exp $ */
3
4 /*-
5 * Copyright (c) 1999 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
49 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 */
57
58 #include "bpfilter.h"
59
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/timeout.h>
63 #include <sys/kernel.h>
64 #include <sys/errno.h>
65 #include <sys/ioctl.h>
66 #include <sys/mbuf.h>
67 #include <sys/socket.h>
68 #include <sys/syslog.h>
69 #include <sys/device.h>
70 #include <sys/malloc.h>
71
72 #include <net/if.h>
73 #include <net/if_media.h>
74
75 #include <netinet/in.h>
76 #include <netinet/if_ether.h>
77
78 #if NBPFILTER > 0
79 #include <net/bpf.h>
80 #endif
81
82 #include <machine/bus.h>
83 #include <machine/intr.h>
84 #include <machine/autoconf.h>
85
86 #include <dev/sbus/sbusvar.h>
87
88 #include <dev/mii/mii.h>
89 #include <dev/mii/miivar.h>
90
91 #include <dev/sbus/qecreg.h>
92 #include <dev/sbus/qecvar.h>
93 #include <dev/sbus/bereg.h>
94
95 struct be_softc {
96 struct device sc_dev;
97 bus_space_tag_t sc_bustag; /* bus & dma tags */
98 bus_dma_tag_t sc_dmatag;
99 bus_dmamap_t sc_dmamap;
100 struct arpcom sc_arpcom;
101 /*struct ifmedia sc_ifmedia; -* interface media */
102 struct mii_data sc_mii; /* MII media control */
103 #define sc_media sc_mii.mii_media/* shorthand */
104 int sc_phys[2]; /* MII instance -> phy */
105
106 struct timeout sc_tick_ch;
107
108 /*
109 * Some `mii_softc' items we need to emulate MII operation
110 * for our internal transceiver.
111 */
112 int sc_mii_inst; /* instance of internal phy */
113 uint64_t sc_mii_active; /* currently active medium */
114 int sc_mii_ticks; /* tick counter */
115 int sc_mii_flags; /* phy status flags */
116 #define MIIF_HAVELINK 0x04000000
117 int sc_intphy_curspeed; /* Established link speed */
118
119 struct qec_softc *sc_qec; /* QEC parent */
120
121 bus_space_handle_t sc_qr; /* QEC registers */
122 bus_space_handle_t sc_br; /* BE registers */
123 bus_space_handle_t sc_cr; /* channel registers */
124 bus_space_handle_t sc_tr; /* transceiver registers */
125
126 u_int sc_rev;
127
128 int sc_channel; /* channel number */
129 int sc_burst;
130
131 struct qec_ring sc_rb; /* Packet Ring Buffer */
132 };
133
134 int bematch(struct device *, void *, void *);
135 void beattach(struct device *, struct device *, void *);
136
137 void beinit(struct be_softc *);
138 void bestart(struct ifnet *);
139 void bestop(struct be_softc *);
140 void bewatchdog(struct ifnet *);
141 int beioctl(struct ifnet *, u_long, caddr_t);
142 void bereset(struct be_softc *);
143
144 int beintr(void *);
145 int berint(struct be_softc *);
146 int betint(struct be_softc *);
147 int beqint(struct be_softc *, u_int32_t);
148 int beeint(struct be_softc *, u_int32_t);
149
150 static void be_read(struct be_softc *, int, int);
151 static int be_put(struct be_softc *, int, struct mbuf *);
152 static struct mbuf *be_get(struct be_softc *, int, int);
153
154 void be_pal_gate(struct be_softc *, int);
155
156 /* ifmedia callbacks */
157 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *);
158 int be_ifmedia_upd(struct ifnet *);
159
160 void be_mcreset(struct be_softc *);
161
162 /* MII methods & callbacks */
163 static int be_mii_readreg(struct device *, int, int);
164 static void be_mii_writereg(struct device *, int, int, int);
165 static void be_mii_statchg(struct device *);
166
167 /* MII helpers */
168 static void be_mii_sync(struct be_softc *);
169 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int);
170 static int be_mii_reset(struct be_softc *, int);
171 static int be_tcvr_read_bit(struct be_softc *, int);
172 static void be_tcvr_write_bit(struct be_softc *, int, int);
173
174 void be_tick(void *);
175 void be_intphy_status(struct be_softc *);
176 int be_intphy_service(struct be_softc *, struct mii_data *, int);
177
178
179 const struct cfattach be_ca = {
180 sizeof(struct be_softc), bematch, beattach
181 };
182
183 struct cfdriver be_cd = {
184 NULL, "be", DV_IFNET
185 };
186
187 int
bematch(struct device * parent,void * vcf,void * aux)188 bematch(struct device *parent, void *vcf, void *aux)
189 {
190 struct cfdata *cf = vcf;
191 struct sbus_attach_args *sa = aux;
192
193 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
194 }
195
196 void
beattach(struct device * parent,struct device * self,void * aux)197 beattach(struct device *parent, struct device *self, void *aux)
198 {
199 struct sbus_attach_args *sa = aux;
200 struct qec_softc *qec = (struct qec_softc *)parent;
201 struct be_softc *sc = (struct be_softc *)self;
202 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
203 struct mii_data *mii = &sc->sc_mii;
204 struct mii_softc *child;
205 int node = sa->sa_node;
206 bus_dma_tag_t dmatag = sa->sa_dmatag;
207 bus_dma_segment_t seg;
208 bus_size_t size;
209 uint64_t instance;
210 int rseg, error;
211 u_int32_t v;
212 extern void myetheraddr(u_char *);
213
214 /* Pass on the bus tags */
215 sc->sc_bustag = sa->sa_bustag;
216 sc->sc_dmatag = sa->sa_dmatag;
217
218 if (sa->sa_nreg < 3) {
219 printf("%s: only %d register sets\n",
220 self->dv_xname, sa->sa_nreg);
221 return;
222 }
223
224 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
225 (bus_addr_t)sa->sa_reg[0].sbr_offset,
226 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) {
227 printf("beattach: cannot map registers\n");
228 return;
229 }
230
231 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
232 (bus_addr_t)sa->sa_reg[1].sbr_offset,
233 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) {
234 printf("beattach: cannot map registers\n");
235 return;
236 }
237
238 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot,
239 (bus_addr_t)sa->sa_reg[2].sbr_offset,
240 (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) {
241 printf("beattach: cannot map registers\n");
242 return;
243 }
244
245 sc->sc_qec = qec;
246 sc->sc_qr = qec->sc_regs;
247
248 sc->sc_rev = getpropint(node, "board-version", -1);
249 printf(" rev %x", sc->sc_rev);
250
251 bestop(sc);
252
253 sc->sc_channel = getpropint(node, "channel#", -1);
254 if (sc->sc_channel == -1)
255 sc->sc_channel = 0;
256
257 sc->sc_burst = getpropint(node, "burst-sizes", -1);
258 if (sc->sc_burst == -1)
259 sc->sc_burst = qec->sc_burst;
260
261 /* Clamp at parent's burst sizes */
262 sc->sc_burst &= qec->sc_burst;
263
264 /* Establish interrupt handler */
265 if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri,
266 IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) {
267 printf(": no interrupt established\n");
268 return;
269 }
270
271 myetheraddr(sc->sc_arpcom.ac_enaddr);
272 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
273
274 /*
275 * Allocate descriptor ring and buffers.
276 */
277
278 /* for now, allocate as many bufs as there are ring descriptors */
279 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
280 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
281
282 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
283 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
284 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ +
285 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ;
286
287 /* Get a DMA handle */
288 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
289 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
290 printf("%s: DMA map create error %d\n", self->dv_xname, error);
291 return;
292 }
293
294 /* Allocate DMA buffer */
295 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0,
296 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
297 printf("%s: DMA buffer alloc error %d\n",
298 self->dv_xname, error);
299 return;
300 }
301
302 /* Map DMA memory in CPU addressable space */
303 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size,
304 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
305 printf("%s: DMA buffer map error %d\n",
306 self->dv_xname, error);
307 bus_dmamem_free(sa->sa_dmatag, &seg, rseg);
308 return;
309 }
310
311 /* Load the buffer */
312 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
313 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) {
314 printf("%s: DMA buffer map load error %d\n",
315 self->dv_xname, error);
316 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
317 bus_dmamem_free(dmatag, &seg, rseg);
318 return;
319 }
320 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
321
322 /*
323 * Initialize our media structures and MII info.
324 */
325 mii->mii_ifp = ifp;
326 mii->mii_readreg = be_mii_readreg;
327 mii->mii_writereg = be_mii_writereg;
328 mii->mii_statchg = be_mii_statchg;
329
330 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts);
331
332 timeout_set(&sc->sc_tick_ch, be_tick, sc);
333
334 /*
335 * Initialize transceiver and determine which PHY connection to use.
336 */
337 be_mii_sync(sc);
338 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL);
339
340 instance = 0;
341
342 if ((v & MGMT_PAL_EXT_MDIO) != 0) {
343
344 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL,
345 MII_OFFSET_ANY, 0);
346
347 child = LIST_FIRST(&mii->mii_phys);
348 if (child == NULL) {
349 /* No PHY attached */
350 ifmedia_add(&sc->sc_media,
351 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance),
352 0, NULL);
353 ifmedia_set(&sc->sc_media,
354 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance));
355 } else {
356 /*
357 * Note: we support just one PHY on the external
358 * MII connector.
359 */
360 #ifdef DIAGNOSTIC
361 if (LIST_NEXT(child, mii_list) != NULL) {
362 printf("%s: spurious MII device %s attached\n",
363 sc->sc_dev.dv_xname,
364 child->mii_dev.dv_xname);
365 }
366 #endif
367 if (child->mii_phy != BE_PHY_EXTERNAL ||
368 child->mii_inst > 0) {
369 printf("%s: cannot accommodate MII device %s"
370 " at phy %d, instance %lld\n",
371 sc->sc_dev.dv_xname,
372 child->mii_dev.dv_xname,
373 child->mii_phy, child->mii_inst);
374 } else {
375 sc->sc_phys[instance] = child->mii_phy;
376 }
377
378 /*
379 * XXX - we can really do the following ONLY if the
380 * phy indeed has the auto negotiation capability!!
381 */
382 ifmedia_set(&sc->sc_media,
383 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance));
384
385 /* Mark our current media setting */
386 be_pal_gate(sc, BE_PHY_EXTERNAL);
387 instance++;
388 }
389
390 }
391
392 if ((v & MGMT_PAL_INT_MDIO) != 0) {
393 /*
394 * The be internal phy looks vaguely like MII hardware,
395 * but not enough to be able to use the MII device
396 * layer. Hence, we have to take care of media selection
397 * ourselves.
398 */
399
400 sc->sc_mii_inst = instance;
401 sc->sc_phys[instance] = BE_PHY_INTERNAL;
402
403 /* Use `ifm_data' to store BMCR bits */
404 ifmedia_add(&sc->sc_media,
405 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL);
406 ifmedia_add(&sc->sc_media,
407 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance),
408 BMCR_S100, NULL);
409 ifmedia_add(&sc->sc_media,
410 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL);
411
412 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n",
413 self->dv_xname);
414
415 be_mii_reset(sc, BE_PHY_INTERNAL);
416 /* Only set default medium here if there's no external PHY */
417 if (instance == 0) {
418 be_pal_gate(sc, BE_PHY_INTERNAL);
419 ifmedia_set(&sc->sc_media,
420 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance));
421 } else
422 be_mii_writereg((void *)sc,
423 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO);
424 }
425
426 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
427 ifp->if_softc = sc;
428 ifp->if_start = bestart;
429 ifp->if_ioctl = beioctl;
430 ifp->if_watchdog = bewatchdog;
431 ifp->if_flags =
432 IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
433
434 /* Attach the interface. */
435 if_attach(ifp);
436 ether_ifattach(ifp);
437 }
438
439
440 /*
441 * Routine to copy from mbuf chain to transmit buffer in
442 * network buffer memory.
443 */
444 static __inline__ int
be_put(struct be_softc * sc,int idx,struct mbuf * m)445 be_put(struct be_softc *sc, int idx, struct mbuf *m)
446 {
447 struct mbuf *n;
448 int len, tlen = 0, boff = 0;
449 caddr_t bp;
450
451 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ;
452
453 for (; m; m = n) {
454 len = m->m_len;
455 if (len == 0) {
456 n = m_free(m);
457 continue;
458 }
459 bcopy(mtod(m, caddr_t), bp+boff, len);
460 boff += len;
461 tlen += len;
462 n = m_free(m);
463 }
464 return (tlen);
465 }
466
467 /*
468 * Pull data off an interface.
469 * Len is the length of data, with local net header stripped.
470 * We copy the data into mbufs. When full cluster sized units are present,
471 * we copy into clusters.
472 */
473 static __inline__ struct mbuf *
be_get(struct be_softc * sc,int idx,int totlen)474 be_get(struct be_softc *sc, int idx, int totlen)
475 {
476 struct mbuf *m;
477 struct mbuf *top, **mp;
478 int len, pad, boff = 0;
479 caddr_t bp;
480
481 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ;
482
483 MGETHDR(m, M_DONTWAIT, MT_DATA);
484 if (m == NULL)
485 return (NULL);
486 m->m_pkthdr.len = totlen;
487
488 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
489 m->m_data += pad;
490 len = MHLEN - pad;
491 top = NULL;
492 mp = ⊤
493
494 while (totlen > 0) {
495 if (top) {
496 MGET(m, M_DONTWAIT, MT_DATA);
497 if (m == NULL) {
498 m_freem(top);
499 return (NULL);
500 }
501 len = MLEN;
502 }
503 if (top && totlen >= MINCLSIZE) {
504 MCLGET(m, M_DONTWAIT);
505 if (m->m_flags & M_EXT)
506 len = MCLBYTES;
507 }
508 m->m_len = len = min(totlen, len);
509 bcopy(bp + boff, mtod(m, caddr_t), len);
510 boff += len;
511 totlen -= len;
512 *mp = m;
513 mp = &m->m_next;
514 }
515
516 return (top);
517 }
518
519 /*
520 * Pass a packet to the higher levels.
521 */
522 static __inline__ void
be_read(struct be_softc * sc,int idx,int len)523 be_read(struct be_softc *sc, int idx, int len)
524 {
525 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
526 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
527 struct mbuf *m;
528
529 if (len <= sizeof(struct ether_header) ||
530 len > ETHERMTU + sizeof(struct ether_header)) {
531
532 printf("%s: invalid packet size %d; dropping\n",
533 ifp->if_xname, len);
534
535 ifp->if_ierrors++;
536 return;
537 }
538
539 /*
540 * Pull packet off interface.
541 */
542 m = be_get(sc, idx, len);
543 if (m == NULL) {
544 ifp->if_ierrors++;
545 return;
546 }
547
548 ml_enqueue(&ml, m);
549 if_input(ifp, &ml);
550 }
551
552 /*
553 * Start output on interface.
554 * We make two assumptions here:
555 * 1) that the current priority is set to splnet _before_ this code
556 * is called *and* is returned to the appropriate priority after
557 * return
558 * 2) that the IFF_OACTIVE flag is checked before this code is called
559 * (i.e. that the output part of the interface is idle)
560 */
561 void
bestart(struct ifnet * ifp)562 bestart(struct ifnet *ifp)
563 {
564 struct be_softc *sc = (struct be_softc *)ifp->if_softc;
565 struct qec_xd *txd = sc->sc_rb.rb_txd;
566 struct mbuf *m;
567 unsigned int bix, len;
568 unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
569
570 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
571 return;
572
573 bix = sc->sc_rb.rb_tdhead;
574
575 for (;;) {
576 m = ifq_dequeue(&ifp->if_snd);
577 if (m == NULL)
578 break;
579
580 #if NBPFILTER > 0
581 /*
582 * If BPF is listening on this interface, let it see the
583 * packet before we commit it to the wire.
584 */
585 if (ifp->if_bpf)
586 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
587 #endif
588
589 /*
590 * Copy the mbuf chain into the transmit buffer.
591 */
592 len = be_put(sc, bix, m);
593
594 /*
595 * Initialize transmit registers and start transmission
596 */
597 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
598 (len & QEC_XD_LENGTH);
599 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL,
600 BE_CR_CTRL_TWAKEUP);
601
602 if (++bix == QEC_XD_RING_MAXSIZE)
603 bix = 0;
604
605 if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
606 ifq_set_oactive(&ifp->if_snd);
607 break;
608 }
609 }
610
611 sc->sc_rb.rb_tdhead = bix;
612 }
613
614 void
bestop(struct be_softc * sc)615 bestop(struct be_softc *sc)
616 {
617 int n;
618 bus_space_tag_t t = sc->sc_bustag;
619 bus_space_handle_t br = sc->sc_br;
620
621 timeout_del(&sc->sc_tick_ch);
622
623 /* Down the MII. */
624 mii_down(&sc->sc_mii);
625 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN);
626
627 /* Stop the transmitter */
628 bus_space_write_4(t, br, BE_BRI_TXCFG, 0);
629 for (n = 32; n > 0; n--) {
630 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0)
631 break;
632 DELAY(20);
633 }
634
635 /* Stop the receiver */
636 bus_space_write_4(t, br, BE_BRI_RXCFG, 0);
637 for (n = 32; n > 0; n--) {
638 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0)
639 break;
640 DELAY(20);
641 }
642 }
643
644 /*
645 * Reset interface.
646 */
647 void
bereset(struct be_softc * sc)648 bereset(struct be_softc *sc)
649 {
650 int s;
651
652 s = splnet();
653 bestop(sc);
654 if ((sc->sc_arpcom.ac_if.if_flags & IFF_UP) != 0)
655 beinit(sc);
656 splx(s);
657 }
658
659 void
bewatchdog(struct ifnet * ifp)660 bewatchdog(struct ifnet *ifp)
661 {
662 struct be_softc *sc = ifp->if_softc;
663
664 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
665 ++sc->sc_arpcom.ac_if.if_oerrors;
666 bereset(sc);
667 }
668
669 int
beintr(void * v)670 beintr(void *v)
671 {
672 struct be_softc *sc = (struct be_softc *)v;
673 bus_space_tag_t t = sc->sc_bustag;
674 u_int32_t whyq, whyb, whyc;
675 int r = 0;
676
677 /* Read QEC status, channel status and BE status */
678 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
679 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT);
680 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT);
681
682 if (whyq & QEC_STAT_BM)
683 r |= beeint(sc, whyb);
684
685 if (whyq & QEC_STAT_ER)
686 r |= beqint(sc, whyc);
687
688 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ)
689 r |= betint(sc);
690
691 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ)
692 r |= berint(sc);
693
694 return (r);
695 }
696
697 /*
698 * QEC Interrupt.
699 */
700 int
beqint(struct be_softc * sc,u_int32_t why)701 beqint(struct be_softc *sc, u_int32_t why)
702 {
703 int r = 0, rst = 0;
704
705 if (why & BE_CR_STAT_TXIRQ)
706 r |= 1;
707 if (why & BE_CR_STAT_RXIRQ)
708 r |= 1;
709
710 if (why & BE_CR_STAT_BERROR) {
711 r |= 1;
712 rst = 1;
713 printf("%s: bigmac error\n", sc->sc_dev.dv_xname);
714 }
715
716 if (why & BE_CR_STAT_TXDERR) {
717 r |= 1;
718 rst = 1;
719 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname);
720 }
721
722 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) {
723 r |= 1;
724 rst = 1;
725 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname);
726 if (why & BE_CR_STAT_TXLERR)
727 printf("Late ");
728 if (why & BE_CR_STAT_TXPERR)
729 printf("Parity ");
730 if (why & BE_CR_STAT_TXSERR)
731 printf("Generic ");
732 printf(")\n");
733 }
734
735 if (why & BE_CR_STAT_RXDROP) {
736 r |= 1;
737 rst = 1;
738 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname);
739 }
740
741 if (why & BE_CR_STAT_RXSMALL) {
742 r |= 1;
743 rst = 1;
744 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname);
745 }
746
747 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) {
748 r |= 1;
749 rst = 1;
750 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname);
751 if (why & BE_CR_STAT_RXLERR)
752 printf("Late ");
753 if (why & BE_CR_STAT_RXPERR)
754 printf("Parity ");
755 if (why & BE_CR_STAT_RXSERR)
756 printf("Generic ");
757 printf(")\n");
758 }
759
760 if (!r) {
761 rst = 1;
762 printf("%s: unexpected error interrupt %08x\n",
763 sc->sc_dev.dv_xname, why);
764 }
765
766 if (rst) {
767 printf("%s: resetting\n", sc->sc_dev.dv_xname);
768 bereset(sc);
769 }
770
771 return (r);
772 }
773
774 /*
775 * Error interrupt.
776 */
777 int
beeint(struct be_softc * sc,u_int32_t why)778 beeint(struct be_softc *sc, u_int32_t why)
779 {
780 int r = 0, rst = 0;
781
782 if (why & BE_BR_STAT_RFIFOVF) {
783 r |= 1;
784 rst = 1;
785 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname);
786 }
787 if (why & BE_BR_STAT_TFIFO_UND) {
788 r |= 1;
789 rst = 1;
790 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname);
791 }
792 if (why & BE_BR_STAT_MAXPKTERR) {
793 r |= 1;
794 rst = 1;
795 printf("%s: max packet size error\n", sc->sc_dev.dv_xname);
796 }
797
798 if (!r) {
799 rst = 1;
800 printf("%s: unexpected error interrupt %08x\n",
801 sc->sc_dev.dv_xname, why);
802 }
803
804 if (rst) {
805 printf("%s: resetting\n", sc->sc_dev.dv_xname);
806 bereset(sc);
807 }
808
809 return (r);
810 }
811
812 /*
813 * Transmit interrupt.
814 */
815 int
betint(struct be_softc * sc)816 betint(struct be_softc *sc)
817 {
818 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
819 bus_space_tag_t t = sc->sc_bustag;
820 bus_space_handle_t br = sc->sc_br;
821 unsigned int bix, txflags;
822
823 /*
824 * Unload collision counters
825 */
826 ifp->if_collisions +=
827 bus_space_read_4(t, br, BE_BRI_NCCNT) +
828 bus_space_read_4(t, br, BE_BRI_FCCNT) +
829 bus_space_read_4(t, br, BE_BRI_EXCNT) +
830 bus_space_read_4(t, br, BE_BRI_LTCNT);
831
832 /*
833 * the clear the hardware counters
834 */
835 bus_space_write_4(t, br, BE_BRI_NCCNT, 0);
836 bus_space_write_4(t, br, BE_BRI_FCCNT, 0);
837 bus_space_write_4(t, br, BE_BRI_EXCNT, 0);
838 bus_space_write_4(t, br, BE_BRI_LTCNT, 0);
839
840 bix = sc->sc_rb.rb_tdtail;
841
842 for (;;) {
843 if (sc->sc_rb.rb_td_nbusy <= 0)
844 break;
845
846 txflags = sc->sc_rb.rb_txd[bix].xd_flags;
847
848 if (txflags & QEC_XD_OWN)
849 break;
850
851 ifq_clr_oactive(&ifp->if_snd);
852
853 if (++bix == QEC_XD_RING_MAXSIZE)
854 bix = 0;
855
856 --sc->sc_rb.rb_td_nbusy;
857 }
858
859 sc->sc_rb.rb_tdtail = bix;
860
861 bestart(ifp);
862
863 if (sc->sc_rb.rb_td_nbusy == 0)
864 ifp->if_timer = 0;
865
866 return (1);
867 }
868
869 /*
870 * Receive interrupt.
871 */
872 int
berint(struct be_softc * sc)873 berint(struct be_softc *sc)
874 {
875 struct qec_xd *xd = sc->sc_rb.rb_rxd;
876 unsigned int bix, len;
877 unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
878
879 bix = sc->sc_rb.rb_rdtail;
880
881 /*
882 * Process all buffers with valid data.
883 */
884 for (;;) {
885 len = xd[bix].xd_flags;
886 if (len & QEC_XD_OWN)
887 break;
888
889 len &= QEC_XD_LENGTH;
890 be_read(sc, bix, len);
891
892 /* ... */
893 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
894 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH);
895
896 if (++bix == QEC_XD_RING_MAXSIZE)
897 bix = 0;
898 }
899
900 sc->sc_rb.rb_rdtail = bix;
901
902 return (1);
903 }
904
905 int
beioctl(struct ifnet * ifp,u_long cmd,caddr_t data)906 beioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
907 {
908 struct be_softc *sc = ifp->if_softc;
909 struct ifreq *ifr = (struct ifreq *)data;
910 int s, error = 0;
911
912 s = splnet();
913
914 switch (cmd) {
915 case SIOCSIFADDR:
916 ifp->if_flags |= IFF_UP;
917 beinit(sc);
918 break;
919
920 case SIOCSIFFLAGS:
921 if ((ifp->if_flags & IFF_UP) == 0 &&
922 (ifp->if_flags & IFF_RUNNING) != 0) {
923 /*
924 * If interface is marked down and it is running, then
925 * stop it.
926 */
927 bestop(sc);
928 ifp->if_flags &= ~IFF_RUNNING;
929 } else if ((ifp->if_flags & IFF_UP) != 0 &&
930 (ifp->if_flags & IFF_RUNNING) == 0) {
931 /*
932 * If interface is marked up and it is stopped, then
933 * start it.
934 */
935 beinit(sc);
936 } else {
937 /*
938 * Reset the interface to pick up changes in any other
939 * flags that affect hardware registers.
940 */
941 bestop(sc);
942 beinit(sc);
943 }
944 #ifdef BEDEBUG
945 if (ifp->if_flags & IFF_DEBUG)
946 sc->sc_debug = 1;
947 else
948 sc->sc_debug = 0;
949 #endif
950 break;
951
952 case SIOCGIFMEDIA:
953 case SIOCSIFMEDIA:
954 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
955 break;
956
957 default:
958 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
959 }
960
961 if (error == ENETRESET) {
962 if (ifp->if_flags & IFF_RUNNING)
963 be_mcreset(sc);
964 error = 0;
965 }
966
967 splx(s);
968 return (error);
969 }
970
971
972 void
beinit(struct be_softc * sc)973 beinit(struct be_softc *sc)
974 {
975 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
976 bus_space_tag_t t = sc->sc_bustag;
977 bus_space_handle_t br = sc->sc_br;
978 bus_space_handle_t cr = sc->sc_cr;
979 struct qec_softc *qec = sc->sc_qec;
980 u_int32_t v;
981 u_int32_t qecaddr;
982 u_int8_t *ea;
983 int s;
984
985 s = splnet();
986
987 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
988
989 bestop(sc);
990
991 ea = sc->sc_arpcom.ac_enaddr;
992 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
993 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
994 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
995
996 /* Clear hash table */
997 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
998 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
999 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
1000 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
1001
1002 /* Re-initialize RX configuration */
1003 v = BE_BR_RXCFG_FIFO;
1004 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1005
1006 be_mcreset(sc);
1007
1008 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
1009
1010 bus_space_write_4(t, br, BE_BRI_XIFCFG,
1011 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
1012
1013 bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
1014
1015 /*
1016 * Turn off counter expiration interrupts as well as
1017 * 'gotframe' and 'sentframe'
1018 */
1019 bus_space_write_4(t, br, BE_BRI_IMASK,
1020 BE_BR_IMASK_GOTFRAME |
1021 BE_BR_IMASK_RCNTEXP |
1022 BE_BR_IMASK_ACNTEXP |
1023 BE_BR_IMASK_CCNTEXP |
1024 BE_BR_IMASK_LCNTEXP |
1025 BE_BR_IMASK_CVCNTEXP |
1026 BE_BR_IMASK_SENTFRAME |
1027 BE_BR_IMASK_NCNTEXP |
1028 BE_BR_IMASK_ECNTEXP |
1029 BE_BR_IMASK_LCCNTEXP |
1030 BE_BR_IMASK_FCNTEXP |
1031 BE_BR_IMASK_DTIMEXP);
1032
1033 /* Channel registers: */
1034 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
1035 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
1036
1037 qecaddr = sc->sc_channel * qec->sc_msize;
1038 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
1039 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
1040 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
1041 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
1042
1043 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
1044 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
1045 bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
1046 bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
1047 bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
1048
1049 /* Enable transmitter */
1050 bus_space_write_4(t, br, BE_BRI_TXCFG,
1051 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
1052
1053 /* Enable receiver */
1054 v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1055 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE;
1056 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1057
1058 ifp->if_flags |= IFF_RUNNING;
1059 ifq_clr_oactive(&ifp->if_snd);
1060
1061 be_ifmedia_upd(ifp);
1062 timeout_add_sec(&sc->sc_tick_ch, 1);
1063 splx(s);
1064 }
1065
1066 void
be_mcreset(struct be_softc * sc)1067 be_mcreset(struct be_softc *sc)
1068 {
1069 struct arpcom *ac = &sc->sc_arpcom;
1070 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1071 bus_space_tag_t t = sc->sc_bustag;
1072 bus_space_handle_t br = sc->sc_br;
1073 u_int32_t crc;
1074 u_int16_t hash[4];
1075 u_int8_t octet;
1076 u_int32_t v;
1077 int i, j;
1078 struct ether_multi *enm;
1079 struct ether_multistep step;
1080
1081 if (ifp->if_flags & IFF_PROMISC) {
1082 v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1083 v |= BE_BR_RXCFG_PMISC;
1084 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1085 return;
1086 }
1087
1088 if (ac->ac_multirangecnt > 0)
1089 ifp->if_flags |= IFF_ALLMULTI;
1090
1091 if (ifp->if_flags & IFF_ALLMULTI) {
1092 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1093 goto chipit;
1094 }
1095
1096 hash[3] = hash[2] = hash[1] = hash[0] = 0;
1097
1098 ETHER_FIRST_MULTI(step, ac, enm);
1099 while (enm != NULL) {
1100 crc = 0xffffffff;
1101
1102 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1103 octet = enm->enm_addrlo[i];
1104
1105 for (j = 0; j < 8; j++) {
1106 if ((crc & 1) ^ (octet & 1)) {
1107 crc >>= 1;
1108 crc ^= MC_POLY_LE;
1109 }
1110 else
1111 crc >>= 1;
1112 octet >>= 1;
1113 }
1114 }
1115
1116 crc >>= 26;
1117 hash[crc >> 4] |= 1 << (crc & 0xf);
1118 ETHER_NEXT_MULTI(step, enm);
1119 }
1120
1121 ifp->if_flags &= ~IFF_ALLMULTI;
1122
1123 chipit:
1124 /* Enable the hash filter */
1125 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]);
1126 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]);
1127 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]);
1128 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]);
1129
1130 v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1131 v &= ~BE_BR_RXCFG_PMISC;
1132 v |= BE_BR_RXCFG_HENABLE;
1133 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1134 }
1135
1136 /*
1137 * Set the tcvr to an idle state
1138 */
1139 void
be_mii_sync(struct be_softc * sc)1140 be_mii_sync(struct be_softc *sc)
1141 {
1142 bus_space_tag_t t = sc->sc_bustag;
1143 bus_space_handle_t tr = sc->sc_tr;
1144 int n = 32;
1145
1146 while (n--) {
1147 bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1148 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB);
1149 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1150 bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1151 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
1152 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK);
1153 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1154 }
1155 }
1156
1157 void
be_pal_gate(struct be_softc * sc,int phy)1158 be_pal_gate(struct be_softc *sc, int phy)
1159 {
1160 bus_space_tag_t t = sc->sc_bustag;
1161 bus_space_handle_t tr = sc->sc_tr;
1162 u_int32_t v;
1163
1164 be_mii_sync(sc);
1165
1166 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE);
1167 if (phy == BE_PHY_INTERNAL)
1168 v &= ~TCVR_PAL_SERIAL;
1169
1170 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v);
1171 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
1172 }
1173
1174 static int
be_tcvr_read_bit(struct be_softc * sc,int phy)1175 be_tcvr_read_bit(struct be_softc *sc, int phy)
1176 {
1177 bus_space_tag_t t = sc->sc_bustag;
1178 bus_space_handle_t tr = sc->sc_tr;
1179 int ret;
1180
1181 if (phy == BE_PHY_INTERNAL) {
1182 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO);
1183 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1184 bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1185 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK);
1186 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1187 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
1188 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT;
1189 } else {
1190 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO);
1191 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1192 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
1193 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT;
1194 bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1195 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK);
1196 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1197 }
1198
1199 return (ret);
1200 }
1201
1202 static void
be_tcvr_write_bit(struct be_softc * sc,int phy,int bit)1203 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit)
1204 {
1205 bus_space_tag_t t = sc->sc_bustag;
1206 bus_space_handle_t tr = sc->sc_tr;
1207 u_int32_t v;
1208
1209 if (phy == BE_PHY_INTERNAL) {
1210 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) |
1211 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO;
1212 } else {
1213 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT)
1214 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO;
1215 }
1216 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v);
1217 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1218 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK);
1219 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1220 }
1221
1222 static void
be_mii_sendbits(struct be_softc * sc,int phy,u_int32_t data,int nbits)1223 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits)
1224 {
1225 int i;
1226
1227 for (i = 1 << (nbits - 1); i != 0; i >>= 1)
1228 be_tcvr_write_bit(sc, phy, (data & i) != 0);
1229 }
1230
1231 static int
be_mii_readreg(struct device * self,int phy,int reg)1232 be_mii_readreg(struct device *self, int phy, int reg)
1233 {
1234 struct be_softc *sc = (struct be_softc *)self;
1235 int val = 0, i;
1236
1237 /*
1238 * Read the PHY register by manually driving the MII control lines.
1239 */
1240 be_mii_sync(sc);
1241 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
1242 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);
1243 be_mii_sendbits(sc, phy, phy, 5);
1244 be_mii_sendbits(sc, phy, reg, 5);
1245
1246 (void) be_tcvr_read_bit(sc, phy);
1247 (void) be_tcvr_read_bit(sc, phy);
1248
1249 for (i = 15; i >= 0; i--)
1250 val |= (be_tcvr_read_bit(sc, phy) << i);
1251
1252 (void) be_tcvr_read_bit(sc, phy);
1253 (void) be_tcvr_read_bit(sc, phy);
1254 (void) be_tcvr_read_bit(sc, phy);
1255
1256 return (val);
1257 }
1258
1259 void
be_mii_writereg(struct device * self,int phy,int reg,int val)1260 be_mii_writereg(struct device *self, int phy, int reg, int val)
1261 {
1262 struct be_softc *sc = (struct be_softc *)self;
1263 int i;
1264
1265 /*
1266 * Write the PHY register by manually driving the MII control lines.
1267 */
1268 be_mii_sync(sc);
1269 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
1270 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);
1271 be_mii_sendbits(sc, phy, phy, 5);
1272 be_mii_sendbits(sc, phy, reg, 5);
1273
1274 be_tcvr_write_bit(sc, phy, 1);
1275 be_tcvr_write_bit(sc, phy, 0);
1276
1277 for (i = 15; i >= 0; i--)
1278 be_tcvr_write_bit(sc, phy, (val >> i) & 1);
1279 }
1280
1281 int
be_mii_reset(struct be_softc * sc,int phy)1282 be_mii_reset(struct be_softc *sc, int phy)
1283 {
1284 int n;
1285
1286 be_mii_writereg((struct device *)sc, phy, MII_BMCR,
1287 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO);
1288 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);
1289
1290 for (n = 16; n >= 0; n--) {
1291 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
1292 if ((bmcr & BMCR_RESET) == 0)
1293 break;
1294 DELAY(20);
1295 }
1296 if (n == 0) {
1297 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname);
1298 return (EIO);
1299 }
1300
1301 return (0);
1302 }
1303
1304 void
be_tick(void * arg)1305 be_tick(void *arg)
1306 {
1307 struct be_softc *sc = arg;
1308 int s = splnet();
1309
1310 mii_tick(&sc->sc_mii);
1311 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK);
1312
1313 timeout_add_sec(&sc->sc_tick_ch, 1);
1314 splx(s);
1315 }
1316
1317 void
be_mii_statchg(struct device * self)1318 be_mii_statchg(struct device *self)
1319 {
1320 struct be_softc *sc = (struct be_softc *)self;
1321 bus_space_tag_t t = sc->sc_bustag;
1322 bus_space_handle_t br = sc->sc_br;
1323 u_int64_t instance;
1324 u_int32_t v;
1325
1326 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1327 #ifdef DIAGNOSTIC
1328 if (instance > 1)
1329 panic("be_mii_statchg: instance %lld out of range", instance);
1330 #endif
1331
1332 /* Update duplex mode in TX configuration */
1333 v = bus_space_read_4(t, br, BE_BRI_TXCFG);
1334 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
1335 v |= BE_BR_TXCFG_FULLDPLX;
1336 else
1337 v &= ~BE_BR_TXCFG_FULLDPLX;
1338 bus_space_write_4(t, br, BE_BRI_TXCFG, v);
1339
1340 /* Change to appropriate gate in transceiver PAL */
1341 be_pal_gate(sc, sc->sc_phys[instance]);
1342 }
1343
1344 /*
1345 * Get current media settings.
1346 */
1347 void
be_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1348 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1349 {
1350 struct be_softc *sc = ifp->if_softc;
1351
1352 mii_pollstat(&sc->sc_mii);
1353 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT);
1354
1355 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1356 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1357 return;
1358 }
1359
1360 /*
1361 * Set media options.
1362 */
1363 int
be_ifmedia_upd(struct ifnet * ifp)1364 be_ifmedia_upd(struct ifnet *ifp)
1365 {
1366 struct be_softc *sc = ifp->if_softc;
1367 int error;
1368
1369 if ((error = mii_mediachg(&sc->sc_mii)) != 0)
1370 return (error);
1371
1372 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG));
1373 }
1374
1375 /*
1376 * Service routine for our pseudo-MII internal transceiver.
1377 */
1378 int
be_intphy_service(struct be_softc * sc,struct mii_data * mii,int cmd)1379 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd)
1380 {
1381 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
1382 int bmcr, bmsr;
1383 int error;
1384
1385 switch (cmd) {
1386 case MII_POLLSTAT:
1387 /*
1388 * If we're not polling our PHY instance, just return.
1389 */
1390 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
1391 return (0);
1392
1393 break;
1394
1395 case MII_MEDIACHG:
1396
1397 /*
1398 * If the media indicates a different PHY instance,
1399 * isolate ourselves.
1400 */
1401 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) {
1402 bmcr = be_mii_readreg((void *)sc,
1403 BE_PHY_INTERNAL, MII_BMCR);
1404 be_mii_writereg((void *)sc,
1405 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
1406 sc->sc_mii_flags &= ~MIIF_HAVELINK;
1407 sc->sc_intphy_curspeed = 0;
1408 return (0);
1409 }
1410
1411
1412 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0)
1413 return (error);
1414
1415 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
1416
1417 /*
1418 * Select the new mode and take out of isolation
1419 */
1420 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
1421 bmcr |= BMCR_S100;
1422 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T)
1423 bmcr &= ~BMCR_S100;
1424 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
1425 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) {
1426 bmcr &= ~BMCR_S100;
1427 bmcr |= sc->sc_intphy_curspeed;
1428 } else {
1429 /* Keep isolated until link is up */
1430 bmcr |= BMCR_ISO;
1431 sc->sc_mii_flags |= MIIF_DOINGAUTO;
1432 }
1433 }
1434
1435 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0)
1436 bmcr |= BMCR_FDX;
1437 else
1438 bmcr &= ~BMCR_FDX;
1439
1440 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
1441 break;
1442
1443 case MII_TICK:
1444 /*
1445 * If we're not currently selected, just return.
1446 */
1447 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
1448 return (0);
1449
1450 /* Only used for automatic media selection */
1451 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
1452 return (0);
1453
1454 /* Is the interface even up? */
1455 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
1456 return (0);
1457
1458 /*
1459 * Check link status; if we don't have a link, try another
1460 * speed. We can't detect duplex mode, so half-duplex is
1461 * what we have to settle for.
1462 */
1463
1464 /* Read twice in case the register is latched */
1465 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) |
1466 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR);
1467
1468 if ((bmsr & BMSR_LINK) != 0) {
1469 /* We have a carrier */
1470 bmcr = be_mii_readreg((void *)sc,
1471 BE_PHY_INTERNAL, MII_BMCR);
1472
1473 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) {
1474 bmcr = be_mii_readreg((void *)sc,
1475 BE_PHY_INTERNAL, MII_BMCR);
1476
1477 sc->sc_mii_flags |= MIIF_HAVELINK;
1478 sc->sc_intphy_curspeed = (bmcr & BMCR_S100);
1479 sc->sc_mii_flags &= ~MIIF_DOINGAUTO;
1480
1481 bmcr &= ~BMCR_ISO;
1482 be_mii_writereg((void *)sc,
1483 BE_PHY_INTERNAL, MII_BMCR, bmcr);
1484
1485 printf("%s: link up at %s Mbps\n",
1486 sc->sc_dev.dv_xname,
1487 (bmcr & BMCR_S100) ? "100" : "10");
1488 }
1489 sc->sc_mii_ticks = 0;
1490 return (0);
1491 }
1492
1493 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) {
1494 sc->sc_mii_flags |= MIIF_DOINGAUTO;
1495 sc->sc_mii_flags &= ~MIIF_HAVELINK;
1496 sc->sc_intphy_curspeed = 0;
1497 printf("%s: link down\n", sc->sc_dev.dv_xname);
1498 }
1499
1500 /* Only retry autonegotiation every 5 seconds. */
1501 if (++sc->sc_mii_ticks < 5)
1502 return(0);
1503
1504 sc->sc_mii_ticks = 0;
1505 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
1506 /* Just flip the fast speed bit */
1507 bmcr ^= BMCR_S100;
1508 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
1509
1510 break;
1511
1512 case MII_DOWN:
1513 /* Isolate this phy */
1514 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
1515 be_mii_writereg((void *)sc,
1516 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
1517 return (0);
1518 }
1519
1520 /* Update the media status. */
1521 be_intphy_status(sc);
1522
1523 /* Callback if something changed. */
1524 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
1525 (*mii->mii_statchg)((struct device *)sc);
1526 sc->sc_mii_active = mii->mii_media_active;
1527 }
1528 return (0);
1529 }
1530
1531 /*
1532 * Determine status of internal transceiver
1533 */
1534 void
be_intphy_status(struct be_softc * sc)1535 be_intphy_status(struct be_softc *sc)
1536 {
1537 struct mii_data *mii = &sc->sc_mii;
1538 uint64_t media_active, media_status;
1539 int bmcr, bmsr;
1540
1541 media_status = IFM_AVALID;
1542 media_active = 0;
1543
1544 /*
1545 * Internal transceiver; do the work here.
1546 */
1547 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR);
1548
1549 switch (bmcr & (BMCR_S100 | BMCR_FDX)) {
1550 case (BMCR_S100 | BMCR_FDX):
1551 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1552 break;
1553 case BMCR_S100:
1554 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1555 break;
1556 case BMCR_FDX:
1557 media_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1558 break;
1559 case 0:
1560 media_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1561 break;
1562 }
1563
1564 /* Read twice in case the register is latched */
1565 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)|
1566 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR);
1567 if (bmsr & BMSR_LINK)
1568 media_status |= IFM_ACTIVE;
1569
1570 mii->mii_media_status = media_status;
1571 mii->mii_media_active = media_active;
1572 }
1573