1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "opt_ddb.h"
32 #include "opt_inet.h"
33 #include "opt_inet6.h"
34 #include "opt_kern_tls.h"
35 #include "opt_ratelimit.h"
36 #include "opt_rss.h"
37
38 #include <sys/param.h>
39 #include <sys/conf.h>
40 #include <sys/priv.h>
41 #include <sys/kernel.h>
42 #include <sys/bus.h>
43 #include <sys/eventhandler.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
53 #include <sys/sbuf.h>
54 #include <sys/smp.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
59 #include <net/if.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
63 #ifdef RSS
64 #include <net/rss_config.h>
65 #endif
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #ifdef KERN_TLS
69 #include <netinet/tcp_seq.h>
70 #endif
71 #if defined(__i386__) || defined(__amd64__)
72 #include <machine/md_var.h>
73 #include <machine/cputypes.h>
74 #include <vm/vm.h>
75 #include <vm/pmap.h>
76 #endif
77 #ifdef DDB
78 #include <ddb/ddb.h>
79 #include <ddb/db_lex.h>
80 #endif
81
82 #include "common/common.h"
83 #include "common/t4_msg.h"
84 #include "common/t4_regs.h"
85 #include "common/t4_regs_values.h"
86 #include "cudbg/cudbg.h"
87 #include "t4_clip.h"
88 #include "t4_ioctl.h"
89 #include "t4_l2t.h"
90 #include "t4_mp_ring.h"
91 #include "t4_if.h"
92 #include "t4_smt.h"
93
94 /* T4 bus driver interface */
95 static int t4_probe(device_t);
96 static int t4_attach(device_t);
97 static int t4_detach(device_t);
98 static int t4_child_location(device_t, device_t, struct sbuf *);
99 static int t4_ready(device_t);
100 static int t4_read_port_device(device_t, int, device_t *);
101 static int t4_suspend(device_t);
102 static int t4_resume(device_t);
103 static int t4_reset_prepare(device_t, device_t);
104 static int t4_reset_post(device_t, device_t);
105 static device_method_t t4_methods[] = {
106 DEVMETHOD(device_probe, t4_probe),
107 DEVMETHOD(device_attach, t4_attach),
108 DEVMETHOD(device_detach, t4_detach),
109 DEVMETHOD(device_suspend, t4_suspend),
110 DEVMETHOD(device_resume, t4_resume),
111
112 DEVMETHOD(bus_child_location, t4_child_location),
113 DEVMETHOD(bus_reset_prepare, t4_reset_prepare),
114 DEVMETHOD(bus_reset_post, t4_reset_post),
115
116 DEVMETHOD(t4_is_main_ready, t4_ready),
117 DEVMETHOD(t4_read_port_device, t4_read_port_device),
118
119 DEVMETHOD_END
120 };
121 static driver_t t4_driver = {
122 "t4nex",
123 t4_methods,
124 sizeof(struct adapter)
125 };
126
127
128 /* T4 port (cxgbe) interface */
129 static int cxgbe_probe(device_t);
130 static int cxgbe_attach(device_t);
131 static int cxgbe_detach(device_t);
132 device_method_t cxgbe_methods[] = {
133 DEVMETHOD(device_probe, cxgbe_probe),
134 DEVMETHOD(device_attach, cxgbe_attach),
135 DEVMETHOD(device_detach, cxgbe_detach),
136 { 0, 0 }
137 };
138 static driver_t cxgbe_driver = {
139 "cxgbe",
140 cxgbe_methods,
141 sizeof(struct port_info)
142 };
143
144 /* T4 VI (vcxgbe) interface */
145 static int vcxgbe_probe(device_t);
146 static int vcxgbe_attach(device_t);
147 static int vcxgbe_detach(device_t);
148 static device_method_t vcxgbe_methods[] = {
149 DEVMETHOD(device_probe, vcxgbe_probe),
150 DEVMETHOD(device_attach, vcxgbe_attach),
151 DEVMETHOD(device_detach, vcxgbe_detach),
152 { 0, 0 }
153 };
154 static driver_t vcxgbe_driver = {
155 "vcxgbe",
156 vcxgbe_methods,
157 sizeof(struct vi_info)
158 };
159
160 static d_ioctl_t t4_ioctl;
161
162 static struct cdevsw t4_cdevsw = {
163 .d_version = D_VERSION,
164 .d_ioctl = t4_ioctl,
165 .d_name = "t4nex",
166 };
167
168 /* T5 bus driver interface */
169 static int t5_probe(device_t);
170 static device_method_t t5_methods[] = {
171 DEVMETHOD(device_probe, t5_probe),
172 DEVMETHOD(device_attach, t4_attach),
173 DEVMETHOD(device_detach, t4_detach),
174 DEVMETHOD(device_suspend, t4_suspend),
175 DEVMETHOD(device_resume, t4_resume),
176
177 DEVMETHOD(bus_child_location, t4_child_location),
178 DEVMETHOD(bus_reset_prepare, t4_reset_prepare),
179 DEVMETHOD(bus_reset_post, t4_reset_post),
180
181 DEVMETHOD(t4_is_main_ready, t4_ready),
182 DEVMETHOD(t4_read_port_device, t4_read_port_device),
183
184 DEVMETHOD_END
185 };
186 static driver_t t5_driver = {
187 "t5nex",
188 t5_methods,
189 sizeof(struct adapter)
190 };
191
192
193 /* T5 port (cxl) interface */
194 static driver_t cxl_driver = {
195 "cxl",
196 cxgbe_methods,
197 sizeof(struct port_info)
198 };
199
200 /* T5 VI (vcxl) interface */
201 static driver_t vcxl_driver = {
202 "vcxl",
203 vcxgbe_methods,
204 sizeof(struct vi_info)
205 };
206
207 /* T6 bus driver interface */
208 static int t6_probe(device_t);
209 static device_method_t t6_methods[] = {
210 DEVMETHOD(device_probe, t6_probe),
211 DEVMETHOD(device_attach, t4_attach),
212 DEVMETHOD(device_detach, t4_detach),
213 DEVMETHOD(device_suspend, t4_suspend),
214 DEVMETHOD(device_resume, t4_resume),
215
216 DEVMETHOD(bus_child_location, t4_child_location),
217 DEVMETHOD(bus_reset_prepare, t4_reset_prepare),
218 DEVMETHOD(bus_reset_post, t4_reset_post),
219
220 DEVMETHOD(t4_is_main_ready, t4_ready),
221 DEVMETHOD(t4_read_port_device, t4_read_port_device),
222
223 DEVMETHOD_END
224 };
225 static driver_t t6_driver = {
226 "t6nex",
227 t6_methods,
228 sizeof(struct adapter)
229 };
230
231
232 /* T6 port (cc) interface */
233 static driver_t cc_driver = {
234 "cc",
235 cxgbe_methods,
236 sizeof(struct port_info)
237 };
238
239 /* T6 VI (vcc) interface */
240 static driver_t vcc_driver = {
241 "vcc",
242 vcxgbe_methods,
243 sizeof(struct vi_info)
244 };
245
246 /* ifnet interface */
247 static void cxgbe_init(void *);
248 static int cxgbe_ioctl(if_t, unsigned long, caddr_t);
249 static int cxgbe_transmit(if_t, struct mbuf *);
250 static void cxgbe_qflush(if_t);
251 #if defined(KERN_TLS) || defined(RATELIMIT)
252 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *,
253 struct m_snd_tag **);
254 #endif
255
256 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
257
258 /*
259 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
260 * then ADAPTER_LOCK, then t4_uld_list_lock.
261 */
262 static struct sx t4_list_lock;
263 SLIST_HEAD(, adapter) t4_list;
264 #ifdef TCP_OFFLOAD
265 static struct sx t4_uld_list_lock;
266 SLIST_HEAD(, uld_info) t4_uld_list;
267 #endif
268
269 /*
270 * Tunables. See tweak_tunables() too.
271 *
272 * Each tunable is set to a default value here if it's known at compile-time.
273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
274 * provide a reasonable default (upto n) when the driver is loaded.
275 *
276 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
277 * T5 are under hw.cxl.
278 */
279 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
280 "cxgbe(4) parameters");
281 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
282 "cxgbe(4) T5+ parameters");
283 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
284 "cxgbe(4) TOE parameters");
285
286 /*
287 * Number of queues for tx and rx, NIC and offload.
288 */
289 #define NTXQ 16
290 int t4_ntxq = -NTXQ;
291 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
292 "Number of TX queues per port");
293 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
294
295 #define NRXQ 8
296 int t4_nrxq = -NRXQ;
297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
298 "Number of RX queues per port");
299 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
300
301 #define NTXQ_VI 1
302 static int t4_ntxq_vi = -NTXQ_VI;
303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
304 "Number of TX queues per VI");
305
306 #define NRXQ_VI 1
307 static int t4_nrxq_vi = -NRXQ_VI;
308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
309 "Number of RX queues per VI");
310
311 static int t4_rsrv_noflowq = 0;
312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
313 0, "Reserve TX queue 0 of each VI for non-flowid packets");
314
315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
316 #define NOFLDTXQ 8
317 static int t4_nofldtxq = -NOFLDTXQ;
318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
319 "Number of offload TX queues per port");
320
321 #define NOFLDRXQ 2
322 static int t4_nofldrxq = -NOFLDRXQ;
323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
324 "Number of offload RX queues per port");
325
326 #define NOFLDTXQ_VI 1
327 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
328 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
329 "Number of offload TX queues per VI");
330
331 #define NOFLDRXQ_VI 1
332 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
334 "Number of offload RX queues per VI");
335
336 #define TMR_IDX_OFLD 1
337 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
338 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
339 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
340
341 #define PKTC_IDX_OFLD (-1)
342 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
343 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
344 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
345
346 /* 0 means chip/fw default, non-zero number is value in microseconds */
347 static u_long t4_toe_keepalive_idle = 0;
348 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
349 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
350
351 /* 0 means chip/fw default, non-zero number is value in microseconds */
352 static u_long t4_toe_keepalive_interval = 0;
353 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
354 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
355
356 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
357 static int t4_toe_keepalive_count = 0;
358 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
359 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
360
361 /* 0 means chip/fw default, non-zero number is value in microseconds */
362 static u_long t4_toe_rexmt_min = 0;
363 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
364 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
365
366 /* 0 means chip/fw default, non-zero number is value in microseconds */
367 static u_long t4_toe_rexmt_max = 0;
368 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
369 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
370
371 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
372 static int t4_toe_rexmt_count = 0;
373 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
374 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
375
376 /* -1 means chip/fw default, other values are raw backoff values to use */
377 static int t4_toe_rexmt_backoff[16] = {
378 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
379 };
380 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff,
381 CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
382 "cxgbe(4) TOE retransmit backoff values");
383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
384 &t4_toe_rexmt_backoff[0], 0, "");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[1], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[2], 0, "");
389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
390 &t4_toe_rexmt_backoff[3], 0, "");
391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
392 &t4_toe_rexmt_backoff[4], 0, "");
393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
394 &t4_toe_rexmt_backoff[5], 0, "");
395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
396 &t4_toe_rexmt_backoff[6], 0, "");
397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
398 &t4_toe_rexmt_backoff[7], 0, "");
399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
400 &t4_toe_rexmt_backoff[8], 0, "");
401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
402 &t4_toe_rexmt_backoff[9], 0, "");
403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
404 &t4_toe_rexmt_backoff[10], 0, "");
405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
406 &t4_toe_rexmt_backoff[11], 0, "");
407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
408 &t4_toe_rexmt_backoff[12], 0, "");
409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
410 &t4_toe_rexmt_backoff[13], 0, "");
411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
412 &t4_toe_rexmt_backoff[14], 0, "");
413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
414 &t4_toe_rexmt_backoff[15], 0, "");
415
416 int t4_ddp_rcvbuf_len = 256 * 1024;
417 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN,
418 &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer");
419
420 unsigned int t4_ddp_rcvbuf_cache = 4;
421 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN,
422 &t4_ddp_rcvbuf_cache, 0,
423 "maximum number of free DDP RX buffers to cache per connection");
424 #endif
425
426 #ifdef DEV_NETMAP
427 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */
428 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */
429 static int t4_native_netmap = NN_EXTRA_VI;
430 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
431 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs");
432
433 #define NNMTXQ 8
434 static int t4_nnmtxq = -NNMTXQ;
435 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
436 "Number of netmap TX queues");
437
438 #define NNMRXQ 8
439 static int t4_nnmrxq = -NNMRXQ;
440 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
441 "Number of netmap RX queues");
442
443 #define NNMTXQ_VI 2
444 static int t4_nnmtxq_vi = -NNMTXQ_VI;
445 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
446 "Number of netmap TX queues per VI");
447
448 #define NNMRXQ_VI 2
449 static int t4_nnmrxq_vi = -NNMRXQ_VI;
450 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
451 "Number of netmap RX queues per VI");
452 #endif
453
454 /*
455 * Holdoff parameters for ports.
456 */
457 #define TMR_IDX 1
458 int t4_tmr_idx = TMR_IDX;
459 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
460 0, "Holdoff timer index");
461 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
462
463 #define PKTC_IDX (-1)
464 int t4_pktc_idx = PKTC_IDX;
465 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
466 0, "Holdoff packet counter index");
467 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
468
469 /*
470 * Size (# of entries) of each tx and rx queue.
471 */
472 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
473 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
474 "Number of descriptors in each TX queue");
475
476 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
477 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
478 "Number of descriptors in each RX queue");
479
480 /*
481 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
482 */
483 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
484 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
485 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
486
487 /*
488 * Configuration file. All the _CF names here are special.
489 */
490 #define DEFAULT_CF "default"
491 #define BUILTIN_CF "built-in"
492 #define FLASH_CF "flash"
493 #define UWIRE_CF "uwire"
494 #define FPGA_CF "fpga"
495 static char t4_cfg_file[32] = DEFAULT_CF;
496 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
497 sizeof(t4_cfg_file), "Firmware configuration file");
498
499 /*
500 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
501 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
502 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
503 * mark or when signalled to do so, 0 to never emit PAUSE.
504 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
505 * negotiated settings will override rx_pause/tx_pause.
506 * Otherwise rx_pause/tx_pause are applied forcibly.
507 */
508 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
510 &t4_pause_settings, 0,
511 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
512
513 /*
514 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
515 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
516 * 0 to disable FEC.
517 */
518 static int t4_fec = -1;
519 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
520 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
521
522 /*
523 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it
524 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the
525 * driver runs as if this is set to 0.
526 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay.
527 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the
528 * transceiver. Multiple FEC bits may not be okay but will be passed on to
529 * the firmware anyway (may result in l1cfg errors with old firmwares).
530 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO
531 * means set all FEC bits that are valid for the speed.
532 */
533 static int t4_force_fec = -1;
534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0,
535 "Controls the use of FORCE_FEC bit in L1 configuration.");
536
537 /*
538 * Link autonegotiation.
539 * -1 to run with the firmware default.
540 * 0 to disable.
541 * 1 to enable.
542 */
543 static int t4_autoneg = -1;
544 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
545 "Link autonegotiation");
546
547 /*
548 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
549 * encouraged respectively). '-n' is the same as 'n' except the firmware
550 * version used in the checks is read from the firmware bundled with the driver.
551 */
552 static int t4_fw_install = 1;
553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
554 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
555
556 /*
557 * ASIC features that will be used. Disable the ones you don't want so that the
558 * chip resources aren't wasted on features that will not be used.
559 */
560 static int t4_nbmcaps_allowed = 0;
561 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
562 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
563
564 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
565 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
566 &t4_linkcaps_allowed, 0, "Default link capabilities");
567
568 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
569 FW_CAPS_CONFIG_SWITCH_EGRESS;
570 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
571 &t4_switchcaps_allowed, 0, "Default switch capabilities");
572
573 #ifdef RATELIMIT
574 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
575 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
576 #else
577 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
578 FW_CAPS_CONFIG_NIC_HASHFILTER;
579 #endif
580 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
581 &t4_niccaps_allowed, 0, "Default NIC capabilities");
582
583 static int t4_toecaps_allowed = -1;
584 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
585 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
586
587 static int t4_rdmacaps_allowed = -1;
588 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
589 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
590
591 static int t4_cryptocaps_allowed = -1;
592 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
593 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
594
595 static int t4_iscsicaps_allowed = -1;
596 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
597 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
598
599 static int t4_fcoecaps_allowed = 0;
600 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
601 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
602
603 static int t5_write_combine = 0;
604 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
605 0, "Use WC instead of UC for BAR2");
606
607 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */
608 static int t4_doorbells_allowed = 0xf;
609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN,
610 &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells");
611
612 static int t4_num_vis = 1;
613 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
614 "Number of VIs per port");
615
616 /*
617 * PCIe Relaxed Ordering.
618 * -1: driver should figure out a good value.
619 * 0: disable RO.
620 * 1: enable RO.
621 * 2: leave RO alone.
622 */
623 static int pcie_relaxed_ordering = -1;
624 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
625 &pcie_relaxed_ordering, 0,
626 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
627
628 static int t4_panic_on_fatal_err = 0;
629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN,
630 &t4_panic_on_fatal_err, 0, "panic on fatal errors");
631
632 static int t4_reset_on_fatal_err = 0;
633 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN,
634 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors");
635
636 static int t4_clock_gate_on_suspend = 0;
637 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN,
638 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend");
639
640 static int t4_tx_vm_wr = 0;
641 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0,
642 "Use VM work requests to transmit packets.");
643
644 /*
645 * Set to non-zero to enable the attack filter. A packet that matches any of
646 * these conditions will get dropped on ingress:
647 * 1) IP && source address == destination address.
648 * 2) TCP/IP && source address is not a unicast address.
649 * 3) TCP/IP && destination address is not a unicast address.
650 * 4) IP && source address is loopback (127.x.y.z).
651 * 5) IP && destination address is loopback (127.x.y.z).
652 * 6) IPv6 && source address == destination address.
653 * 7) IPv6 && source address is not a unicast address.
654 * 8) IPv6 && source address is loopback (::1/128).
655 * 9) IPv6 && destination address is loopback (::1/128).
656 * 10) IPv6 && source address is unspecified (::/128).
657 * 11) IPv6 && destination address is unspecified (::/128).
658 * 12) TCP/IPv6 && source address is multicast (ff00::/8).
659 * 13) TCP/IPv6 && destination address is multicast (ff00::/8).
660 */
661 static int t4_attack_filter = 0;
662 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN,
663 &t4_attack_filter, 0, "Drop suspicious traffic");
664
665 static int t4_drop_ip_fragments = 0;
666 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN,
667 &t4_drop_ip_fragments, 0, "Drop IP fragments");
668
669 static int t4_drop_pkts_with_l2_errors = 1;
670 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN,
671 &t4_drop_pkts_with_l2_errors, 0,
672 "Drop all frames with Layer 2 length or checksum errors");
673
674 static int t4_drop_pkts_with_l3_errors = 0;
675 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN,
676 &t4_drop_pkts_with_l3_errors, 0,
677 "Drop all frames with IP version, length, or checksum errors");
678
679 static int t4_drop_pkts_with_l4_errors = 0;
680 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN,
681 &t4_drop_pkts_with_l4_errors, 0,
682 "Drop all frames with Layer 4 length, checksum, or other errors");
683
684 #ifdef TCP_OFFLOAD
685 /*
686 * TOE tunables.
687 */
688 static int t4_cop_managed_offloading = 0;
689 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
690 &t4_cop_managed_offloading, 0,
691 "COP (Connection Offload Policy) controls all TOE offload");
692 #endif
693
694 #ifdef KERN_TLS
695 /*
696 * This enables KERN_TLS for all adapters if set.
697 */
698 static int t4_kern_tls = 0;
699 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
700 "Enable KERN_TLS mode for T6 adapters");
701
702 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
703 "cxgbe(4) KERN_TLS parameters");
704
705 static int t4_tls_inline_keys = 0;
706 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
707 &t4_tls_inline_keys, 0,
708 "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
709 "in card memory.");
710
711 static int t4_tls_combo_wrs = 0;
712 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
713 0, "Attempt to combine TCB field updates with TLS record work requests.");
714 #endif
715
716 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
717 static int vi_mac_funcs[] = {
718 FW_VI_FUNC_ETH,
719 FW_VI_FUNC_OFLD,
720 FW_VI_FUNC_IWARP,
721 FW_VI_FUNC_OPENISCSI,
722 FW_VI_FUNC_OPENFCOE,
723 FW_VI_FUNC_FOISCSI,
724 FW_VI_FUNC_FOFCOE,
725 };
726
727 struct intrs_and_queues {
728 uint16_t intr_type; /* INTx, MSI, or MSI-X */
729 uint16_t num_vis; /* number of VIs for each port */
730 uint16_t nirq; /* Total # of vectors */
731 uint16_t ntxq; /* # of NIC txq's for each port */
732 uint16_t nrxq; /* # of NIC rxq's for each port */
733 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
734 uint16_t nofldrxq; /* # of TOE rxq's for each port */
735 uint16_t nnmtxq; /* # of netmap txq's */
736 uint16_t nnmrxq; /* # of netmap rxq's */
737
738 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
739 uint16_t ntxq_vi; /* # of NIC txq's */
740 uint16_t nrxq_vi; /* # of NIC rxq's */
741 uint16_t nofldtxq_vi; /* # of TOE txq's */
742 uint16_t nofldrxq_vi; /* # of TOE rxq's */
743 uint16_t nnmtxq_vi; /* # of netmap txq's */
744 uint16_t nnmrxq_vi; /* # of netmap rxq's */
745 };
746
747 static void setup_memwin(struct adapter *);
748 static void position_memwin(struct adapter *, int, uint32_t);
749 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
750 static int fwmtype_to_hwmtype(int);
751 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
752 uint32_t *);
753 static int fixup_devlog_params(struct adapter *);
754 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
755 static int contact_firmware(struct adapter *);
756 static int partition_resources(struct adapter *);
757 static int get_params__pre_init(struct adapter *);
758 static int set_params__pre_init(struct adapter *);
759 static int get_params__post_init(struct adapter *);
760 static int set_params__post_init(struct adapter *);
761 static void t4_set_desc(struct adapter *);
762 static bool fixed_ifmedia(struct port_info *);
763 static void build_medialist(struct port_info *);
764 static void init_link_config(struct port_info *);
765 static int fixup_link_config(struct port_info *);
766 static int apply_link_config(struct port_info *);
767 static int cxgbe_init_synchronized(struct vi_info *);
768 static int cxgbe_uninit_synchronized(struct vi_info *);
769 static int adapter_full_init(struct adapter *);
770 static void adapter_full_uninit(struct adapter *);
771 static int vi_full_init(struct vi_info *);
772 static void vi_full_uninit(struct vi_info *);
773 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *);
774 static void quiesce_txq(struct sge_txq *);
775 static void quiesce_wrq(struct sge_wrq *);
776 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
777 static void quiesce_vi(struct vi_info *);
778 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
779 driver_intr_t *, void *, char *);
780 static int t4_free_irq(struct adapter *, struct irq *);
781 static void t4_init_atid_table(struct adapter *);
782 static void t4_free_atid_table(struct adapter *);
783 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
784 static void vi_refresh_stats(struct vi_info *);
785 static void cxgbe_refresh_stats(struct vi_info *);
786 static void cxgbe_tick(void *);
787 static void vi_tick(void *);
788 static void cxgbe_sysctls(struct port_info *);
789 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
790 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
791 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
792 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
793 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
794 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS);
795 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
796 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
797 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
798 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
799 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
800 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS);
801 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS);
802 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
803 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
804 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS);
805 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
806 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
807 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
808 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
809 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
810 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
811 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
812 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
813 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
814 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
815 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
816 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
817 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
818 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS);
819 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
820 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
821 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
822 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
823 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
824 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
825 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
826 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
827 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
828 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
829 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
830 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
831 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
832 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
833 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS);
834 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
835 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
836 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
837 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
838 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
839 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
840 static int sysctl_reset(SYSCTL_HANDLER_ARGS);
841 #ifdef TCP_OFFLOAD
842 static int sysctl_tls(SYSCTL_HANDLER_ARGS);
843 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
844 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
845 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
846 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
847 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
848 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
849 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
850 #endif
851 static int get_sge_context(struct adapter *, struct t4_sge_context *);
852 static int load_fw(struct adapter *, struct t4_data *);
853 static int load_cfg(struct adapter *, struct t4_data *);
854 static int load_boot(struct adapter *, struct t4_bootrom *);
855 static int load_bootcfg(struct adapter *, struct t4_data *);
856 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
857 static void free_offload_policy(struct t4_offload_policy *);
858 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
859 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
860 static int read_i2c(struct adapter *, struct t4_i2c_data *);
861 static int clear_stats(struct adapter *, u_int);
862 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *);
863 static int release_clip_addr(struct adapter *, struct t4_clip_addr *);
864 #ifdef TCP_OFFLOAD
865 static int toe_capability(struct vi_info *, bool);
866 static int t4_deactivate_all_uld(struct adapter *);
867 static void t4_async_event(struct adapter *);
868 #endif
869 #ifdef KERN_TLS
870 static int ktls_capability(struct adapter *, bool);
871 #endif
872 static int mod_event(module_t, int, void *);
873 static int notify_siblings(device_t, int);
874 static uint64_t vi_get_counter(if_t, ift_counter);
875 static uint64_t cxgbe_get_counter(if_t, ift_counter);
876 static void enable_vxlan_rx(struct adapter *);
877 static void reset_adapter_task(void *, int);
878 static void fatal_error_task(void *, int);
879 static void dump_devlog(struct adapter *);
880 static void dump_cim_regs(struct adapter *);
881 static void dump_cimla(struct adapter *);
882
883 struct {
884 uint16_t device;
885 char *desc;
886 } t4_pciids[] = {
887 {0xa000, "Chelsio Terminator 4 FPGA"},
888 {0x4400, "Chelsio T440-dbg"},
889 {0x4401, "Chelsio T420-CR"},
890 {0x4402, "Chelsio T422-CR"},
891 {0x4403, "Chelsio T440-CR"},
892 {0x4404, "Chelsio T420-BCH"},
893 {0x4405, "Chelsio T440-BCH"},
894 {0x4406, "Chelsio T440-CH"},
895 {0x4407, "Chelsio T420-SO"},
896 {0x4408, "Chelsio T420-CX"},
897 {0x4409, "Chelsio T420-BT"},
898 {0x440a, "Chelsio T404-BT"},
899 {0x440e, "Chelsio T440-LP-CR"},
900 }, t5_pciids[] = {
901 {0xb000, "Chelsio Terminator 5 FPGA"},
902 {0x5400, "Chelsio T580-dbg"},
903 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
904 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
905 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
906 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
907 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
908 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
909 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
910 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
911 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
912 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
913 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
914 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
915 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
916 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
917 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
918 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
919 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
920
921 /* Custom */
922 {0x5483, "Custom T540-CR"},
923 {0x5484, "Custom T540-BT"},
924 }, t6_pciids[] = {
925 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
926 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
927 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
928 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
929 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
930 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
931 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
932 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
933 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
934 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
935 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
936 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
937 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
938 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
939 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
940 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
941
942 /* Custom */
943 {0x6480, "Custom T6225-CR"},
944 {0x6481, "Custom T62100-CR"},
945 {0x6482, "Custom T6225-CR"},
946 {0x6483, "Custom T62100-CR"},
947 {0x6484, "Custom T64100-CR"},
948 {0x6485, "Custom T6240-SO"},
949 {0x6486, "Custom T6225-SO-CR"},
950 {0x6487, "Custom T6225-CR"},
951 };
952
953 #ifdef TCP_OFFLOAD
954 /*
955 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
956 * be exactly the same for both rxq and ofld_rxq.
957 */
958 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
959 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
960 #endif
961 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
962
963 static int
t4_probe(device_t dev)964 t4_probe(device_t dev)
965 {
966 int i;
967 uint16_t v = pci_get_vendor(dev);
968 uint16_t d = pci_get_device(dev);
969 uint8_t f = pci_get_function(dev);
970
971 if (v != PCI_VENDOR_ID_CHELSIO)
972 return (ENXIO);
973
974 /* Attach only to PF0 of the FPGA */
975 if (d == 0xa000 && f != 0)
976 return (ENXIO);
977
978 for (i = 0; i < nitems(t4_pciids); i++) {
979 if (d == t4_pciids[i].device) {
980 device_set_desc(dev, t4_pciids[i].desc);
981 return (BUS_PROBE_DEFAULT);
982 }
983 }
984
985 return (ENXIO);
986 }
987
988 static int
t5_probe(device_t dev)989 t5_probe(device_t dev)
990 {
991 int i;
992 uint16_t v = pci_get_vendor(dev);
993 uint16_t d = pci_get_device(dev);
994 uint8_t f = pci_get_function(dev);
995
996 if (v != PCI_VENDOR_ID_CHELSIO)
997 return (ENXIO);
998
999 /* Attach only to PF0 of the FPGA */
1000 if (d == 0xb000 && f != 0)
1001 return (ENXIO);
1002
1003 for (i = 0; i < nitems(t5_pciids); i++) {
1004 if (d == t5_pciids[i].device) {
1005 device_set_desc(dev, t5_pciids[i].desc);
1006 return (BUS_PROBE_DEFAULT);
1007 }
1008 }
1009
1010 return (ENXIO);
1011 }
1012
1013 static int
t6_probe(device_t dev)1014 t6_probe(device_t dev)
1015 {
1016 int i;
1017 uint16_t v = pci_get_vendor(dev);
1018 uint16_t d = pci_get_device(dev);
1019
1020 if (v != PCI_VENDOR_ID_CHELSIO)
1021 return (ENXIO);
1022
1023 for (i = 0; i < nitems(t6_pciids); i++) {
1024 if (d == t6_pciids[i].device) {
1025 device_set_desc(dev, t6_pciids[i].desc);
1026 return (BUS_PROBE_DEFAULT);
1027 }
1028 }
1029
1030 return (ENXIO);
1031 }
1032
1033 static void
t5_attribute_workaround(device_t dev)1034 t5_attribute_workaround(device_t dev)
1035 {
1036 device_t root_port;
1037 uint32_t v;
1038
1039 /*
1040 * The T5 chips do not properly echo the No Snoop and Relaxed
1041 * Ordering attributes when replying to a TLP from a Root
1042 * Port. As a workaround, find the parent Root Port and
1043 * disable No Snoop and Relaxed Ordering. Note that this
1044 * affects all devices under this root port.
1045 */
1046 root_port = pci_find_pcie_root_port(dev);
1047 if (root_port == NULL) {
1048 device_printf(dev, "Unable to find parent root port\n");
1049 return;
1050 }
1051
1052 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
1053 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
1054 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
1055 0)
1056 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
1057 device_get_nameunit(root_port));
1058 }
1059
1060 static const struct devnames devnames[] = {
1061 {
1062 .nexus_name = "t4nex",
1063 .ifnet_name = "cxgbe",
1064 .vi_ifnet_name = "vcxgbe",
1065 .pf03_drv_name = "t4iov",
1066 .vf_nexus_name = "t4vf",
1067 .vf_ifnet_name = "cxgbev"
1068 }, {
1069 .nexus_name = "t5nex",
1070 .ifnet_name = "cxl",
1071 .vi_ifnet_name = "vcxl",
1072 .pf03_drv_name = "t5iov",
1073 .vf_nexus_name = "t5vf",
1074 .vf_ifnet_name = "cxlv"
1075 }, {
1076 .nexus_name = "t6nex",
1077 .ifnet_name = "cc",
1078 .vi_ifnet_name = "vcc",
1079 .pf03_drv_name = "t6iov",
1080 .vf_nexus_name = "t6vf",
1081 .vf_ifnet_name = "ccv"
1082 }
1083 };
1084
1085 void
t4_init_devnames(struct adapter * sc)1086 t4_init_devnames(struct adapter *sc)
1087 {
1088 int id;
1089
1090 id = chip_id(sc);
1091 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
1092 sc->names = &devnames[id - CHELSIO_T4];
1093 else {
1094 device_printf(sc->dev, "chip id %d is not supported.\n", id);
1095 sc->names = NULL;
1096 }
1097 }
1098
1099 static int
t4_ifnet_unit(struct adapter * sc,struct port_info * pi)1100 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
1101 {
1102 const char *parent, *name;
1103 long value;
1104 int line, unit;
1105
1106 line = 0;
1107 parent = device_get_nameunit(sc->dev);
1108 name = sc->names->ifnet_name;
1109 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
1110 if (resource_long_value(name, unit, "port", &value) == 0 &&
1111 value == pi->port_id)
1112 return (unit);
1113 }
1114 return (-1);
1115 }
1116
1117 static void
t4_calibration(void * arg)1118 t4_calibration(void *arg)
1119 {
1120 struct adapter *sc;
1121 struct clock_sync *cur, *nex;
1122 uint64_t hw;
1123 sbintime_t sbt;
1124 int next_up;
1125
1126 sc = (struct adapter *)arg;
1127
1128 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration"));
1129 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO);
1130 sbt = sbinuptime();
1131
1132 cur = &sc->cal_info[sc->cal_current];
1133 next_up = (sc->cal_current + 1) % CNT_CAL_INFO;
1134 nex = &sc->cal_info[next_up];
1135 if (__predict_false(sc->cal_count == 0)) {
1136 /* First time in, just get the values in */
1137 cur->hw_cur = hw;
1138 cur->sbt_cur = sbt;
1139 sc->cal_count++;
1140 goto done;
1141 }
1142
1143 if (cur->hw_cur == hw) {
1144 /* The clock is not advancing? */
1145 sc->cal_count = 0;
1146 atomic_store_rel_int(&cur->gen, 0);
1147 goto done;
1148 }
1149
1150 seqc_write_begin(&nex->gen);
1151 nex->hw_prev = cur->hw_cur;
1152 nex->sbt_prev = cur->sbt_cur;
1153 nex->hw_cur = hw;
1154 nex->sbt_cur = sbt;
1155 seqc_write_end(&nex->gen);
1156 sc->cal_current = next_up;
1157 done:
1158 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration,
1159 sc, C_DIRECT_EXEC);
1160 }
1161
1162 static void
t4_calibration_start(struct adapter * sc)1163 t4_calibration_start(struct adapter *sc)
1164 {
1165 /*
1166 * Here if we have not done a calibration
1167 * then do so otherwise start the appropriate
1168 * timer.
1169 */
1170 int i;
1171
1172 for (i = 0; i < CNT_CAL_INFO; i++) {
1173 sc->cal_info[i].gen = 0;
1174 }
1175 sc->cal_current = 0;
1176 sc->cal_count = 0;
1177 sc->cal_gen = 0;
1178 t4_calibration(sc);
1179 }
1180
1181 static int
t4_attach(device_t dev)1182 t4_attach(device_t dev)
1183 {
1184 struct adapter *sc;
1185 int rc = 0, i, j, rqidx, tqidx, nports;
1186 struct make_dev_args mda;
1187 struct intrs_and_queues iaq;
1188 struct sge *s;
1189 uint32_t *buf;
1190 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1191 int ofld_tqidx;
1192 #endif
1193 #ifdef TCP_OFFLOAD
1194 int ofld_rqidx;
1195 #endif
1196 #ifdef DEV_NETMAP
1197 int nm_rqidx, nm_tqidx;
1198 #endif
1199 int num_vis;
1200
1201 sc = device_get_softc(dev);
1202 sc->dev = dev;
1203 sysctl_ctx_init(&sc->ctx);
1204 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1205
1206 if ((pci_get_device(dev) & 0xff00) == 0x5400)
1207 t5_attribute_workaround(dev);
1208 pci_enable_busmaster(dev);
1209 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1210 uint32_t v;
1211
1212 pci_set_max_read_req(dev, 4096);
1213 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1214 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1215 if (pcie_relaxed_ordering == 0 &&
1216 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1217 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1218 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1219 } else if (pcie_relaxed_ordering == 1 &&
1220 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1221 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1222 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1223 }
1224 }
1225
1226 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1227 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1228 sc->traceq = -1;
1229 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1230 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1231 device_get_nameunit(dev));
1232
1233 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1234 device_get_nameunit(dev));
1235 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1236 t4_add_adapter(sc);
1237
1238 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1239 TAILQ_INIT(&sc->sfl);
1240 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1241
1242 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1243
1244 sc->policy = NULL;
1245 rw_init(&sc->policy_lock, "connection offload policy");
1246
1247 callout_init(&sc->ktls_tick, 1);
1248
1249 callout_init(&sc->cal_callout, 1);
1250
1251 refcount_init(&sc->vxlan_refcount, 0);
1252
1253 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc);
1254 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc);
1255
1256 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1257 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq",
1258 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1259 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1260 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq",
1261 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
1262
1263 rc = t4_map_bars_0_and_4(sc);
1264 if (rc != 0)
1265 goto done; /* error message displayed already */
1266
1267 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1268
1269 /* Prepare the adapter for operation. */
1270 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1271 rc = -t4_prep_adapter(sc, buf);
1272 free(buf, M_CXGBE);
1273 if (rc != 0) {
1274 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1275 goto done;
1276 }
1277
1278 /*
1279 * This is the real PF# to which we're attaching. Works from within PCI
1280 * passthrough environments too, where pci_get_function() could return a
1281 * different PF# depending on the passthrough configuration. We need to
1282 * use the real PF# in all our communication with the firmware.
1283 */
1284 j = t4_read_reg(sc, A_PL_WHOAMI);
1285 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1286 sc->mbox = sc->pf;
1287
1288 t4_init_devnames(sc);
1289 if (sc->names == NULL) {
1290 rc = ENOTSUP;
1291 goto done; /* error message displayed already */
1292 }
1293
1294 /*
1295 * Do this really early, with the memory windows set up even before the
1296 * character device. The userland tool's register i/o and mem read
1297 * will work even in "recovery mode".
1298 */
1299 setup_memwin(sc);
1300 if (t4_init_devlog_params(sc, 0) == 0)
1301 fixup_devlog_params(sc);
1302 make_dev_args_init(&mda);
1303 mda.mda_devsw = &t4_cdevsw;
1304 mda.mda_uid = UID_ROOT;
1305 mda.mda_gid = GID_WHEEL;
1306 mda.mda_mode = 0600;
1307 mda.mda_si_drv1 = sc;
1308 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1309 if (rc != 0)
1310 device_printf(dev, "failed to create nexus char device: %d.\n",
1311 rc);
1312
1313 /* Go no further if recovery mode has been requested. */
1314 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1315 device_printf(dev, "recovery mode.\n");
1316 goto done;
1317 }
1318
1319 #if defined(__i386__)
1320 if ((cpu_feature & CPUID_CX8) == 0) {
1321 device_printf(dev, "64 bit atomics not available.\n");
1322 rc = ENOTSUP;
1323 goto done;
1324 }
1325 #endif
1326
1327 /* Contact the firmware and try to become the master driver. */
1328 rc = contact_firmware(sc);
1329 if (rc != 0)
1330 goto done; /* error message displayed already */
1331 MPASS(sc->flags & FW_OK);
1332
1333 rc = get_params__pre_init(sc);
1334 if (rc != 0)
1335 goto done; /* error message displayed already */
1336
1337 if (sc->flags & MASTER_PF) {
1338 rc = partition_resources(sc);
1339 if (rc != 0)
1340 goto done; /* error message displayed already */
1341 }
1342
1343 rc = get_params__post_init(sc);
1344 if (rc != 0)
1345 goto done; /* error message displayed already */
1346
1347 rc = set_params__post_init(sc);
1348 if (rc != 0)
1349 goto done; /* error message displayed already */
1350
1351 rc = t4_map_bar_2(sc);
1352 if (rc != 0)
1353 goto done; /* error message displayed already */
1354
1355 rc = t4_adj_doorbells(sc);
1356 if (rc != 0)
1357 goto done; /* error message displayed already */
1358
1359 rc = t4_create_dma_tag(sc);
1360 if (rc != 0)
1361 goto done; /* error message displayed already */
1362
1363 /*
1364 * First pass over all the ports - allocate VIs and initialize some
1365 * basic parameters like mac address, port type, etc.
1366 */
1367 for_each_port(sc, i) {
1368 struct port_info *pi;
1369
1370 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1371 sc->port[i] = pi;
1372
1373 /* These must be set before t4_port_init */
1374 pi->adapter = sc;
1375 pi->port_id = i;
1376 /*
1377 * XXX: vi[0] is special so we can't delay this allocation until
1378 * pi->nvi's final value is known.
1379 */
1380 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1381 M_ZERO | M_WAITOK);
1382
1383 /*
1384 * Allocate the "main" VI and initialize parameters
1385 * like mac addr.
1386 */
1387 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1388 if (rc != 0) {
1389 device_printf(dev, "unable to initialize port %d: %d\n",
1390 i, rc);
1391 free(pi->vi, M_CXGBE);
1392 free(pi, M_CXGBE);
1393 sc->port[i] = NULL;
1394 goto done;
1395 }
1396
1397 if (is_bt(pi->port_type))
1398 setbit(&sc->bt_map, pi->tx_chan);
1399 else
1400 MPASS(!isset(&sc->bt_map, pi->tx_chan));
1401
1402 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1403 device_get_nameunit(dev), i);
1404 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1405 sc->chan_map[pi->tx_chan] = i;
1406
1407 /*
1408 * The MPS counter for FCS errors doesn't work correctly on the
1409 * T6 so we use the MAC counter here. Which MAC is in use
1410 * depends on the link settings which will be known when the
1411 * link comes up.
1412 */
1413 if (is_t6(sc))
1414 pi->fcs_reg = -1;
1415 else {
1416 pi->fcs_reg = t4_port_reg(sc, pi->tx_chan,
1417 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L);
1418 }
1419 pi->fcs_base = 0;
1420
1421 /* All VIs on this port share this media. */
1422 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1423 cxgbe_media_status);
1424
1425 PORT_LOCK(pi);
1426 init_link_config(pi);
1427 fixup_link_config(pi);
1428 build_medialist(pi);
1429 if (fixed_ifmedia(pi))
1430 pi->flags |= FIXED_IFMEDIA;
1431 PORT_UNLOCK(pi);
1432
1433 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1434 t4_ifnet_unit(sc, pi));
1435 if (pi->dev == NULL) {
1436 device_printf(dev,
1437 "failed to add device for port %d.\n", i);
1438 rc = ENXIO;
1439 goto done;
1440 }
1441 pi->vi[0].dev = pi->dev;
1442 device_set_softc(pi->dev, pi);
1443 }
1444
1445 /*
1446 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1447 */
1448 nports = sc->params.nports;
1449 rc = cfg_itype_and_nqueues(sc, &iaq);
1450 if (rc != 0)
1451 goto done; /* error message displayed already */
1452
1453 num_vis = iaq.num_vis;
1454 sc->intr_type = iaq.intr_type;
1455 sc->intr_count = iaq.nirq;
1456
1457 s = &sc->sge;
1458 s->nrxq = nports * iaq.nrxq;
1459 s->ntxq = nports * iaq.ntxq;
1460 if (num_vis > 1) {
1461 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1462 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1463 }
1464 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1465 s->neq += nports; /* ctrl queues: 1 per port */
1466 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1467 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1468 if (is_offload(sc) || is_ethoffload(sc)) {
1469 s->nofldtxq = nports * iaq.nofldtxq;
1470 if (num_vis > 1)
1471 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1472 s->neq += s->nofldtxq;
1473
1474 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq),
1475 M_CXGBE, M_ZERO | M_WAITOK);
1476 }
1477 #endif
1478 #ifdef TCP_OFFLOAD
1479 if (is_offload(sc)) {
1480 s->nofldrxq = nports * iaq.nofldrxq;
1481 if (num_vis > 1)
1482 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1483 s->neq += s->nofldrxq; /* free list */
1484 s->niq += s->nofldrxq;
1485
1486 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1487 M_CXGBE, M_ZERO | M_WAITOK);
1488 }
1489 #endif
1490 #ifdef DEV_NETMAP
1491 s->nnmrxq = 0;
1492 s->nnmtxq = 0;
1493 if (t4_native_netmap & NN_MAIN_VI) {
1494 s->nnmrxq += nports * iaq.nnmrxq;
1495 s->nnmtxq += nports * iaq.nnmtxq;
1496 }
1497 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1498 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1499 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1500 }
1501 s->neq += s->nnmtxq + s->nnmrxq;
1502 s->niq += s->nnmrxq;
1503
1504 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1505 M_CXGBE, M_ZERO | M_WAITOK);
1506 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1507 M_CXGBE, M_ZERO | M_WAITOK);
1508 #endif
1509 MPASS(s->niq <= s->iqmap_sz);
1510 MPASS(s->neq <= s->eqmap_sz);
1511
1512 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1513 M_ZERO | M_WAITOK);
1514 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1515 M_ZERO | M_WAITOK);
1516 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1517 M_ZERO | M_WAITOK);
1518 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
1519 M_ZERO | M_WAITOK);
1520 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
1521 M_ZERO | M_WAITOK);
1522
1523 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1524 M_ZERO | M_WAITOK);
1525
1526 t4_init_l2t(sc, M_WAITOK);
1527 t4_init_smt(sc, M_WAITOK);
1528 t4_init_tx_sched(sc);
1529 t4_init_atid_table(sc);
1530 #ifdef RATELIMIT
1531 t4_init_etid_table(sc);
1532 #endif
1533 #ifdef INET6
1534 t4_init_clip_table(sc);
1535 #endif
1536 if (sc->vres.key.size != 0)
1537 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1538 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1539
1540 /*
1541 * Second pass over the ports. This time we know the number of rx and
1542 * tx queues that each port should get.
1543 */
1544 rqidx = tqidx = 0;
1545 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1546 ofld_tqidx = 0;
1547 #endif
1548 #ifdef TCP_OFFLOAD
1549 ofld_rqidx = 0;
1550 #endif
1551 #ifdef DEV_NETMAP
1552 nm_rqidx = nm_tqidx = 0;
1553 #endif
1554 for_each_port(sc, i) {
1555 struct port_info *pi = sc->port[i];
1556 struct vi_info *vi;
1557
1558 if (pi == NULL)
1559 continue;
1560
1561 pi->nvi = num_vis;
1562 for_each_vi(pi, j, vi) {
1563 vi->pi = pi;
1564 vi->adapter = sc;
1565 vi->first_intr = -1;
1566 vi->qsize_rxq = t4_qsize_rxq;
1567 vi->qsize_txq = t4_qsize_txq;
1568
1569 vi->first_rxq = rqidx;
1570 vi->first_txq = tqidx;
1571 vi->tmr_idx = t4_tmr_idx;
1572 vi->pktc_idx = t4_pktc_idx;
1573 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1574 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1575
1576 rqidx += vi->nrxq;
1577 tqidx += vi->ntxq;
1578
1579 if (j == 0 && vi->ntxq > 1)
1580 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1581 else
1582 vi->rsrv_noflowq = 0;
1583
1584 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1585 vi->first_ofld_txq = ofld_tqidx;
1586 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1587 ofld_tqidx += vi->nofldtxq;
1588 #endif
1589 #ifdef TCP_OFFLOAD
1590 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1591 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1592 vi->first_ofld_rxq = ofld_rqidx;
1593 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1594
1595 ofld_rqidx += vi->nofldrxq;
1596 #endif
1597 #ifdef DEV_NETMAP
1598 vi->first_nm_rxq = nm_rqidx;
1599 vi->first_nm_txq = nm_tqidx;
1600 if (j == 0) {
1601 vi->nnmrxq = iaq.nnmrxq;
1602 vi->nnmtxq = iaq.nnmtxq;
1603 } else {
1604 vi->nnmrxq = iaq.nnmrxq_vi;
1605 vi->nnmtxq = iaq.nnmtxq_vi;
1606 }
1607 nm_rqidx += vi->nnmrxq;
1608 nm_tqidx += vi->nnmtxq;
1609 #endif
1610 }
1611 }
1612
1613 rc = t4_setup_intr_handlers(sc);
1614 if (rc != 0) {
1615 device_printf(dev,
1616 "failed to setup interrupt handlers: %d\n", rc);
1617 goto done;
1618 }
1619
1620 rc = bus_generic_probe(dev);
1621 if (rc != 0) {
1622 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1623 goto done;
1624 }
1625
1626 /*
1627 * Ensure thread-safe mailbox access (in debug builds).
1628 *
1629 * So far this was the only thread accessing the mailbox but various
1630 * ifnets and sysctls are about to be created and their handlers/ioctls
1631 * will access the mailbox from different threads.
1632 */
1633 sc->flags |= CHK_MBOX_ACCESS;
1634
1635 rc = bus_generic_attach(dev);
1636 if (rc != 0) {
1637 device_printf(dev,
1638 "failed to attach all child ports: %d\n", rc);
1639 goto done;
1640 }
1641 t4_calibration_start(sc);
1642
1643 device_printf(dev,
1644 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1645 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1646 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1647 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1648 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1649
1650 t4_set_desc(sc);
1651
1652 notify_siblings(dev, 0);
1653
1654 done:
1655 if (rc != 0 && sc->cdev) {
1656 /* cdev was created and so cxgbetool works; recover that way. */
1657 device_printf(dev,
1658 "error during attach, adapter is now in recovery mode.\n");
1659 rc = 0;
1660 }
1661
1662 if (rc != 0)
1663 t4_detach_common(dev);
1664 else
1665 t4_sysctls(sc);
1666
1667 return (rc);
1668 }
1669
1670 static int
t4_child_location(device_t bus,device_t dev,struct sbuf * sb)1671 t4_child_location(device_t bus, device_t dev, struct sbuf *sb)
1672 {
1673 struct adapter *sc;
1674 struct port_info *pi;
1675 int i;
1676
1677 sc = device_get_softc(bus);
1678 for_each_port(sc, i) {
1679 pi = sc->port[i];
1680 if (pi != NULL && pi->dev == dev) {
1681 sbuf_printf(sb, "port=%d", pi->port_id);
1682 break;
1683 }
1684 }
1685 return (0);
1686 }
1687
1688 static int
t4_ready(device_t dev)1689 t4_ready(device_t dev)
1690 {
1691 struct adapter *sc;
1692
1693 sc = device_get_softc(dev);
1694 if (sc->flags & FW_OK)
1695 return (0);
1696 return (ENXIO);
1697 }
1698
1699 static int
t4_read_port_device(device_t dev,int port,device_t * child)1700 t4_read_port_device(device_t dev, int port, device_t *child)
1701 {
1702 struct adapter *sc;
1703 struct port_info *pi;
1704
1705 sc = device_get_softc(dev);
1706 if (port < 0 || port >= MAX_NPORTS)
1707 return (EINVAL);
1708 pi = sc->port[port];
1709 if (pi == NULL || pi->dev == NULL)
1710 return (ENXIO);
1711 *child = pi->dev;
1712 return (0);
1713 }
1714
1715 static int
notify_siblings(device_t dev,int detaching)1716 notify_siblings(device_t dev, int detaching)
1717 {
1718 device_t sibling;
1719 int error, i;
1720
1721 error = 0;
1722 for (i = 0; i < PCI_FUNCMAX; i++) {
1723 if (i == pci_get_function(dev))
1724 continue;
1725 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1726 pci_get_slot(dev), i);
1727 if (sibling == NULL || !device_is_attached(sibling))
1728 continue;
1729 if (detaching)
1730 error = T4_DETACH_CHILD(sibling);
1731 else
1732 (void)T4_ATTACH_CHILD(sibling);
1733 if (error)
1734 break;
1735 }
1736 return (error);
1737 }
1738
1739 /*
1740 * Idempotent
1741 */
1742 static int
t4_detach(device_t dev)1743 t4_detach(device_t dev)
1744 {
1745 int rc;
1746
1747 rc = notify_siblings(dev, 1);
1748 if (rc) {
1749 device_printf(dev,
1750 "failed to detach sibling devices: %d\n", rc);
1751 return (rc);
1752 }
1753
1754 return (t4_detach_common(dev));
1755 }
1756
1757 int
t4_detach_common(device_t dev)1758 t4_detach_common(device_t dev)
1759 {
1760 struct adapter *sc;
1761 struct port_info *pi;
1762 int i, rc;
1763
1764 sc = device_get_softc(dev);
1765
1766 #ifdef TCP_OFFLOAD
1767 rc = t4_deactivate_all_uld(sc);
1768 if (rc) {
1769 device_printf(dev,
1770 "failed to detach upper layer drivers: %d\n", rc);
1771 return (rc);
1772 }
1773 #endif
1774
1775 if (sc->cdev) {
1776 destroy_dev(sc->cdev);
1777 sc->cdev = NULL;
1778 }
1779
1780 sx_xlock(&t4_list_lock);
1781 SLIST_REMOVE(&t4_list, sc, adapter, link);
1782 sx_xunlock(&t4_list_lock);
1783
1784 sc->flags &= ~CHK_MBOX_ACCESS;
1785 if (sc->flags & FULL_INIT_DONE) {
1786 if (!(sc->flags & IS_VF))
1787 t4_intr_disable(sc);
1788 }
1789
1790 if (device_is_attached(dev)) {
1791 rc = bus_generic_detach(dev);
1792 if (rc) {
1793 device_printf(dev,
1794 "failed to detach child devices: %d\n", rc);
1795 return (rc);
1796 }
1797 }
1798
1799 for (i = 0; i < sc->intr_count; i++)
1800 t4_free_irq(sc, &sc->irq[i]);
1801
1802 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1803 t4_free_tx_sched(sc);
1804
1805 for (i = 0; i < MAX_NPORTS; i++) {
1806 pi = sc->port[i];
1807 if (pi) {
1808 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1809 if (pi->dev)
1810 device_delete_child(dev, pi->dev);
1811
1812 mtx_destroy(&pi->pi_lock);
1813 free(pi->vi, M_CXGBE);
1814 free(pi, M_CXGBE);
1815 }
1816 }
1817 callout_stop(&sc->cal_callout);
1818 callout_drain(&sc->cal_callout);
1819 device_delete_children(dev);
1820 sysctl_ctx_free(&sc->ctx);
1821 adapter_full_uninit(sc);
1822
1823 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1824 t4_fw_bye(sc, sc->mbox);
1825
1826 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1827 pci_release_msi(dev);
1828
1829 if (sc->regs_res)
1830 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1831 sc->regs_res);
1832
1833 if (sc->udbs_res)
1834 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1835 sc->udbs_res);
1836
1837 if (sc->msix_res)
1838 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1839 sc->msix_res);
1840
1841 if (sc->l2t)
1842 t4_free_l2t(sc->l2t);
1843 if (sc->smt)
1844 t4_free_smt(sc->smt);
1845 t4_free_atid_table(sc);
1846 #ifdef RATELIMIT
1847 t4_free_etid_table(sc);
1848 #endif
1849 if (sc->key_map)
1850 vmem_destroy(sc->key_map);
1851 #ifdef INET6
1852 t4_destroy_clip_table(sc);
1853 #endif
1854
1855 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1856 free(sc->sge.ofld_txq, M_CXGBE);
1857 #endif
1858 #ifdef TCP_OFFLOAD
1859 free(sc->sge.ofld_rxq, M_CXGBE);
1860 #endif
1861 #ifdef DEV_NETMAP
1862 free(sc->sge.nm_rxq, M_CXGBE);
1863 free(sc->sge.nm_txq, M_CXGBE);
1864 #endif
1865 free(sc->irq, M_CXGBE);
1866 free(sc->sge.rxq, M_CXGBE);
1867 free(sc->sge.txq, M_CXGBE);
1868 free(sc->sge.ctrlq, M_CXGBE);
1869 free(sc->sge.iqmap, M_CXGBE);
1870 free(sc->sge.eqmap, M_CXGBE);
1871 free(sc->tids.ftid_tab, M_CXGBE);
1872 free(sc->tids.hpftid_tab, M_CXGBE);
1873 free_hftid_hash(&sc->tids);
1874 free(sc->tids.tid_tab, M_CXGBE);
1875 t4_destroy_dma_tag(sc);
1876
1877 callout_drain(&sc->ktls_tick);
1878 callout_drain(&sc->sfl_callout);
1879 if (mtx_initialized(&sc->tids.ftid_lock)) {
1880 mtx_destroy(&sc->tids.ftid_lock);
1881 cv_destroy(&sc->tids.ftid_cv);
1882 }
1883 if (mtx_initialized(&sc->tids.atid_lock))
1884 mtx_destroy(&sc->tids.atid_lock);
1885 if (mtx_initialized(&sc->ifp_lock))
1886 mtx_destroy(&sc->ifp_lock);
1887
1888 if (rw_initialized(&sc->policy_lock)) {
1889 rw_destroy(&sc->policy_lock);
1890 #ifdef TCP_OFFLOAD
1891 if (sc->policy != NULL)
1892 free_offload_policy(sc->policy);
1893 #endif
1894 }
1895
1896 for (i = 0; i < NUM_MEMWIN; i++) {
1897 struct memwin *mw = &sc->memwin[i];
1898
1899 if (rw_initialized(&mw->mw_lock))
1900 rw_destroy(&mw->mw_lock);
1901 }
1902
1903 mtx_destroy(&sc->sfl_lock);
1904 mtx_destroy(&sc->reg_lock);
1905 mtx_destroy(&sc->sc_lock);
1906
1907 bzero(sc, sizeof(*sc));
1908
1909 return (0);
1910 }
1911
1912 static inline bool
ok_to_reset(struct adapter * sc)1913 ok_to_reset(struct adapter *sc)
1914 {
1915 struct tid_info *t = &sc->tids;
1916 struct port_info *pi;
1917 struct vi_info *vi;
1918 int i, j;
1919 int caps = IFCAP_TOE | IFCAP_NETMAP | IFCAP_TXRTLMT;
1920
1921 if (is_t6(sc))
1922 caps |= IFCAP_TXTLS;
1923
1924 ASSERT_SYNCHRONIZED_OP(sc);
1925 MPASS(!(sc->flags & IS_VF));
1926
1927 for_each_port(sc, i) {
1928 pi = sc->port[i];
1929 for_each_vi(pi, j, vi) {
1930 if (if_getcapenable(vi->ifp) & caps)
1931 return (false);
1932 }
1933 }
1934
1935 if (atomic_load_int(&t->tids_in_use) > 0)
1936 return (false);
1937 if (atomic_load_int(&t->stids_in_use) > 0)
1938 return (false);
1939 if (atomic_load_int(&t->atids_in_use) > 0)
1940 return (false);
1941 if (atomic_load_int(&t->ftids_in_use) > 0)
1942 return (false);
1943 if (atomic_load_int(&t->hpftids_in_use) > 0)
1944 return (false);
1945 if (atomic_load_int(&t->etids_in_use) > 0)
1946 return (false);
1947
1948 return (true);
1949 }
1950
1951 static inline int
stop_adapter(struct adapter * sc)1952 stop_adapter(struct adapter *sc)
1953 {
1954 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED)))
1955 return (1); /* Already stopped. */
1956 return (t4_shutdown_adapter(sc));
1957 }
1958
1959 static int
t4_suspend(device_t dev)1960 t4_suspend(device_t dev)
1961 {
1962 struct adapter *sc = device_get_softc(dev);
1963 struct port_info *pi;
1964 struct vi_info *vi;
1965 if_t ifp;
1966 struct sge_rxq *rxq;
1967 struct sge_txq *txq;
1968 struct sge_wrq *wrq;
1969 #ifdef TCP_OFFLOAD
1970 struct sge_ofld_rxq *ofld_rxq;
1971 #endif
1972 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1973 struct sge_ofld_txq *ofld_txq;
1974 #endif
1975 int rc, i, j, k;
1976
1977 CH_ALERT(sc, "suspend requested\n");
1978
1979 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4sus");
1980 if (rc != 0)
1981 return (ENXIO);
1982
1983 /* XXX: Can the kernel call suspend repeatedly without resume? */
1984 MPASS(!hw_off_limits(sc));
1985
1986 if (!ok_to_reset(sc)) {
1987 /* XXX: should list what resource is preventing suspend. */
1988 CH_ERR(sc, "not safe to suspend.\n");
1989 rc = EBUSY;
1990 goto done;
1991 }
1992
1993 /* No more DMA or interrupts. */
1994 stop_adapter(sc);
1995
1996 /* Quiesce all activity. */
1997 for_each_port(sc, i) {
1998 pi = sc->port[i];
1999 pi->vxlan_tcam_entry = false;
2000
2001 PORT_LOCK(pi);
2002 if (pi->up_vis > 0) {
2003 /*
2004 * t4_shutdown_adapter has already shut down all the
2005 * PHYs but it also disables interrupts and DMA so there
2006 * won't be a link interrupt. So we update the state
2007 * manually and inform the kernel.
2008 */
2009 pi->link_cfg.link_ok = false;
2010 t4_os_link_changed(pi);
2011 }
2012 PORT_UNLOCK(pi);
2013
2014 for_each_vi(pi, j, vi) {
2015 vi->xact_addr_filt = -1;
2016 mtx_lock(&vi->tick_mtx);
2017 vi->flags |= VI_SKIP_STATS;
2018 mtx_unlock(&vi->tick_mtx);
2019 if (!(vi->flags & VI_INIT_DONE))
2020 continue;
2021
2022 ifp = vi->ifp;
2023 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2024 mtx_lock(&vi->tick_mtx);
2025 callout_stop(&vi->tick);
2026 mtx_unlock(&vi->tick_mtx);
2027 callout_drain(&vi->tick);
2028 }
2029
2030 /*
2031 * Note that the HW is not available.
2032 */
2033 for_each_txq(vi, k, txq) {
2034 TXQ_LOCK(txq);
2035 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED);
2036 TXQ_UNLOCK(txq);
2037 }
2038 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2039 for_each_ofld_txq(vi, k, ofld_txq) {
2040 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED;
2041 }
2042 #endif
2043 for_each_rxq(vi, k, rxq) {
2044 rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2045 }
2046 #if defined(TCP_OFFLOAD)
2047 for_each_ofld_rxq(vi, k, ofld_rxq) {
2048 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2049 }
2050 #endif
2051
2052 quiesce_vi(vi);
2053 }
2054
2055 if (sc->flags & FULL_INIT_DONE) {
2056 /* Control queue */
2057 wrq = &sc->sge.ctrlq[i];
2058 wrq->eq.flags &= ~EQ_HW_ALLOCATED;
2059 quiesce_wrq(wrq);
2060 }
2061 }
2062 if (sc->flags & FULL_INIT_DONE) {
2063 /* Firmware event queue */
2064 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED;
2065 quiesce_iq_fl(sc, &sc->sge.fwq, NULL);
2066 }
2067
2068 /* Stop calibration */
2069 callout_stop(&sc->cal_callout);
2070 callout_drain(&sc->cal_callout);
2071
2072 /* Mark the adapter totally off limits. */
2073 mtx_lock(&sc->reg_lock);
2074 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS);
2075 sc->flags &= ~(FW_OK | MASTER_PF);
2076 sc->reset_thread = NULL;
2077 mtx_unlock(&sc->reg_lock);
2078
2079 if (t4_clock_gate_on_suspend) {
2080 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN |
2081 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN |
2082 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0);
2083 }
2084
2085 CH_ALERT(sc, "suspend completed.\n");
2086 done:
2087 end_synchronized_op(sc, 0);
2088 return (rc);
2089 }
2090
2091 struct adapter_pre_reset_state {
2092 u_int flags;
2093 uint16_t nbmcaps;
2094 uint16_t linkcaps;
2095 uint16_t switchcaps;
2096 uint16_t niccaps;
2097 uint16_t toecaps;
2098 uint16_t rdmacaps;
2099 uint16_t cryptocaps;
2100 uint16_t iscsicaps;
2101 uint16_t fcoecaps;
2102
2103 u_int cfcsum;
2104 char cfg_file[32];
2105
2106 struct adapter_params params;
2107 struct t4_virt_res vres;
2108 struct tid_info tids;
2109 struct sge sge;
2110
2111 int rawf_base;
2112 int nrawf;
2113
2114 };
2115
2116 static void
save_caps_and_params(struct adapter * sc,struct adapter_pre_reset_state * o)2117 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2118 {
2119
2120 ASSERT_SYNCHRONIZED_OP(sc);
2121
2122 o->flags = sc->flags;
2123
2124 o->nbmcaps = sc->nbmcaps;
2125 o->linkcaps = sc->linkcaps;
2126 o->switchcaps = sc->switchcaps;
2127 o->niccaps = sc->niccaps;
2128 o->toecaps = sc->toecaps;
2129 o->rdmacaps = sc->rdmacaps;
2130 o->cryptocaps = sc->cryptocaps;
2131 o->iscsicaps = sc->iscsicaps;
2132 o->fcoecaps = sc->fcoecaps;
2133
2134 o->cfcsum = sc->cfcsum;
2135 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file));
2136 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file));
2137
2138 o->params = sc->params;
2139 o->vres = sc->vres;
2140 o->tids = sc->tids;
2141 o->sge = sc->sge;
2142
2143 o->rawf_base = sc->rawf_base;
2144 o->nrawf = sc->nrawf;
2145 }
2146
2147 static int
compare_caps_and_params(struct adapter * sc,struct adapter_pre_reset_state * o)2148 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2149 {
2150 int rc = 0;
2151
2152 ASSERT_SYNCHRONIZED_OP(sc);
2153
2154 /* Capabilities */
2155 #define COMPARE_CAPS(c) do { \
2156 if (o->c##caps != sc->c##caps) { \
2157 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \
2158 sc->c##caps); \
2159 rc = EINVAL; \
2160 } \
2161 } while (0)
2162 COMPARE_CAPS(nbm);
2163 COMPARE_CAPS(link);
2164 COMPARE_CAPS(switch);
2165 COMPARE_CAPS(nic);
2166 COMPARE_CAPS(toe);
2167 COMPARE_CAPS(rdma);
2168 COMPARE_CAPS(crypto);
2169 COMPARE_CAPS(iscsi);
2170 COMPARE_CAPS(fcoe);
2171 #undef COMPARE_CAPS
2172
2173 /* Firmware config file */
2174 if (o->cfcsum != sc->cfcsum) {
2175 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file,
2176 o->cfcsum, sc->cfg_file, sc->cfcsum);
2177 rc = EINVAL;
2178 }
2179
2180 #define COMPARE_PARAM(p, name) do { \
2181 if (o->p != sc->p) { \
2182 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \
2183 rc = EINVAL; \
2184 } \
2185 } while (0)
2186 COMPARE_PARAM(sge.iq_start, iq_start);
2187 COMPARE_PARAM(sge.eq_start, eq_start);
2188 COMPARE_PARAM(tids.ftid_base, ftid_base);
2189 COMPARE_PARAM(tids.ftid_end, ftid_end);
2190 COMPARE_PARAM(tids.nftids, nftids);
2191 COMPARE_PARAM(vres.l2t.start, l2t_start);
2192 COMPARE_PARAM(vres.l2t.size, l2t_size);
2193 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz);
2194 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz);
2195 COMPARE_PARAM(tids.tid_base, tid_base);
2196 COMPARE_PARAM(tids.hpftid_base, hpftid_base);
2197 COMPARE_PARAM(tids.hpftid_end, hpftid_end);
2198 COMPARE_PARAM(tids.nhpftids, nhpftids);
2199 COMPARE_PARAM(rawf_base, rawf_base);
2200 COMPARE_PARAM(nrawf, nrawf);
2201 COMPARE_PARAM(params.mps_bg_map, mps_bg_map);
2202 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support);
2203 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl);
2204 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support);
2205 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr);
2206 COMPARE_PARAM(tids.ntids, ntids);
2207 COMPARE_PARAM(tids.etid_base, etid_base);
2208 COMPARE_PARAM(tids.etid_end, etid_end);
2209 COMPARE_PARAM(tids.netids, netids);
2210 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred);
2211 COMPARE_PARAM(params.ethoffload, ethoffload);
2212 COMPARE_PARAM(tids.natids, natids);
2213 COMPARE_PARAM(tids.stid_base, stid_base);
2214 COMPARE_PARAM(vres.ddp.start, ddp_start);
2215 COMPARE_PARAM(vres.ddp.size, ddp_size);
2216 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred);
2217 COMPARE_PARAM(vres.stag.start, stag_start);
2218 COMPARE_PARAM(vres.stag.size, stag_size);
2219 COMPARE_PARAM(vres.rq.start, rq_start);
2220 COMPARE_PARAM(vres.rq.size, rq_size);
2221 COMPARE_PARAM(vres.pbl.start, pbl_start);
2222 COMPARE_PARAM(vres.pbl.size, pbl_size);
2223 COMPARE_PARAM(vres.qp.start, qp_start);
2224 COMPARE_PARAM(vres.qp.size, qp_size);
2225 COMPARE_PARAM(vres.cq.start, cq_start);
2226 COMPARE_PARAM(vres.cq.size, cq_size);
2227 COMPARE_PARAM(vres.ocq.start, ocq_start);
2228 COMPARE_PARAM(vres.ocq.size, ocq_size);
2229 COMPARE_PARAM(vres.srq.start, srq_start);
2230 COMPARE_PARAM(vres.srq.size, srq_size);
2231 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp);
2232 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter);
2233 COMPARE_PARAM(vres.iscsi.start, iscsi_start);
2234 COMPARE_PARAM(vres.iscsi.size, iscsi_size);
2235 COMPARE_PARAM(vres.key.start, key_start);
2236 COMPARE_PARAM(vres.key.size, key_size);
2237 #undef COMPARE_PARAM
2238
2239 return (rc);
2240 }
2241
2242 static int
t4_resume(device_t dev)2243 t4_resume(device_t dev)
2244 {
2245 struct adapter *sc = device_get_softc(dev);
2246 struct adapter_pre_reset_state *old_state = NULL;
2247 struct port_info *pi;
2248 struct vi_info *vi;
2249 if_t ifp;
2250 struct sge_txq *txq;
2251 int rc, i, j, k;
2252
2253 CH_ALERT(sc, "resume requested.\n");
2254
2255 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4res");
2256 if (rc != 0)
2257 return (ENXIO);
2258 MPASS(hw_off_limits(sc));
2259 MPASS((sc->flags & FW_OK) == 0);
2260 MPASS((sc->flags & MASTER_PF) == 0);
2261 MPASS(sc->reset_thread == NULL);
2262 sc->reset_thread = curthread;
2263
2264 /* Register access is expected to work by the time we're here. */
2265 if (t4_read_reg(sc, A_PL_WHOAMI) == 0xffffffff) {
2266 CH_ERR(sc, "%s: can't read device registers\n", __func__);
2267 rc = ENXIO;
2268 goto done;
2269 }
2270
2271 /* Note that HW_OFF_LIMITS is cleared a bit later. */
2272 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR | ADAP_STOPPED);
2273
2274 /* Restore memory window. */
2275 setup_memwin(sc);
2276
2277 /* Go no further if recovery mode has been requested. */
2278 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
2279 CH_ALERT(sc, "recovery mode on resume.\n");
2280 rc = 0;
2281 mtx_lock(&sc->reg_lock);
2282 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2283 mtx_unlock(&sc->reg_lock);
2284 goto done;
2285 }
2286
2287 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK);
2288 save_caps_and_params(sc, old_state);
2289
2290 /* Reestablish contact with firmware and become the primary PF. */
2291 rc = contact_firmware(sc);
2292 if (rc != 0)
2293 goto done; /* error message displayed already */
2294 MPASS(sc->flags & FW_OK);
2295
2296 if (sc->flags & MASTER_PF) {
2297 rc = partition_resources(sc);
2298 if (rc != 0)
2299 goto done; /* error message displayed already */
2300 }
2301
2302 rc = get_params__post_init(sc);
2303 if (rc != 0)
2304 goto done; /* error message displayed already */
2305
2306 rc = set_params__post_init(sc);
2307 if (rc != 0)
2308 goto done; /* error message displayed already */
2309
2310 rc = compare_caps_and_params(sc, old_state);
2311 if (rc != 0)
2312 goto done; /* error message displayed already */
2313
2314 for_each_port(sc, i) {
2315 pi = sc->port[i];
2316 MPASS(pi != NULL);
2317 MPASS(pi->vi != NULL);
2318 MPASS(pi->vi[0].dev == pi->dev);
2319
2320 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
2321 if (rc != 0) {
2322 CH_ERR(sc,
2323 "failed to re-initialize port %d: %d\n", i, rc);
2324 goto done;
2325 }
2326 MPASS(sc->chan_map[pi->tx_chan] == i);
2327
2328 PORT_LOCK(pi);
2329 fixup_link_config(pi);
2330 build_medialist(pi);
2331 PORT_UNLOCK(pi);
2332 for_each_vi(pi, j, vi) {
2333 if (IS_MAIN_VI(vi))
2334 continue;
2335 rc = alloc_extra_vi(sc, pi, vi);
2336 if (rc != 0) {
2337 CH_ERR(vi,
2338 "failed to re-allocate extra VI: %d\n", rc);
2339 goto done;
2340 }
2341 }
2342 }
2343
2344 /*
2345 * Interrupts and queues are about to be enabled and other threads will
2346 * want to access the hardware too. It is safe to do so. Note that
2347 * this thread is still in the middle of a synchronized_op.
2348 */
2349 mtx_lock(&sc->reg_lock);
2350 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2351 mtx_unlock(&sc->reg_lock);
2352
2353 if (sc->flags & FULL_INIT_DONE) {
2354 rc = adapter_full_init(sc);
2355 if (rc != 0) {
2356 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc);
2357 goto done;
2358 }
2359
2360 if (sc->vxlan_refcount > 0)
2361 enable_vxlan_rx(sc);
2362
2363 for_each_port(sc, i) {
2364 pi = sc->port[i];
2365 for_each_vi(pi, j, vi) {
2366 mtx_lock(&vi->tick_mtx);
2367 vi->flags &= ~VI_SKIP_STATS;
2368 mtx_unlock(&vi->tick_mtx);
2369 if (!(vi->flags & VI_INIT_DONE))
2370 continue;
2371 rc = vi_full_init(vi);
2372 if (rc != 0) {
2373 CH_ERR(vi, "failed to re-initialize "
2374 "interface: %d\n", rc);
2375 goto done;
2376 }
2377
2378 ifp = vi->ifp;
2379 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2380 continue;
2381 /*
2382 * Note that we do not setup multicast addresses
2383 * in the first pass. This ensures that the
2384 * unicast DMACs for all VIs on all ports get an
2385 * MPS TCAM entry.
2386 */
2387 rc = update_mac_settings(ifp, XGMAC_ALL &
2388 ~XGMAC_MCADDRS);
2389 if (rc != 0) {
2390 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc);
2391 goto done;
2392 }
2393 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true,
2394 true);
2395 if (rc != 0) {
2396 CH_ERR(vi, "failed to re-enable VI: %d\n", rc);
2397 goto done;
2398 }
2399 for_each_txq(vi, k, txq) {
2400 TXQ_LOCK(txq);
2401 txq->eq.flags |= EQ_ENABLED;
2402 TXQ_UNLOCK(txq);
2403 }
2404 mtx_lock(&vi->tick_mtx);
2405 callout_schedule(&vi->tick, hz);
2406 mtx_unlock(&vi->tick_mtx);
2407 }
2408 PORT_LOCK(pi);
2409 if (pi->up_vis > 0) {
2410 t4_update_port_info(pi);
2411 fixup_link_config(pi);
2412 build_medialist(pi);
2413 apply_link_config(pi);
2414 if (pi->link_cfg.link_ok)
2415 t4_os_link_changed(pi);
2416 }
2417 PORT_UNLOCK(pi);
2418 }
2419
2420 /* Now reprogram the L2 multicast addresses. */
2421 for_each_port(sc, i) {
2422 pi = sc->port[i];
2423 for_each_vi(pi, j, vi) {
2424 if (!(vi->flags & VI_INIT_DONE))
2425 continue;
2426 ifp = vi->ifp;
2427 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2428 continue;
2429 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2430 if (rc != 0) {
2431 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc);
2432 rc = 0; /* carry on */
2433 }
2434 }
2435 }
2436 }
2437
2438 /* Reset all calibration */
2439 t4_calibration_start(sc);
2440
2441 done:
2442 if (rc == 0) {
2443 sc->incarnation++;
2444 CH_ALERT(sc, "resume completed.\n");
2445 }
2446 end_synchronized_op(sc, 0);
2447 free(old_state, M_CXGBE);
2448 return (rc);
2449 }
2450
2451 static int
t4_reset_prepare(device_t dev,device_t child)2452 t4_reset_prepare(device_t dev, device_t child)
2453 {
2454 struct adapter *sc = device_get_softc(dev);
2455
2456 CH_ALERT(sc, "reset_prepare.\n");
2457 return (0);
2458 }
2459
2460 static int
t4_reset_post(device_t dev,device_t child)2461 t4_reset_post(device_t dev, device_t child)
2462 {
2463 struct adapter *sc = device_get_softc(dev);
2464
2465 CH_ALERT(sc, "reset_post.\n");
2466 return (0);
2467 }
2468
2469 static int
reset_adapter(struct adapter * sc)2470 reset_adapter(struct adapter *sc)
2471 {
2472 int rc, oldinc, error_flags;
2473
2474 CH_ALERT(sc, "reset requested.\n");
2475
2476 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst1");
2477 if (rc != 0)
2478 return (EBUSY);
2479
2480 if (hw_off_limits(sc)) {
2481 CH_ERR(sc, "adapter is suspended, use resume (not reset).\n");
2482 rc = ENXIO;
2483 goto done;
2484 }
2485
2486 if (!ok_to_reset(sc)) {
2487 /* XXX: should list what resource is preventing reset. */
2488 CH_ERR(sc, "not safe to reset.\n");
2489 rc = EBUSY;
2490 goto done;
2491 }
2492
2493 done:
2494 oldinc = sc->incarnation;
2495 end_synchronized_op(sc, 0);
2496 if (rc != 0)
2497 return (rc); /* Error logged already. */
2498
2499 atomic_add_int(&sc->num_resets, 1);
2500 mtx_lock(&Giant);
2501 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0);
2502 mtx_unlock(&Giant);
2503 if (rc != 0)
2504 CH_ERR(sc, "bus_reset_child failed: %d.\n", rc);
2505 else {
2506 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst2");
2507 if (rc != 0)
2508 return (EBUSY);
2509 error_flags = atomic_load_int(&sc->error_flags);
2510 if (sc->incarnation > oldinc && error_flags == 0) {
2511 CH_ALERT(sc, "bus_reset_child succeeded.\n");
2512 } else {
2513 CH_ERR(sc, "adapter did not reset properly, flags "
2514 "0x%08x, error_flags 0x%08x.\n", sc->flags,
2515 error_flags);
2516 rc = ENXIO;
2517 }
2518 end_synchronized_op(sc, 0);
2519 }
2520
2521 return (rc);
2522 }
2523
2524 static void
reset_adapter_task(void * arg,int pending)2525 reset_adapter_task(void *arg, int pending)
2526 {
2527 /* XXX: t4_async_event here? */
2528 reset_adapter(arg);
2529 }
2530
2531 static int
cxgbe_probe(device_t dev)2532 cxgbe_probe(device_t dev)
2533 {
2534 struct port_info *pi = device_get_softc(dev);
2535
2536 device_set_descf(dev, "port %d", pi->port_id);
2537
2538 return (BUS_PROBE_DEFAULT);
2539 }
2540
2541 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
2542 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
2543 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
2544 IFCAP_HWRXTSTMP | IFCAP_MEXTPG)
2545 #define T4_CAP_ENABLE (T4_CAP)
2546
2547 static int
cxgbe_vi_attach(device_t dev,struct vi_info * vi)2548 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
2549 {
2550 if_t ifp;
2551 struct sbuf *sb;
2552 struct sysctl_ctx_list *ctx = &vi->ctx;
2553 struct sysctl_oid_list *children;
2554 struct pfil_head_args pa;
2555 struct adapter *sc = vi->adapter;
2556
2557 sysctl_ctx_init(ctx);
2558 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev));
2559 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq",
2560 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues");
2561 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq",
2562 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues");
2563 #ifdef DEV_NETMAP
2564 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq",
2565 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues");
2566 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq",
2567 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues");
2568 #endif
2569 #ifdef TCP_OFFLOAD
2570 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq",
2571 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues");
2572 #endif
2573 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2574 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq",
2575 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues");
2576 #endif
2577
2578 vi->xact_addr_filt = -1;
2579 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF);
2580 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0);
2581 if (sc->flags & IS_VF || t4_tx_vm_wr != 0)
2582 vi->flags |= TX_USES_VM_WR;
2583
2584 /* Allocate an ifnet and set it up */
2585 ifp = if_alloc_dev(IFT_ETHER, dev);
2586 if (ifp == NULL) {
2587 device_printf(dev, "Cannot allocate ifnet\n");
2588 return (ENOMEM);
2589 }
2590 vi->ifp = ifp;
2591 if_setsoftc(ifp, vi);
2592
2593 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2594 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
2595
2596 if_setinitfn(ifp, cxgbe_init);
2597 if_setioctlfn(ifp, cxgbe_ioctl);
2598 if_settransmitfn(ifp, cxgbe_transmit);
2599 if_setqflushfn(ifp, cxgbe_qflush);
2600 if (vi->pi->nvi > 1 || sc->flags & IS_VF)
2601 if_setgetcounterfn(ifp, vi_get_counter);
2602 else
2603 if_setgetcounterfn(ifp, cxgbe_get_counter);
2604 #if defined(KERN_TLS) || defined(RATELIMIT)
2605 if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc);
2606 #endif
2607 #ifdef RATELIMIT
2608 if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query);
2609 #endif
2610
2611 if_setcapabilities(ifp, T4_CAP);
2612 if_setcapenable(ifp, T4_CAP_ENABLE);
2613 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
2614 CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2615 if (chip_id(sc) >= CHELSIO_T6) {
2616 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2617 if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2618 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
2619 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2620 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0);
2621 }
2622
2623 #ifdef TCP_OFFLOAD
2624 if (vi->nofldrxq != 0)
2625 if_setcapabilitiesbit(ifp, IFCAP_TOE, 0);
2626 #endif
2627 #ifdef RATELIMIT
2628 if (is_ethoffload(sc) && vi->nofldtxq != 0) {
2629 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0);
2630 if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0);
2631 }
2632 #endif
2633
2634 if_sethwtsomax(ifp, IP_MAXPACKET);
2635 if (vi->flags & TX_USES_VM_WR)
2636 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO);
2637 else
2638 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO);
2639 #ifdef RATELIMIT
2640 if (is_ethoffload(sc) && vi->nofldtxq != 0)
2641 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO);
2642 #endif
2643 if_sethwtsomaxsegsize(ifp, 65536);
2644 #ifdef KERN_TLS
2645 if (is_ktls(sc)) {
2646 if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0);
2647 if (sc->flags & KERN_TLS_ON || !is_t6(sc))
2648 if_setcapenablebit(ifp, IFCAP_TXTLS, 0);
2649 }
2650 #endif
2651
2652 ether_ifattach(ifp, vi->hw_addr);
2653 #ifdef DEV_NETMAP
2654 if (vi->nnmrxq != 0)
2655 cxgbe_nm_attach(vi);
2656 #endif
2657 sb = sbuf_new_auto();
2658 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
2659 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2660 switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) {
2661 case IFCAP_TOE:
2662 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
2663 break;
2664 case IFCAP_TOE | IFCAP_TXRTLMT:
2665 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
2666 break;
2667 case IFCAP_TXRTLMT:
2668 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
2669 break;
2670 }
2671 #endif
2672 #ifdef TCP_OFFLOAD
2673 if (if_getcapabilities(ifp) & IFCAP_TOE)
2674 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
2675 #endif
2676 #ifdef DEV_NETMAP
2677 if (if_getcapabilities(ifp) & IFCAP_NETMAP)
2678 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
2679 vi->nnmtxq, vi->nnmrxq);
2680 #endif
2681 sbuf_finish(sb);
2682 device_printf(dev, "%s\n", sbuf_data(sb));
2683 sbuf_delete(sb);
2684
2685 vi_sysctls(vi);
2686
2687 pa.pa_version = PFIL_VERSION;
2688 pa.pa_flags = PFIL_IN;
2689 pa.pa_type = PFIL_TYPE_ETHERNET;
2690 pa.pa_headname = if_name(ifp);
2691 vi->pfil = pfil_head_register(&pa);
2692
2693 return (0);
2694 }
2695
2696 static int
cxgbe_attach(device_t dev)2697 cxgbe_attach(device_t dev)
2698 {
2699 struct port_info *pi = device_get_softc(dev);
2700 struct adapter *sc = pi->adapter;
2701 struct vi_info *vi;
2702 int i, rc;
2703
2704 sysctl_ctx_init(&pi->ctx);
2705
2706 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
2707 if (rc)
2708 return (rc);
2709
2710 for_each_vi(pi, i, vi) {
2711 if (i == 0)
2712 continue;
2713 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
2714 if (vi->dev == NULL) {
2715 device_printf(dev, "failed to add VI %d\n", i);
2716 continue;
2717 }
2718 device_set_softc(vi->dev, vi);
2719 }
2720
2721 cxgbe_sysctls(pi);
2722
2723 bus_generic_attach(dev);
2724
2725 return (0);
2726 }
2727
2728 static void
cxgbe_vi_detach(struct vi_info * vi)2729 cxgbe_vi_detach(struct vi_info *vi)
2730 {
2731 if_t ifp = vi->ifp;
2732
2733 if (vi->pfil != NULL) {
2734 pfil_head_unregister(vi->pfil);
2735 vi->pfil = NULL;
2736 }
2737
2738 ether_ifdetach(ifp);
2739
2740 /* Let detach proceed even if these fail. */
2741 #ifdef DEV_NETMAP
2742 if (if_getcapabilities(ifp) & IFCAP_NETMAP)
2743 cxgbe_nm_detach(vi);
2744 #endif
2745 cxgbe_uninit_synchronized(vi);
2746 callout_drain(&vi->tick);
2747 mtx_destroy(&vi->tick_mtx);
2748 sysctl_ctx_free(&vi->ctx);
2749 vi_full_uninit(vi);
2750
2751 if_free(vi->ifp);
2752 vi->ifp = NULL;
2753 }
2754
2755 static int
cxgbe_detach(device_t dev)2756 cxgbe_detach(device_t dev)
2757 {
2758 struct port_info *pi = device_get_softc(dev);
2759 struct adapter *sc = pi->adapter;
2760 int rc;
2761
2762 /* Detach the extra VIs first. */
2763 rc = bus_generic_detach(dev);
2764 if (rc)
2765 return (rc);
2766 device_delete_children(dev);
2767
2768 sysctl_ctx_free(&pi->ctx);
2769 begin_vi_detach(sc, &pi->vi[0]);
2770 if (pi->flags & HAS_TRACEQ) {
2771 sc->traceq = -1; /* cloner should not create ifnet */
2772 t4_tracer_port_detach(sc);
2773 }
2774 cxgbe_vi_detach(&pi->vi[0]);
2775 ifmedia_removeall(&pi->media);
2776 end_vi_detach(sc, &pi->vi[0]);
2777
2778 return (0);
2779 }
2780
2781 static void
cxgbe_init(void * arg)2782 cxgbe_init(void *arg)
2783 {
2784 struct vi_info *vi = arg;
2785 struct adapter *sc = vi->adapter;
2786
2787 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
2788 return;
2789 cxgbe_init_synchronized(vi);
2790 end_synchronized_op(sc, 0);
2791 }
2792
2793 static int
cxgbe_ioctl(if_t ifp,unsigned long cmd,caddr_t data)2794 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data)
2795 {
2796 int rc = 0, mtu, flags;
2797 struct vi_info *vi = if_getsoftc(ifp);
2798 struct port_info *pi = vi->pi;
2799 struct adapter *sc = pi->adapter;
2800 struct ifreq *ifr = (struct ifreq *)data;
2801 uint32_t mask;
2802
2803 switch (cmd) {
2804 case SIOCSIFMTU:
2805 mtu = ifr->ifr_mtu;
2806 if (mtu < ETHERMIN || mtu > MAX_MTU)
2807 return (EINVAL);
2808
2809 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
2810 if (rc)
2811 return (rc);
2812 if_setmtu(ifp, mtu);
2813 if (vi->flags & VI_INIT_DONE) {
2814 t4_update_fl_bufsize(ifp);
2815 if (!hw_off_limits(sc) &&
2816 if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2817 rc = update_mac_settings(ifp, XGMAC_MTU);
2818 }
2819 end_synchronized_op(sc, 0);
2820 break;
2821
2822 case SIOCSIFFLAGS:
2823 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
2824 if (rc)
2825 return (rc);
2826
2827 if (hw_off_limits(sc)) {
2828 rc = ENXIO;
2829 goto fail;
2830 }
2831
2832 if (if_getflags(ifp) & IFF_UP) {
2833 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2834 flags = vi->if_flags;
2835 if ((if_getflags(ifp) ^ flags) &
2836 (IFF_PROMISC | IFF_ALLMULTI)) {
2837 rc = update_mac_settings(ifp,
2838 XGMAC_PROMISC | XGMAC_ALLMULTI);
2839 }
2840 } else {
2841 rc = cxgbe_init_synchronized(vi);
2842 }
2843 vi->if_flags = if_getflags(ifp);
2844 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2845 rc = cxgbe_uninit_synchronized(vi);
2846 }
2847 end_synchronized_op(sc, 0);
2848 break;
2849
2850 case SIOCADDMULTI:
2851 case SIOCDELMULTI:
2852 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
2853 if (rc)
2854 return (rc);
2855 if (!hw_off_limits(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2856 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2857 end_synchronized_op(sc, 0);
2858 break;
2859
2860 case SIOCSIFCAP:
2861 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
2862 if (rc)
2863 return (rc);
2864
2865 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2866 if (mask & IFCAP_TXCSUM) {
2867 if_togglecapenable(ifp, IFCAP_TXCSUM);
2868 if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP);
2869
2870 if (IFCAP_TSO4 & if_getcapenable(ifp) &&
2871 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
2872 mask &= ~IFCAP_TSO4;
2873 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
2874 if_printf(ifp,
2875 "tso4 disabled due to -txcsum.\n");
2876 }
2877 }
2878 if (mask & IFCAP_TXCSUM_IPV6) {
2879 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
2880 if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2881
2882 if (IFCAP_TSO6 & if_getcapenable(ifp) &&
2883 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
2884 mask &= ~IFCAP_TSO6;
2885 if_setcapenablebit(ifp, 0, IFCAP_TSO6);
2886 if_printf(ifp,
2887 "tso6 disabled due to -txcsum6.\n");
2888 }
2889 }
2890 if (mask & IFCAP_RXCSUM)
2891 if_togglecapenable(ifp, IFCAP_RXCSUM);
2892 if (mask & IFCAP_RXCSUM_IPV6)
2893 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
2894
2895 /*
2896 * Note that we leave CSUM_TSO alone (it is always set). The
2897 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
2898 * sending a TSO request our way, so it's sufficient to toggle
2899 * IFCAP_TSOx only.
2900 */
2901 if (mask & IFCAP_TSO4) {
2902 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) &&
2903 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
2904 if_printf(ifp, "enable txcsum first.\n");
2905 rc = EAGAIN;
2906 goto fail;
2907 }
2908 if_togglecapenable(ifp, IFCAP_TSO4);
2909 }
2910 if (mask & IFCAP_TSO6) {
2911 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) &&
2912 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
2913 if_printf(ifp, "enable txcsum6 first.\n");
2914 rc = EAGAIN;
2915 goto fail;
2916 }
2917 if_togglecapenable(ifp, IFCAP_TSO6);
2918 }
2919 if (mask & IFCAP_LRO) {
2920 #if defined(INET) || defined(INET6)
2921 int i;
2922 struct sge_rxq *rxq;
2923
2924 if_togglecapenable(ifp, IFCAP_LRO);
2925 for_each_rxq(vi, i, rxq) {
2926 if (if_getcapenable(ifp) & IFCAP_LRO)
2927 rxq->iq.flags |= IQ_LRO_ENABLED;
2928 else
2929 rxq->iq.flags &= ~IQ_LRO_ENABLED;
2930 }
2931 #endif
2932 }
2933 #ifdef TCP_OFFLOAD
2934 if (mask & IFCAP_TOE) {
2935 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE;
2936
2937 rc = toe_capability(vi, enable);
2938 if (rc != 0)
2939 goto fail;
2940
2941 if_togglecapenable(ifp, mask);
2942 }
2943 #endif
2944 if (mask & IFCAP_VLAN_HWTAGGING) {
2945 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2946 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2947 rc = update_mac_settings(ifp, XGMAC_VLANEX);
2948 }
2949 if (mask & IFCAP_VLAN_MTU) {
2950 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2951
2952 /* Need to find out how to disable auto-mtu-inflation */
2953 }
2954 if (mask & IFCAP_VLAN_HWTSO)
2955 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2956 if (mask & IFCAP_VLAN_HWCSUM)
2957 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2958 #ifdef RATELIMIT
2959 if (mask & IFCAP_TXRTLMT)
2960 if_togglecapenable(ifp, IFCAP_TXRTLMT);
2961 #endif
2962 if (mask & IFCAP_HWRXTSTMP) {
2963 int i;
2964 struct sge_rxq *rxq;
2965
2966 if_togglecapenable(ifp, IFCAP_HWRXTSTMP);
2967 for_each_rxq(vi, i, rxq) {
2968 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP)
2969 rxq->iq.flags |= IQ_RX_TIMESTAMP;
2970 else
2971 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
2972 }
2973 }
2974 if (mask & IFCAP_MEXTPG)
2975 if_togglecapenable(ifp, IFCAP_MEXTPG);
2976
2977 #ifdef KERN_TLS
2978 if (mask & IFCAP_TXTLS) {
2979 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS;
2980
2981 rc = ktls_capability(sc, enable);
2982 if (rc != 0)
2983 goto fail;
2984
2985 if_togglecapenable(ifp, mask & IFCAP_TXTLS);
2986 }
2987 #endif
2988 if (mask & IFCAP_VXLAN_HWCSUM) {
2989 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM);
2990 if_togglehwassist(ifp, CSUM_INNER_IP6_UDP |
2991 CSUM_INNER_IP6_TCP | CSUM_INNER_IP |
2992 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP);
2993 }
2994 if (mask & IFCAP_VXLAN_HWTSO) {
2995 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO);
2996 if_togglehwassist(ifp, CSUM_INNER_IP6_TSO |
2997 CSUM_INNER_IP_TSO);
2998 }
2999
3000 #ifdef VLAN_CAPABILITIES
3001 VLAN_CAPABILITIES(ifp);
3002 #endif
3003 fail:
3004 end_synchronized_op(sc, 0);
3005 break;
3006
3007 case SIOCSIFMEDIA:
3008 case SIOCGIFMEDIA:
3009 case SIOCGIFXMEDIA:
3010 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
3011 break;
3012
3013 case SIOCGI2C: {
3014 struct ifi2creq i2c;
3015
3016 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3017 if (rc != 0)
3018 break;
3019 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3020 rc = EPERM;
3021 break;
3022 }
3023 if (i2c.len > sizeof(i2c.data)) {
3024 rc = EINVAL;
3025 break;
3026 }
3027 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
3028 if (rc)
3029 return (rc);
3030 if (hw_off_limits(sc))
3031 rc = ENXIO;
3032 else
3033 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
3034 i2c.offset, i2c.len, &i2c.data[0]);
3035 end_synchronized_op(sc, 0);
3036 if (rc == 0)
3037 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3038 break;
3039 }
3040
3041 default:
3042 rc = ether_ioctl(ifp, cmd, data);
3043 }
3044
3045 return (rc);
3046 }
3047
3048 static int
cxgbe_transmit(if_t ifp,struct mbuf * m)3049 cxgbe_transmit(if_t ifp, struct mbuf *m)
3050 {
3051 struct vi_info *vi = if_getsoftc(ifp);
3052 struct port_info *pi = vi->pi;
3053 struct adapter *sc;
3054 struct sge_txq *txq;
3055 void *items[1];
3056 int rc;
3057
3058 M_ASSERTPKTHDR(m);
3059 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
3060 #if defined(KERN_TLS) || defined(RATELIMIT)
3061 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
3062 MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
3063 #endif
3064
3065 if (__predict_false(pi->link_cfg.link_ok == false)) {
3066 m_freem(m);
3067 return (ENETDOWN);
3068 }
3069
3070 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR);
3071 if (__predict_false(rc != 0)) {
3072 if (__predict_true(rc == EINPROGRESS)) {
3073 /* queued by parse_pkt */
3074 MPASS(m != NULL);
3075 return (0);
3076 }
3077
3078 MPASS(m == NULL); /* was freed already */
3079 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
3080 return (rc);
3081 }
3082
3083 /* Select a txq. */
3084 sc = vi->adapter;
3085 txq = &sc->sge.txq[vi->first_txq];
3086 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
3087 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
3088 vi->rsrv_noflowq);
3089
3090 items[0] = m;
3091 rc = mp_ring_enqueue(txq->r, items, 1, 256);
3092 if (__predict_false(rc != 0))
3093 m_freem(m);
3094
3095 return (rc);
3096 }
3097
3098 static void
cxgbe_qflush(if_t ifp)3099 cxgbe_qflush(if_t ifp)
3100 {
3101 struct vi_info *vi = if_getsoftc(ifp);
3102 struct sge_txq *txq;
3103 int i;
3104
3105 /* queues do not exist if !VI_INIT_DONE. */
3106 if (vi->flags & VI_INIT_DONE) {
3107 for_each_txq(vi, i, txq) {
3108 TXQ_LOCK(txq);
3109 txq->eq.flags |= EQ_QFLUSH;
3110 TXQ_UNLOCK(txq);
3111 while (!mp_ring_is_idle(txq->r)) {
3112 mp_ring_check_drainage(txq->r, 4096);
3113 pause("qflush", 1);
3114 }
3115 TXQ_LOCK(txq);
3116 txq->eq.flags &= ~EQ_QFLUSH;
3117 TXQ_UNLOCK(txq);
3118 }
3119 }
3120 if_qflush(ifp);
3121 }
3122
3123 static uint64_t
vi_get_counter(if_t ifp,ift_counter c)3124 vi_get_counter(if_t ifp, ift_counter c)
3125 {
3126 struct vi_info *vi = if_getsoftc(ifp);
3127 struct fw_vi_stats_vf *s = &vi->stats;
3128
3129 mtx_lock(&vi->tick_mtx);
3130 vi_refresh_stats(vi);
3131 mtx_unlock(&vi->tick_mtx);
3132
3133 switch (c) {
3134 case IFCOUNTER_IPACKETS:
3135 return (s->rx_bcast_frames + s->rx_mcast_frames +
3136 s->rx_ucast_frames);
3137 case IFCOUNTER_IERRORS:
3138 return (s->rx_err_frames);
3139 case IFCOUNTER_OPACKETS:
3140 return (s->tx_bcast_frames + s->tx_mcast_frames +
3141 s->tx_ucast_frames + s->tx_offload_frames);
3142 case IFCOUNTER_OERRORS:
3143 return (s->tx_drop_frames);
3144 case IFCOUNTER_IBYTES:
3145 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
3146 s->rx_ucast_bytes);
3147 case IFCOUNTER_OBYTES:
3148 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
3149 s->tx_ucast_bytes + s->tx_offload_bytes);
3150 case IFCOUNTER_IMCASTS:
3151 return (s->rx_mcast_frames);
3152 case IFCOUNTER_OMCASTS:
3153 return (s->tx_mcast_frames);
3154 case IFCOUNTER_OQDROPS: {
3155 uint64_t drops;
3156
3157 drops = 0;
3158 if (vi->flags & VI_INIT_DONE) {
3159 int i;
3160 struct sge_txq *txq;
3161
3162 for_each_txq(vi, i, txq)
3163 drops += counter_u64_fetch(txq->r->dropped);
3164 }
3165
3166 return (drops);
3167
3168 }
3169
3170 default:
3171 return (if_get_counter_default(ifp, c));
3172 }
3173 }
3174
3175 static uint64_t
cxgbe_get_counter(if_t ifp,ift_counter c)3176 cxgbe_get_counter(if_t ifp, ift_counter c)
3177 {
3178 struct vi_info *vi = if_getsoftc(ifp);
3179 struct port_info *pi = vi->pi;
3180 struct port_stats *s = &pi->stats;
3181
3182 mtx_lock(&vi->tick_mtx);
3183 cxgbe_refresh_stats(vi);
3184 mtx_unlock(&vi->tick_mtx);
3185
3186 switch (c) {
3187 case IFCOUNTER_IPACKETS:
3188 return (s->rx_frames);
3189
3190 case IFCOUNTER_IERRORS:
3191 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
3192 s->rx_fcs_err + s->rx_len_err);
3193
3194 case IFCOUNTER_OPACKETS:
3195 return (s->tx_frames);
3196
3197 case IFCOUNTER_OERRORS:
3198 return (s->tx_error_frames);
3199
3200 case IFCOUNTER_IBYTES:
3201 return (s->rx_octets);
3202
3203 case IFCOUNTER_OBYTES:
3204 return (s->tx_octets);
3205
3206 case IFCOUNTER_IMCASTS:
3207 return (s->rx_mcast_frames);
3208
3209 case IFCOUNTER_OMCASTS:
3210 return (s->tx_mcast_frames);
3211
3212 case IFCOUNTER_IQDROPS:
3213 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
3214 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
3215 s->rx_trunc3 + pi->tnl_cong_drops);
3216
3217 case IFCOUNTER_OQDROPS: {
3218 uint64_t drops;
3219
3220 drops = s->tx_drop;
3221 if (vi->flags & VI_INIT_DONE) {
3222 int i;
3223 struct sge_txq *txq;
3224
3225 for_each_txq(vi, i, txq)
3226 drops += counter_u64_fetch(txq->r->dropped);
3227 }
3228
3229 return (drops);
3230
3231 }
3232
3233 default:
3234 return (if_get_counter_default(ifp, c));
3235 }
3236 }
3237
3238 #if defined(KERN_TLS) || defined(RATELIMIT)
3239 static int
cxgbe_snd_tag_alloc(if_t ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** pt)3240 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params,
3241 struct m_snd_tag **pt)
3242 {
3243 int error;
3244
3245 switch (params->hdr.type) {
3246 #ifdef RATELIMIT
3247 case IF_SND_TAG_TYPE_RATE_LIMIT:
3248 error = cxgbe_rate_tag_alloc(ifp, params, pt);
3249 break;
3250 #endif
3251 #ifdef KERN_TLS
3252 case IF_SND_TAG_TYPE_TLS:
3253 {
3254 struct vi_info *vi = if_getsoftc(ifp);
3255
3256 if (is_t6(vi->pi->adapter))
3257 error = t6_tls_tag_alloc(ifp, params, pt);
3258 else
3259 error = EOPNOTSUPP;
3260 break;
3261 }
3262 #endif
3263 default:
3264 error = EOPNOTSUPP;
3265 }
3266 return (error);
3267 }
3268 #endif
3269
3270 /*
3271 * The kernel picks a media from the list we had provided but we still validate
3272 * the requeste.
3273 */
3274 int
cxgbe_media_change(if_t ifp)3275 cxgbe_media_change(if_t ifp)
3276 {
3277 struct vi_info *vi = if_getsoftc(ifp);
3278 struct port_info *pi = vi->pi;
3279 struct ifmedia *ifm = &pi->media;
3280 struct link_config *lc = &pi->link_cfg;
3281 struct adapter *sc = pi->adapter;
3282 int rc;
3283
3284 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
3285 if (rc != 0)
3286 return (rc);
3287 PORT_LOCK(pi);
3288 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
3289 /* ifconfig .. media autoselect */
3290 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
3291 rc = ENOTSUP; /* AN not supported by transceiver */
3292 goto done;
3293 }
3294 lc->requested_aneg = AUTONEG_ENABLE;
3295 lc->requested_speed = 0;
3296 lc->requested_fc |= PAUSE_AUTONEG;
3297 } else {
3298 lc->requested_aneg = AUTONEG_DISABLE;
3299 lc->requested_speed =
3300 ifmedia_baudrate(ifm->ifm_media) / 1000000;
3301 lc->requested_fc = 0;
3302 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
3303 lc->requested_fc |= PAUSE_RX;
3304 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
3305 lc->requested_fc |= PAUSE_TX;
3306 }
3307 if (pi->up_vis > 0 && !hw_off_limits(sc)) {
3308 fixup_link_config(pi);
3309 rc = apply_link_config(pi);
3310 }
3311 done:
3312 PORT_UNLOCK(pi);
3313 end_synchronized_op(sc, 0);
3314 return (rc);
3315 }
3316
3317 /*
3318 * Base media word (without ETHER, pause, link active, etc.) for the port at the
3319 * given speed.
3320 */
3321 static int
port_mword(struct port_info * pi,uint32_t speed)3322 port_mword(struct port_info *pi, uint32_t speed)
3323 {
3324
3325 MPASS(speed & M_FW_PORT_CAP32_SPEED);
3326 MPASS(powerof2(speed));
3327
3328 switch(pi->port_type) {
3329 case FW_PORT_TYPE_BT_SGMII:
3330 case FW_PORT_TYPE_BT_XFI:
3331 case FW_PORT_TYPE_BT_XAUI:
3332 /* BaseT */
3333 switch (speed) {
3334 case FW_PORT_CAP32_SPEED_100M:
3335 return (IFM_100_T);
3336 case FW_PORT_CAP32_SPEED_1G:
3337 return (IFM_1000_T);
3338 case FW_PORT_CAP32_SPEED_10G:
3339 return (IFM_10G_T);
3340 }
3341 break;
3342 case FW_PORT_TYPE_KX4:
3343 if (speed == FW_PORT_CAP32_SPEED_10G)
3344 return (IFM_10G_KX4);
3345 break;
3346 case FW_PORT_TYPE_CX4:
3347 if (speed == FW_PORT_CAP32_SPEED_10G)
3348 return (IFM_10G_CX4);
3349 break;
3350 case FW_PORT_TYPE_KX:
3351 if (speed == FW_PORT_CAP32_SPEED_1G)
3352 return (IFM_1000_KX);
3353 break;
3354 case FW_PORT_TYPE_KR:
3355 case FW_PORT_TYPE_BP_AP:
3356 case FW_PORT_TYPE_BP4_AP:
3357 case FW_PORT_TYPE_BP40_BA:
3358 case FW_PORT_TYPE_KR4_100G:
3359 case FW_PORT_TYPE_KR_SFP28:
3360 case FW_PORT_TYPE_KR_XLAUI:
3361 switch (speed) {
3362 case FW_PORT_CAP32_SPEED_1G:
3363 return (IFM_1000_KX);
3364 case FW_PORT_CAP32_SPEED_10G:
3365 return (IFM_10G_KR);
3366 case FW_PORT_CAP32_SPEED_25G:
3367 return (IFM_25G_KR);
3368 case FW_PORT_CAP32_SPEED_40G:
3369 return (IFM_40G_KR4);
3370 case FW_PORT_CAP32_SPEED_50G:
3371 return (IFM_50G_KR2);
3372 case FW_PORT_CAP32_SPEED_100G:
3373 return (IFM_100G_KR4);
3374 }
3375 break;
3376 case FW_PORT_TYPE_FIBER_XFI:
3377 case FW_PORT_TYPE_FIBER_XAUI:
3378 case FW_PORT_TYPE_SFP:
3379 case FW_PORT_TYPE_QSFP_10G:
3380 case FW_PORT_TYPE_QSA:
3381 case FW_PORT_TYPE_QSFP:
3382 case FW_PORT_TYPE_CR4_QSFP:
3383 case FW_PORT_TYPE_CR_QSFP:
3384 case FW_PORT_TYPE_CR2_QSFP:
3385 case FW_PORT_TYPE_SFP28:
3386 /* Pluggable transceiver */
3387 switch (pi->mod_type) {
3388 case FW_PORT_MOD_TYPE_LR:
3389 switch (speed) {
3390 case FW_PORT_CAP32_SPEED_1G:
3391 return (IFM_1000_LX);
3392 case FW_PORT_CAP32_SPEED_10G:
3393 return (IFM_10G_LR);
3394 case FW_PORT_CAP32_SPEED_25G:
3395 return (IFM_25G_LR);
3396 case FW_PORT_CAP32_SPEED_40G:
3397 return (IFM_40G_LR4);
3398 case FW_PORT_CAP32_SPEED_50G:
3399 return (IFM_50G_LR2);
3400 case FW_PORT_CAP32_SPEED_100G:
3401 return (IFM_100G_LR4);
3402 }
3403 break;
3404 case FW_PORT_MOD_TYPE_SR:
3405 switch (speed) {
3406 case FW_PORT_CAP32_SPEED_1G:
3407 return (IFM_1000_SX);
3408 case FW_PORT_CAP32_SPEED_10G:
3409 return (IFM_10G_SR);
3410 case FW_PORT_CAP32_SPEED_25G:
3411 return (IFM_25G_SR);
3412 case FW_PORT_CAP32_SPEED_40G:
3413 return (IFM_40G_SR4);
3414 case FW_PORT_CAP32_SPEED_50G:
3415 return (IFM_50G_SR2);
3416 case FW_PORT_CAP32_SPEED_100G:
3417 return (IFM_100G_SR4);
3418 }
3419 break;
3420 case FW_PORT_MOD_TYPE_ER:
3421 if (speed == FW_PORT_CAP32_SPEED_10G)
3422 return (IFM_10G_ER);
3423 break;
3424 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3425 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3426 switch (speed) {
3427 case FW_PORT_CAP32_SPEED_1G:
3428 return (IFM_1000_CX);
3429 case FW_PORT_CAP32_SPEED_10G:
3430 return (IFM_10G_TWINAX);
3431 case FW_PORT_CAP32_SPEED_25G:
3432 return (IFM_25G_CR);
3433 case FW_PORT_CAP32_SPEED_40G:
3434 return (IFM_40G_CR4);
3435 case FW_PORT_CAP32_SPEED_50G:
3436 return (IFM_50G_CR2);
3437 case FW_PORT_CAP32_SPEED_100G:
3438 return (IFM_100G_CR4);
3439 }
3440 break;
3441 case FW_PORT_MOD_TYPE_LRM:
3442 if (speed == FW_PORT_CAP32_SPEED_10G)
3443 return (IFM_10G_LRM);
3444 break;
3445 case FW_PORT_MOD_TYPE_NA:
3446 MPASS(0); /* Not pluggable? */
3447 /* fall throough */
3448 case FW_PORT_MOD_TYPE_ERROR:
3449 case FW_PORT_MOD_TYPE_UNKNOWN:
3450 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
3451 break;
3452 case FW_PORT_MOD_TYPE_NONE:
3453 return (IFM_NONE);
3454 }
3455 break;
3456 case FW_PORT_TYPE_NONE:
3457 return (IFM_NONE);
3458 }
3459
3460 return (IFM_UNKNOWN);
3461 }
3462
3463 void
cxgbe_media_status(if_t ifp,struct ifmediareq * ifmr)3464 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr)
3465 {
3466 struct vi_info *vi = if_getsoftc(ifp);
3467 struct port_info *pi = vi->pi;
3468 struct adapter *sc = pi->adapter;
3469 struct link_config *lc = &pi->link_cfg;
3470
3471 if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0)
3472 return;
3473 PORT_LOCK(pi);
3474
3475 if (pi->up_vis == 0 && !hw_off_limits(sc)) {
3476 /*
3477 * If all the interfaces are administratively down the firmware
3478 * does not report transceiver changes. Refresh port info here
3479 * so that ifconfig displays accurate ifmedia at all times.
3480 * This is the only reason we have a synchronized op in this
3481 * function. Just PORT_LOCK would have been enough otherwise.
3482 */
3483 t4_update_port_info(pi);
3484 build_medialist(pi);
3485 }
3486
3487 /* ifm_status */
3488 ifmr->ifm_status = IFM_AVALID;
3489 if (lc->link_ok == false)
3490 goto done;
3491 ifmr->ifm_status |= IFM_ACTIVE;
3492
3493 /* ifm_active */
3494 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
3495 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
3496 if (lc->fc & PAUSE_RX)
3497 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3498 if (lc->fc & PAUSE_TX)
3499 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3500 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
3501 done:
3502 PORT_UNLOCK(pi);
3503 end_synchronized_op(sc, 0);
3504 }
3505
3506 static int
vcxgbe_probe(device_t dev)3507 vcxgbe_probe(device_t dev)
3508 {
3509 struct vi_info *vi = device_get_softc(dev);
3510
3511 device_set_descf(dev, "port %d vi %td", vi->pi->port_id,
3512 vi - vi->pi->vi);
3513
3514 return (BUS_PROBE_DEFAULT);
3515 }
3516
3517 static int
alloc_extra_vi(struct adapter * sc,struct port_info * pi,struct vi_info * vi)3518 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
3519 {
3520 int func, index, rc;
3521 uint32_t param, val;
3522
3523 ASSERT_SYNCHRONIZED_OP(sc);
3524
3525 index = vi - pi->vi;
3526 MPASS(index > 0); /* This function deals with _extra_ VIs only */
3527 KASSERT(index < nitems(vi_mac_funcs),
3528 ("%s: VI %s doesn't have a MAC func", __func__,
3529 device_get_nameunit(vi->dev)));
3530 func = vi_mac_funcs[index];
3531 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
3532 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
3533 if (rc < 0) {
3534 CH_ERR(vi, "failed to allocate virtual interface %d"
3535 "for port %d: %d\n", index, pi->port_id, -rc);
3536 return (-rc);
3537 }
3538 vi->viid = rc;
3539
3540 if (vi->rss_size == 1) {
3541 /*
3542 * This VI didn't get a slice of the RSS table. Reduce the
3543 * number of VIs being created (hw.cxgbe.num_vis) or modify the
3544 * configuration file (nvi, rssnvi for this PF) if this is a
3545 * problem.
3546 */
3547 device_printf(vi->dev, "RSS table not available.\n");
3548 vi->rss_base = 0xffff;
3549
3550 return (0);
3551 }
3552
3553 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3554 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
3555 V_FW_PARAMS_PARAM_YZ(vi->viid);
3556 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3557 if (rc)
3558 vi->rss_base = 0xffff;
3559 else {
3560 MPASS((val >> 16) == vi->rss_size);
3561 vi->rss_base = val & 0xffff;
3562 }
3563
3564 return (0);
3565 }
3566
3567 static int
vcxgbe_attach(device_t dev)3568 vcxgbe_attach(device_t dev)
3569 {
3570 struct vi_info *vi;
3571 struct port_info *pi;
3572 struct adapter *sc;
3573 int rc;
3574
3575 vi = device_get_softc(dev);
3576 pi = vi->pi;
3577 sc = pi->adapter;
3578
3579 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
3580 if (rc)
3581 return (rc);
3582 rc = alloc_extra_vi(sc, pi, vi);
3583 end_synchronized_op(sc, 0);
3584 if (rc)
3585 return (rc);
3586
3587 rc = cxgbe_vi_attach(dev, vi);
3588 if (rc) {
3589 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3590 return (rc);
3591 }
3592 return (0);
3593 }
3594
3595 static int
vcxgbe_detach(device_t dev)3596 vcxgbe_detach(device_t dev)
3597 {
3598 struct vi_info *vi;
3599 struct adapter *sc;
3600
3601 vi = device_get_softc(dev);
3602 sc = vi->adapter;
3603
3604 begin_vi_detach(sc, vi);
3605 cxgbe_vi_detach(vi);
3606 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3607 end_vi_detach(sc, vi);
3608
3609 return (0);
3610 }
3611
3612 static struct callout fatal_callout;
3613 static struct taskqueue *reset_tq;
3614
3615 static void
delayed_panic(void * arg)3616 delayed_panic(void *arg)
3617 {
3618 struct adapter *sc = arg;
3619
3620 panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
3621 }
3622
3623 static void
fatal_error_task(void * arg,int pending)3624 fatal_error_task(void *arg, int pending)
3625 {
3626 struct adapter *sc = arg;
3627 int rc;
3628
3629 #ifdef TCP_OFFLOAD
3630 t4_async_event(sc);
3631 #endif
3632 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) {
3633 dump_cim_regs(sc);
3634 dump_cimla(sc);
3635 dump_devlog(sc);
3636 }
3637
3638 if (t4_reset_on_fatal_err) {
3639 CH_ALERT(sc, "resetting on fatal error.\n");
3640 rc = reset_adapter(sc);
3641 if (rc == 0 && t4_panic_on_fatal_err) {
3642 CH_ALERT(sc, "reset was successful, "
3643 "system will NOT panic.\n");
3644 return;
3645 }
3646 }
3647
3648 if (t4_panic_on_fatal_err) {
3649 CH_ALERT(sc, "panicking on fatal error (after 30s).\n");
3650 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
3651 }
3652 }
3653
3654 void
t4_fatal_err(struct adapter * sc,bool fw_error)3655 t4_fatal_err(struct adapter *sc, bool fw_error)
3656 {
3657 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
3658
3659 stop_adapter(sc);
3660 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR)))
3661 return;
3662 if (fw_error) {
3663 /*
3664 * We are here because of a firmware error/timeout and not
3665 * because of a hardware interrupt. It is possible (although
3666 * not very likely) that an error interrupt was also raised but
3667 * this thread ran first and inhibited t4_intr_err. We walk the
3668 * main INT_CAUSE registers here to make sure we haven't missed
3669 * anything interesting.
3670 */
3671 t4_slow_intr_handler(sc, verbose);
3672 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
3673 }
3674 t4_report_fw_error(sc);
3675 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n",
3676 device_get_nameunit(sc->dev), fw_error);
3677 taskqueue_enqueue(reset_tq, &sc->fatal_error_task);
3678 }
3679
3680 void
t4_add_adapter(struct adapter * sc)3681 t4_add_adapter(struct adapter *sc)
3682 {
3683 sx_xlock(&t4_list_lock);
3684 SLIST_INSERT_HEAD(&t4_list, sc, link);
3685 sx_xunlock(&t4_list_lock);
3686 }
3687
3688 int
t4_map_bars_0_and_4(struct adapter * sc)3689 t4_map_bars_0_and_4(struct adapter *sc)
3690 {
3691 sc->regs_rid = PCIR_BAR(0);
3692 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3693 &sc->regs_rid, RF_ACTIVE);
3694 if (sc->regs_res == NULL) {
3695 device_printf(sc->dev, "cannot map registers.\n");
3696 return (ENXIO);
3697 }
3698 sc->bt = rman_get_bustag(sc->regs_res);
3699 sc->bh = rman_get_bushandle(sc->regs_res);
3700 sc->mmio_len = rman_get_size(sc->regs_res);
3701 setbit(&sc->doorbells, DOORBELL_KDB);
3702
3703 sc->msix_rid = PCIR_BAR(4);
3704 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3705 &sc->msix_rid, RF_ACTIVE);
3706 if (sc->msix_res == NULL) {
3707 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
3708 return (ENXIO);
3709 }
3710
3711 return (0);
3712 }
3713
3714 int
t4_map_bar_2(struct adapter * sc)3715 t4_map_bar_2(struct adapter *sc)
3716 {
3717
3718 /*
3719 * T4: only iWARP driver uses the userspace doorbells. There is no need
3720 * to map it if RDMA is disabled.
3721 */
3722 if (is_t4(sc) && sc->rdmacaps == 0)
3723 return (0);
3724
3725 sc->udbs_rid = PCIR_BAR(2);
3726 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3727 &sc->udbs_rid, RF_ACTIVE);
3728 if (sc->udbs_res == NULL) {
3729 device_printf(sc->dev, "cannot map doorbell BAR.\n");
3730 return (ENXIO);
3731 }
3732 sc->udbs_base = rman_get_virtual(sc->udbs_res);
3733
3734 if (chip_id(sc) >= CHELSIO_T5) {
3735 setbit(&sc->doorbells, DOORBELL_UDB);
3736 #if defined(__i386__) || defined(__amd64__)
3737 if (t5_write_combine) {
3738 int rc, mode;
3739
3740 /*
3741 * Enable write combining on BAR2. This is the
3742 * userspace doorbell BAR and is split into 128B
3743 * (UDBS_SEG_SIZE) doorbell regions, each associated
3744 * with an egress queue. The first 64B has the doorbell
3745 * and the second 64B can be used to submit a tx work
3746 * request with an implicit doorbell.
3747 */
3748
3749 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
3750 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
3751 if (rc == 0) {
3752 clrbit(&sc->doorbells, DOORBELL_UDB);
3753 setbit(&sc->doorbells, DOORBELL_WCWR);
3754 setbit(&sc->doorbells, DOORBELL_UDBWC);
3755 } else {
3756 device_printf(sc->dev,
3757 "couldn't enable write combining: %d\n",
3758 rc);
3759 }
3760
3761 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
3762 t4_write_reg(sc, A_SGE_STAT_CFG,
3763 V_STATSOURCE_T5(7) | mode);
3764 }
3765 #endif
3766 }
3767 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
3768
3769 return (0);
3770 }
3771
3772 int
t4_adj_doorbells(struct adapter * sc)3773 t4_adj_doorbells(struct adapter *sc)
3774 {
3775 if ((sc->doorbells & t4_doorbells_allowed) != 0) {
3776 sc->doorbells &= t4_doorbells_allowed;
3777 return (0);
3778 }
3779 CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n",
3780 sc->doorbells, t4_doorbells_allowed);
3781 return (EINVAL);
3782 }
3783
3784 struct memwin_init {
3785 uint32_t base;
3786 uint32_t aperture;
3787 };
3788
3789 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
3790 { MEMWIN0_BASE, MEMWIN0_APERTURE },
3791 { MEMWIN1_BASE, MEMWIN1_APERTURE },
3792 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
3793 };
3794
3795 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
3796 { MEMWIN0_BASE, MEMWIN0_APERTURE },
3797 { MEMWIN1_BASE, MEMWIN1_APERTURE },
3798 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
3799 };
3800
3801 static void
setup_memwin(struct adapter * sc)3802 setup_memwin(struct adapter *sc)
3803 {
3804 const struct memwin_init *mw_init;
3805 struct memwin *mw;
3806 int i;
3807 uint32_t bar0;
3808
3809 if (is_t4(sc)) {
3810 /*
3811 * Read low 32b of bar0 indirectly via the hardware backdoor
3812 * mechanism. Works from within PCI passthrough environments
3813 * too, where rman_get_start() can return a different value. We
3814 * need to program the T4 memory window decoders with the actual
3815 * addresses that will be coming across the PCIe link.
3816 */
3817 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
3818 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
3819
3820 mw_init = &t4_memwin[0];
3821 } else {
3822 /* T5+ use the relative offset inside the PCIe BAR */
3823 bar0 = 0;
3824
3825 mw_init = &t5_memwin[0];
3826 }
3827
3828 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
3829 if (!rw_initialized(&mw->mw_lock)) {
3830 rw_init(&mw->mw_lock, "memory window access");
3831 mw->mw_base = mw_init->base;
3832 mw->mw_aperture = mw_init->aperture;
3833 mw->mw_curpos = 0;
3834 }
3835 t4_write_reg(sc,
3836 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
3837 (mw->mw_base + bar0) | V_BIR(0) |
3838 V_WINDOW(ilog2(mw->mw_aperture) - 10));
3839 rw_wlock(&mw->mw_lock);
3840 position_memwin(sc, i, mw->mw_curpos);
3841 rw_wunlock(&mw->mw_lock);
3842 }
3843
3844 /* flush */
3845 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
3846 }
3847
3848 /*
3849 * Positions the memory window at the given address in the card's address space.
3850 * There are some alignment requirements and the actual position may be at an
3851 * address prior to the requested address. mw->mw_curpos always has the actual
3852 * position of the window.
3853 */
3854 static void
position_memwin(struct adapter * sc,int idx,uint32_t addr)3855 position_memwin(struct adapter *sc, int idx, uint32_t addr)
3856 {
3857 struct memwin *mw;
3858 uint32_t pf;
3859 uint32_t reg;
3860
3861 MPASS(idx >= 0 && idx < NUM_MEMWIN);
3862 mw = &sc->memwin[idx];
3863 rw_assert(&mw->mw_lock, RA_WLOCKED);
3864
3865 if (is_t4(sc)) {
3866 pf = 0;
3867 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
3868 } else {
3869 pf = V_PFNUM(sc->pf);
3870 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
3871 }
3872 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
3873 t4_write_reg(sc, reg, mw->mw_curpos | pf);
3874 t4_read_reg(sc, reg); /* flush */
3875 }
3876
3877 int
rw_via_memwin(struct adapter * sc,int idx,uint32_t addr,uint32_t * val,int len,int rw)3878 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
3879 int len, int rw)
3880 {
3881 struct memwin *mw;
3882 uint32_t mw_end, v;
3883
3884 MPASS(idx >= 0 && idx < NUM_MEMWIN);
3885
3886 /* Memory can only be accessed in naturally aligned 4 byte units */
3887 if (addr & 3 || len & 3 || len <= 0)
3888 return (EINVAL);
3889
3890 mw = &sc->memwin[idx];
3891 while (len > 0) {
3892 rw_rlock(&mw->mw_lock);
3893 mw_end = mw->mw_curpos + mw->mw_aperture;
3894 if (addr >= mw_end || addr < mw->mw_curpos) {
3895 /* Will need to reposition the window */
3896 if (!rw_try_upgrade(&mw->mw_lock)) {
3897 rw_runlock(&mw->mw_lock);
3898 rw_wlock(&mw->mw_lock);
3899 }
3900 rw_assert(&mw->mw_lock, RA_WLOCKED);
3901 position_memwin(sc, idx, addr);
3902 rw_downgrade(&mw->mw_lock);
3903 mw_end = mw->mw_curpos + mw->mw_aperture;
3904 }
3905 rw_assert(&mw->mw_lock, RA_RLOCKED);
3906 while (addr < mw_end && len > 0) {
3907 if (rw == 0) {
3908 v = t4_read_reg(sc, mw->mw_base + addr -
3909 mw->mw_curpos);
3910 *val++ = le32toh(v);
3911 } else {
3912 v = *val++;
3913 t4_write_reg(sc, mw->mw_base + addr -
3914 mw->mw_curpos, htole32(v));
3915 }
3916 addr += 4;
3917 len -= 4;
3918 }
3919 rw_runlock(&mw->mw_lock);
3920 }
3921
3922 return (0);
3923 }
3924
3925 CTASSERT(M_TID_COOKIE == M_COOKIE);
3926 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1));
3927
3928 static void
t4_init_atid_table(struct adapter * sc)3929 t4_init_atid_table(struct adapter *sc)
3930 {
3931 struct tid_info *t;
3932 int i;
3933
3934 t = &sc->tids;
3935 if (t->natids == 0)
3936 return;
3937
3938 MPASS(t->atid_tab == NULL);
3939
3940 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
3941 M_ZERO | M_WAITOK);
3942 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
3943 t->afree = t->atid_tab;
3944 t->atids_in_use = 0;
3945 for (i = 1; i < t->natids; i++)
3946 t->atid_tab[i - 1].next = &t->atid_tab[i];
3947 t->atid_tab[t->natids - 1].next = NULL;
3948 }
3949
3950 static void
t4_free_atid_table(struct adapter * sc)3951 t4_free_atid_table(struct adapter *sc)
3952 {
3953 struct tid_info *t;
3954
3955 t = &sc->tids;
3956
3957 KASSERT(t->atids_in_use == 0,
3958 ("%s: %d atids still in use.", __func__, t->atids_in_use));
3959
3960 if (mtx_initialized(&t->atid_lock))
3961 mtx_destroy(&t->atid_lock);
3962 free(t->atid_tab, M_CXGBE);
3963 t->atid_tab = NULL;
3964 }
3965
3966 int
alloc_atid(struct adapter * sc,void * ctx)3967 alloc_atid(struct adapter *sc, void *ctx)
3968 {
3969 struct tid_info *t = &sc->tids;
3970 int atid = -1;
3971
3972 mtx_lock(&t->atid_lock);
3973 if (t->afree) {
3974 union aopen_entry *p = t->afree;
3975
3976 atid = p - t->atid_tab;
3977 MPASS(atid <= M_TID_TID);
3978 t->afree = p->next;
3979 p->data = ctx;
3980 t->atids_in_use++;
3981 }
3982 mtx_unlock(&t->atid_lock);
3983 return (atid);
3984 }
3985
3986 void *
lookup_atid(struct adapter * sc,int atid)3987 lookup_atid(struct adapter *sc, int atid)
3988 {
3989 struct tid_info *t = &sc->tids;
3990
3991 return (t->atid_tab[atid].data);
3992 }
3993
3994 void
free_atid(struct adapter * sc,int atid)3995 free_atid(struct adapter *sc, int atid)
3996 {
3997 struct tid_info *t = &sc->tids;
3998 union aopen_entry *p = &t->atid_tab[atid];
3999
4000 mtx_lock(&t->atid_lock);
4001 p->next = t->afree;
4002 t->afree = p;
4003 t->atids_in_use--;
4004 mtx_unlock(&t->atid_lock);
4005 }
4006
4007 static void
queue_tid_release(struct adapter * sc,int tid)4008 queue_tid_release(struct adapter *sc, int tid)
4009 {
4010
4011 CXGBE_UNIMPLEMENTED("deferred tid release");
4012 }
4013
4014 void
release_tid(struct adapter * sc,int tid,struct sge_wrq * ctrlq)4015 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
4016 {
4017 struct wrqe *wr;
4018 struct cpl_tid_release *req;
4019
4020 wr = alloc_wrqe(sizeof(*req), ctrlq);
4021 if (wr == NULL) {
4022 queue_tid_release(sc, tid); /* defer */
4023 return;
4024 }
4025 req = wrtod(wr);
4026
4027 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
4028
4029 t4_wrq_tx(sc, wr);
4030 }
4031
4032 static int
t4_range_cmp(const void * a,const void * b)4033 t4_range_cmp(const void *a, const void *b)
4034 {
4035 return ((const struct t4_range *)a)->start -
4036 ((const struct t4_range *)b)->start;
4037 }
4038
4039 /*
4040 * Verify that the memory range specified by the addr/len pair is valid within
4041 * the card's address space.
4042 */
4043 static int
validate_mem_range(struct adapter * sc,uint32_t addr,uint32_t len)4044 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
4045 {
4046 struct t4_range mem_ranges[4], *r, *next;
4047 uint32_t em, addr_len;
4048 int i, n, remaining;
4049
4050 /* Memory can only be accessed in naturally aligned 4 byte units */
4051 if (addr & 3 || len & 3 || len == 0)
4052 return (EINVAL);
4053
4054 /* Enabled memories */
4055 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4056
4057 r = &mem_ranges[0];
4058 n = 0;
4059 bzero(r, sizeof(mem_ranges));
4060 if (em & F_EDRAM0_ENABLE) {
4061 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4062 r->size = G_EDRAM0_SIZE(addr_len) << 20;
4063 if (r->size > 0) {
4064 r->start = G_EDRAM0_BASE(addr_len) << 20;
4065 if (addr >= r->start &&
4066 addr + len <= r->start + r->size)
4067 return (0);
4068 r++;
4069 n++;
4070 }
4071 }
4072 if (em & F_EDRAM1_ENABLE) {
4073 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4074 r->size = G_EDRAM1_SIZE(addr_len) << 20;
4075 if (r->size > 0) {
4076 r->start = G_EDRAM1_BASE(addr_len) << 20;
4077 if (addr >= r->start &&
4078 addr + len <= r->start + r->size)
4079 return (0);
4080 r++;
4081 n++;
4082 }
4083 }
4084 if (em & F_EXT_MEM_ENABLE) {
4085 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4086 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
4087 if (r->size > 0) {
4088 r->start = G_EXT_MEM_BASE(addr_len) << 20;
4089 if (addr >= r->start &&
4090 addr + len <= r->start + r->size)
4091 return (0);
4092 r++;
4093 n++;
4094 }
4095 }
4096 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
4097 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4098 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
4099 if (r->size > 0) {
4100 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
4101 if (addr >= r->start &&
4102 addr + len <= r->start + r->size)
4103 return (0);
4104 r++;
4105 n++;
4106 }
4107 }
4108 MPASS(n <= nitems(mem_ranges));
4109
4110 if (n > 1) {
4111 /* Sort and merge the ranges. */
4112 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
4113
4114 /* Start from index 0 and examine the next n - 1 entries. */
4115 r = &mem_ranges[0];
4116 for (remaining = n - 1; remaining > 0; remaining--, r++) {
4117
4118 MPASS(r->size > 0); /* r is a valid entry. */
4119 next = r + 1;
4120 MPASS(next->size > 0); /* and so is the next one. */
4121
4122 while (r->start + r->size >= next->start) {
4123 /* Merge the next one into the current entry. */
4124 r->size = max(r->start + r->size,
4125 next->start + next->size) - r->start;
4126 n--; /* One fewer entry in total. */
4127 if (--remaining == 0)
4128 goto done; /* short circuit */
4129 next++;
4130 }
4131 if (next != r + 1) {
4132 /*
4133 * Some entries were merged into r and next
4134 * points to the first valid entry that couldn't
4135 * be merged.
4136 */
4137 MPASS(next->size > 0); /* must be valid */
4138 memcpy(r + 1, next, remaining * sizeof(*r));
4139 #ifdef INVARIANTS
4140 /*
4141 * This so that the foo->size assertion in the
4142 * next iteration of the loop do the right
4143 * thing for entries that were pulled up and are
4144 * no longer valid.
4145 */
4146 MPASS(n < nitems(mem_ranges));
4147 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
4148 sizeof(struct t4_range));
4149 #endif
4150 }
4151 }
4152 done:
4153 /* Done merging the ranges. */
4154 MPASS(n > 0);
4155 r = &mem_ranges[0];
4156 for (i = 0; i < n; i++, r++) {
4157 if (addr >= r->start &&
4158 addr + len <= r->start + r->size)
4159 return (0);
4160 }
4161 }
4162
4163 return (EFAULT);
4164 }
4165
4166 static int
fwmtype_to_hwmtype(int mtype)4167 fwmtype_to_hwmtype(int mtype)
4168 {
4169
4170 switch (mtype) {
4171 case FW_MEMTYPE_EDC0:
4172 return (MEM_EDC0);
4173 case FW_MEMTYPE_EDC1:
4174 return (MEM_EDC1);
4175 case FW_MEMTYPE_EXTMEM:
4176 return (MEM_MC0);
4177 case FW_MEMTYPE_EXTMEM1:
4178 return (MEM_MC1);
4179 default:
4180 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
4181 }
4182 }
4183
4184 /*
4185 * Verify that the memory range specified by the memtype/offset/len pair is
4186 * valid and lies entirely within the memtype specified. The global address of
4187 * the start of the range is returned in addr.
4188 */
4189 static int
validate_mt_off_len(struct adapter * sc,int mtype,uint32_t off,uint32_t len,uint32_t * addr)4190 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
4191 uint32_t *addr)
4192 {
4193 uint32_t em, addr_len, maddr;
4194
4195 /* Memory can only be accessed in naturally aligned 4 byte units */
4196 if (off & 3 || len & 3 || len == 0)
4197 return (EINVAL);
4198
4199 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4200 switch (fwmtype_to_hwmtype(mtype)) {
4201 case MEM_EDC0:
4202 if (!(em & F_EDRAM0_ENABLE))
4203 return (EINVAL);
4204 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4205 maddr = G_EDRAM0_BASE(addr_len) << 20;
4206 break;
4207 case MEM_EDC1:
4208 if (!(em & F_EDRAM1_ENABLE))
4209 return (EINVAL);
4210 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4211 maddr = G_EDRAM1_BASE(addr_len) << 20;
4212 break;
4213 case MEM_MC:
4214 if (!(em & F_EXT_MEM_ENABLE))
4215 return (EINVAL);
4216 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4217 maddr = G_EXT_MEM_BASE(addr_len) << 20;
4218 break;
4219 case MEM_MC1:
4220 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
4221 return (EINVAL);
4222 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4223 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
4224 break;
4225 default:
4226 return (EINVAL);
4227 }
4228
4229 *addr = maddr + off; /* global address */
4230 return (validate_mem_range(sc, *addr, len));
4231 }
4232
4233 static int
fixup_devlog_params(struct adapter * sc)4234 fixup_devlog_params(struct adapter *sc)
4235 {
4236 struct devlog_params *dparams = &sc->params.devlog;
4237 int rc;
4238
4239 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
4240 dparams->size, &dparams->addr);
4241
4242 return (rc);
4243 }
4244
4245 static void
update_nirq(struct intrs_and_queues * iaq,int nports)4246 update_nirq(struct intrs_and_queues *iaq, int nports)
4247 {
4248
4249 iaq->nirq = T4_EXTRA_INTR;
4250 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
4251 iaq->nirq += nports * iaq->nofldrxq;
4252 iaq->nirq += nports * (iaq->num_vis - 1) *
4253 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
4254 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
4255 }
4256
4257 /*
4258 * Adjust requirements to fit the number of interrupts available.
4259 */
4260 static void
calculate_iaq(struct adapter * sc,struct intrs_and_queues * iaq,int itype,int navail)4261 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
4262 int navail)
4263 {
4264 int old_nirq;
4265 const int nports = sc->params.nports;
4266
4267 MPASS(nports > 0);
4268 MPASS(navail > 0);
4269
4270 bzero(iaq, sizeof(*iaq));
4271 iaq->intr_type = itype;
4272 iaq->num_vis = t4_num_vis;
4273 iaq->ntxq = t4_ntxq;
4274 iaq->ntxq_vi = t4_ntxq_vi;
4275 iaq->nrxq = t4_nrxq;
4276 iaq->nrxq_vi = t4_nrxq_vi;
4277 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4278 if (is_offload(sc) || is_ethoffload(sc)) {
4279 iaq->nofldtxq = t4_nofldtxq;
4280 iaq->nofldtxq_vi = t4_nofldtxq_vi;
4281 }
4282 #endif
4283 #ifdef TCP_OFFLOAD
4284 if (is_offload(sc)) {
4285 iaq->nofldrxq = t4_nofldrxq;
4286 iaq->nofldrxq_vi = t4_nofldrxq_vi;
4287 }
4288 #endif
4289 #ifdef DEV_NETMAP
4290 if (t4_native_netmap & NN_MAIN_VI) {
4291 iaq->nnmtxq = t4_nnmtxq;
4292 iaq->nnmrxq = t4_nnmrxq;
4293 }
4294 if (t4_native_netmap & NN_EXTRA_VI) {
4295 iaq->nnmtxq_vi = t4_nnmtxq_vi;
4296 iaq->nnmrxq_vi = t4_nnmrxq_vi;
4297 }
4298 #endif
4299
4300 update_nirq(iaq, nports);
4301 if (iaq->nirq <= navail &&
4302 (itype != INTR_MSI || powerof2(iaq->nirq))) {
4303 /*
4304 * This is the normal case -- there are enough interrupts for
4305 * everything.
4306 */
4307 goto done;
4308 }
4309
4310 /*
4311 * If extra VIs have been configured try reducing their count and see if
4312 * that works.
4313 */
4314 while (iaq->num_vis > 1) {
4315 iaq->num_vis--;
4316 update_nirq(iaq, nports);
4317 if (iaq->nirq <= navail &&
4318 (itype != INTR_MSI || powerof2(iaq->nirq))) {
4319 device_printf(sc->dev, "virtual interfaces per port "
4320 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
4321 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
4322 "itype %d, navail %u, nirq %d.\n",
4323 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
4324 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
4325 itype, navail, iaq->nirq);
4326 goto done;
4327 }
4328 }
4329
4330 /*
4331 * Extra VIs will not be created. Log a message if they were requested.
4332 */
4333 MPASS(iaq->num_vis == 1);
4334 iaq->ntxq_vi = iaq->nrxq_vi = 0;
4335 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
4336 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
4337 if (iaq->num_vis != t4_num_vis) {
4338 device_printf(sc->dev, "extra virtual interfaces disabled. "
4339 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
4340 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
4341 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
4342 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
4343 }
4344
4345 /*
4346 * Keep reducing the number of NIC rx queues to the next lower power of
4347 * 2 (for even RSS distribution) and halving the TOE rx queues and see
4348 * if that works.
4349 */
4350 do {
4351 if (iaq->nrxq > 1) {
4352 do {
4353 iaq->nrxq--;
4354 } while (!powerof2(iaq->nrxq));
4355 if (iaq->nnmrxq > iaq->nrxq)
4356 iaq->nnmrxq = iaq->nrxq;
4357 }
4358 if (iaq->nofldrxq > 1)
4359 iaq->nofldrxq >>= 1;
4360
4361 old_nirq = iaq->nirq;
4362 update_nirq(iaq, nports);
4363 if (iaq->nirq <= navail &&
4364 (itype != INTR_MSI || powerof2(iaq->nirq))) {
4365 device_printf(sc->dev, "running with reduced number of "
4366 "rx queues because of shortage of interrupts. "
4367 "nrxq=%u, nofldrxq=%u. "
4368 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
4369 iaq->nofldrxq, itype, navail, iaq->nirq);
4370 goto done;
4371 }
4372 } while (old_nirq != iaq->nirq);
4373
4374 /* One interrupt for everything. Ugh. */
4375 device_printf(sc->dev, "running with minimal number of queues. "
4376 "itype %d, navail %u.\n", itype, navail);
4377 iaq->nirq = 1;
4378 iaq->nrxq = 1;
4379 iaq->ntxq = 1;
4380 if (iaq->nofldrxq > 0) {
4381 iaq->nofldrxq = 1;
4382 iaq->nofldtxq = 1;
4383 }
4384 iaq->nnmtxq = 0;
4385 iaq->nnmrxq = 0;
4386 done:
4387 MPASS(iaq->num_vis > 0);
4388 if (iaq->num_vis > 1) {
4389 MPASS(iaq->nrxq_vi > 0);
4390 MPASS(iaq->ntxq_vi > 0);
4391 }
4392 MPASS(iaq->nirq > 0);
4393 MPASS(iaq->nrxq > 0);
4394 MPASS(iaq->ntxq > 0);
4395 if (itype == INTR_MSI) {
4396 MPASS(powerof2(iaq->nirq));
4397 }
4398 }
4399
4400 static int
cfg_itype_and_nqueues(struct adapter * sc,struct intrs_and_queues * iaq)4401 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
4402 {
4403 int rc, itype, navail, nalloc;
4404
4405 for (itype = INTR_MSIX; itype; itype >>= 1) {
4406
4407 if ((itype & t4_intr_types) == 0)
4408 continue; /* not allowed */
4409
4410 if (itype == INTR_MSIX)
4411 navail = pci_msix_count(sc->dev);
4412 else if (itype == INTR_MSI)
4413 navail = pci_msi_count(sc->dev);
4414 else
4415 navail = 1;
4416 restart:
4417 if (navail == 0)
4418 continue;
4419
4420 calculate_iaq(sc, iaq, itype, navail);
4421 nalloc = iaq->nirq;
4422 rc = 0;
4423 if (itype == INTR_MSIX)
4424 rc = pci_alloc_msix(sc->dev, &nalloc);
4425 else if (itype == INTR_MSI)
4426 rc = pci_alloc_msi(sc->dev, &nalloc);
4427
4428 if (rc == 0 && nalloc > 0) {
4429 if (nalloc == iaq->nirq)
4430 return (0);
4431
4432 /*
4433 * Didn't get the number requested. Use whatever number
4434 * the kernel is willing to allocate.
4435 */
4436 device_printf(sc->dev, "fewer vectors than requested, "
4437 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
4438 itype, iaq->nirq, nalloc);
4439 pci_release_msi(sc->dev);
4440 navail = nalloc;
4441 goto restart;
4442 }
4443
4444 device_printf(sc->dev,
4445 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
4446 itype, rc, iaq->nirq, nalloc);
4447 }
4448
4449 device_printf(sc->dev,
4450 "failed to find a usable interrupt type. "
4451 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
4452 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
4453
4454 return (ENXIO);
4455 }
4456
4457 #define FW_VERSION(chip) ( \
4458 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
4459 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
4460 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
4461 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
4462 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
4463
4464 /* Just enough of fw_hdr to cover all version info. */
4465 struct fw_h {
4466 __u8 ver;
4467 __u8 chip;
4468 __be16 len512;
4469 __be32 fw_ver;
4470 __be32 tp_microcode_ver;
4471 __u8 intfver_nic;
4472 __u8 intfver_vnic;
4473 __u8 intfver_ofld;
4474 __u8 intfver_ri;
4475 __u8 intfver_iscsipdu;
4476 __u8 intfver_iscsi;
4477 __u8 intfver_fcoepdu;
4478 __u8 intfver_fcoe;
4479 };
4480 /* Spot check a couple of fields. */
4481 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
4482 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
4483 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
4484
4485 struct fw_info {
4486 uint8_t chip;
4487 char *kld_name;
4488 char *fw_mod_name;
4489 struct fw_h fw_h;
4490 } fw_info[] = {
4491 {
4492 .chip = CHELSIO_T4,
4493 .kld_name = "t4fw_cfg",
4494 .fw_mod_name = "t4fw",
4495 .fw_h = {
4496 .chip = FW_HDR_CHIP_T4,
4497 .fw_ver = htobe32(FW_VERSION(T4)),
4498 .intfver_nic = FW_INTFVER(T4, NIC),
4499 .intfver_vnic = FW_INTFVER(T4, VNIC),
4500 .intfver_ofld = FW_INTFVER(T4, OFLD),
4501 .intfver_ri = FW_INTFVER(T4, RI),
4502 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
4503 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4504 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
4505 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4506 },
4507 }, {
4508 .chip = CHELSIO_T5,
4509 .kld_name = "t5fw_cfg",
4510 .fw_mod_name = "t5fw",
4511 .fw_h = {
4512 .chip = FW_HDR_CHIP_T5,
4513 .fw_ver = htobe32(FW_VERSION(T5)),
4514 .intfver_nic = FW_INTFVER(T5, NIC),
4515 .intfver_vnic = FW_INTFVER(T5, VNIC),
4516 .intfver_ofld = FW_INTFVER(T5, OFLD),
4517 .intfver_ri = FW_INTFVER(T5, RI),
4518 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
4519 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4520 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
4521 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4522 },
4523 }, {
4524 .chip = CHELSIO_T6,
4525 .kld_name = "t6fw_cfg",
4526 .fw_mod_name = "t6fw",
4527 .fw_h = {
4528 .chip = FW_HDR_CHIP_T6,
4529 .fw_ver = htobe32(FW_VERSION(T6)),
4530 .intfver_nic = FW_INTFVER(T6, NIC),
4531 .intfver_vnic = FW_INTFVER(T6, VNIC),
4532 .intfver_ofld = FW_INTFVER(T6, OFLD),
4533 .intfver_ri = FW_INTFVER(T6, RI),
4534 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4535 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4536 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4537 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4538 },
4539 }
4540 };
4541
4542 static struct fw_info *
find_fw_info(int chip)4543 find_fw_info(int chip)
4544 {
4545 int i;
4546
4547 for (i = 0; i < nitems(fw_info); i++) {
4548 if (fw_info[i].chip == chip)
4549 return (&fw_info[i]);
4550 }
4551 return (NULL);
4552 }
4553
4554 /*
4555 * Is the given firmware API compatible with the one the driver was compiled
4556 * with?
4557 */
4558 static int
fw_compatible(const struct fw_h * hdr1,const struct fw_h * hdr2)4559 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
4560 {
4561
4562 /* short circuit if it's the exact same firmware version */
4563 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
4564 return (1);
4565
4566 /*
4567 * XXX: Is this too conservative? Perhaps I should limit this to the
4568 * features that are supported in the driver.
4569 */
4570 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
4571 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
4572 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
4573 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
4574 return (1);
4575 #undef SAME_INTF
4576
4577 return (0);
4578 }
4579
4580 static int
load_fw_module(struct adapter * sc,const struct firmware ** dcfg,const struct firmware ** fw)4581 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
4582 const struct firmware **fw)
4583 {
4584 struct fw_info *fw_info;
4585
4586 *dcfg = NULL;
4587 if (fw != NULL)
4588 *fw = NULL;
4589
4590 fw_info = find_fw_info(chip_id(sc));
4591 if (fw_info == NULL) {
4592 device_printf(sc->dev,
4593 "unable to look up firmware information for chip %d.\n",
4594 chip_id(sc));
4595 return (EINVAL);
4596 }
4597
4598 *dcfg = firmware_get(fw_info->kld_name);
4599 if (*dcfg != NULL) {
4600 if (fw != NULL)
4601 *fw = firmware_get(fw_info->fw_mod_name);
4602 return (0);
4603 }
4604
4605 return (ENOENT);
4606 }
4607
4608 static void
unload_fw_module(struct adapter * sc,const struct firmware * dcfg,const struct firmware * fw)4609 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
4610 const struct firmware *fw)
4611 {
4612
4613 if (fw != NULL)
4614 firmware_put(fw, FIRMWARE_UNLOAD);
4615 if (dcfg != NULL)
4616 firmware_put(dcfg, FIRMWARE_UNLOAD);
4617 }
4618
4619 /*
4620 * Return values:
4621 * 0 means no firmware install attempted.
4622 * ERESTART means a firmware install was attempted and was successful.
4623 * +ve errno means a firmware install was attempted but failed.
4624 */
4625 static int
install_kld_firmware(struct adapter * sc,struct fw_h * card_fw,const struct fw_h * drv_fw,const char * reason,int * already)4626 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
4627 const struct fw_h *drv_fw, const char *reason, int *already)
4628 {
4629 const struct firmware *cfg, *fw;
4630 const uint32_t c = be32toh(card_fw->fw_ver);
4631 uint32_t d, k;
4632 int rc, fw_install;
4633 struct fw_h bundled_fw;
4634 bool load_attempted;
4635
4636 cfg = fw = NULL;
4637 load_attempted = false;
4638 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
4639
4640 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
4641 if (t4_fw_install < 0) {
4642 rc = load_fw_module(sc, &cfg, &fw);
4643 if (rc != 0 || fw == NULL) {
4644 device_printf(sc->dev,
4645 "failed to load firmware module: %d. cfg %p, fw %p;"
4646 " will use compiled-in firmware version for"
4647 "hw.cxgbe.fw_install checks.\n",
4648 rc, cfg, fw);
4649 } else {
4650 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
4651 }
4652 load_attempted = true;
4653 }
4654 d = be32toh(bundled_fw.fw_ver);
4655
4656 if (reason != NULL)
4657 goto install;
4658
4659 if ((sc->flags & FW_OK) == 0) {
4660
4661 if (c == 0xffffffff) {
4662 reason = "missing";
4663 goto install;
4664 }
4665
4666 rc = 0;
4667 goto done;
4668 }
4669
4670 if (!fw_compatible(card_fw, &bundled_fw)) {
4671 reason = "incompatible or unusable";
4672 goto install;
4673 }
4674
4675 if (d > c) {
4676 reason = "older than the version bundled with this driver";
4677 goto install;
4678 }
4679
4680 if (fw_install == 2 && d != c) {
4681 reason = "different than the version bundled with this driver";
4682 goto install;
4683 }
4684
4685 /* No reason to do anything to the firmware already on the card. */
4686 rc = 0;
4687 goto done;
4688
4689 install:
4690 rc = 0;
4691 if ((*already)++)
4692 goto done;
4693
4694 if (fw_install == 0) {
4695 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
4696 "but the driver is prohibited from installing a firmware "
4697 "on the card.\n",
4698 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
4699 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
4700
4701 goto done;
4702 }
4703
4704 /*
4705 * We'll attempt to install a firmware. Load the module first (if it
4706 * hasn't been loaded already).
4707 */
4708 if (!load_attempted) {
4709 rc = load_fw_module(sc, &cfg, &fw);
4710 if (rc != 0 || fw == NULL) {
4711 device_printf(sc->dev,
4712 "failed to load firmware module: %d. cfg %p, fw %p\n",
4713 rc, cfg, fw);
4714 /* carry on */
4715 }
4716 }
4717 if (fw == NULL) {
4718 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
4719 "but the driver cannot take corrective action because it "
4720 "is unable to load the firmware module.\n",
4721 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
4722 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
4723 rc = sc->flags & FW_OK ? 0 : ENOENT;
4724 goto done;
4725 }
4726 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
4727 if (k != d) {
4728 MPASS(t4_fw_install > 0);
4729 device_printf(sc->dev,
4730 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
4731 "expecting (%u.%u.%u.%u) and will not be used.\n",
4732 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
4733 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
4734 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
4735 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
4736 rc = sc->flags & FW_OK ? 0 : EINVAL;
4737 goto done;
4738 }
4739
4740 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
4741 "installing firmware %u.%u.%u.%u on card.\n",
4742 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
4743 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
4744 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
4745 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
4746
4747 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
4748 if (rc != 0) {
4749 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
4750 } else {
4751 /* Installed successfully, update the cached header too. */
4752 rc = ERESTART;
4753 memcpy(card_fw, fw->data, sizeof(*card_fw));
4754 }
4755 done:
4756 unload_fw_module(sc, cfg, fw);
4757
4758 return (rc);
4759 }
4760
4761 /*
4762 * Establish contact with the firmware and attempt to become the master driver.
4763 *
4764 * A firmware will be installed to the card if needed (if the driver is allowed
4765 * to do so).
4766 */
4767 static int
contact_firmware(struct adapter * sc)4768 contact_firmware(struct adapter *sc)
4769 {
4770 int rc, already = 0;
4771 enum dev_state state;
4772 struct fw_info *fw_info;
4773 struct fw_hdr *card_fw; /* fw on the card */
4774 const struct fw_h *drv_fw;
4775
4776 fw_info = find_fw_info(chip_id(sc));
4777 if (fw_info == NULL) {
4778 device_printf(sc->dev,
4779 "unable to look up firmware information for chip %d.\n",
4780 chip_id(sc));
4781 return (EINVAL);
4782 }
4783 drv_fw = &fw_info->fw_h;
4784
4785 /* Read the header of the firmware on the card */
4786 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
4787 restart:
4788 rc = -t4_get_fw_hdr(sc, card_fw);
4789 if (rc != 0) {
4790 device_printf(sc->dev,
4791 "unable to read firmware header from card's flash: %d\n",
4792 rc);
4793 goto done;
4794 }
4795
4796 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
4797 &already);
4798 if (rc == ERESTART)
4799 goto restart;
4800 if (rc != 0)
4801 goto done;
4802
4803 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
4804 if (rc < 0 || state == DEV_STATE_ERR) {
4805 rc = -rc;
4806 device_printf(sc->dev,
4807 "failed to connect to the firmware: %d, %d. "
4808 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
4809 #if 0
4810 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
4811 "not responding properly to HELLO", &already) == ERESTART)
4812 goto restart;
4813 #endif
4814 goto done;
4815 }
4816 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
4817 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
4818
4819 if (rc == sc->pf) {
4820 sc->flags |= MASTER_PF;
4821 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
4822 NULL, &already);
4823 if (rc == ERESTART)
4824 rc = 0;
4825 else if (rc != 0)
4826 goto done;
4827 } else if (state == DEV_STATE_UNINIT) {
4828 /*
4829 * We didn't get to be the master so we definitely won't be
4830 * configuring the chip. It's a bug if someone else hasn't
4831 * configured it already.
4832 */
4833 device_printf(sc->dev, "couldn't be master(%d), "
4834 "device not already initialized either(%d). "
4835 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
4836 rc = EPROTO;
4837 goto done;
4838 } else {
4839 /*
4840 * Some other PF is the master and has configured the chip.
4841 * This is allowed but untested.
4842 */
4843 device_printf(sc->dev, "PF%d is master, device state %d. "
4844 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
4845 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
4846 sc->cfcsum = 0;
4847 rc = 0;
4848 }
4849 done:
4850 if (rc != 0 && sc->flags & FW_OK) {
4851 t4_fw_bye(sc, sc->mbox);
4852 sc->flags &= ~FW_OK;
4853 }
4854 free(card_fw, M_CXGBE);
4855 return (rc);
4856 }
4857
4858 static int
copy_cfg_file_to_card(struct adapter * sc,char * cfg_file,uint32_t mtype,uint32_t moff)4859 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
4860 uint32_t mtype, uint32_t moff)
4861 {
4862 struct fw_info *fw_info;
4863 const struct firmware *dcfg, *rcfg = NULL;
4864 const uint32_t *cfdata;
4865 uint32_t cflen, addr;
4866 int rc;
4867
4868 load_fw_module(sc, &dcfg, NULL);
4869
4870 /* Card specific interpretation of "default". */
4871 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
4872 if (pci_get_device(sc->dev) == 0x440a)
4873 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
4874 if (is_fpga(sc))
4875 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
4876 }
4877
4878 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
4879 if (dcfg == NULL) {
4880 device_printf(sc->dev,
4881 "KLD with default config is not available.\n");
4882 rc = ENOENT;
4883 goto done;
4884 }
4885 cfdata = dcfg->data;
4886 cflen = dcfg->datasize & ~3;
4887 } else {
4888 char s[32];
4889
4890 fw_info = find_fw_info(chip_id(sc));
4891 if (fw_info == NULL) {
4892 device_printf(sc->dev,
4893 "unable to look up firmware information for chip %d.\n",
4894 chip_id(sc));
4895 rc = EINVAL;
4896 goto done;
4897 }
4898 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
4899
4900 rcfg = firmware_get(s);
4901 if (rcfg == NULL) {
4902 device_printf(sc->dev,
4903 "unable to load module \"%s\" for configuration "
4904 "profile \"%s\".\n", s, cfg_file);
4905 rc = ENOENT;
4906 goto done;
4907 }
4908 cfdata = rcfg->data;
4909 cflen = rcfg->datasize & ~3;
4910 }
4911
4912 if (cflen > FLASH_CFG_MAX_SIZE) {
4913 device_printf(sc->dev,
4914 "config file too long (%d, max allowed is %d).\n",
4915 cflen, FLASH_CFG_MAX_SIZE);
4916 rc = EINVAL;
4917 goto done;
4918 }
4919
4920 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
4921 if (rc != 0) {
4922 device_printf(sc->dev,
4923 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
4924 __func__, mtype, moff, cflen, rc);
4925 rc = EINVAL;
4926 goto done;
4927 }
4928 write_via_memwin(sc, 2, addr, cfdata, cflen);
4929 done:
4930 if (rcfg != NULL)
4931 firmware_put(rcfg, FIRMWARE_UNLOAD);
4932 unload_fw_module(sc, dcfg, NULL);
4933 return (rc);
4934 }
4935
4936 struct caps_allowed {
4937 uint16_t nbmcaps;
4938 uint16_t linkcaps;
4939 uint16_t switchcaps;
4940 uint16_t niccaps;
4941 uint16_t toecaps;
4942 uint16_t rdmacaps;
4943 uint16_t cryptocaps;
4944 uint16_t iscsicaps;
4945 uint16_t fcoecaps;
4946 };
4947
4948 #define FW_PARAM_DEV(param) \
4949 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
4950 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
4951 #define FW_PARAM_PFVF(param) \
4952 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
4953 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
4954
4955 /*
4956 * Provide a configuration profile to the firmware and have it initialize the
4957 * chip accordingly. This may involve uploading a configuration file to the
4958 * card.
4959 */
4960 static int
apply_cfg_and_initialize(struct adapter * sc,char * cfg_file,const struct caps_allowed * caps_allowed)4961 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
4962 const struct caps_allowed *caps_allowed)
4963 {
4964 int rc;
4965 struct fw_caps_config_cmd caps;
4966 uint32_t mtype, moff, finicsum, cfcsum, param, val;
4967
4968 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
4969 if (rc != 0) {
4970 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
4971 return (rc);
4972 }
4973
4974 bzero(&caps, sizeof(caps));
4975 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4976 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4977 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
4978 mtype = 0;
4979 moff = 0;
4980 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4981 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
4982 mtype = FW_MEMTYPE_FLASH;
4983 moff = t4_flash_cfg_addr(sc);
4984 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4985 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4986 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4987 FW_LEN16(caps));
4988 } else {
4989 /*
4990 * Ask the firmware where it wants us to upload the config file.
4991 */
4992 param = FW_PARAM_DEV(CF);
4993 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4994 if (rc != 0) {
4995 /* No support for config file? Shouldn't happen. */
4996 device_printf(sc->dev,
4997 "failed to query config file location: %d.\n", rc);
4998 goto done;
4999 }
5000 mtype = G_FW_PARAMS_PARAM_Y(val);
5001 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
5002 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5003 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5004 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5005 FW_LEN16(caps));
5006
5007 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
5008 if (rc != 0) {
5009 device_printf(sc->dev,
5010 "failed to upload config file to card: %d.\n", rc);
5011 goto done;
5012 }
5013 }
5014 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5015 if (rc != 0) {
5016 device_printf(sc->dev, "failed to pre-process config file: %d "
5017 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
5018 goto done;
5019 }
5020
5021 finicsum = be32toh(caps.finicsum);
5022 cfcsum = be32toh(caps.cfcsum); /* actual */
5023 if (finicsum != cfcsum) {
5024 device_printf(sc->dev,
5025 "WARNING: config file checksum mismatch: %08x %08x\n",
5026 finicsum, cfcsum);
5027 }
5028 sc->cfcsum = cfcsum;
5029 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
5030
5031 /*
5032 * Let the firmware know what features will (not) be used so it can tune
5033 * things accordingly.
5034 */
5035 #define LIMIT_CAPS(x) do { \
5036 caps.x##caps &= htobe16(caps_allowed->x##caps); \
5037 } while (0)
5038 LIMIT_CAPS(nbm);
5039 LIMIT_CAPS(link);
5040 LIMIT_CAPS(switch);
5041 LIMIT_CAPS(nic);
5042 LIMIT_CAPS(toe);
5043 LIMIT_CAPS(rdma);
5044 LIMIT_CAPS(crypto);
5045 LIMIT_CAPS(iscsi);
5046 LIMIT_CAPS(fcoe);
5047 #undef LIMIT_CAPS
5048 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
5049 /*
5050 * TOE and hashfilters are mutually exclusive. It is a config
5051 * file or firmware bug if both are reported as available. Try
5052 * to cope with the situation in non-debug builds by disabling
5053 * TOE.
5054 */
5055 MPASS(caps.toecaps == 0);
5056
5057 caps.toecaps = 0;
5058 caps.rdmacaps = 0;
5059 caps.iscsicaps = 0;
5060 }
5061
5062 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5063 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5064 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5065 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
5066 if (rc != 0) {
5067 device_printf(sc->dev,
5068 "failed to process config file: %d.\n", rc);
5069 goto done;
5070 }
5071
5072 t4_tweak_chip_settings(sc);
5073 set_params__pre_init(sc);
5074
5075 /* get basic stuff going */
5076 rc = -t4_fw_initialize(sc, sc->mbox);
5077 if (rc != 0) {
5078 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
5079 goto done;
5080 }
5081 done:
5082 return (rc);
5083 }
5084
5085 /*
5086 * Partition chip resources for use between various PFs, VFs, etc.
5087 */
5088 static int
partition_resources(struct adapter * sc)5089 partition_resources(struct adapter *sc)
5090 {
5091 char cfg_file[sizeof(t4_cfg_file)];
5092 struct caps_allowed caps_allowed;
5093 int rc;
5094 bool fallback;
5095
5096 /* Only the master driver gets to configure the chip resources. */
5097 MPASS(sc->flags & MASTER_PF);
5098
5099 #define COPY_CAPS(x) do { \
5100 caps_allowed.x##caps = t4_##x##caps_allowed; \
5101 } while (0)
5102 bzero(&caps_allowed, sizeof(caps_allowed));
5103 COPY_CAPS(nbm);
5104 COPY_CAPS(link);
5105 COPY_CAPS(switch);
5106 COPY_CAPS(nic);
5107 COPY_CAPS(toe);
5108 COPY_CAPS(rdma);
5109 COPY_CAPS(crypto);
5110 COPY_CAPS(iscsi);
5111 COPY_CAPS(fcoe);
5112 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
5113 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
5114 retry:
5115 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
5116 if (rc != 0 && fallback) {
5117 dump_devlog(sc);
5118 device_printf(sc->dev,
5119 "failed (%d) to configure card with \"%s\" profile, "
5120 "will fall back to a basic configuration and retry.\n",
5121 rc, cfg_file);
5122 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
5123 bzero(&caps_allowed, sizeof(caps_allowed));
5124 COPY_CAPS(switch);
5125 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
5126 fallback = false;
5127 goto retry;
5128 }
5129 #undef COPY_CAPS
5130 return (rc);
5131 }
5132
5133 /*
5134 * Retrieve parameters that are needed (or nice to have) very early.
5135 */
5136 static int
get_params__pre_init(struct adapter * sc)5137 get_params__pre_init(struct adapter *sc)
5138 {
5139 int rc;
5140 uint32_t param[2], val[2];
5141
5142 t4_get_version_info(sc);
5143
5144 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
5145 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
5146 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
5147 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
5148 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
5149
5150 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
5151 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
5152 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
5153 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
5154 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
5155
5156 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
5157 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
5158 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
5159 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
5160 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
5161
5162 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
5163 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
5164 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
5165 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
5166 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
5167
5168 param[0] = FW_PARAM_DEV(PORTVEC);
5169 param[1] = FW_PARAM_DEV(CCLK);
5170 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5171 if (rc != 0) {
5172 device_printf(sc->dev,
5173 "failed to query parameters (pre_init): %d.\n", rc);
5174 return (rc);
5175 }
5176
5177 sc->params.portvec = val[0];
5178 sc->params.nports = bitcount32(val[0]);
5179 sc->params.vpd.cclk = val[1];
5180
5181 /* Read device log parameters. */
5182 rc = -t4_init_devlog_params(sc, 1);
5183 if (rc == 0)
5184 fixup_devlog_params(sc);
5185 else {
5186 device_printf(sc->dev,
5187 "failed to get devlog parameters: %d.\n", rc);
5188 rc = 0; /* devlog isn't critical for device operation */
5189 }
5190
5191 return (rc);
5192 }
5193
5194 /*
5195 * Any params that need to be set before FW_INITIALIZE.
5196 */
5197 static int
set_params__pre_init(struct adapter * sc)5198 set_params__pre_init(struct adapter *sc)
5199 {
5200 int rc = 0;
5201 uint32_t param, val;
5202
5203 if (chip_id(sc) >= CHELSIO_T6) {
5204 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
5205 val = 1;
5206 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5207 /* firmwares < 1.20.1.0 do not have this param. */
5208 if (rc == FW_EINVAL &&
5209 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
5210 rc = 0;
5211 }
5212 if (rc != 0) {
5213 device_printf(sc->dev,
5214 "failed to enable high priority filters :%d.\n",
5215 rc);
5216 }
5217
5218 param = FW_PARAM_DEV(PPOD_EDRAM);
5219 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5220 if (rc == 0 && val == 1) {
5221 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m,
5222 &val);
5223 if (rc != 0) {
5224 device_printf(sc->dev,
5225 "failed to set PPOD_EDRAM: %d.\n", rc);
5226 }
5227 }
5228 }
5229
5230 /* Enable opaque VIIDs with firmwares that support it. */
5231 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
5232 val = 1;
5233 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5234 if (rc == 0 && val == 1)
5235 sc->params.viid_smt_extn_support = true;
5236 else
5237 sc->params.viid_smt_extn_support = false;
5238
5239 return (rc);
5240 }
5241
5242 /*
5243 * Retrieve various parameters that are of interest to the driver. The device
5244 * has been initialized by the firmware at this point.
5245 */
5246 static int
get_params__post_init(struct adapter * sc)5247 get_params__post_init(struct adapter *sc)
5248 {
5249 int rc;
5250 uint32_t param[7], val[7];
5251 struct fw_caps_config_cmd caps;
5252
5253 param[0] = FW_PARAM_PFVF(IQFLINT_START);
5254 param[1] = FW_PARAM_PFVF(EQ_START);
5255 param[2] = FW_PARAM_PFVF(FILTER_START);
5256 param[3] = FW_PARAM_PFVF(FILTER_END);
5257 param[4] = FW_PARAM_PFVF(L2T_START);
5258 param[5] = FW_PARAM_PFVF(L2T_END);
5259 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5260 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5261 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
5262 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
5263 if (rc != 0) {
5264 device_printf(sc->dev,
5265 "failed to query parameters (post_init): %d.\n", rc);
5266 return (rc);
5267 }
5268
5269 sc->sge.iq_start = val[0];
5270 sc->sge.eq_start = val[1];
5271 if ((int)val[3] > (int)val[2]) {
5272 sc->tids.ftid_base = val[2];
5273 sc->tids.ftid_end = val[3];
5274 sc->tids.nftids = val[3] - val[2] + 1;
5275 }
5276 sc->vres.l2t.start = val[4];
5277 sc->vres.l2t.size = val[5] - val[4] + 1;
5278 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
5279 ("%s: L2 table size (%u) larger than expected (%u)",
5280 __func__, sc->vres.l2t.size, L2T_SIZE));
5281 sc->params.core_vdd = val[6];
5282
5283 param[0] = FW_PARAM_PFVF(IQFLINT_END);
5284 param[1] = FW_PARAM_PFVF(EQ_END);
5285 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5286 if (rc != 0) {
5287 device_printf(sc->dev,
5288 "failed to query parameters (post_init2): %d.\n", rc);
5289 return (rc);
5290 }
5291 MPASS((int)val[0] >= sc->sge.iq_start);
5292 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1;
5293 MPASS((int)val[1] >= sc->sge.eq_start);
5294 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1;
5295
5296 if (chip_id(sc) >= CHELSIO_T6) {
5297
5298 sc->tids.tid_base = t4_read_reg(sc,
5299 A_LE_DB_ACTIVE_TABLE_START_INDEX);
5300
5301 param[0] = FW_PARAM_PFVF(HPFILTER_START);
5302 param[1] = FW_PARAM_PFVF(HPFILTER_END);
5303 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5304 if (rc != 0) {
5305 device_printf(sc->dev,
5306 "failed to query hpfilter parameters: %d.\n", rc);
5307 return (rc);
5308 }
5309 if ((int)val[1] > (int)val[0]) {
5310 sc->tids.hpftid_base = val[0];
5311 sc->tids.hpftid_end = val[1];
5312 sc->tids.nhpftids = val[1] - val[0] + 1;
5313
5314 /*
5315 * These should go off if the layout changes and the
5316 * driver needs to catch up.
5317 */
5318 MPASS(sc->tids.hpftid_base == 0);
5319 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
5320 }
5321
5322 param[0] = FW_PARAM_PFVF(RAWF_START);
5323 param[1] = FW_PARAM_PFVF(RAWF_END);
5324 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5325 if (rc != 0) {
5326 device_printf(sc->dev,
5327 "failed to query rawf parameters: %d.\n", rc);
5328 return (rc);
5329 }
5330 if ((int)val[1] > (int)val[0]) {
5331 sc->rawf_base = val[0];
5332 sc->nrawf = val[1] - val[0] + 1;
5333 }
5334 }
5335
5336 /*
5337 * The parameters that follow may not be available on all firmwares. We
5338 * query them individually rather than in a compound query because old
5339 * firmwares fail the entire query if an unknown parameter is queried.
5340 */
5341
5342 /*
5343 * MPS buffer group configuration.
5344 */
5345 param[0] = FW_PARAM_DEV(MPSBGMAP);
5346 val[0] = 0;
5347 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5348 if (rc == 0)
5349 sc->params.mps_bg_map = val[0];
5350 else
5351 sc->params.mps_bg_map = UINT32_MAX; /* Not a legal value. */
5352
5353 param[0] = FW_PARAM_DEV(TPCHMAP);
5354 val[0] = 0;
5355 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5356 if (rc == 0)
5357 sc->params.tp_ch_map = val[0];
5358 else
5359 sc->params.tp_ch_map = UINT32_MAX; /* Not a legal value. */
5360
5361 /*
5362 * Determine whether the firmware supports the filter2 work request.
5363 */
5364 param[0] = FW_PARAM_DEV(FILTER2_WR);
5365 val[0] = 0;
5366 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5367 if (rc == 0)
5368 sc->params.filter2_wr_support = val[0] != 0;
5369 else
5370 sc->params.filter2_wr_support = 0;
5371
5372 /*
5373 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
5374 */
5375 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5376 val[0] = 0;
5377 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5378 if (rc == 0)
5379 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
5380 else
5381 sc->params.ulptx_memwrite_dsgl = false;
5382
5383 /* FW_RI_FR_NSMR_TPTE_WR support */
5384 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
5385 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5386 if (rc == 0)
5387 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
5388 else
5389 sc->params.fr_nsmr_tpte_wr_support = false;
5390
5391 /* Support for 512 SGL entries per FR MR. */
5392 param[0] = FW_PARAM_DEV(DEV_512SGL_MR);
5393 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5394 if (rc == 0)
5395 sc->params.dev_512sgl_mr = val[0] != 0;
5396 else
5397 sc->params.dev_512sgl_mr = false;
5398
5399 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
5400 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5401 if (rc == 0)
5402 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0];
5403 else
5404 sc->params.max_pkts_per_eth_tx_pkts_wr = 15;
5405
5406 param[0] = FW_PARAM_DEV(NUM_TM_CLASS);
5407 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5408 if (rc == 0) {
5409 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */
5410 sc->params.nsched_cls = val[0];
5411 } else
5412 sc->params.nsched_cls = sc->chip_params->nsched_cls;
5413
5414 /* get capabilites */
5415 bzero(&caps, sizeof(caps));
5416 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5417 F_FW_CMD_REQUEST | F_FW_CMD_READ);
5418 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5419 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5420 if (rc != 0) {
5421 device_printf(sc->dev,
5422 "failed to get card capabilities: %d.\n", rc);
5423 return (rc);
5424 }
5425
5426 #define READ_CAPS(x) do { \
5427 sc->x = htobe16(caps.x); \
5428 } while (0)
5429 READ_CAPS(nbmcaps);
5430 READ_CAPS(linkcaps);
5431 READ_CAPS(switchcaps);
5432 READ_CAPS(niccaps);
5433 READ_CAPS(toecaps);
5434 READ_CAPS(rdmacaps);
5435 READ_CAPS(cryptocaps);
5436 READ_CAPS(iscsicaps);
5437 READ_CAPS(fcoecaps);
5438
5439 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
5440 MPASS(chip_id(sc) > CHELSIO_T4);
5441 MPASS(sc->toecaps == 0);
5442 sc->toecaps = 0;
5443
5444 param[0] = FW_PARAM_DEV(NTID);
5445 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5446 if (rc != 0) {
5447 device_printf(sc->dev,
5448 "failed to query HASHFILTER parameters: %d.\n", rc);
5449 return (rc);
5450 }
5451 sc->tids.ntids = val[0];
5452 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5453 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5454 sc->tids.ntids -= sc->tids.nhpftids;
5455 }
5456 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5457 sc->params.hash_filter = 1;
5458 }
5459 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
5460 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
5461 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
5462 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5463 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
5464 if (rc != 0) {
5465 device_printf(sc->dev,
5466 "failed to query NIC parameters: %d.\n", rc);
5467 return (rc);
5468 }
5469 if ((int)val[1] > (int)val[0]) {
5470 sc->tids.etid_base = val[0];
5471 sc->tids.etid_end = val[1];
5472 sc->tids.netids = val[1] - val[0] + 1;
5473 sc->params.eo_wr_cred = val[2];
5474 sc->params.ethoffload = 1;
5475 }
5476 }
5477 if (sc->toecaps) {
5478 /* query offload-related parameters */
5479 param[0] = FW_PARAM_DEV(NTID);
5480 param[1] = FW_PARAM_PFVF(SERVER_START);
5481 param[2] = FW_PARAM_PFVF(SERVER_END);
5482 param[3] = FW_PARAM_PFVF(TDDP_START);
5483 param[4] = FW_PARAM_PFVF(TDDP_END);
5484 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5485 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5486 if (rc != 0) {
5487 device_printf(sc->dev,
5488 "failed to query TOE parameters: %d.\n", rc);
5489 return (rc);
5490 }
5491 sc->tids.ntids = val[0];
5492 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5493 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5494 sc->tids.ntids -= sc->tids.nhpftids;
5495 }
5496 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5497 if ((int)val[2] > (int)val[1]) {
5498 sc->tids.stid_base = val[1];
5499 sc->tids.nstids = val[2] - val[1] + 1;
5500 }
5501 sc->vres.ddp.start = val[3];
5502 sc->vres.ddp.size = val[4] - val[3] + 1;
5503 sc->params.ofldq_wr_cred = val[5];
5504 sc->params.offload = 1;
5505 } else {
5506 /*
5507 * The firmware attempts memfree TOE configuration for -SO cards
5508 * and will report toecaps=0 if it runs out of resources (this
5509 * depends on the config file). It may not report 0 for other
5510 * capabilities dependent on the TOE in this case. Set them to
5511 * 0 here so that the driver doesn't bother tracking resources
5512 * that will never be used.
5513 */
5514 sc->iscsicaps = 0;
5515 sc->rdmacaps = 0;
5516 }
5517 if (sc->rdmacaps) {
5518 param[0] = FW_PARAM_PFVF(STAG_START);
5519 param[1] = FW_PARAM_PFVF(STAG_END);
5520 param[2] = FW_PARAM_PFVF(RQ_START);
5521 param[3] = FW_PARAM_PFVF(RQ_END);
5522 param[4] = FW_PARAM_PFVF(PBL_START);
5523 param[5] = FW_PARAM_PFVF(PBL_END);
5524 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5525 if (rc != 0) {
5526 device_printf(sc->dev,
5527 "failed to query RDMA parameters(1): %d.\n", rc);
5528 return (rc);
5529 }
5530 sc->vres.stag.start = val[0];
5531 sc->vres.stag.size = val[1] - val[0] + 1;
5532 sc->vres.rq.start = val[2];
5533 sc->vres.rq.size = val[3] - val[2] + 1;
5534 sc->vres.pbl.start = val[4];
5535 sc->vres.pbl.size = val[5] - val[4] + 1;
5536
5537 param[0] = FW_PARAM_PFVF(SQRQ_START);
5538 param[1] = FW_PARAM_PFVF(SQRQ_END);
5539 param[2] = FW_PARAM_PFVF(CQ_START);
5540 param[3] = FW_PARAM_PFVF(CQ_END);
5541 param[4] = FW_PARAM_PFVF(OCQ_START);
5542 param[5] = FW_PARAM_PFVF(OCQ_END);
5543 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5544 if (rc != 0) {
5545 device_printf(sc->dev,
5546 "failed to query RDMA parameters(2): %d.\n", rc);
5547 return (rc);
5548 }
5549 sc->vres.qp.start = val[0];
5550 sc->vres.qp.size = val[1] - val[0] + 1;
5551 sc->vres.cq.start = val[2];
5552 sc->vres.cq.size = val[3] - val[2] + 1;
5553 sc->vres.ocq.start = val[4];
5554 sc->vres.ocq.size = val[5] - val[4] + 1;
5555
5556 param[0] = FW_PARAM_PFVF(SRQ_START);
5557 param[1] = FW_PARAM_PFVF(SRQ_END);
5558 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
5559 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5560 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
5561 if (rc != 0) {
5562 device_printf(sc->dev,
5563 "failed to query RDMA parameters(3): %d.\n", rc);
5564 return (rc);
5565 }
5566 sc->vres.srq.start = val[0];
5567 sc->vres.srq.size = val[1] - val[0] + 1;
5568 sc->params.max_ordird_qp = val[2];
5569 sc->params.max_ird_adapter = val[3];
5570 }
5571 if (sc->iscsicaps) {
5572 param[0] = FW_PARAM_PFVF(ISCSI_START);
5573 param[1] = FW_PARAM_PFVF(ISCSI_END);
5574 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5575 if (rc != 0) {
5576 device_printf(sc->dev,
5577 "failed to query iSCSI parameters: %d.\n", rc);
5578 return (rc);
5579 }
5580 sc->vres.iscsi.start = val[0];
5581 sc->vres.iscsi.size = val[1] - val[0] + 1;
5582 }
5583 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
5584 param[0] = FW_PARAM_PFVF(TLS_START);
5585 param[1] = FW_PARAM_PFVF(TLS_END);
5586 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5587 if (rc != 0) {
5588 device_printf(sc->dev,
5589 "failed to query TLS parameters: %d.\n", rc);
5590 return (rc);
5591 }
5592 sc->vres.key.start = val[0];
5593 sc->vres.key.size = val[1] - val[0] + 1;
5594 }
5595
5596 /*
5597 * We've got the params we wanted to query directly from the firmware.
5598 * Grab some others via other means.
5599 */
5600 t4_init_sge_params(sc);
5601 t4_init_tp_params(sc);
5602 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
5603 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
5604
5605 rc = t4_verify_chip_settings(sc);
5606 if (rc != 0)
5607 return (rc);
5608 t4_init_rx_buf_info(sc);
5609
5610 return (rc);
5611 }
5612
5613 #ifdef KERN_TLS
5614 static void
ktls_tick(void * arg)5615 ktls_tick(void *arg)
5616 {
5617 struct adapter *sc;
5618 uint32_t tstamp;
5619
5620 sc = arg;
5621 tstamp = tcp_ts_getticks();
5622 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
5623 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
5624 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
5625 }
5626
5627 static int
t6_config_kern_tls(struct adapter * sc,bool enable)5628 t6_config_kern_tls(struct adapter *sc, bool enable)
5629 {
5630 int rc;
5631 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5632 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) |
5633 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) |
5634 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE);
5635
5636 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m);
5637 if (rc != 0) {
5638 CH_ERR(sc, "failed to %s NIC TLS: %d\n",
5639 enable ? "enable" : "disable", rc);
5640 return (rc);
5641 }
5642
5643 if (enable) {
5644 sc->flags |= KERN_TLS_ON;
5645 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
5646 C_HARDCLOCK);
5647 } else {
5648 sc->flags &= ~KERN_TLS_ON;
5649 callout_stop(&sc->ktls_tick);
5650 }
5651
5652 return (rc);
5653 }
5654 #endif
5655
5656 static int
set_params__post_init(struct adapter * sc)5657 set_params__post_init(struct adapter *sc)
5658 {
5659 uint32_t mask, param, val;
5660 #ifdef TCP_OFFLOAD
5661 int i, v, shift;
5662 #endif
5663
5664 /* ask for encapsulated CPLs */
5665 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5666 val = 1;
5667 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5668
5669 /* Enable 32b port caps if the firmware supports it. */
5670 param = FW_PARAM_PFVF(PORT_CAPS32);
5671 val = 1;
5672 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
5673 sc->params.port_caps32 = 1;
5674
5675 /* Let filter + maskhash steer to a part of the VI's RSS region. */
5676 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
5677 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
5678 V_MASKFILTER(val - 1));
5679
5680 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER |
5681 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN |
5682 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
5683 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM;
5684 val = 0;
5685 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) {
5686 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE,
5687 F_ATTACKFILTERENABLE);
5688 val |= F_DROPERRORATTACK;
5689 }
5690 if (t4_drop_ip_fragments != 0) {
5691 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP,
5692 F_FRAGMENTDROP);
5693 val |= F_DROPERRORFRAG;
5694 }
5695 if (t4_drop_pkts_with_l2_errors != 0)
5696 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN;
5697 if (t4_drop_pkts_with_l3_errors != 0) {
5698 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN |
5699 F_DROPERRORCSUMIP;
5700 }
5701 if (t4_drop_pkts_with_l4_errors != 0) {
5702 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
5703 F_DROPERRORTCPOPT | F_DROPERRORCSUM;
5704 }
5705 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val);
5706
5707 #ifdef TCP_OFFLOAD
5708 /*
5709 * Override the TOE timers with user provided tunables. This is not the
5710 * recommended way to change the timers (the firmware config file is) so
5711 * these tunables are not documented.
5712 *
5713 * All the timer tunables are in microseconds.
5714 */
5715 if (t4_toe_keepalive_idle != 0) {
5716 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
5717 v &= M_KEEPALIVEIDLE;
5718 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
5719 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
5720 }
5721 if (t4_toe_keepalive_interval != 0) {
5722 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
5723 v &= M_KEEPALIVEINTVL;
5724 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
5725 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
5726 }
5727 if (t4_toe_keepalive_count != 0) {
5728 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
5729 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
5730 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
5731 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
5732 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
5733 }
5734 if (t4_toe_rexmt_min != 0) {
5735 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
5736 v &= M_RXTMIN;
5737 t4_set_reg_field(sc, A_TP_RXT_MIN,
5738 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
5739 }
5740 if (t4_toe_rexmt_max != 0) {
5741 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
5742 v &= M_RXTMAX;
5743 t4_set_reg_field(sc, A_TP_RXT_MAX,
5744 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
5745 }
5746 if (t4_toe_rexmt_count != 0) {
5747 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
5748 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
5749 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
5750 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
5751 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
5752 }
5753 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
5754 if (t4_toe_rexmt_backoff[i] != -1) {
5755 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
5756 shift = (i & 3) << 3;
5757 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
5758 M_TIMERBACKOFFINDEX0 << shift, v << shift);
5759 }
5760 }
5761 #endif
5762
5763 /*
5764 * Limit TOE connections to 2 reassembly "islands". This is
5765 * required to permit migrating TOE connections to either
5766 * ULP_MODE_TCPDDP or UPL_MODE_TLS.
5767 */
5768 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE),
5769 V_PASSMODE(2));
5770
5771 #ifdef KERN_TLS
5772 if (is_ktls(sc)) {
5773 sc->tlst.inline_keys = t4_tls_inline_keys;
5774 sc->tlst.combo_wrs = t4_tls_combo_wrs;
5775 if (t4_kern_tls != 0 && is_t6(sc))
5776 t6_config_kern_tls(sc, true);
5777 }
5778 #endif
5779 return (0);
5780 }
5781
5782 #undef FW_PARAM_PFVF
5783 #undef FW_PARAM_DEV
5784
5785 static void
t4_set_desc(struct adapter * sc)5786 t4_set_desc(struct adapter *sc)
5787 {
5788 struct adapter_params *p = &sc->params;
5789
5790 device_set_descf(sc->dev, "Chelsio %s", p->vpd.id);
5791 }
5792
5793 static inline void
ifmedia_add4(struct ifmedia * ifm,int m)5794 ifmedia_add4(struct ifmedia *ifm, int m)
5795 {
5796
5797 ifmedia_add(ifm, m, 0, NULL);
5798 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
5799 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
5800 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
5801 }
5802
5803 /*
5804 * This is the selected media, which is not quite the same as the active media.
5805 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
5806 * and active are not the same, and "media: Ethernet selected" otherwise.
5807 */
5808 static void
set_current_media(struct port_info * pi)5809 set_current_media(struct port_info *pi)
5810 {
5811 struct link_config *lc;
5812 struct ifmedia *ifm;
5813 int mword;
5814 u_int speed;
5815
5816 PORT_LOCK_ASSERT_OWNED(pi);
5817
5818 /* Leave current media alone if it's already set to IFM_NONE. */
5819 ifm = &pi->media;
5820 if (ifm->ifm_cur != NULL &&
5821 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
5822 return;
5823
5824 lc = &pi->link_cfg;
5825 if (lc->requested_aneg != AUTONEG_DISABLE &&
5826 lc->pcaps & FW_PORT_CAP32_ANEG) {
5827 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
5828 return;
5829 }
5830 mword = IFM_ETHER | IFM_FDX;
5831 if (lc->requested_fc & PAUSE_TX)
5832 mword |= IFM_ETH_TXPAUSE;
5833 if (lc->requested_fc & PAUSE_RX)
5834 mword |= IFM_ETH_RXPAUSE;
5835 if (lc->requested_speed == 0)
5836 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
5837 else
5838 speed = lc->requested_speed;
5839 mword |= port_mword(pi, speed_to_fwcap(speed));
5840 ifmedia_set(ifm, mword);
5841 }
5842
5843 /*
5844 * Returns true if the ifmedia list for the port cannot change.
5845 */
5846 static bool
fixed_ifmedia(struct port_info * pi)5847 fixed_ifmedia(struct port_info *pi)
5848 {
5849
5850 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
5851 pi->port_type == FW_PORT_TYPE_BT_XFI ||
5852 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
5853 pi->port_type == FW_PORT_TYPE_KX4 ||
5854 pi->port_type == FW_PORT_TYPE_KX ||
5855 pi->port_type == FW_PORT_TYPE_KR ||
5856 pi->port_type == FW_PORT_TYPE_BP_AP ||
5857 pi->port_type == FW_PORT_TYPE_BP4_AP ||
5858 pi->port_type == FW_PORT_TYPE_BP40_BA ||
5859 pi->port_type == FW_PORT_TYPE_KR4_100G ||
5860 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
5861 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
5862 }
5863
5864 static void
build_medialist(struct port_info * pi)5865 build_medialist(struct port_info *pi)
5866 {
5867 uint32_t ss, speed;
5868 int unknown, mword, bit;
5869 struct link_config *lc;
5870 struct ifmedia *ifm;
5871
5872 PORT_LOCK_ASSERT_OWNED(pi);
5873
5874 if (pi->flags & FIXED_IFMEDIA)
5875 return;
5876
5877 /*
5878 * Rebuild the ifmedia list.
5879 */
5880 ifm = &pi->media;
5881 ifmedia_removeall(ifm);
5882 lc = &pi->link_cfg;
5883 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
5884 if (__predict_false(ss == 0)) { /* not supposed to happen. */
5885 MPASS(ss != 0);
5886 no_media:
5887 MPASS(LIST_EMPTY(&ifm->ifm_list));
5888 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
5889 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
5890 return;
5891 }
5892
5893 unknown = 0;
5894 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
5895 speed = 1 << bit;
5896 MPASS(speed & M_FW_PORT_CAP32_SPEED);
5897 if (ss & speed) {
5898 mword = port_mword(pi, speed);
5899 if (mword == IFM_NONE) {
5900 goto no_media;
5901 } else if (mword == IFM_UNKNOWN)
5902 unknown++;
5903 else
5904 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
5905 }
5906 }
5907 if (unknown > 0) /* Add one unknown for all unknown media types. */
5908 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
5909 if (lc->pcaps & FW_PORT_CAP32_ANEG)
5910 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
5911
5912 set_current_media(pi);
5913 }
5914
5915 /*
5916 * Initialize the requested fields in the link config based on driver tunables.
5917 */
5918 static void
init_link_config(struct port_info * pi)5919 init_link_config(struct port_info *pi)
5920 {
5921 struct link_config *lc = &pi->link_cfg;
5922
5923 PORT_LOCK_ASSERT_OWNED(pi);
5924
5925 lc->requested_caps = 0;
5926 lc->requested_speed = 0;
5927
5928 if (t4_autoneg == 0)
5929 lc->requested_aneg = AUTONEG_DISABLE;
5930 else if (t4_autoneg == 1)
5931 lc->requested_aneg = AUTONEG_ENABLE;
5932 else
5933 lc->requested_aneg = AUTONEG_AUTO;
5934
5935 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
5936 PAUSE_AUTONEG);
5937
5938 if (t4_fec & FEC_AUTO)
5939 lc->requested_fec = FEC_AUTO;
5940 else if (t4_fec == 0)
5941 lc->requested_fec = FEC_NONE;
5942 else {
5943 /* -1 is handled by the FEC_AUTO block above and not here. */
5944 lc->requested_fec = t4_fec &
5945 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
5946 if (lc->requested_fec == 0)
5947 lc->requested_fec = FEC_AUTO;
5948 }
5949 if (t4_force_fec < 0)
5950 lc->force_fec = -1;
5951 else if (t4_force_fec > 0)
5952 lc->force_fec = 1;
5953 else
5954 lc->force_fec = 0;
5955 }
5956
5957 /*
5958 * Makes sure that all requested settings comply with what's supported by the
5959 * port. Returns the number of settings that were invalid and had to be fixed.
5960 */
5961 static int
fixup_link_config(struct port_info * pi)5962 fixup_link_config(struct port_info *pi)
5963 {
5964 int n = 0;
5965 struct link_config *lc = &pi->link_cfg;
5966 uint32_t fwspeed;
5967
5968 PORT_LOCK_ASSERT_OWNED(pi);
5969
5970 /* Speed (when not autonegotiating) */
5971 if (lc->requested_speed != 0) {
5972 fwspeed = speed_to_fwcap(lc->requested_speed);
5973 if ((fwspeed & lc->pcaps) == 0) {
5974 n++;
5975 lc->requested_speed = 0;
5976 }
5977 }
5978
5979 /* Link autonegotiation */
5980 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
5981 lc->requested_aneg == AUTONEG_DISABLE ||
5982 lc->requested_aneg == AUTONEG_AUTO);
5983 if (lc->requested_aneg == AUTONEG_ENABLE &&
5984 !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
5985 n++;
5986 lc->requested_aneg = AUTONEG_AUTO;
5987 }
5988
5989 /* Flow control */
5990 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
5991 if (lc->requested_fc & PAUSE_TX &&
5992 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
5993 n++;
5994 lc->requested_fc &= ~PAUSE_TX;
5995 }
5996 if (lc->requested_fc & PAUSE_RX &&
5997 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
5998 n++;
5999 lc->requested_fc &= ~PAUSE_RX;
6000 }
6001 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
6002 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
6003 n++;
6004 lc->requested_fc |= PAUSE_AUTONEG;
6005 }
6006
6007 /* FEC */
6008 if ((lc->requested_fec & FEC_RS &&
6009 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
6010 (lc->requested_fec & FEC_BASER_RS &&
6011 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
6012 n++;
6013 lc->requested_fec = FEC_AUTO;
6014 }
6015
6016 return (n);
6017 }
6018
6019 /*
6020 * Apply the requested L1 settings, which are expected to be valid, to the
6021 * hardware.
6022 */
6023 static int
apply_link_config(struct port_info * pi)6024 apply_link_config(struct port_info *pi)
6025 {
6026 struct adapter *sc = pi->adapter;
6027 struct link_config *lc = &pi->link_cfg;
6028 int rc;
6029
6030 #ifdef INVARIANTS
6031 ASSERT_SYNCHRONIZED_OP(sc);
6032 PORT_LOCK_ASSERT_OWNED(pi);
6033
6034 if (lc->requested_aneg == AUTONEG_ENABLE)
6035 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
6036 if (!(lc->requested_fc & PAUSE_AUTONEG))
6037 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
6038 if (lc->requested_fc & PAUSE_TX)
6039 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
6040 if (lc->requested_fc & PAUSE_RX)
6041 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
6042 if (lc->requested_fec & FEC_RS)
6043 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
6044 if (lc->requested_fec & FEC_BASER_RS)
6045 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
6046 #endif
6047 if (!(sc->flags & IS_VF)) {
6048 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6049 if (rc != 0) {
6050 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
6051 return (rc);
6052 }
6053 }
6054
6055 /*
6056 * An L1_CFG will almost always result in a link-change event if the
6057 * link is up, and the driver will refresh the actual fec/fc/etc. when
6058 * the notification is processed. If the link is down then the actual
6059 * settings are meaningless.
6060 *
6061 * This takes care of the case where a change in the L1 settings may not
6062 * result in a notification.
6063 */
6064 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
6065 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
6066
6067 return (0);
6068 }
6069
6070 #define FW_MAC_EXACT_CHUNK 7
6071 struct mcaddr_ctx {
6072 if_t ifp;
6073 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
6074 uint64_t hash;
6075 int i;
6076 int del;
6077 int rc;
6078 };
6079
6080 static u_int
add_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)6081 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
6082 {
6083 struct mcaddr_ctx *ctx = arg;
6084 struct vi_info *vi = if_getsoftc(ctx->ifp);
6085 struct port_info *pi = vi->pi;
6086 struct adapter *sc = pi->adapter;
6087
6088 if (ctx->rc < 0)
6089 return (0);
6090
6091 ctx->mcaddr[ctx->i] = LLADDR(sdl);
6092 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
6093 ctx->i++;
6094
6095 if (ctx->i == FW_MAC_EXACT_CHUNK) {
6096 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
6097 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
6098 if (ctx->rc < 0) {
6099 int j;
6100
6101 for (j = 0; j < ctx->i; j++) {
6102 if_printf(ctx->ifp,
6103 "failed to add mc address"
6104 " %02x:%02x:%02x:"
6105 "%02x:%02x:%02x rc=%d\n",
6106 ctx->mcaddr[j][0], ctx->mcaddr[j][1],
6107 ctx->mcaddr[j][2], ctx->mcaddr[j][3],
6108 ctx->mcaddr[j][4], ctx->mcaddr[j][5],
6109 -ctx->rc);
6110 }
6111 return (0);
6112 }
6113 ctx->del = 0;
6114 ctx->i = 0;
6115 }
6116
6117 return (1);
6118 }
6119
6120 /*
6121 * Program the port's XGMAC based on parameters in ifnet. The caller also
6122 * indicates which parameters should be programmed (the rest are left alone).
6123 */
6124 int
update_mac_settings(if_t ifp,int flags)6125 update_mac_settings(if_t ifp, int flags)
6126 {
6127 int rc = 0;
6128 struct vi_info *vi = if_getsoftc(ifp);
6129 struct port_info *pi = vi->pi;
6130 struct adapter *sc = pi->adapter;
6131 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
6132 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
6133
6134 ASSERT_SYNCHRONIZED_OP(sc);
6135 KASSERT(flags, ("%s: not told what to update.", __func__));
6136
6137 if (flags & XGMAC_MTU)
6138 mtu = if_getmtu(ifp);
6139
6140 if (flags & XGMAC_PROMISC)
6141 promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0;
6142
6143 if (flags & XGMAC_ALLMULTI)
6144 allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0;
6145
6146 if (flags & XGMAC_VLANEX)
6147 vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0;
6148
6149 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
6150 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
6151 allmulti, 1, vlanex, false);
6152 if (rc) {
6153 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
6154 rc);
6155 return (rc);
6156 }
6157 }
6158
6159 if (flags & XGMAC_UCADDR) {
6160 uint8_t ucaddr[ETHER_ADDR_LEN];
6161
6162 bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr));
6163 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
6164 ucaddr, true, &vi->smt_idx);
6165 if (rc < 0) {
6166 rc = -rc;
6167 if_printf(ifp, "change_mac failed: %d\n", rc);
6168 return (rc);
6169 } else {
6170 vi->xact_addr_filt = rc;
6171 rc = 0;
6172 }
6173 }
6174
6175 if (flags & XGMAC_MCADDRS) {
6176 struct epoch_tracker et;
6177 struct mcaddr_ctx ctx;
6178 int j;
6179
6180 ctx.ifp = ifp;
6181 ctx.hash = 0;
6182 ctx.i = 0;
6183 ctx.del = 1;
6184 ctx.rc = 0;
6185 /*
6186 * Unlike other drivers, we accumulate list of pointers into
6187 * interface address lists and we need to keep it safe even
6188 * after if_foreach_llmaddr() returns, thus we must enter the
6189 * network epoch.
6190 */
6191 NET_EPOCH_ENTER(et);
6192 if_foreach_llmaddr(ifp, add_maddr, &ctx);
6193 if (ctx.rc < 0) {
6194 NET_EPOCH_EXIT(et);
6195 rc = -ctx.rc;
6196 return (rc);
6197 }
6198 if (ctx.i > 0) {
6199 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
6200 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
6201 NET_EPOCH_EXIT(et);
6202 if (rc < 0) {
6203 rc = -rc;
6204 for (j = 0; j < ctx.i; j++) {
6205 if_printf(ifp,
6206 "failed to add mcast address"
6207 " %02x:%02x:%02x:"
6208 "%02x:%02x:%02x rc=%d\n",
6209 ctx.mcaddr[j][0], ctx.mcaddr[j][1],
6210 ctx.mcaddr[j][2], ctx.mcaddr[j][3],
6211 ctx.mcaddr[j][4], ctx.mcaddr[j][5],
6212 rc);
6213 }
6214 return (rc);
6215 }
6216 ctx.del = 0;
6217 } else
6218 NET_EPOCH_EXIT(et);
6219
6220 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
6221 if (rc != 0)
6222 if_printf(ifp, "failed to set mcast address hash: %d\n",
6223 rc);
6224 if (ctx.del == 0) {
6225 /* We clobbered the VXLAN entry if there was one. */
6226 pi->vxlan_tcam_entry = false;
6227 }
6228 }
6229
6230 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 &&
6231 pi->vxlan_tcam_entry == false) {
6232 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac,
6233 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
6234 true);
6235 if (rc < 0) {
6236 rc = -rc;
6237 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n",
6238 rc);
6239 } else {
6240 MPASS(rc == sc->rawf_base + pi->port_id);
6241 rc = 0;
6242 pi->vxlan_tcam_entry = true;
6243 }
6244 }
6245
6246 return (rc);
6247 }
6248
6249 /*
6250 * {begin|end}_synchronized_op must be called from the same thread.
6251 */
6252 int
begin_synchronized_op(struct adapter * sc,struct vi_info * vi,int flags,char * wmesg)6253 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
6254 char *wmesg)
6255 {
6256 int rc, pri;
6257
6258 #ifdef WITNESS
6259 /* the caller thinks it's ok to sleep, but is it really? */
6260 if (flags & SLEEP_OK)
6261 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
6262 "begin_synchronized_op");
6263 #endif
6264
6265 if (INTR_OK)
6266 pri = PCATCH;
6267 else
6268 pri = 0;
6269
6270 ADAPTER_LOCK(sc);
6271 for (;;) {
6272
6273 if (vi && IS_DETACHING(vi)) {
6274 rc = ENXIO;
6275 goto done;
6276 }
6277
6278 if (!IS_BUSY(sc)) {
6279 rc = 0;
6280 break;
6281 }
6282
6283 if (!(flags & SLEEP_OK)) {
6284 rc = EBUSY;
6285 goto done;
6286 }
6287
6288 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
6289 rc = EINTR;
6290 goto done;
6291 }
6292 }
6293
6294 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
6295 SET_BUSY(sc);
6296 #ifdef INVARIANTS
6297 sc->last_op = wmesg;
6298 sc->last_op_thr = curthread;
6299 sc->last_op_flags = flags;
6300 #endif
6301
6302 done:
6303 if (!(flags & HOLD_LOCK) || rc)
6304 ADAPTER_UNLOCK(sc);
6305
6306 return (rc);
6307 }
6308
6309 /*
6310 * Tell if_ioctl and if_init that the VI is going away. This is
6311 * special variant of begin_synchronized_op and must be paired with a
6312 * call to end_vi_detach.
6313 */
6314 void
begin_vi_detach(struct adapter * sc,struct vi_info * vi)6315 begin_vi_detach(struct adapter *sc, struct vi_info *vi)
6316 {
6317 ADAPTER_LOCK(sc);
6318 SET_DETACHING(vi);
6319 wakeup(&sc->flags);
6320 while (IS_BUSY(sc))
6321 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
6322 SET_BUSY(sc);
6323 #ifdef INVARIANTS
6324 sc->last_op = "t4detach";
6325 sc->last_op_thr = curthread;
6326 sc->last_op_flags = 0;
6327 #endif
6328 ADAPTER_UNLOCK(sc);
6329 }
6330
6331 void
end_vi_detach(struct adapter * sc,struct vi_info * vi)6332 end_vi_detach(struct adapter *sc, struct vi_info *vi)
6333 {
6334 ADAPTER_LOCK(sc);
6335 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6336 CLR_BUSY(sc);
6337 CLR_DETACHING(vi);
6338 wakeup(&sc->flags);
6339 ADAPTER_UNLOCK(sc);
6340 }
6341
6342 /*
6343 * {begin|end}_synchronized_op must be called from the same thread.
6344 */
6345 void
end_synchronized_op(struct adapter * sc,int flags)6346 end_synchronized_op(struct adapter *sc, int flags)
6347 {
6348
6349 if (flags & LOCK_HELD)
6350 ADAPTER_LOCK_ASSERT_OWNED(sc);
6351 else
6352 ADAPTER_LOCK(sc);
6353
6354 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6355 CLR_BUSY(sc);
6356 wakeup(&sc->flags);
6357 ADAPTER_UNLOCK(sc);
6358 }
6359
6360 static int
cxgbe_init_synchronized(struct vi_info * vi)6361 cxgbe_init_synchronized(struct vi_info *vi)
6362 {
6363 struct port_info *pi = vi->pi;
6364 struct adapter *sc = pi->adapter;
6365 if_t ifp = vi->ifp;
6366 int rc = 0, i;
6367 struct sge_txq *txq;
6368
6369 ASSERT_SYNCHRONIZED_OP(sc);
6370
6371 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6372 return (0); /* already running */
6373
6374 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0))
6375 return (rc); /* error message displayed already */
6376
6377 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
6378 return (rc); /* error message displayed already */
6379
6380 rc = update_mac_settings(ifp, XGMAC_ALL);
6381 if (rc)
6382 goto done; /* error message displayed already */
6383
6384 PORT_LOCK(pi);
6385 if (pi->up_vis == 0) {
6386 t4_update_port_info(pi);
6387 fixup_link_config(pi);
6388 build_medialist(pi);
6389 apply_link_config(pi);
6390 }
6391
6392 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
6393 if (rc != 0) {
6394 if_printf(ifp, "enable_vi failed: %d\n", rc);
6395 PORT_UNLOCK(pi);
6396 goto done;
6397 }
6398
6399 /*
6400 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
6401 * if this changes.
6402 */
6403
6404 for_each_txq(vi, i, txq) {
6405 TXQ_LOCK(txq);
6406 txq->eq.flags |= EQ_ENABLED;
6407 TXQ_UNLOCK(txq);
6408 }
6409
6410 /*
6411 * The first iq of the first port to come up is used for tracing.
6412 */
6413 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
6414 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
6415 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
6416 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
6417 V_QUEUENUMBER(sc->traceq));
6418 pi->flags |= HAS_TRACEQ;
6419 }
6420
6421 /* all ok */
6422 pi->up_vis++;
6423 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
6424 if (pi->link_cfg.link_ok)
6425 t4_os_link_changed(pi);
6426 PORT_UNLOCK(pi);
6427
6428 mtx_lock(&vi->tick_mtx);
6429 if (vi->pi->nvi > 1 || sc->flags & IS_VF)
6430 callout_reset(&vi->tick, hz, vi_tick, vi);
6431 else
6432 callout_reset(&vi->tick, hz, cxgbe_tick, vi);
6433 mtx_unlock(&vi->tick_mtx);
6434 done:
6435 if (rc != 0)
6436 cxgbe_uninit_synchronized(vi);
6437
6438 return (rc);
6439 }
6440
6441 /*
6442 * Idempotent.
6443 */
6444 static int
cxgbe_uninit_synchronized(struct vi_info * vi)6445 cxgbe_uninit_synchronized(struct vi_info *vi)
6446 {
6447 struct port_info *pi = vi->pi;
6448 struct adapter *sc = pi->adapter;
6449 if_t ifp = vi->ifp;
6450 int rc, i;
6451 struct sge_txq *txq;
6452
6453 ASSERT_SYNCHRONIZED_OP(sc);
6454
6455 if (!(vi->flags & VI_INIT_DONE)) {
6456 if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6457 KASSERT(0, ("uninited VI is running"));
6458 if_printf(ifp, "uninited VI with running ifnet. "
6459 "vi->flags 0x%016lx, if_flags 0x%08x, "
6460 "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp),
6461 if_getdrvflags(ifp));
6462 }
6463 return (0);
6464 }
6465
6466 /*
6467 * Disable the VI so that all its data in either direction is discarded
6468 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
6469 * tick) intact as the TP can deliver negative advice or data that it's
6470 * holding in its RAM (for an offloaded connection) even after the VI is
6471 * disabled.
6472 */
6473 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
6474 if (rc) {
6475 if_printf(ifp, "disable_vi failed: %d\n", rc);
6476 return (rc);
6477 }
6478
6479 for_each_txq(vi, i, txq) {
6480 TXQ_LOCK(txq);
6481 txq->eq.flags &= ~EQ_ENABLED;
6482 TXQ_UNLOCK(txq);
6483 }
6484
6485 mtx_lock(&vi->tick_mtx);
6486 callout_stop(&vi->tick);
6487 mtx_unlock(&vi->tick_mtx);
6488
6489 PORT_LOCK(pi);
6490 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6491 PORT_UNLOCK(pi);
6492 return (0);
6493 }
6494 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
6495 pi->up_vis--;
6496 if (pi->up_vis > 0) {
6497 PORT_UNLOCK(pi);
6498 return (0);
6499 }
6500
6501 pi->link_cfg.link_ok = false;
6502 pi->link_cfg.speed = 0;
6503 pi->link_cfg.link_down_rc = 255;
6504 t4_os_link_changed(pi);
6505 PORT_UNLOCK(pi);
6506
6507 return (0);
6508 }
6509
6510 /*
6511 * It is ok for this function to fail midway and return right away. t4_detach
6512 * will walk the entire sc->irq list and clean up whatever is valid.
6513 */
6514 int
t4_setup_intr_handlers(struct adapter * sc)6515 t4_setup_intr_handlers(struct adapter *sc)
6516 {
6517 int rc, rid, p, q, v;
6518 char s[8];
6519 struct irq *irq;
6520 struct port_info *pi;
6521 struct vi_info *vi;
6522 struct sge *sge = &sc->sge;
6523 struct sge_rxq *rxq;
6524 #ifdef TCP_OFFLOAD
6525 struct sge_ofld_rxq *ofld_rxq;
6526 #endif
6527 #ifdef DEV_NETMAP
6528 struct sge_nm_rxq *nm_rxq;
6529 #endif
6530 #ifdef RSS
6531 int nbuckets = rss_getnumbuckets();
6532 #endif
6533
6534 /*
6535 * Setup interrupts.
6536 */
6537 irq = &sc->irq[0];
6538 rid = sc->intr_type == INTR_INTX ? 0 : 1;
6539 if (forwarding_intr_to_fwq(sc))
6540 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
6541
6542 /* Multiple interrupts. */
6543 if (sc->flags & IS_VF)
6544 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
6545 ("%s: too few intr.", __func__));
6546 else
6547 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
6548 ("%s: too few intr.", __func__));
6549
6550 /* The first one is always error intr on PFs */
6551 if (!(sc->flags & IS_VF)) {
6552 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
6553 if (rc != 0)
6554 return (rc);
6555 irq++;
6556 rid++;
6557 }
6558
6559 /* The second one is always the firmware event queue (first on VFs) */
6560 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
6561 if (rc != 0)
6562 return (rc);
6563 irq++;
6564 rid++;
6565
6566 for_each_port(sc, p) {
6567 pi = sc->port[p];
6568 for_each_vi(pi, v, vi) {
6569 vi->first_intr = rid - 1;
6570
6571 if (vi->nnmrxq > 0) {
6572 int n = max(vi->nrxq, vi->nnmrxq);
6573
6574 rxq = &sge->rxq[vi->first_rxq];
6575 #ifdef DEV_NETMAP
6576 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
6577 #endif
6578 for (q = 0; q < n; q++) {
6579 snprintf(s, sizeof(s), "%x%c%x", p,
6580 'a' + v, q);
6581 if (q < vi->nrxq)
6582 irq->rxq = rxq++;
6583 #ifdef DEV_NETMAP
6584 if (q < vi->nnmrxq)
6585 irq->nm_rxq = nm_rxq++;
6586
6587 if (irq->nm_rxq != NULL &&
6588 irq->rxq == NULL) {
6589 /* Netmap rx only */
6590 rc = t4_alloc_irq(sc, irq, rid,
6591 t4_nm_intr, irq->nm_rxq, s);
6592 }
6593 if (irq->nm_rxq != NULL &&
6594 irq->rxq != NULL) {
6595 /* NIC and Netmap rx */
6596 rc = t4_alloc_irq(sc, irq, rid,
6597 t4_vi_intr, irq, s);
6598 }
6599 #endif
6600 if (irq->rxq != NULL &&
6601 irq->nm_rxq == NULL) {
6602 /* NIC rx only */
6603 rc = t4_alloc_irq(sc, irq, rid,
6604 t4_intr, irq->rxq, s);
6605 }
6606 if (rc != 0)
6607 return (rc);
6608 #ifdef RSS
6609 if (q < vi->nrxq) {
6610 bus_bind_intr(sc->dev, irq->res,
6611 rss_getcpu(q % nbuckets));
6612 }
6613 #endif
6614 irq++;
6615 rid++;
6616 vi->nintr++;
6617 }
6618 } else {
6619 for_each_rxq(vi, q, rxq) {
6620 snprintf(s, sizeof(s), "%x%c%x", p,
6621 'a' + v, q);
6622 rc = t4_alloc_irq(sc, irq, rid,
6623 t4_intr, rxq, s);
6624 if (rc != 0)
6625 return (rc);
6626 #ifdef RSS
6627 bus_bind_intr(sc->dev, irq->res,
6628 rss_getcpu(q % nbuckets));
6629 #endif
6630 irq++;
6631 rid++;
6632 vi->nintr++;
6633 }
6634 }
6635 #ifdef TCP_OFFLOAD
6636 for_each_ofld_rxq(vi, q, ofld_rxq) {
6637 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
6638 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
6639 ofld_rxq, s);
6640 if (rc != 0)
6641 return (rc);
6642 irq++;
6643 rid++;
6644 vi->nintr++;
6645 }
6646 #endif
6647 }
6648 }
6649 MPASS(irq == &sc->irq[sc->intr_count]);
6650
6651 return (0);
6652 }
6653
6654 static void
write_global_rss_key(struct adapter * sc)6655 write_global_rss_key(struct adapter *sc)
6656 {
6657 #ifdef RSS
6658 int i;
6659 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
6660 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
6661
6662 CTASSERT(RSS_KEYSIZE == 40);
6663
6664 rss_getkey((void *)&raw_rss_key[0]);
6665 for (i = 0; i < nitems(rss_key); i++) {
6666 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
6667 }
6668 t4_write_rss_key(sc, &rss_key[0], -1, 1);
6669 #endif
6670 }
6671
6672 /*
6673 * Idempotent.
6674 */
6675 static int
adapter_full_init(struct adapter * sc)6676 adapter_full_init(struct adapter *sc)
6677 {
6678 int rc, i;
6679
6680 ASSERT_SYNCHRONIZED_OP(sc);
6681
6682 /*
6683 * queues that belong to the adapter (not any particular port).
6684 */
6685 rc = t4_setup_adapter_queues(sc);
6686 if (rc != 0)
6687 return (rc);
6688
6689 MPASS(sc->params.nports <= nitems(sc->tq));
6690 for (i = 0; i < sc->params.nports; i++) {
6691 if (sc->tq[i] != NULL)
6692 continue;
6693 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
6694 taskqueue_thread_enqueue, &sc->tq[i]);
6695 if (sc->tq[i] == NULL) {
6696 CH_ERR(sc, "failed to allocate task queue %d\n", i);
6697 return (ENOMEM);
6698 }
6699 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
6700 device_get_nameunit(sc->dev), i);
6701 }
6702
6703 if (!(sc->flags & IS_VF)) {
6704 write_global_rss_key(sc);
6705 t4_intr_enable(sc);
6706 }
6707 return (0);
6708 }
6709
6710 int
adapter_init(struct adapter * sc)6711 adapter_init(struct adapter *sc)
6712 {
6713 int rc;
6714
6715 ASSERT_SYNCHRONIZED_OP(sc);
6716 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
6717 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
6718 ("%s: FULL_INIT_DONE already", __func__));
6719
6720 rc = adapter_full_init(sc);
6721 if (rc != 0)
6722 adapter_full_uninit(sc);
6723 else
6724 sc->flags |= FULL_INIT_DONE;
6725
6726 return (rc);
6727 }
6728
6729 /*
6730 * Idempotent.
6731 */
6732 static void
adapter_full_uninit(struct adapter * sc)6733 adapter_full_uninit(struct adapter *sc)
6734 {
6735 int i;
6736
6737 t4_teardown_adapter_queues(sc);
6738
6739 for (i = 0; i < nitems(sc->tq); i++) {
6740 if (sc->tq[i] == NULL)
6741 continue;
6742 taskqueue_free(sc->tq[i]);
6743 sc->tq[i] = NULL;
6744 }
6745
6746 sc->flags &= ~FULL_INIT_DONE;
6747 }
6748
6749 #ifdef RSS
6750 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
6751 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
6752 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
6753 RSS_HASHTYPE_RSS_UDP_IPV6)
6754
6755 /* Translates kernel hash types to hardware. */
6756 static int
hashconfig_to_hashen(int hashconfig)6757 hashconfig_to_hashen(int hashconfig)
6758 {
6759 int hashen = 0;
6760
6761 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
6762 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
6763 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
6764 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
6765 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
6766 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
6767 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
6768 }
6769 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
6770 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
6771 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
6772 }
6773 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
6774 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
6775 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
6776 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
6777
6778 return (hashen);
6779 }
6780
6781 /* Translates hardware hash types to kernel. */
6782 static int
hashen_to_hashconfig(int hashen)6783 hashen_to_hashconfig(int hashen)
6784 {
6785 int hashconfig = 0;
6786
6787 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
6788 /*
6789 * If UDP hashing was enabled it must have been enabled for
6790 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
6791 * enabling any 4-tuple hash is nonsense configuration.
6792 */
6793 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
6794 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
6795
6796 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6797 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
6798 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6799 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
6800 }
6801 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6802 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
6803 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6804 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
6805 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
6806 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
6807 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
6808 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
6809
6810 return (hashconfig);
6811 }
6812 #endif
6813
6814 /*
6815 * Idempotent.
6816 */
6817 static int
vi_full_init(struct vi_info * vi)6818 vi_full_init(struct vi_info *vi)
6819 {
6820 struct adapter *sc = vi->adapter;
6821 struct sge_rxq *rxq;
6822 int rc, i, j;
6823 #ifdef RSS
6824 int nbuckets = rss_getnumbuckets();
6825 int hashconfig = rss_gethashconfig();
6826 int extra;
6827 #endif
6828
6829 ASSERT_SYNCHRONIZED_OP(sc);
6830
6831 /*
6832 * Allocate tx/rx/fl queues for this VI.
6833 */
6834 rc = t4_setup_vi_queues(vi);
6835 if (rc != 0)
6836 return (rc);
6837
6838 /*
6839 * Setup RSS for this VI. Save a copy of the RSS table for later use.
6840 */
6841 if (vi->nrxq > vi->rss_size) {
6842 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); "
6843 "some queues will never receive traffic.\n", vi->nrxq,
6844 vi->rss_size);
6845 } else if (vi->rss_size % vi->nrxq) {
6846 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); "
6847 "expect uneven traffic distribution.\n", vi->nrxq,
6848 vi->rss_size);
6849 }
6850 #ifdef RSS
6851 if (vi->nrxq != nbuckets) {
6852 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);"
6853 "performance will be impacted.\n", vi->nrxq, nbuckets);
6854 }
6855 #endif
6856 if (vi->rss == NULL)
6857 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE,
6858 M_ZERO | M_WAITOK);
6859 for (i = 0; i < vi->rss_size;) {
6860 #ifdef RSS
6861 j = rss_get_indirection_to_bucket(i);
6862 j %= vi->nrxq;
6863 rxq = &sc->sge.rxq[vi->first_rxq + j];
6864 vi->rss[i++] = rxq->iq.abs_id;
6865 #else
6866 for_each_rxq(vi, j, rxq) {
6867 vi->rss[i++] = rxq->iq.abs_id;
6868 if (i == vi->rss_size)
6869 break;
6870 }
6871 #endif
6872 }
6873
6874 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
6875 vi->rss, vi->rss_size);
6876 if (rc != 0) {
6877 CH_ERR(vi, "rss_config failed: %d\n", rc);
6878 return (rc);
6879 }
6880
6881 #ifdef RSS
6882 vi->hashen = hashconfig_to_hashen(hashconfig);
6883
6884 /*
6885 * We may have had to enable some hashes even though the global config
6886 * wants them disabled. This is a potential problem that must be
6887 * reported to the user.
6888 */
6889 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
6890
6891 /*
6892 * If we consider only the supported hash types, then the enabled hashes
6893 * are a superset of the requested hashes. In other words, there cannot
6894 * be any supported hash that was requested but not enabled, but there
6895 * can be hashes that were not requested but had to be enabled.
6896 */
6897 extra &= SUPPORTED_RSS_HASHTYPES;
6898 MPASS((extra & hashconfig) == 0);
6899
6900 if (extra) {
6901 CH_ALERT(vi,
6902 "global RSS config (0x%x) cannot be accommodated.\n",
6903 hashconfig);
6904 }
6905 if (extra & RSS_HASHTYPE_RSS_IPV4)
6906 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n");
6907 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
6908 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n");
6909 if (extra & RSS_HASHTYPE_RSS_IPV6)
6910 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n");
6911 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
6912 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n");
6913 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
6914 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n");
6915 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
6916 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n");
6917 #else
6918 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
6919 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
6920 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
6921 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
6922 #endif
6923 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0],
6924 0, 0);
6925 if (rc != 0) {
6926 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc);
6927 return (rc);
6928 }
6929
6930 return (0);
6931 }
6932
6933 int
vi_init(struct vi_info * vi)6934 vi_init(struct vi_info *vi)
6935 {
6936 int rc;
6937
6938 ASSERT_SYNCHRONIZED_OP(vi->adapter);
6939 KASSERT((vi->flags & VI_INIT_DONE) == 0,
6940 ("%s: VI_INIT_DONE already", __func__));
6941
6942 rc = vi_full_init(vi);
6943 if (rc != 0)
6944 vi_full_uninit(vi);
6945 else
6946 vi->flags |= VI_INIT_DONE;
6947
6948 return (rc);
6949 }
6950
6951 /*
6952 * Idempotent.
6953 */
6954 static void
vi_full_uninit(struct vi_info * vi)6955 vi_full_uninit(struct vi_info *vi)
6956 {
6957
6958 if (vi->flags & VI_INIT_DONE) {
6959 quiesce_vi(vi);
6960 free(vi->rss, M_CXGBE);
6961 free(vi->nm_rss, M_CXGBE);
6962 }
6963
6964 t4_teardown_vi_queues(vi);
6965 vi->flags &= ~VI_INIT_DONE;
6966 }
6967
6968 static void
quiesce_txq(struct sge_txq * txq)6969 quiesce_txq(struct sge_txq *txq)
6970 {
6971 struct sge_eq *eq = &txq->eq;
6972 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6973
6974 MPASS(eq->flags & EQ_SW_ALLOCATED);
6975 MPASS(!(eq->flags & EQ_ENABLED));
6976
6977 /* Wait for the mp_ring to empty. */
6978 while (!mp_ring_is_idle(txq->r)) {
6979 mp_ring_check_drainage(txq->r, 4096);
6980 pause("rquiesce", 1);
6981 }
6982 MPASS(txq->txp.npkt == 0);
6983
6984 if (eq->flags & EQ_HW_ALLOCATED) {
6985 /*
6986 * Hardware is alive and working normally. Wait for it to
6987 * finish and then wait for the driver to catch up and reclaim
6988 * all descriptors.
6989 */
6990 while (spg->cidx != htobe16(eq->pidx))
6991 pause("equiesce", 1);
6992 while (eq->cidx != eq->pidx)
6993 pause("dquiesce", 1);
6994 } else {
6995 /*
6996 * Hardware is unavailable. Discard all pending tx and reclaim
6997 * descriptors directly.
6998 */
6999 TXQ_LOCK(txq);
7000 while (eq->cidx != eq->pidx) {
7001 struct mbuf *m, *nextpkt;
7002 struct tx_sdesc *txsd;
7003
7004 txsd = &txq->sdesc[eq->cidx];
7005 for (m = txsd->m; m != NULL; m = nextpkt) {
7006 nextpkt = m->m_nextpkt;
7007 m->m_nextpkt = NULL;
7008 m_freem(m);
7009 }
7010 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx);
7011 }
7012 spg->pidx = spg->cidx = htobe16(eq->cidx);
7013 TXQ_UNLOCK(txq);
7014 }
7015 }
7016
7017 static void
quiesce_wrq(struct sge_wrq * wrq)7018 quiesce_wrq(struct sge_wrq *wrq)
7019 {
7020
7021 /* XXXTX */
7022 }
7023
7024 static void
quiesce_iq_fl(struct adapter * sc,struct sge_iq * iq,struct sge_fl * fl)7025 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
7026 {
7027 /* Synchronize with the interrupt handler */
7028 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
7029 pause("iqfree", 1);
7030
7031 if (fl != NULL) {
7032 MPASS(iq->flags & IQ_HAS_FL);
7033
7034 mtx_lock(&sc->sfl_lock);
7035 FL_LOCK(fl);
7036 fl->flags |= FL_DOOMED;
7037 FL_UNLOCK(fl);
7038 callout_stop(&sc->sfl_callout);
7039 mtx_unlock(&sc->sfl_lock);
7040
7041 KASSERT((fl->flags & FL_STARVING) == 0,
7042 ("%s: still starving", __func__));
7043
7044 /* Release all buffers if hardware is no longer available. */
7045 if (!(iq->flags & IQ_HW_ALLOCATED))
7046 free_fl_buffers(sc, fl);
7047 }
7048 }
7049
7050 /*
7051 * Wait for all activity on all the queues of the VI to complete. It is assumed
7052 * that no new work is being enqueued by the hardware or the driver. That part
7053 * should be arranged before calling this function.
7054 */
7055 static void
quiesce_vi(struct vi_info * vi)7056 quiesce_vi(struct vi_info *vi)
7057 {
7058 int i;
7059 struct adapter *sc = vi->adapter;
7060 struct sge_rxq *rxq;
7061 struct sge_txq *txq;
7062 #ifdef TCP_OFFLOAD
7063 struct sge_ofld_rxq *ofld_rxq;
7064 #endif
7065 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7066 struct sge_ofld_txq *ofld_txq;
7067 #endif
7068
7069 if (!(vi->flags & VI_INIT_DONE))
7070 return;
7071
7072 for_each_txq(vi, i, txq) {
7073 quiesce_txq(txq);
7074 }
7075
7076 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7077 for_each_ofld_txq(vi, i, ofld_txq) {
7078 quiesce_wrq(&ofld_txq->wrq);
7079 }
7080 #endif
7081
7082 for_each_rxq(vi, i, rxq) {
7083 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl);
7084 }
7085
7086 #ifdef TCP_OFFLOAD
7087 for_each_ofld_rxq(vi, i, ofld_rxq) {
7088 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl);
7089 }
7090 #endif
7091 }
7092
7093 static int
t4_alloc_irq(struct adapter * sc,struct irq * irq,int rid,driver_intr_t * handler,void * arg,char * name)7094 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
7095 driver_intr_t *handler, void *arg, char *name)
7096 {
7097 int rc;
7098
7099 irq->rid = rid;
7100 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
7101 RF_SHAREABLE | RF_ACTIVE);
7102 if (irq->res == NULL) {
7103 device_printf(sc->dev,
7104 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
7105 return (ENOMEM);
7106 }
7107
7108 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
7109 NULL, handler, arg, &irq->tag);
7110 if (rc != 0) {
7111 device_printf(sc->dev,
7112 "failed to setup interrupt for rid %d, name %s: %d\n",
7113 rid, name, rc);
7114 } else if (name)
7115 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
7116
7117 return (rc);
7118 }
7119
7120 static int
t4_free_irq(struct adapter * sc,struct irq * irq)7121 t4_free_irq(struct adapter *sc, struct irq *irq)
7122 {
7123 if (irq->tag)
7124 bus_teardown_intr(sc->dev, irq->res, irq->tag);
7125 if (irq->res)
7126 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
7127
7128 bzero(irq, sizeof(*irq));
7129
7130 return (0);
7131 }
7132
7133 static void
get_regs(struct adapter * sc,struct t4_regdump * regs,uint8_t * buf)7134 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
7135 {
7136
7137 regs->version = chip_id(sc) | chip_rev(sc) << 10;
7138 t4_get_regs(sc, buf, regs->len);
7139 }
7140
7141 #define A_PL_INDIR_CMD 0x1f8
7142
7143 #define S_PL_AUTOINC 31
7144 #define M_PL_AUTOINC 0x1U
7145 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
7146 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
7147
7148 #define S_PL_VFID 20
7149 #define M_PL_VFID 0xffU
7150 #define V_PL_VFID(x) ((x) << S_PL_VFID)
7151 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
7152
7153 #define S_PL_ADDR 0
7154 #define M_PL_ADDR 0xfffffU
7155 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
7156 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
7157
7158 #define A_PL_INDIR_DATA 0x1fc
7159
7160 static uint64_t
read_vf_stat(struct adapter * sc,u_int vin,int reg)7161 read_vf_stat(struct adapter *sc, u_int vin, int reg)
7162 {
7163 u32 stats[2];
7164
7165 if (sc->flags & IS_VF) {
7166 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
7167 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
7168 } else {
7169 mtx_assert(&sc->reg_lock, MA_OWNED);
7170 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
7171 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
7172 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
7173 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
7174 }
7175 return (((uint64_t)stats[1]) << 32 | stats[0]);
7176 }
7177
7178 static void
t4_get_vi_stats(struct adapter * sc,u_int vin,struct fw_vi_stats_vf * stats)7179 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
7180 {
7181
7182 #define GET_STAT(name) \
7183 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
7184
7185 if (!(sc->flags & IS_VF))
7186 mtx_lock(&sc->reg_lock);
7187 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
7188 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
7189 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
7190 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
7191 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
7192 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
7193 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
7194 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
7195 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
7196 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
7197 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
7198 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
7199 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
7200 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
7201 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
7202 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
7203 if (!(sc->flags & IS_VF))
7204 mtx_unlock(&sc->reg_lock);
7205
7206 #undef GET_STAT
7207 }
7208
7209 static void
t4_clr_vi_stats(struct adapter * sc,u_int vin)7210 t4_clr_vi_stats(struct adapter *sc, u_int vin)
7211 {
7212 int reg;
7213
7214 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
7215 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
7216 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
7217 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
7218 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
7219 }
7220
7221 static void
vi_refresh_stats(struct vi_info * vi)7222 vi_refresh_stats(struct vi_info *vi)
7223 {
7224 struct timeval tv;
7225 const struct timeval interval = {0, 250000}; /* 250ms */
7226
7227 mtx_assert(&vi->tick_mtx, MA_OWNED);
7228
7229 if (vi->flags & VI_SKIP_STATS)
7230 return;
7231
7232 getmicrotime(&tv);
7233 timevalsub(&tv, &interval);
7234 if (timevalcmp(&tv, &vi->last_refreshed, <))
7235 return;
7236
7237 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats);
7238 getmicrotime(&vi->last_refreshed);
7239 }
7240
7241 static void
cxgbe_refresh_stats(struct vi_info * vi)7242 cxgbe_refresh_stats(struct vi_info *vi)
7243 {
7244 u_int i, v, tnl_cong_drops, chan_map;
7245 struct timeval tv;
7246 const struct timeval interval = {0, 250000}; /* 250ms */
7247 struct port_info *pi;
7248 struct adapter *sc;
7249
7250 mtx_assert(&vi->tick_mtx, MA_OWNED);
7251
7252 if (vi->flags & VI_SKIP_STATS)
7253 return;
7254
7255 getmicrotime(&tv);
7256 timevalsub(&tv, &interval);
7257 if (timevalcmp(&tv, &vi->last_refreshed, <))
7258 return;
7259
7260 pi = vi->pi;
7261 sc = vi->adapter;
7262 tnl_cong_drops = 0;
7263 t4_get_port_stats(sc, pi->port_id, &pi->stats);
7264 chan_map = pi->rx_e_chan_map;
7265 while (chan_map) {
7266 i = ffs(chan_map) - 1;
7267 mtx_lock(&sc->reg_lock);
7268 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
7269 A_TP_MIB_TNL_CNG_DROP_0 + i);
7270 mtx_unlock(&sc->reg_lock);
7271 tnl_cong_drops += v;
7272 chan_map &= ~(1 << i);
7273 }
7274 pi->tnl_cong_drops = tnl_cong_drops;
7275 getmicrotime(&vi->last_refreshed);
7276 }
7277
7278 static void
cxgbe_tick(void * arg)7279 cxgbe_tick(void *arg)
7280 {
7281 struct vi_info *vi = arg;
7282
7283 MPASS(IS_MAIN_VI(vi));
7284 mtx_assert(&vi->tick_mtx, MA_OWNED);
7285
7286 cxgbe_refresh_stats(vi);
7287 callout_schedule(&vi->tick, hz);
7288 }
7289
7290 static void
vi_tick(void * arg)7291 vi_tick(void *arg)
7292 {
7293 struct vi_info *vi = arg;
7294
7295 mtx_assert(&vi->tick_mtx, MA_OWNED);
7296
7297 vi_refresh_stats(vi);
7298 callout_schedule(&vi->tick, hz);
7299 }
7300
7301 /*
7302 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
7303 */
7304 static char *caps_decoder[] = {
7305 "\20\001IPMI\002NCSI", /* 0: NBM */
7306 "\20\001PPP\002QFC\003DCBX", /* 1: link */
7307 "\20\001INGRESS\002EGRESS", /* 2: switch */
7308 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
7309 "\006HASHFILTER\007ETHOFLD",
7310 "\20\001TOE", /* 4: TOE */
7311 "\20\001RDDP\002RDMAC", /* 5: RDMA */
7312 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
7313 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
7314 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
7315 "\007T10DIF"
7316 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
7317 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */
7318 "\004TLS_HW",
7319 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
7320 "\004PO_INITIATOR\005PO_TARGET",
7321 };
7322
7323 void
t4_sysctls(struct adapter * sc)7324 t4_sysctls(struct adapter *sc)
7325 {
7326 struct sysctl_ctx_list *ctx = &sc->ctx;
7327 struct sysctl_oid *oid;
7328 struct sysctl_oid_list *children, *c0;
7329 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
7330
7331 /*
7332 * dev.t4nex.X.
7333 */
7334 oid = device_get_sysctl_tree(sc->dev);
7335 c0 = children = SYSCTL_CHILDREN(oid);
7336
7337 sc->sc_do_rxcopy = 1;
7338 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
7339 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
7340
7341 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
7342 sc->params.nports, "# of ports");
7343
7344 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
7345 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells,
7346 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A",
7347 "available doorbells");
7348
7349 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
7350 sc->params.vpd.cclk, "core clock frequency (in KHz)");
7351
7352 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
7353 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7354 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val),
7355 sysctl_int_array, "A", "interrupt holdoff timer values (us)");
7356
7357 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
7358 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7359 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val),
7360 sysctl_int_array, "A", "interrupt holdoff packet counter values");
7361
7362 t4_sge_sysctls(sc, ctx, children);
7363
7364 sc->lro_timeout = 100;
7365 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
7366 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
7367
7368 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
7369 &sc->debug_flags, 0, "flags to enable runtime debugging");
7370
7371 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
7372 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
7373
7374 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
7375 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
7376
7377 if (sc->flags & IS_VF)
7378 return;
7379
7380 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
7381 NULL, chip_rev(sc), "chip hardware revision");
7382
7383 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
7384 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
7385
7386 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
7387 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
7388
7389 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
7390 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
7391
7392 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
7393 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
7394
7395 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
7396 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
7397
7398 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
7399 sc->er_version, 0, "expansion ROM version");
7400
7401 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
7402 sc->bs_version, 0, "bootstrap firmware version");
7403
7404 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
7405 NULL, sc->params.scfg_vers, "serial config version");
7406
7407 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
7408 NULL, sc->params.vpd_vers, "VPD version");
7409
7410 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
7411 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
7412
7413 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
7414 sc->cfcsum, "config file checksum");
7415
7416 #define SYSCTL_CAP(name, n, text) \
7417 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
7418 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \
7419 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \
7420 "available " text " capabilities")
7421
7422 SYSCTL_CAP(nbmcaps, 0, "NBM");
7423 SYSCTL_CAP(linkcaps, 1, "link");
7424 SYSCTL_CAP(switchcaps, 2, "switch");
7425 SYSCTL_CAP(niccaps, 3, "NIC");
7426 SYSCTL_CAP(toecaps, 4, "TCP offload");
7427 SYSCTL_CAP(rdmacaps, 5, "RDMA");
7428 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
7429 SYSCTL_CAP(cryptocaps, 7, "crypto");
7430 SYSCTL_CAP(fcoecaps, 8, "FCoE");
7431 #undef SYSCTL_CAP
7432
7433 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
7434 NULL, sc->tids.nftids, "number of filters");
7435
7436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
7437 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7438 sysctl_temperature, "I", "chip temperature (in Celsius)");
7439 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor",
7440 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7441 sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
7442
7443 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg",
7444 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7445 sysctl_loadavg, "A",
7446 "microprocessor load averages (debug firmwares only)");
7447
7448 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
7449 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd,
7450 "I", "core Vdd (in mV)");
7451
7452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
7453 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS,
7454 sysctl_cpus, "A", "local CPUs");
7455
7456 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
7457 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS,
7458 sysctl_cpus, "A", "preferred CPUs for interrupts");
7459
7460 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
7461 &sc->swintr, 0, "software triggered interrupts");
7462
7463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset",
7464 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I",
7465 "1 = reset adapter, 0 = zero reset counter");
7466
7467 /*
7468 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
7469 */
7470 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
7471 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL,
7472 "logs and miscellaneous information");
7473 children = SYSCTL_CHILDREN(oid);
7474
7475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
7476 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7477 sysctl_cctrl, "A", "congestion control");
7478
7479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
7480 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7481 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
7482
7483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
7484 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
7485 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
7486
7487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
7488 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
7489 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
7490
7491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
7492 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3,
7493 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
7494
7495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
7496 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4,
7497 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
7498
7499 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
7500 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5,
7501 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
7502
7503 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
7504 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7505 sysctl_cim_la, "A", "CIM logic analyzer");
7506
7507 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
7508 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7509 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
7510
7511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
7512 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7513 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
7514
7515 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
7516 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7517 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
7518
7519 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
7520 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7521 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
7522
7523 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
7524 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7525 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
7526
7527 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
7528 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7529 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
7530
7531 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
7532 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7533 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
7534
7535 if (chip_id(sc) > CHELSIO_T4) {
7536 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
7537 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7538 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
7539 "CIM OBQ 6 (SGE0-RX)");
7540
7541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
7542 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7543 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
7544 "CIM OBQ 7 (SGE1-RX)");
7545 }
7546
7547 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
7548 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7549 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
7550
7551 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
7552 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7553 sysctl_cim_qcfg, "A", "CIM queue configuration");
7554
7555 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
7556 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7557 sysctl_cpl_stats, "A", "CPL statistics");
7558
7559 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
7560 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7561 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
7562
7563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats",
7564 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7565 sysctl_tid_stats, "A", "tid stats");
7566
7567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
7568 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7569 sysctl_devlog, "A", "firmware's device log");
7570
7571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
7572 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7573 sysctl_fcoe_stats, "A", "FCoE statistics");
7574
7575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
7576 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7577 sysctl_hw_sched, "A", "hardware scheduler ");
7578
7579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
7580 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7581 sysctl_l2t, "A", "hardware L2 table");
7582
7583 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
7584 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7585 sysctl_smt, "A", "hardware source MAC table");
7586
7587 #ifdef INET6
7588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
7589 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7590 sysctl_clip, "A", "active CLIP table entries");
7591 #endif
7592
7593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
7594 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7595 sysctl_lb_stats, "A", "loopback statistics");
7596
7597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
7598 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7599 sysctl_meminfo, "A", "memory regions");
7600
7601 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
7602 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7603 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
7604 "A", "MPS TCAM entries");
7605
7606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
7607 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7608 sysctl_path_mtus, "A", "path MTUs");
7609
7610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
7611 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7612 sysctl_pm_stats, "A", "PM statistics");
7613
7614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
7615 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7616 sysctl_rdma_stats, "A", "RDMA statistics");
7617
7618 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
7619 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7620 sysctl_tcp_stats, "A", "TCP statistics");
7621
7622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
7623 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7624 sysctl_tids, "A", "TID information");
7625
7626 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
7627 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7628 sysctl_tp_err_stats, "A", "TP error statistics");
7629
7630 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats",
7631 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7632 sysctl_tnl_stats, "A", "TP tunnel statistics");
7633
7634 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
7635 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7636 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask");
7637
7638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
7639 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7640 sysctl_tp_la, "A", "TP logic analyzer");
7641
7642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
7643 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7644 sysctl_tx_rate, "A", "Tx rate");
7645
7646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
7647 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7648 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
7649
7650 if (chip_id(sc) >= CHELSIO_T5) {
7651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
7652 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7653 sysctl_wcwr_stats, "A", "write combined work requests");
7654 }
7655
7656 #ifdef KERN_TLS
7657 if (is_ktls(sc)) {
7658 /*
7659 * dev.t4nex.0.tls.
7660 */
7661 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls",
7662 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters");
7663 children = SYSCTL_CHILDREN(oid);
7664
7665 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
7666 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
7667 "keys in work requests (1) or attempt to store TLS keys "
7668 "in card memory.");
7669
7670 if (is_t6(sc))
7671 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
7672 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to "
7673 "combine TCB field updates with TLS record work "
7674 "requests.");
7675 }
7676 #endif
7677
7678 #ifdef TCP_OFFLOAD
7679 if (is_offload(sc)) {
7680 int i;
7681 char s[4];
7682
7683 /*
7684 * dev.t4nex.X.toe.
7685 */
7686 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe",
7687 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters");
7688 children = SYSCTL_CHILDREN(oid);
7689
7690 sc->tt.cong_algorithm = -1;
7691 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
7692 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
7693 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
7694 "3 = highspeed)");
7695
7696 sc->tt.sndbuf = -1;
7697 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
7698 &sc->tt.sndbuf, 0, "hardware send buffer");
7699
7700 sc->tt.ddp = 0;
7701 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
7702 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
7703 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
7704 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
7705
7706 sc->tt.rx_coalesce = -1;
7707 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
7708 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
7709
7710 sc->tt.tls = 0;
7711 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT |
7712 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I",
7713 "Inline TLS allowed");
7714
7715 sc->tt.tx_align = -1;
7716 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
7717 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
7718
7719 sc->tt.tx_zcopy = 0;
7720 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
7721 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
7722 "Enable zero-copy aio_write(2)");
7723
7724 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
7725 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7726 "cop_managed_offloading", CTLFLAG_RW,
7727 &sc->tt.cop_managed_offloading, 0,
7728 "COP (Connection Offload Policy) controls all TOE offload");
7729
7730 sc->tt.autorcvbuf_inc = 16 * 1024;
7731 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
7732 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
7733 "autorcvbuf increment");
7734
7735 sc->tt.update_hc_on_pmtu_change = 1;
7736 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7737 "update_hc_on_pmtu_change", CTLFLAG_RW,
7738 &sc->tt.update_hc_on_pmtu_change, 0,
7739 "Update hostcache entry if the PMTU changes");
7740
7741 sc->tt.iso = 1;
7742 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW,
7743 &sc->tt.iso, 0, "Enable iSCSI segmentation offload");
7744
7745 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
7746 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7747 sysctl_tp_tick, "A", "TP timer tick (us)");
7748
7749 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
7750 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
7751 sysctl_tp_tick, "A", "TCP timestamp tick (us)");
7752
7753 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
7754 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
7755 sysctl_tp_tick, "A", "DACK tick (us)");
7756
7757 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
7758 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7759 sysctl_tp_dack_timer, "IU", "DACK timer (us)");
7760
7761 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
7762 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7763 A_TP_RXT_MIN, sysctl_tp_timer, "LU",
7764 "Minimum retransmit interval (us)");
7765
7766 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
7767 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7768 A_TP_RXT_MAX, sysctl_tp_timer, "LU",
7769 "Maximum retransmit interval (us)");
7770
7771 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
7772 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7773 A_TP_PERS_MIN, sysctl_tp_timer, "LU",
7774 "Persist timer min (us)");
7775
7776 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
7777 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7778 A_TP_PERS_MAX, sysctl_tp_timer, "LU",
7779 "Persist timer max (us)");
7780
7781 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
7782 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7783 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU",
7784 "Keepalive idle timer (us)");
7785
7786 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
7787 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7788 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU",
7789 "Keepalive interval timer (us)");
7790
7791 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
7792 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7793 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)");
7794
7795 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
7796 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7797 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU",
7798 "FINWAIT2 timer (us)");
7799
7800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
7801 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7802 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU",
7803 "Number of SYN retransmissions before abort");
7804
7805 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
7806 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7807 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU",
7808 "Number of retransmissions before abort");
7809
7810 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
7811 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7812 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU",
7813 "Number of keepalive probes before abort");
7814
7815 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
7816 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
7817 "TOE retransmit backoffs");
7818 children = SYSCTL_CHILDREN(oid);
7819 for (i = 0; i < 16; i++) {
7820 snprintf(s, sizeof(s), "%u", i);
7821 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
7822 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7823 i, sysctl_tp_backoff, "IU",
7824 "TOE retransmit backoff");
7825 }
7826 }
7827 #endif
7828 }
7829
7830 void
vi_sysctls(struct vi_info * vi)7831 vi_sysctls(struct vi_info *vi)
7832 {
7833 struct sysctl_ctx_list *ctx = &vi->ctx;
7834 struct sysctl_oid *oid;
7835 struct sysctl_oid_list *children;
7836
7837 /*
7838 * dev.v?(cxgbe|cxl).X.
7839 */
7840 oid = device_get_sysctl_tree(vi->dev);
7841 children = SYSCTL_CHILDREN(oid);
7842
7843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
7844 vi->viid, "VI identifer");
7845 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
7846 &vi->nrxq, 0, "# of rx queues");
7847 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
7848 &vi->ntxq, 0, "# of tx queues");
7849 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
7850 &vi->first_rxq, 0, "index of first rx queue");
7851 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
7852 &vi->first_txq, 0, "index of first tx queue");
7853 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
7854 vi->rss_base, "start of RSS indirection table");
7855 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
7856 vi->rss_size, "size of RSS indirection table");
7857
7858 if (IS_MAIN_VI(vi)) {
7859 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
7860 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7861 sysctl_noflowq, "IU",
7862 "Reserve queue 0 for non-flowid packets");
7863 }
7864
7865 if (vi->adapter->flags & IS_VF) {
7866 MPASS(vi->flags & TX_USES_VM_WR);
7867 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD,
7868 NULL, 1, "use VM work requests for transmit");
7869 } else {
7870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr",
7871 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7872 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit");
7873 }
7874
7875 #ifdef TCP_OFFLOAD
7876 if (vi->nofldrxq != 0) {
7877 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
7878 &vi->nofldrxq, 0,
7879 "# of rx queues for offloaded TCP connections");
7880 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
7881 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
7882 "index of first TOE rx queue");
7883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
7884 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7885 sysctl_holdoff_tmr_idx_ofld, "I",
7886 "holdoff timer index for TOE queues");
7887 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
7888 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7889 sysctl_holdoff_pktc_idx_ofld, "I",
7890 "holdoff packet counter index for TOE queues");
7891 }
7892 #endif
7893 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7894 if (vi->nofldtxq != 0) {
7895 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
7896 &vi->nofldtxq, 0,
7897 "# of tx queues for TOE/ETHOFLD");
7898 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
7899 CTLFLAG_RD, &vi->first_ofld_txq, 0,
7900 "index of first TOE/ETHOFLD tx queue");
7901 }
7902 #endif
7903 #ifdef DEV_NETMAP
7904 if (vi->nnmrxq != 0) {
7905 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
7906 &vi->nnmrxq, 0, "# of netmap rx queues");
7907 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
7908 &vi->nnmtxq, 0, "# of netmap tx queues");
7909 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
7910 CTLFLAG_RD, &vi->first_nm_rxq, 0,
7911 "index of first netmap rx queue");
7912 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
7913 CTLFLAG_RD, &vi->first_nm_txq, 0,
7914 "index of first netmap tx queue");
7915 }
7916 #endif
7917
7918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
7919 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7920 sysctl_holdoff_tmr_idx, "I", "holdoff timer index");
7921 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
7922 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7923 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index");
7924
7925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
7926 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7927 sysctl_qsize_rxq, "I", "rx queue size");
7928 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
7929 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7930 sysctl_qsize_txq, "I", "tx queue size");
7931 }
7932
7933 static void
cxgbe_sysctls(struct port_info * pi)7934 cxgbe_sysctls(struct port_info *pi)
7935 {
7936 struct sysctl_ctx_list *ctx = &pi->ctx;
7937 struct sysctl_oid *oid;
7938 struct sysctl_oid_list *children, *children2;
7939 struct adapter *sc = pi->adapter;
7940 int i;
7941 char name[16];
7942 static char *tc_flags = {"\20\1USER"};
7943
7944 /*
7945 * dev.cxgbe.X.
7946 */
7947 oid = device_get_sysctl_tree(pi->dev);
7948 children = SYSCTL_CHILDREN(oid);
7949
7950 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc",
7951 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
7952 sysctl_linkdnrc, "A", "reason why link is down");
7953 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
7954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
7955 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
7956 sysctl_btphy, "I", "PHY temperature (in Celsius)");
7957 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
7958 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1,
7959 sysctl_btphy, "I", "PHY firmware version");
7960 }
7961
7962 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
7963 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7964 sysctl_pause_settings, "A",
7965 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
7966 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec",
7967 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A",
7968 "FEC in use on the link");
7969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec",
7970 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7971 sysctl_requested_fec, "A",
7972 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
7973 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
7974 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A",
7975 "FEC recommended by the cable/transceiver");
7976 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
7977 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7978 sysctl_autoneg, "I",
7979 "autonegotiation (-1 = not supported)");
7980 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec",
7981 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7982 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config");
7983
7984 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD,
7985 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver");
7986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
7987 &pi->link_cfg.pcaps, 0, "port capabilities");
7988 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
7989 &pi->link_cfg.acaps, 0, "advertised capabilities");
7990 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
7991 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
7992
7993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
7994 port_top_speed(pi), "max speed (in Gbps)");
7995 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
7996 pi->mps_bg_map, "MPS buffer group map");
7997 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
7998 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
7999 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL,
8000 pi->tx_chan, "TP tx c-channel");
8001 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL,
8002 pi->rx_chan, "TP rx c-channel");
8003
8004 if (sc->flags & IS_VF)
8005 return;
8006
8007 /*
8008 * dev.(cxgbe|cxl).X.tc.
8009 */
8010 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc",
8011 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8012 "Tx scheduler traffic classes (cl_rl)");
8013 children2 = SYSCTL_CHILDREN(oid);
8014 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
8015 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
8016 "pktsize for per-flow cl-rl (0 means up to the driver )");
8017 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
8018 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
8019 "burstsize for per-flow cl-rl (0 means up to the driver)");
8020 for (i = 0; i < sc->params.nsched_cls; i++) {
8021 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
8022
8023 snprintf(name, sizeof(name), "%d", i);
8024 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
8025 SYSCTL_CHILDREN(oid), OID_AUTO, name,
8026 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class"));
8027 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state",
8028 CTLFLAG_RD, &tc->state, 0, "current state");
8029 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
8030 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags,
8031 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags");
8032 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
8033 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
8034 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
8035 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8036 (pi->port_id << 16) | i, sysctl_tc_params, "A",
8037 "traffic class parameters");
8038 }
8039
8040 /*
8041 * dev.cxgbe.X.stats.
8042 */
8043 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
8044 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics");
8045 children = SYSCTL_CHILDREN(oid);
8046 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
8047 &pi->tx_parse_error, 0,
8048 "# of tx packets with invalid length or # of segments");
8049
8050 #define T4_REGSTAT(name, stat, desc) \
8051 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8052 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8053 t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \
8054 sysctl_handle_t4_reg64, "QU", desc)
8055
8056 /* We get these from port_stats and they may be stale by up to 1s */
8057 #define T4_PORTSTAT(name, desc) \
8058 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
8059 &pi->stats.name, desc)
8060
8061 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
8062 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
8063 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
8064 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
8065 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
8066 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
8067 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
8068 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
8069 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
8070 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
8071 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
8072 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
8073 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
8074 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
8075 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
8076 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
8077 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
8078 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
8079 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
8080 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
8081 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
8082 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
8083 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
8084
8085 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
8086 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
8087 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
8088 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
8089 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
8090 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
8091 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
8092 if (is_t6(sc)) {
8093 T4_PORTSTAT(rx_fcs_err,
8094 "# of frames received with bad FCS since last link up");
8095 } else {
8096 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
8097 "# of frames received with bad FCS");
8098 }
8099 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
8100 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
8101 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
8102 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
8103 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
8104 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
8105 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
8106 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
8107 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
8108 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
8109 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
8110 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
8111 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
8112 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
8113 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
8114 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
8115 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
8116 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
8117 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
8118
8119 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows");
8120 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows");
8121 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows");
8122 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows");
8123 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets");
8124 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets");
8125 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets");
8126 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets");
8127
8128 #undef T4_REGSTAT
8129 #undef T4_PORTSTAT
8130 }
8131
8132 static int
sysctl_int_array(SYSCTL_HANDLER_ARGS)8133 sysctl_int_array(SYSCTL_HANDLER_ARGS)
8134 {
8135 int rc, *i, space = 0;
8136 struct sbuf sb;
8137
8138 sbuf_new_for_sysctl(&sb, NULL, 64, req);
8139 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
8140 if (space)
8141 sbuf_printf(&sb, " ");
8142 sbuf_printf(&sb, "%d", *i);
8143 space = 1;
8144 }
8145 rc = sbuf_finish(&sb);
8146 sbuf_delete(&sb);
8147 return (rc);
8148 }
8149
8150 static int
sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)8151 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
8152 {
8153 int rc;
8154 struct sbuf *sb;
8155
8156 rc = sysctl_wire_old_buffer(req, 0);
8157 if (rc != 0)
8158 return(rc);
8159
8160 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8161 if (sb == NULL)
8162 return (ENOMEM);
8163
8164 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
8165 rc = sbuf_finish(sb);
8166 sbuf_delete(sb);
8167
8168 return (rc);
8169 }
8170
8171 static int
sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)8172 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
8173 {
8174 int rc;
8175 struct sbuf *sb;
8176
8177 rc = sysctl_wire_old_buffer(req, 0);
8178 if (rc != 0)
8179 return(rc);
8180
8181 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8182 if (sb == NULL)
8183 return (ENOMEM);
8184
8185 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
8186 rc = sbuf_finish(sb);
8187 sbuf_delete(sb);
8188
8189 return (rc);
8190 }
8191
8192 static int
sysctl_btphy(SYSCTL_HANDLER_ARGS)8193 sysctl_btphy(SYSCTL_HANDLER_ARGS)
8194 {
8195 struct port_info *pi = arg1;
8196 int op = arg2;
8197 struct adapter *sc = pi->adapter;
8198 u_int v;
8199 int rc;
8200
8201 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
8202 if (rc)
8203 return (rc);
8204 if (hw_off_limits(sc))
8205 rc = ENXIO;
8206 else {
8207 /* XXX: magic numbers */
8208 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e,
8209 op ? 0x20 : 0xc820, &v);
8210 }
8211 end_synchronized_op(sc, 0);
8212 if (rc)
8213 return (rc);
8214 if (op == 0)
8215 v /= 256;
8216
8217 rc = sysctl_handle_int(oidp, &v, 0, req);
8218 return (rc);
8219 }
8220
8221 static int
sysctl_noflowq(SYSCTL_HANDLER_ARGS)8222 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
8223 {
8224 struct vi_info *vi = arg1;
8225 int rc, val;
8226
8227 val = vi->rsrv_noflowq;
8228 rc = sysctl_handle_int(oidp, &val, 0, req);
8229 if (rc != 0 || req->newptr == NULL)
8230 return (rc);
8231
8232 if ((val >= 1) && (vi->ntxq > 1))
8233 vi->rsrv_noflowq = 1;
8234 else
8235 vi->rsrv_noflowq = 0;
8236
8237 return (rc);
8238 }
8239
8240 static int
sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)8241 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)
8242 {
8243 struct vi_info *vi = arg1;
8244 struct adapter *sc = vi->adapter;
8245 int rc, val, i;
8246
8247 MPASS(!(sc->flags & IS_VF));
8248
8249 val = vi->flags & TX_USES_VM_WR ? 1 : 0;
8250 rc = sysctl_handle_int(oidp, &val, 0, req);
8251 if (rc != 0 || req->newptr == NULL)
8252 return (rc);
8253
8254 if (val != 0 && val != 1)
8255 return (EINVAL);
8256
8257 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8258 "t4txvm");
8259 if (rc)
8260 return (rc);
8261 if (hw_off_limits(sc))
8262 rc = ENXIO;
8263 else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) {
8264 /*
8265 * We don't want parse_pkt to run with one setting (VF or PF)
8266 * and then eth_tx to see a different setting but still use
8267 * stale information calculated by parse_pkt.
8268 */
8269 rc = EBUSY;
8270 } else {
8271 struct port_info *pi = vi->pi;
8272 struct sge_txq *txq;
8273 uint32_t ctrl0;
8274 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr;
8275
8276 if (val) {
8277 vi->flags |= TX_USES_VM_WR;
8278 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO);
8279 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8280 V_TXPKT_INTF(pi->tx_chan));
8281 if (!(sc->flags & IS_VF))
8282 npkt--;
8283 } else {
8284 vi->flags &= ~TX_USES_VM_WR;
8285 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO);
8286 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8287 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
8288 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
8289 }
8290 for_each_txq(vi, i, txq) {
8291 txq->cpl_ctrl0 = ctrl0;
8292 txq->txp.max_npkt = npkt;
8293 }
8294 }
8295 end_synchronized_op(sc, LOCK_HELD);
8296 return (rc);
8297 }
8298
8299 static int
sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)8300 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
8301 {
8302 struct vi_info *vi = arg1;
8303 struct adapter *sc = vi->adapter;
8304 int idx, rc, i;
8305 struct sge_rxq *rxq;
8306 uint8_t v;
8307
8308 idx = vi->tmr_idx;
8309
8310 rc = sysctl_handle_int(oidp, &idx, 0, req);
8311 if (rc != 0 || req->newptr == NULL)
8312 return (rc);
8313
8314 if (idx < 0 || idx >= SGE_NTIMERS)
8315 return (EINVAL);
8316
8317 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8318 "t4tmr");
8319 if (rc)
8320 return (rc);
8321
8322 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
8323 for_each_rxq(vi, i, rxq) {
8324 #ifdef atomic_store_rel_8
8325 atomic_store_rel_8(&rxq->iq.intr_params, v);
8326 #else
8327 rxq->iq.intr_params = v;
8328 #endif
8329 }
8330 vi->tmr_idx = idx;
8331
8332 end_synchronized_op(sc, LOCK_HELD);
8333 return (0);
8334 }
8335
8336 static int
sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)8337 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
8338 {
8339 struct vi_info *vi = arg1;
8340 struct adapter *sc = vi->adapter;
8341 int idx, rc;
8342
8343 idx = vi->pktc_idx;
8344
8345 rc = sysctl_handle_int(oidp, &idx, 0, req);
8346 if (rc != 0 || req->newptr == NULL)
8347 return (rc);
8348
8349 if (idx < -1 || idx >= SGE_NCOUNTERS)
8350 return (EINVAL);
8351
8352 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8353 "t4pktc");
8354 if (rc)
8355 return (rc);
8356
8357 if (vi->flags & VI_INIT_DONE)
8358 rc = EBUSY; /* cannot be changed once the queues are created */
8359 else
8360 vi->pktc_idx = idx;
8361
8362 end_synchronized_op(sc, LOCK_HELD);
8363 return (rc);
8364 }
8365
8366 static int
sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)8367 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
8368 {
8369 struct vi_info *vi = arg1;
8370 struct adapter *sc = vi->adapter;
8371 int qsize, rc;
8372
8373 qsize = vi->qsize_rxq;
8374
8375 rc = sysctl_handle_int(oidp, &qsize, 0, req);
8376 if (rc != 0 || req->newptr == NULL)
8377 return (rc);
8378
8379 if (qsize < 128 || (qsize & 7))
8380 return (EINVAL);
8381
8382 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8383 "t4rxqs");
8384 if (rc)
8385 return (rc);
8386
8387 if (vi->flags & VI_INIT_DONE)
8388 rc = EBUSY; /* cannot be changed once the queues are created */
8389 else
8390 vi->qsize_rxq = qsize;
8391
8392 end_synchronized_op(sc, LOCK_HELD);
8393 return (rc);
8394 }
8395
8396 static int
sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)8397 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
8398 {
8399 struct vi_info *vi = arg1;
8400 struct adapter *sc = vi->adapter;
8401 int qsize, rc;
8402
8403 qsize = vi->qsize_txq;
8404
8405 rc = sysctl_handle_int(oidp, &qsize, 0, req);
8406 if (rc != 0 || req->newptr == NULL)
8407 return (rc);
8408
8409 if (qsize < 128 || qsize > 65536)
8410 return (EINVAL);
8411
8412 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8413 "t4txqs");
8414 if (rc)
8415 return (rc);
8416
8417 if (vi->flags & VI_INIT_DONE)
8418 rc = EBUSY; /* cannot be changed once the queues are created */
8419 else
8420 vi->qsize_txq = qsize;
8421
8422 end_synchronized_op(sc, LOCK_HELD);
8423 return (rc);
8424 }
8425
8426 static int
sysctl_pause_settings(SYSCTL_HANDLER_ARGS)8427 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
8428 {
8429 struct port_info *pi = arg1;
8430 struct adapter *sc = pi->adapter;
8431 struct link_config *lc = &pi->link_cfg;
8432 int rc;
8433
8434 if (req->newptr == NULL) {
8435 struct sbuf *sb;
8436 static char *bits = "\20\1RX\2TX\3AUTO";
8437
8438 rc = sysctl_wire_old_buffer(req, 0);
8439 if (rc != 0)
8440 return(rc);
8441
8442 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8443 if (sb == NULL)
8444 return (ENOMEM);
8445
8446 if (lc->link_ok) {
8447 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
8448 (lc->requested_fc & PAUSE_AUTONEG), bits);
8449 } else {
8450 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
8451 PAUSE_RX | PAUSE_AUTONEG), bits);
8452 }
8453 rc = sbuf_finish(sb);
8454 sbuf_delete(sb);
8455 } else {
8456 char s[2];
8457 int n;
8458
8459 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
8460 PAUSE_AUTONEG));
8461 s[1] = 0;
8462
8463 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8464 if (rc != 0)
8465 return(rc);
8466
8467 if (s[1] != 0)
8468 return (EINVAL);
8469 if (s[0] < '0' || s[0] > '9')
8470 return (EINVAL); /* not a number */
8471 n = s[0] - '0';
8472 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
8473 return (EINVAL); /* some other bit is set too */
8474
8475 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8476 "t4PAUSE");
8477 if (rc)
8478 return (rc);
8479 if (!hw_off_limits(sc)) {
8480 PORT_LOCK(pi);
8481 lc->requested_fc = n;
8482 fixup_link_config(pi);
8483 if (pi->up_vis > 0)
8484 rc = apply_link_config(pi);
8485 set_current_media(pi);
8486 PORT_UNLOCK(pi);
8487 }
8488 end_synchronized_op(sc, 0);
8489 }
8490
8491 return (rc);
8492 }
8493
8494 static int
sysctl_link_fec(SYSCTL_HANDLER_ARGS)8495 sysctl_link_fec(SYSCTL_HANDLER_ARGS)
8496 {
8497 struct port_info *pi = arg1;
8498 struct link_config *lc = &pi->link_cfg;
8499 int rc;
8500 struct sbuf *sb;
8501 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2";
8502
8503 rc = sysctl_wire_old_buffer(req, 0);
8504 if (rc != 0)
8505 return(rc);
8506
8507 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8508 if (sb == NULL)
8509 return (ENOMEM);
8510 if (lc->link_ok)
8511 sbuf_printf(sb, "%b", lc->fec, bits);
8512 else
8513 sbuf_printf(sb, "no link");
8514 rc = sbuf_finish(sb);
8515 sbuf_delete(sb);
8516
8517 return (rc);
8518 }
8519
8520 static int
sysctl_requested_fec(SYSCTL_HANDLER_ARGS)8521 sysctl_requested_fec(SYSCTL_HANDLER_ARGS)
8522 {
8523 struct port_info *pi = arg1;
8524 struct adapter *sc = pi->adapter;
8525 struct link_config *lc = &pi->link_cfg;
8526 int rc;
8527 int8_t old;
8528
8529 if (req->newptr == NULL) {
8530 struct sbuf *sb;
8531 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2"
8532 "\5RSVD3\6auto\7module";
8533
8534 rc = sysctl_wire_old_buffer(req, 0);
8535 if (rc != 0)
8536 return(rc);
8537
8538 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8539 if (sb == NULL)
8540 return (ENOMEM);
8541
8542 sbuf_printf(sb, "%b", lc->requested_fec, bits);
8543 rc = sbuf_finish(sb);
8544 sbuf_delete(sb);
8545 } else {
8546 char s[8];
8547 int n;
8548
8549 snprintf(s, sizeof(s), "%d",
8550 lc->requested_fec == FEC_AUTO ? -1 :
8551 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
8552
8553 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8554 if (rc != 0)
8555 return(rc);
8556
8557 n = strtol(&s[0], NULL, 0);
8558 if (n < 0 || n & FEC_AUTO)
8559 n = FEC_AUTO;
8560 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
8561 return (EINVAL);/* some other bit is set too */
8562
8563 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8564 "t4reqf");
8565 if (rc)
8566 return (rc);
8567 PORT_LOCK(pi);
8568 old = lc->requested_fec;
8569 if (n == FEC_AUTO)
8570 lc->requested_fec = FEC_AUTO;
8571 else if (n == 0 || n == FEC_NONE)
8572 lc->requested_fec = FEC_NONE;
8573 else {
8574 if ((lc->pcaps |
8575 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
8576 lc->pcaps) {
8577 rc = ENOTSUP;
8578 goto done;
8579 }
8580 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
8581 FEC_MODULE);
8582 }
8583 if (!hw_off_limits(sc)) {
8584 fixup_link_config(pi);
8585 if (pi->up_vis > 0) {
8586 rc = apply_link_config(pi);
8587 if (rc != 0) {
8588 lc->requested_fec = old;
8589 if (rc == FW_EPROTO)
8590 rc = ENOTSUP;
8591 }
8592 }
8593 }
8594 done:
8595 PORT_UNLOCK(pi);
8596 end_synchronized_op(sc, 0);
8597 }
8598
8599 return (rc);
8600 }
8601
8602 static int
sysctl_module_fec(SYSCTL_HANDLER_ARGS)8603 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
8604 {
8605 struct port_info *pi = arg1;
8606 struct adapter *sc = pi->adapter;
8607 struct link_config *lc = &pi->link_cfg;
8608 int rc;
8609 int8_t fec;
8610 struct sbuf *sb;
8611 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3";
8612
8613 rc = sysctl_wire_old_buffer(req, 0);
8614 if (rc != 0)
8615 return (rc);
8616
8617 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8618 if (sb == NULL)
8619 return (ENOMEM);
8620
8621 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) {
8622 rc = EBUSY;
8623 goto done;
8624 }
8625 if (hw_off_limits(sc)) {
8626 rc = ENXIO;
8627 goto done;
8628 }
8629 PORT_LOCK(pi);
8630 if (pi->up_vis == 0) {
8631 /*
8632 * If all the interfaces are administratively down the firmware
8633 * does not report transceiver changes. Refresh port info here.
8634 * This is the only reason we have a synchronized op in this
8635 * function. Just PORT_LOCK would have been enough otherwise.
8636 */
8637 t4_update_port_info(pi);
8638 }
8639
8640 fec = lc->fec_hint;
8641 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
8642 !fec_supported(lc->pcaps)) {
8643 sbuf_printf(sb, "n/a");
8644 } else {
8645 if (fec == 0)
8646 fec = FEC_NONE;
8647 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits);
8648 }
8649 rc = sbuf_finish(sb);
8650 PORT_UNLOCK(pi);
8651 done:
8652 sbuf_delete(sb);
8653 end_synchronized_op(sc, 0);
8654
8655 return (rc);
8656 }
8657
8658 static int
sysctl_autoneg(SYSCTL_HANDLER_ARGS)8659 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
8660 {
8661 struct port_info *pi = arg1;
8662 struct adapter *sc = pi->adapter;
8663 struct link_config *lc = &pi->link_cfg;
8664 int rc, val;
8665
8666 if (lc->pcaps & FW_PORT_CAP32_ANEG)
8667 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
8668 else
8669 val = -1;
8670 rc = sysctl_handle_int(oidp, &val, 0, req);
8671 if (rc != 0 || req->newptr == NULL)
8672 return (rc);
8673 if (val == 0)
8674 val = AUTONEG_DISABLE;
8675 else if (val == 1)
8676 val = AUTONEG_ENABLE;
8677 else
8678 val = AUTONEG_AUTO;
8679
8680 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8681 "t4aneg");
8682 if (rc)
8683 return (rc);
8684 PORT_LOCK(pi);
8685 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
8686 rc = ENOTSUP;
8687 goto done;
8688 }
8689 lc->requested_aneg = val;
8690 if (!hw_off_limits(sc)) {
8691 fixup_link_config(pi);
8692 if (pi->up_vis > 0)
8693 rc = apply_link_config(pi);
8694 set_current_media(pi);
8695 }
8696 done:
8697 PORT_UNLOCK(pi);
8698 end_synchronized_op(sc, 0);
8699 return (rc);
8700 }
8701
8702 static int
sysctl_force_fec(SYSCTL_HANDLER_ARGS)8703 sysctl_force_fec(SYSCTL_HANDLER_ARGS)
8704 {
8705 struct port_info *pi = arg1;
8706 struct adapter *sc = pi->adapter;
8707 struct link_config *lc = &pi->link_cfg;
8708 int rc, val;
8709
8710 val = lc->force_fec;
8711 MPASS(val >= -1 && val <= 1);
8712 rc = sysctl_handle_int(oidp, &val, 0, req);
8713 if (rc != 0 || req->newptr == NULL)
8714 return (rc);
8715 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC))
8716 return (ENOTSUP);
8717 if (val < -1 || val > 1)
8718 return (EINVAL);
8719
8720 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff");
8721 if (rc)
8722 return (rc);
8723 PORT_LOCK(pi);
8724 lc->force_fec = val;
8725 if (!hw_off_limits(sc)) {
8726 fixup_link_config(pi);
8727 if (pi->up_vis > 0)
8728 rc = apply_link_config(pi);
8729 }
8730 PORT_UNLOCK(pi);
8731 end_synchronized_op(sc, 0);
8732 return (rc);
8733 }
8734
8735 static int
sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)8736 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
8737 {
8738 struct adapter *sc = arg1;
8739 int rc, reg = arg2;
8740 uint64_t val;
8741
8742 mtx_lock(&sc->reg_lock);
8743 if (hw_off_limits(sc))
8744 rc = ENXIO;
8745 else {
8746 rc = 0;
8747 val = t4_read_reg64(sc, reg);
8748 }
8749 mtx_unlock(&sc->reg_lock);
8750 if (rc == 0)
8751 rc = sysctl_handle_64(oidp, &val, 0, req);
8752 return (rc);
8753 }
8754
8755 static int
sysctl_temperature(SYSCTL_HANDLER_ARGS)8756 sysctl_temperature(SYSCTL_HANDLER_ARGS)
8757 {
8758 struct adapter *sc = arg1;
8759 int rc, t;
8760 uint32_t param, val;
8761
8762 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
8763 if (rc)
8764 return (rc);
8765 if (hw_off_limits(sc))
8766 rc = ENXIO;
8767 else {
8768 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8769 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
8770 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
8771 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
8772 }
8773 end_synchronized_op(sc, 0);
8774 if (rc)
8775 return (rc);
8776
8777 /* unknown is returned as 0 but we display -1 in that case */
8778 t = val == 0 ? -1 : val;
8779
8780 rc = sysctl_handle_int(oidp, &t, 0, req);
8781 return (rc);
8782 }
8783
8784 static int
sysctl_vdd(SYSCTL_HANDLER_ARGS)8785 sysctl_vdd(SYSCTL_HANDLER_ARGS)
8786 {
8787 struct adapter *sc = arg1;
8788 int rc;
8789 uint32_t param, val;
8790
8791 if (sc->params.core_vdd == 0) {
8792 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8793 "t4vdd");
8794 if (rc)
8795 return (rc);
8796 if (hw_off_limits(sc))
8797 rc = ENXIO;
8798 else {
8799 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8800 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
8801 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
8802 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1,
8803 ¶m, &val);
8804 }
8805 end_synchronized_op(sc, 0);
8806 if (rc)
8807 return (rc);
8808 sc->params.core_vdd = val;
8809 }
8810
8811 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
8812 }
8813
8814 static int
sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)8815 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
8816 {
8817 struct adapter *sc = arg1;
8818 int rc, v;
8819 uint32_t param, val;
8820
8821 v = sc->sensor_resets;
8822 rc = sysctl_handle_int(oidp, &v, 0, req);
8823 if (rc != 0 || req->newptr == NULL || v <= 0)
8824 return (rc);
8825
8826 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
8827 chip_id(sc) < CHELSIO_T5)
8828 return (ENOTSUP);
8829
8830 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
8831 if (rc)
8832 return (rc);
8833 if (hw_off_limits(sc))
8834 rc = ENXIO;
8835 else {
8836 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8837 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
8838 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
8839 val = 1;
8840 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
8841 }
8842 end_synchronized_op(sc, 0);
8843 if (rc == 0)
8844 sc->sensor_resets++;
8845 return (rc);
8846 }
8847
8848 static int
sysctl_loadavg(SYSCTL_HANDLER_ARGS)8849 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
8850 {
8851 struct adapter *sc = arg1;
8852 struct sbuf *sb;
8853 int rc;
8854 uint32_t param, val;
8855
8856 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
8857 if (rc)
8858 return (rc);
8859 if (hw_off_limits(sc))
8860 rc = ENXIO;
8861 else {
8862 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8863 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
8864 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
8865 }
8866 end_synchronized_op(sc, 0);
8867 if (rc)
8868 return (rc);
8869
8870 rc = sysctl_wire_old_buffer(req, 0);
8871 if (rc != 0)
8872 return (rc);
8873
8874 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8875 if (sb == NULL)
8876 return (ENOMEM);
8877
8878 if (val == 0xffffffff) {
8879 /* Only debug and custom firmwares report load averages. */
8880 sbuf_printf(sb, "not available");
8881 } else {
8882 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
8883 (val >> 16) & 0xff);
8884 }
8885 rc = sbuf_finish(sb);
8886 sbuf_delete(sb);
8887
8888 return (rc);
8889 }
8890
8891 static int
sysctl_cctrl(SYSCTL_HANDLER_ARGS)8892 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
8893 {
8894 struct adapter *sc = arg1;
8895 struct sbuf *sb;
8896 int rc, i;
8897 uint16_t incr[NMTUS][NCCTRL_WIN];
8898 static const char *dec_fac[] = {
8899 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
8900 "0.9375"
8901 };
8902
8903 rc = sysctl_wire_old_buffer(req, 0);
8904 if (rc != 0)
8905 return (rc);
8906
8907 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8908 if (sb == NULL)
8909 return (ENOMEM);
8910
8911 mtx_lock(&sc->reg_lock);
8912 if (hw_off_limits(sc))
8913 rc = ENXIO;
8914 else
8915 t4_read_cong_tbl(sc, incr);
8916 mtx_unlock(&sc->reg_lock);
8917 if (rc)
8918 goto done;
8919
8920 for (i = 0; i < NCCTRL_WIN; ++i) {
8921 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
8922 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
8923 incr[5][i], incr[6][i], incr[7][i]);
8924 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
8925 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
8926 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
8927 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
8928 }
8929
8930 rc = sbuf_finish(sb);
8931 done:
8932 sbuf_delete(sb);
8933 return (rc);
8934 }
8935
8936 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
8937 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
8938 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
8939 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
8940 };
8941
8942 static int
sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)8943 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
8944 {
8945 struct adapter *sc = arg1;
8946 struct sbuf *sb;
8947 int rc, i, n, qid = arg2;
8948 uint32_t *buf, *p;
8949 char *qtype;
8950 u_int cim_num_obq = sc->chip_params->cim_num_obq;
8951
8952 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
8953 ("%s: bad qid %d\n", __func__, qid));
8954
8955 if (qid < CIM_NUM_IBQ) {
8956 /* inbound queue */
8957 qtype = "IBQ";
8958 n = 4 * CIM_IBQ_SIZE;
8959 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
8960 mtx_lock(&sc->reg_lock);
8961 if (hw_off_limits(sc))
8962 rc = -ENXIO;
8963 else
8964 rc = t4_read_cim_ibq(sc, qid, buf, n);
8965 mtx_unlock(&sc->reg_lock);
8966 } else {
8967 /* outbound queue */
8968 qtype = "OBQ";
8969 qid -= CIM_NUM_IBQ;
8970 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
8971 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
8972 mtx_lock(&sc->reg_lock);
8973 if (hw_off_limits(sc))
8974 rc = -ENXIO;
8975 else
8976 rc = t4_read_cim_obq(sc, qid, buf, n);
8977 mtx_unlock(&sc->reg_lock);
8978 }
8979
8980 if (rc < 0) {
8981 rc = -rc;
8982 goto done;
8983 }
8984 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
8985
8986 rc = sysctl_wire_old_buffer(req, 0);
8987 if (rc != 0)
8988 goto done;
8989
8990 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
8991 if (sb == NULL) {
8992 rc = ENOMEM;
8993 goto done;
8994 }
8995
8996 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
8997 for (i = 0, p = buf; i < n; i += 16, p += 4)
8998 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
8999 p[2], p[3]);
9000
9001 rc = sbuf_finish(sb);
9002 sbuf_delete(sb);
9003 done:
9004 free(buf, M_CXGBE);
9005 return (rc);
9006 }
9007
9008 static void
sbuf_cim_la4(struct adapter * sc,struct sbuf * sb,uint32_t * buf,uint32_t cfg)9009 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9010 {
9011 uint32_t *p;
9012
9013 sbuf_printf(sb, "Status Data PC%s",
9014 cfg & F_UPDBGLACAPTPCONLY ? "" :
9015 " LS0Stat LS0Addr LS0Data");
9016
9017 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
9018 if (cfg & F_UPDBGLACAPTPCONLY) {
9019 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
9020 p[6], p[7]);
9021 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
9022 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
9023 p[4] & 0xff, p[5] >> 8);
9024 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
9025 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9026 p[1] & 0xf, p[2] >> 4);
9027 } else {
9028 sbuf_printf(sb,
9029 "\n %02x %x%07x %x%07x %08x %08x "
9030 "%08x%08x%08x%08x",
9031 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9032 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
9033 p[6], p[7]);
9034 }
9035 }
9036 }
9037
9038 static void
sbuf_cim_la6(struct adapter * sc,struct sbuf * sb,uint32_t * buf,uint32_t cfg)9039 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9040 {
9041 uint32_t *p;
9042
9043 sbuf_printf(sb, "Status Inst Data PC%s",
9044 cfg & F_UPDBGLACAPTPCONLY ? "" :
9045 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
9046
9047 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
9048 if (cfg & F_UPDBGLACAPTPCONLY) {
9049 sbuf_printf(sb, "\n %02x %08x %08x %08x",
9050 p[3] & 0xff, p[2], p[1], p[0]);
9051 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
9052 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
9053 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
9054 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
9055 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
9056 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
9057 p[6] >> 16);
9058 } else {
9059 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
9060 "%08x %08x %08x %08x %08x %08x",
9061 (p[9] >> 16) & 0xff,
9062 p[9] & 0xffff, p[8] >> 16,
9063 p[8] & 0xffff, p[7] >> 16,
9064 p[7] & 0xffff, p[6] >> 16,
9065 p[2], p[1], p[0], p[5], p[4], p[3]);
9066 }
9067 }
9068 }
9069
9070 static int
sbuf_cim_la(struct adapter * sc,struct sbuf * sb,int flags)9071 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
9072 {
9073 uint32_t cfg, *buf;
9074 int rc;
9075
9076 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
9077 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
9078 M_ZERO | flags);
9079 if (buf == NULL)
9080 return (ENOMEM);
9081
9082 mtx_lock(&sc->reg_lock);
9083 if (hw_off_limits(sc))
9084 rc = ENXIO;
9085 else {
9086 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
9087 if (rc == 0)
9088 rc = -t4_cim_read_la(sc, buf, NULL);
9089 }
9090 mtx_unlock(&sc->reg_lock);
9091 if (rc == 0) {
9092 if (chip_id(sc) < CHELSIO_T6)
9093 sbuf_cim_la4(sc, sb, buf, cfg);
9094 else
9095 sbuf_cim_la6(sc, sb, buf, cfg);
9096 }
9097 free(buf, M_CXGBE);
9098 return (rc);
9099 }
9100
9101 static int
sysctl_cim_la(SYSCTL_HANDLER_ARGS)9102 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
9103 {
9104 struct adapter *sc = arg1;
9105 struct sbuf *sb;
9106 int rc;
9107
9108 rc = sysctl_wire_old_buffer(req, 0);
9109 if (rc != 0)
9110 return (rc);
9111 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9112 if (sb == NULL)
9113 return (ENOMEM);
9114
9115 rc = sbuf_cim_la(sc, sb, M_WAITOK);
9116 if (rc == 0)
9117 rc = sbuf_finish(sb);
9118 sbuf_delete(sb);
9119 return (rc);
9120 }
9121
9122 static void
dump_cim_regs(struct adapter * sc)9123 dump_cim_regs(struct adapter *sc)
9124 {
9125 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n",
9126 device_get_nameunit(sc->dev),
9127 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9128 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9129 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2),
9130 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN),
9131 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA));
9132 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n",
9133 device_get_nameunit(sc->dev),
9134 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9135 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9136 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800),
9137 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800),
9138 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN));
9139 }
9140
9141 static void
dump_cimla(struct adapter * sc)9142 dump_cimla(struct adapter *sc)
9143 {
9144 struct sbuf sb;
9145 int rc;
9146
9147 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9148 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n",
9149 device_get_nameunit(sc->dev));
9150 return;
9151 }
9152 rc = sbuf_cim_la(sc, &sb, M_WAITOK);
9153 if (rc == 0) {
9154 rc = sbuf_finish(&sb);
9155 if (rc == 0) {
9156 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n",
9157 device_get_nameunit(sc->dev), sbuf_data(&sb));
9158 }
9159 }
9160 sbuf_delete(&sb);
9161 }
9162
9163 void
t4_os_cim_err(struct adapter * sc)9164 t4_os_cim_err(struct adapter *sc)
9165 {
9166 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
9167 }
9168
9169 static int
sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)9170 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
9171 {
9172 struct adapter *sc = arg1;
9173 u_int i;
9174 struct sbuf *sb;
9175 uint32_t *buf, *p;
9176 int rc;
9177
9178 rc = sysctl_wire_old_buffer(req, 0);
9179 if (rc != 0)
9180 return (rc);
9181
9182 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9183 if (sb == NULL)
9184 return (ENOMEM);
9185
9186 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
9187 M_ZERO | M_WAITOK);
9188
9189 mtx_lock(&sc->reg_lock);
9190 if (hw_off_limits(sc))
9191 rc = ENXIO;
9192 else
9193 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
9194 mtx_unlock(&sc->reg_lock);
9195 if (rc)
9196 goto done;
9197
9198 p = buf;
9199 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9200 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
9201 p[1], p[0]);
9202 }
9203
9204 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
9205 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9206 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
9207 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
9208 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
9209 (p[1] >> 2) | ((p[2] & 3) << 30),
9210 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
9211 p[0] & 1);
9212 }
9213 rc = sbuf_finish(sb);
9214 done:
9215 sbuf_delete(sb);
9216 free(buf, M_CXGBE);
9217 return (rc);
9218 }
9219
9220 static int
sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)9221 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
9222 {
9223 struct adapter *sc = arg1;
9224 u_int i;
9225 struct sbuf *sb;
9226 uint32_t *buf, *p;
9227 int rc;
9228
9229 rc = sysctl_wire_old_buffer(req, 0);
9230 if (rc != 0)
9231 return (rc);
9232
9233 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9234 if (sb == NULL)
9235 return (ENOMEM);
9236
9237 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
9238 M_ZERO | M_WAITOK);
9239
9240 mtx_lock(&sc->reg_lock);
9241 if (hw_off_limits(sc))
9242 rc = ENXIO;
9243 else
9244 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
9245 mtx_unlock(&sc->reg_lock);
9246 if (rc)
9247 goto done;
9248
9249 p = buf;
9250 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
9251 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9252 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
9253 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
9254 p[4], p[3], p[2], p[1], p[0]);
9255 }
9256
9257 sbuf_printf(sb, "\n\nCntl ID Data");
9258 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9259 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
9260 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
9261 }
9262
9263 rc = sbuf_finish(sb);
9264 done:
9265 sbuf_delete(sb);
9266 free(buf, M_CXGBE);
9267 return (rc);
9268 }
9269
9270 static int
sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)9271 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
9272 {
9273 struct adapter *sc = arg1;
9274 struct sbuf *sb;
9275 int rc, i;
9276 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9277 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9278 uint16_t thres[CIM_NUM_IBQ];
9279 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
9280 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
9281 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
9282
9283 cim_num_obq = sc->chip_params->cim_num_obq;
9284 if (is_t4(sc)) {
9285 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
9286 obq_rdaddr = A_UP_OBQ_0_REALADDR;
9287 } else {
9288 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
9289 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
9290 }
9291 nq = CIM_NUM_IBQ + cim_num_obq;
9292
9293 mtx_lock(&sc->reg_lock);
9294 if (hw_off_limits(sc))
9295 rc = ENXIO;
9296 else {
9297 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
9298 if (rc == 0) {
9299 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq,
9300 obq_wr);
9301 if (rc == 0)
9302 t4_read_cimq_cfg(sc, base, size, thres);
9303 }
9304 }
9305 mtx_unlock(&sc->reg_lock);
9306 if (rc)
9307 return (rc);
9308
9309 rc = sysctl_wire_old_buffer(req, 0);
9310 if (rc != 0)
9311 return (rc);
9312
9313 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9314 if (sb == NULL)
9315 return (ENOMEM);
9316
9317 sbuf_printf(sb,
9318 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
9319
9320 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
9321 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
9322 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
9323 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9324 G_QUEREMFLITS(p[2]) * 16);
9325 for ( ; i < nq; i++, p += 4, wr += 2)
9326 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
9327 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
9328 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9329 G_QUEREMFLITS(p[2]) * 16);
9330
9331 rc = sbuf_finish(sb);
9332 sbuf_delete(sb);
9333
9334 return (rc);
9335 }
9336
9337 static int
sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)9338 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
9339 {
9340 struct adapter *sc = arg1;
9341 struct sbuf *sb;
9342 int rc;
9343 struct tp_cpl_stats stats;
9344
9345 rc = sysctl_wire_old_buffer(req, 0);
9346 if (rc != 0)
9347 return (rc);
9348
9349 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9350 if (sb == NULL)
9351 return (ENOMEM);
9352
9353 mtx_lock(&sc->reg_lock);
9354 if (hw_off_limits(sc))
9355 rc = ENXIO;
9356 else
9357 t4_tp_get_cpl_stats(sc, &stats, 0);
9358 mtx_unlock(&sc->reg_lock);
9359 if (rc)
9360 goto done;
9361
9362 if (sc->chip_params->nchan > 2) {
9363 sbuf_printf(sb, " channel 0 channel 1"
9364 " channel 2 channel 3");
9365 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
9366 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
9367 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
9368 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
9369 } else {
9370 sbuf_printf(sb, " channel 0 channel 1");
9371 sbuf_printf(sb, "\nCPL requests: %10u %10u",
9372 stats.req[0], stats.req[1]);
9373 sbuf_printf(sb, "\nCPL responses: %10u %10u",
9374 stats.rsp[0], stats.rsp[1]);
9375 }
9376
9377 rc = sbuf_finish(sb);
9378 done:
9379 sbuf_delete(sb);
9380 return (rc);
9381 }
9382
9383 static int
sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)9384 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
9385 {
9386 struct adapter *sc = arg1;
9387 struct sbuf *sb;
9388 int rc;
9389 struct tp_usm_stats stats;
9390
9391 rc = sysctl_wire_old_buffer(req, 0);
9392 if (rc != 0)
9393 return(rc);
9394
9395 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9396 if (sb == NULL)
9397 return (ENOMEM);
9398
9399 mtx_lock(&sc->reg_lock);
9400 if (hw_off_limits(sc))
9401 rc = ENXIO;
9402 else
9403 t4_get_usm_stats(sc, &stats, 1);
9404 mtx_unlock(&sc->reg_lock);
9405 if (rc == 0) {
9406 sbuf_printf(sb, "Frames: %u\n", stats.frames);
9407 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
9408 sbuf_printf(sb, "Drops: %u", stats.drops);
9409 rc = sbuf_finish(sb);
9410 }
9411 sbuf_delete(sb);
9412
9413 return (rc);
9414 }
9415
9416 static int
sysctl_tid_stats(SYSCTL_HANDLER_ARGS)9417 sysctl_tid_stats(SYSCTL_HANDLER_ARGS)
9418 {
9419 struct adapter *sc = arg1;
9420 struct sbuf *sb;
9421 int rc;
9422 struct tp_tid_stats stats;
9423
9424 rc = sysctl_wire_old_buffer(req, 0);
9425 if (rc != 0)
9426 return(rc);
9427
9428 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9429 if (sb == NULL)
9430 return (ENOMEM);
9431
9432 mtx_lock(&sc->reg_lock);
9433 if (hw_off_limits(sc))
9434 rc = ENXIO;
9435 else
9436 t4_tp_get_tid_stats(sc, &stats, 1);
9437 mtx_unlock(&sc->reg_lock);
9438 if (rc == 0) {
9439 sbuf_printf(sb, "Delete: %u\n", stats.del);
9440 sbuf_printf(sb, "Invalidate: %u\n", stats.inv);
9441 sbuf_printf(sb, "Active: %u\n", stats.act);
9442 sbuf_printf(sb, "Passive: %u", stats.pas);
9443 rc = sbuf_finish(sb);
9444 }
9445 sbuf_delete(sb);
9446
9447 return (rc);
9448 }
9449
9450 static const char * const devlog_level_strings[] = {
9451 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
9452 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
9453 [FW_DEVLOG_LEVEL_ERR] = "ERR",
9454 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
9455 [FW_DEVLOG_LEVEL_INFO] = "INFO",
9456 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
9457 };
9458
9459 static const char * const devlog_facility_strings[] = {
9460 [FW_DEVLOG_FACILITY_CORE] = "CORE",
9461 [FW_DEVLOG_FACILITY_CF] = "CF",
9462 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
9463 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
9464 [FW_DEVLOG_FACILITY_RES] = "RES",
9465 [FW_DEVLOG_FACILITY_HW] = "HW",
9466 [FW_DEVLOG_FACILITY_FLR] = "FLR",
9467 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
9468 [FW_DEVLOG_FACILITY_PHY] = "PHY",
9469 [FW_DEVLOG_FACILITY_MAC] = "MAC",
9470 [FW_DEVLOG_FACILITY_PORT] = "PORT",
9471 [FW_DEVLOG_FACILITY_VI] = "VI",
9472 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
9473 [FW_DEVLOG_FACILITY_ACL] = "ACL",
9474 [FW_DEVLOG_FACILITY_TM] = "TM",
9475 [FW_DEVLOG_FACILITY_QFC] = "QFC",
9476 [FW_DEVLOG_FACILITY_DCB] = "DCB",
9477 [FW_DEVLOG_FACILITY_ETH] = "ETH",
9478 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
9479 [FW_DEVLOG_FACILITY_RI] = "RI",
9480 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
9481 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
9482 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
9483 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
9484 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
9485 };
9486
9487 static int
sbuf_devlog(struct adapter * sc,struct sbuf * sb,int flags)9488 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
9489 {
9490 int i, j, rc, nentries, first = 0;
9491 struct devlog_params *dparams = &sc->params.devlog;
9492 struct fw_devlog_e *buf, *e;
9493 uint64_t ftstamp = UINT64_MAX;
9494
9495 if (dparams->addr == 0)
9496 return (ENXIO);
9497
9498 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
9499 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
9500 if (buf == NULL)
9501 return (ENOMEM);
9502
9503 mtx_lock(&sc->reg_lock);
9504 if (hw_off_limits(sc))
9505 rc = ENXIO;
9506 else
9507 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf,
9508 dparams->size);
9509 mtx_unlock(&sc->reg_lock);
9510 if (rc != 0)
9511 goto done;
9512
9513 nentries = dparams->size / sizeof(struct fw_devlog_e);
9514 for (i = 0; i < nentries; i++) {
9515 e = &buf[i];
9516
9517 if (e->timestamp == 0)
9518 break; /* end */
9519
9520 e->timestamp = be64toh(e->timestamp);
9521 e->seqno = be32toh(e->seqno);
9522 for (j = 0; j < 8; j++)
9523 e->params[j] = be32toh(e->params[j]);
9524
9525 if (e->timestamp < ftstamp) {
9526 ftstamp = e->timestamp;
9527 first = i;
9528 }
9529 }
9530
9531 if (buf[first].timestamp == 0)
9532 goto done; /* nothing in the log */
9533
9534 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
9535 "Seq#", "Tstamp", "Level", "Facility", "Message");
9536
9537 i = first;
9538 do {
9539 e = &buf[i];
9540 if (e->timestamp == 0)
9541 break; /* end */
9542
9543 sbuf_printf(sb, "%10d %15ju %8s %8s ",
9544 e->seqno, e->timestamp,
9545 (e->level < nitems(devlog_level_strings) ?
9546 devlog_level_strings[e->level] : "UNKNOWN"),
9547 (e->facility < nitems(devlog_facility_strings) ?
9548 devlog_facility_strings[e->facility] : "UNKNOWN"));
9549 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
9550 e->params[2], e->params[3], e->params[4],
9551 e->params[5], e->params[6], e->params[7]);
9552
9553 if (++i == nentries)
9554 i = 0;
9555 } while (i != first);
9556 done:
9557 free(buf, M_CXGBE);
9558 return (rc);
9559 }
9560
9561 static int
sysctl_devlog(SYSCTL_HANDLER_ARGS)9562 sysctl_devlog(SYSCTL_HANDLER_ARGS)
9563 {
9564 struct adapter *sc = arg1;
9565 int rc;
9566 struct sbuf *sb;
9567
9568 rc = sysctl_wire_old_buffer(req, 0);
9569 if (rc != 0)
9570 return (rc);
9571 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9572 if (sb == NULL)
9573 return (ENOMEM);
9574
9575 rc = sbuf_devlog(sc, sb, M_WAITOK);
9576 if (rc == 0)
9577 rc = sbuf_finish(sb);
9578 sbuf_delete(sb);
9579 return (rc);
9580 }
9581
9582 static void
dump_devlog(struct adapter * sc)9583 dump_devlog(struct adapter *sc)
9584 {
9585 int rc;
9586 struct sbuf sb;
9587
9588 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9589 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n",
9590 device_get_nameunit(sc->dev));
9591 return;
9592 }
9593 rc = sbuf_devlog(sc, &sb, M_WAITOK);
9594 if (rc == 0) {
9595 rc = sbuf_finish(&sb);
9596 if (rc == 0) {
9597 log(LOG_DEBUG, "%s: device log follows.\n%s",
9598 device_get_nameunit(sc->dev), sbuf_data(&sb));
9599 }
9600 }
9601 sbuf_delete(&sb);
9602 }
9603
9604 static int
sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)9605 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
9606 {
9607 struct adapter *sc = arg1;
9608 struct sbuf *sb;
9609 int rc;
9610 struct tp_fcoe_stats stats[MAX_NCHAN];
9611 int i, nchan = sc->chip_params->nchan;
9612
9613 rc = sysctl_wire_old_buffer(req, 0);
9614 if (rc != 0)
9615 return (rc);
9616
9617 mtx_lock(&sc->reg_lock);
9618 if (hw_off_limits(sc))
9619 rc = ENXIO;
9620 else {
9621 for (i = 0; i < nchan; i++)
9622 t4_get_fcoe_stats(sc, i, &stats[i], 1);
9623 }
9624 mtx_unlock(&sc->reg_lock);
9625 if (rc != 0)
9626 return (rc);
9627
9628 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9629 if (sb == NULL)
9630 return (ENOMEM);
9631
9632 if (nchan > 2) {
9633 sbuf_printf(sb, " channel 0 channel 1"
9634 " channel 2 channel 3");
9635 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
9636 stats[0].octets_ddp, stats[1].octets_ddp,
9637 stats[2].octets_ddp, stats[3].octets_ddp);
9638 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
9639 stats[0].frames_ddp, stats[1].frames_ddp,
9640 stats[2].frames_ddp, stats[3].frames_ddp);
9641 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
9642 stats[0].frames_drop, stats[1].frames_drop,
9643 stats[2].frames_drop, stats[3].frames_drop);
9644 } else {
9645 sbuf_printf(sb, " channel 0 channel 1");
9646 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
9647 stats[0].octets_ddp, stats[1].octets_ddp);
9648 sbuf_printf(sb, "\nframesDDP: %16u %16u",
9649 stats[0].frames_ddp, stats[1].frames_ddp);
9650 sbuf_printf(sb, "\nframesDrop: %16u %16u",
9651 stats[0].frames_drop, stats[1].frames_drop);
9652 }
9653
9654 rc = sbuf_finish(sb);
9655 sbuf_delete(sb);
9656
9657 return (rc);
9658 }
9659
9660 static int
sysctl_hw_sched(SYSCTL_HANDLER_ARGS)9661 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
9662 {
9663 struct adapter *sc = arg1;
9664 struct sbuf *sb;
9665 int rc, i;
9666 unsigned int map, kbps, ipg, mode;
9667 unsigned int pace_tab[NTX_SCHED];
9668
9669 rc = sysctl_wire_old_buffer(req, 0);
9670 if (rc != 0)
9671 return (rc);
9672
9673 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req);
9674 if (sb == NULL)
9675 return (ENOMEM);
9676
9677 mtx_lock(&sc->reg_lock);
9678 if (hw_off_limits(sc)) {
9679 rc = ENXIO;
9680 goto done;
9681 }
9682
9683 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
9684 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
9685 t4_read_pace_tbl(sc, pace_tab);
9686
9687 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
9688 "Class IPG (0.1 ns) Flow IPG (us)");
9689
9690 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
9691 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
9692 sbuf_printf(sb, "\n %u %-5s %u ", i,
9693 (mode & (1 << i)) ? "flow" : "class", map & 3);
9694 if (kbps)
9695 sbuf_printf(sb, "%9u ", kbps);
9696 else
9697 sbuf_printf(sb, " disabled ");
9698
9699 if (ipg)
9700 sbuf_printf(sb, "%13u ", ipg);
9701 else
9702 sbuf_printf(sb, " disabled ");
9703
9704 if (pace_tab[i])
9705 sbuf_printf(sb, "%10u", pace_tab[i]);
9706 else
9707 sbuf_printf(sb, " disabled");
9708 }
9709 rc = sbuf_finish(sb);
9710 done:
9711 mtx_unlock(&sc->reg_lock);
9712 sbuf_delete(sb);
9713 return (rc);
9714 }
9715
9716 static int
sysctl_lb_stats(SYSCTL_HANDLER_ARGS)9717 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
9718 {
9719 struct adapter *sc = arg1;
9720 struct sbuf *sb;
9721 int rc, i, j;
9722 uint64_t *p0, *p1;
9723 struct lb_port_stats s[2];
9724 static const char *stat_name[] = {
9725 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
9726 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
9727 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
9728 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
9729 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
9730 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
9731 "BG2FramesTrunc:", "BG3FramesTrunc:"
9732 };
9733
9734 rc = sysctl_wire_old_buffer(req, 0);
9735 if (rc != 0)
9736 return (rc);
9737
9738 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9739 if (sb == NULL)
9740 return (ENOMEM);
9741
9742 memset(s, 0, sizeof(s));
9743
9744 for (i = 0; i < sc->chip_params->nchan; i += 2) {
9745 mtx_lock(&sc->reg_lock);
9746 if (hw_off_limits(sc))
9747 rc = ENXIO;
9748 else {
9749 t4_get_lb_stats(sc, i, &s[0]);
9750 t4_get_lb_stats(sc, i + 1, &s[1]);
9751 }
9752 mtx_unlock(&sc->reg_lock);
9753 if (rc != 0)
9754 break;
9755
9756 p0 = &s[0].octets;
9757 p1 = &s[1].octets;
9758 sbuf_printf(sb, "%s Loopback %u"
9759 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
9760
9761 for (j = 0; j < nitems(stat_name); j++)
9762 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
9763 *p0++, *p1++);
9764 }
9765
9766 rc = sbuf_finish(sb);
9767 sbuf_delete(sb);
9768
9769 return (rc);
9770 }
9771
9772 static int
sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)9773 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
9774 {
9775 int rc = 0;
9776 struct port_info *pi = arg1;
9777 struct link_config *lc = &pi->link_cfg;
9778 struct sbuf *sb;
9779
9780 rc = sysctl_wire_old_buffer(req, 0);
9781 if (rc != 0)
9782 return(rc);
9783 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
9784 if (sb == NULL)
9785 return (ENOMEM);
9786
9787 if (lc->link_ok || lc->link_down_rc == 255)
9788 sbuf_printf(sb, "n/a");
9789 else
9790 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
9791
9792 rc = sbuf_finish(sb);
9793 sbuf_delete(sb);
9794
9795 return (rc);
9796 }
9797
9798 struct mem_desc {
9799 u_int base;
9800 u_int limit;
9801 u_int idx;
9802 };
9803
9804 static int
mem_desc_cmp(const void * a,const void * b)9805 mem_desc_cmp(const void *a, const void *b)
9806 {
9807 const u_int v1 = ((const struct mem_desc *)a)->base;
9808 const u_int v2 = ((const struct mem_desc *)b)->base;
9809
9810 if (v1 < v2)
9811 return (-1);
9812 else if (v1 > v2)
9813 return (1);
9814
9815 return (0);
9816 }
9817
9818 static void
mem_region_show(struct sbuf * sb,const char * name,unsigned int from,unsigned int to)9819 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
9820 unsigned int to)
9821 {
9822 unsigned int size;
9823
9824 if (from == to)
9825 return;
9826
9827 size = to - from + 1;
9828 if (size == 0)
9829 return;
9830
9831 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
9832 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
9833 }
9834
9835 static int
sysctl_meminfo(SYSCTL_HANDLER_ARGS)9836 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
9837 {
9838 struct adapter *sc = arg1;
9839 struct sbuf *sb;
9840 int rc, i, n;
9841 uint32_t lo, hi, used, free, alloc;
9842 static const char *memory[] = {
9843 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:"
9844 };
9845 static const char *region[] = {
9846 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
9847 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
9848 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
9849 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
9850 "RQUDP region:", "PBL region:", "TXPBL region:",
9851 "TLSKey region:", "DBVFIFO region:", "ULPRX state:",
9852 "ULPTX state:", "On-chip queues:",
9853 };
9854 struct mem_desc avail[4];
9855 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
9856 struct mem_desc *md = mem;
9857
9858 rc = sysctl_wire_old_buffer(req, 0);
9859 if (rc != 0)
9860 return (rc);
9861
9862 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9863 if (sb == NULL)
9864 return (ENOMEM);
9865
9866 for (i = 0; i < nitems(mem); i++) {
9867 mem[i].limit = 0;
9868 mem[i].idx = i;
9869 }
9870
9871 mtx_lock(&sc->reg_lock);
9872 if (hw_off_limits(sc)) {
9873 rc = ENXIO;
9874 goto done;
9875 }
9876
9877 /* Find and sort the populated memory ranges */
9878 i = 0;
9879 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
9880 if (lo & F_EDRAM0_ENABLE) {
9881 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
9882 avail[i].base = G_EDRAM0_BASE(hi) << 20;
9883 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
9884 avail[i].idx = 0;
9885 i++;
9886 }
9887 if (lo & F_EDRAM1_ENABLE) {
9888 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
9889 avail[i].base = G_EDRAM1_BASE(hi) << 20;
9890 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
9891 avail[i].idx = 1;
9892 i++;
9893 }
9894 if (lo & F_EXT_MEM_ENABLE) {
9895 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
9896 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
9897 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20);
9898 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
9899 i++;
9900 }
9901 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
9902 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
9903 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
9904 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20);
9905 avail[i].idx = 4;
9906 i++;
9907 }
9908 if (is_t6(sc) && lo & F_HMA_MUX) {
9909 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
9910 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
9911 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20);
9912 avail[i].idx = 5;
9913 i++;
9914 }
9915 MPASS(i <= nitems(avail));
9916 if (!i) /* no memory available */
9917 goto done;
9918 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
9919
9920 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
9921 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
9922 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
9923 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9924 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
9925 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
9926 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
9927 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
9928 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
9929
9930 /* the next few have explicit upper bounds */
9931 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
9932 md->limit = md->base - 1 +
9933 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
9934 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
9935 md++;
9936
9937 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
9938 md->limit = md->base - 1 +
9939 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
9940 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
9941 md++;
9942
9943 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
9944 if (chip_id(sc) <= CHELSIO_T5)
9945 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
9946 else
9947 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
9948 md->limit = 0;
9949 } else {
9950 md->base = 0;
9951 md->idx = nitems(region); /* hide it */
9952 }
9953 md++;
9954
9955 #define ulp_region(reg) \
9956 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
9957 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
9958
9959 ulp_region(RX_ISCSI);
9960 ulp_region(RX_TDDP);
9961 ulp_region(TX_TPT);
9962 ulp_region(RX_STAG);
9963 ulp_region(RX_RQ);
9964 ulp_region(RX_RQUDP);
9965 ulp_region(RX_PBL);
9966 ulp_region(TX_PBL);
9967 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
9968 ulp_region(RX_TLS_KEY);
9969 }
9970 #undef ulp_region
9971
9972 md->base = 0;
9973 if (is_t4(sc))
9974 md->idx = nitems(region);
9975 else {
9976 uint32_t size = 0;
9977 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
9978 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
9979
9980 if (is_t5(sc)) {
9981 if (sge_ctrl & F_VFIFO_ENABLE)
9982 size = fifo_size << 2;
9983 } else
9984 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6;
9985
9986 if (size) {
9987 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR);
9988 md->limit = md->base + size - 1;
9989 } else
9990 md->idx = nitems(region);
9991 }
9992 md++;
9993
9994 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
9995 md->limit = 0;
9996 md++;
9997 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
9998 md->limit = 0;
9999 md++;
10000
10001 md->base = sc->vres.ocq.start;
10002 if (sc->vres.ocq.size)
10003 md->limit = md->base + sc->vres.ocq.size - 1;
10004 else
10005 md->idx = nitems(region); /* hide it */
10006 md++;
10007
10008 /* add any address-space holes, there can be up to 3 */
10009 for (n = 0; n < i - 1; n++)
10010 if (avail[n].limit < avail[n + 1].base)
10011 (md++)->base = avail[n].limit;
10012 if (avail[n].limit)
10013 (md++)->base = avail[n].limit;
10014
10015 n = md - mem;
10016 MPASS(n <= nitems(mem));
10017 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
10018
10019 for (lo = 0; lo < i; lo++)
10020 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
10021 avail[lo].limit - 1);
10022
10023 sbuf_printf(sb, "\n");
10024 for (i = 0; i < n; i++) {
10025 if (mem[i].idx >= nitems(region))
10026 continue; /* skip holes */
10027 if (!mem[i].limit)
10028 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
10029 mem_region_show(sb, region[mem[i].idx], mem[i].base,
10030 mem[i].limit);
10031 }
10032
10033 sbuf_printf(sb, "\n");
10034 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
10035 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
10036 mem_region_show(sb, "uP RAM:", lo, hi);
10037
10038 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
10039 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
10040 mem_region_show(sb, "uP Extmem2:", lo, hi);
10041
10042 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
10043 for (i = 0, free = 0; i < 2; i++)
10044 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT));
10045 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
10046 G_PMRXMAXPAGE(lo), free,
10047 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
10048 (lo & F_PMRXNUMCHN) ? 2 : 1);
10049
10050 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
10051 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
10052 for (i = 0, free = 0; i < 4; i++)
10053 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT));
10054 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n",
10055 G_PMTXMAXPAGE(lo), free,
10056 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
10057 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
10058 sbuf_printf(sb, "%u p-structs (%u free)\n",
10059 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT),
10060 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT)));
10061
10062 for (i = 0; i < 4; i++) {
10063 if (chip_id(sc) > CHELSIO_T5)
10064 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
10065 else
10066 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
10067 if (is_t5(sc)) {
10068 used = G_T5_USED(lo);
10069 alloc = G_T5_ALLOC(lo);
10070 } else {
10071 used = G_USED(lo);
10072 alloc = G_ALLOC(lo);
10073 }
10074 /* For T6 these are MAC buffer groups */
10075 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
10076 i, used, alloc);
10077 }
10078 for (i = 0; i < sc->chip_params->nchan; i++) {
10079 if (chip_id(sc) > CHELSIO_T5)
10080 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
10081 else
10082 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
10083 if (is_t5(sc)) {
10084 used = G_T5_USED(lo);
10085 alloc = G_T5_ALLOC(lo);
10086 } else {
10087 used = G_USED(lo);
10088 alloc = G_ALLOC(lo);
10089 }
10090 /* For T6 these are MAC buffer groups */
10091 sbuf_printf(sb,
10092 "\nLoopback %d using %u pages out of %u allocated",
10093 i, used, alloc);
10094 }
10095 done:
10096 mtx_unlock(&sc->reg_lock);
10097 if (rc == 0)
10098 rc = sbuf_finish(sb);
10099 sbuf_delete(sb);
10100 return (rc);
10101 }
10102
10103 static inline void
tcamxy2valmask(uint64_t x,uint64_t y,uint8_t * addr,uint64_t * mask)10104 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
10105 {
10106 *mask = x | y;
10107 y = htobe64(y);
10108 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
10109 }
10110
10111 static int
sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)10112 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
10113 {
10114 struct adapter *sc = arg1;
10115 struct sbuf *sb;
10116 int rc, i;
10117
10118 MPASS(chip_id(sc) <= CHELSIO_T5);
10119
10120 rc = sysctl_wire_old_buffer(req, 0);
10121 if (rc != 0)
10122 return (rc);
10123
10124 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10125 if (sb == NULL)
10126 return (ENOMEM);
10127
10128 sbuf_printf(sb,
10129 "Idx Ethernet address Mask Vld Ports PF"
10130 " VF Replication P0 P1 P2 P3 ML");
10131 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10132 uint64_t tcamx, tcamy, mask;
10133 uint32_t cls_lo, cls_hi;
10134 uint8_t addr[ETHER_ADDR_LEN];
10135
10136 mtx_lock(&sc->reg_lock);
10137 if (hw_off_limits(sc))
10138 rc = ENXIO;
10139 else {
10140 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
10141 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
10142 }
10143 mtx_unlock(&sc->reg_lock);
10144 if (rc != 0)
10145 break;
10146 if (tcamx & tcamy)
10147 continue;
10148 tcamxy2valmask(tcamx, tcamy, addr, &mask);
10149 mtx_lock(&sc->reg_lock);
10150 if (hw_off_limits(sc))
10151 rc = ENXIO;
10152 else {
10153 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10154 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10155 }
10156 mtx_unlock(&sc->reg_lock);
10157 if (rc != 0)
10158 break;
10159 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
10160 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
10161 addr[3], addr[4], addr[5], (uintmax_t)mask,
10162 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
10163 G_PORTMAP(cls_hi), G_PF(cls_lo),
10164 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
10165
10166 if (cls_lo & F_REPLICATE) {
10167 struct fw_ldst_cmd ldst_cmd;
10168
10169 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10170 ldst_cmd.op_to_addrspace =
10171 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10172 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10173 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10174 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10175 ldst_cmd.u.mps.rplc.fid_idx =
10176 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10177 V_FW_LDST_CMD_IDX(i));
10178
10179 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10180 "t4mps");
10181 if (rc)
10182 break;
10183 if (hw_off_limits(sc))
10184 rc = ENXIO;
10185 else
10186 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10187 sizeof(ldst_cmd), &ldst_cmd);
10188 end_synchronized_op(sc, 0);
10189 if (rc != 0)
10190 break;
10191 else {
10192 sbuf_printf(sb, " %08x %08x %08x %08x",
10193 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10194 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10195 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10196 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10197 }
10198 } else
10199 sbuf_printf(sb, "%36s", "");
10200
10201 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
10202 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
10203 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
10204 }
10205
10206 if (rc)
10207 (void) sbuf_finish(sb);
10208 else
10209 rc = sbuf_finish(sb);
10210 sbuf_delete(sb);
10211
10212 return (rc);
10213 }
10214
10215 static int
sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)10216 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
10217 {
10218 struct adapter *sc = arg1;
10219 struct sbuf *sb;
10220 int rc, i;
10221
10222 MPASS(chip_id(sc) > CHELSIO_T5);
10223
10224 rc = sysctl_wire_old_buffer(req, 0);
10225 if (rc != 0)
10226 return (rc);
10227
10228 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10229 if (sb == NULL)
10230 return (ENOMEM);
10231
10232 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
10233 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
10234 " Replication"
10235 " P0 P1 P2 P3 ML\n");
10236
10237 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10238 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
10239 uint16_t ivlan;
10240 uint64_t tcamx, tcamy, val, mask;
10241 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
10242 uint8_t addr[ETHER_ADDR_LEN];
10243
10244 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
10245 if (i < 256)
10246 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
10247 else
10248 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
10249 mtx_lock(&sc->reg_lock);
10250 if (hw_off_limits(sc))
10251 rc = ENXIO;
10252 else {
10253 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10254 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10255 tcamy = G_DMACH(val) << 32;
10256 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10257 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10258 }
10259 mtx_unlock(&sc->reg_lock);
10260 if (rc != 0)
10261 break;
10262
10263 lookup_type = G_DATALKPTYPE(data2);
10264 port_num = G_DATAPORTNUM(data2);
10265 if (lookup_type && lookup_type != M_DATALKPTYPE) {
10266 /* Inner header VNI */
10267 vniy = ((data2 & F_DATAVIDH2) << 23) |
10268 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
10269 dip_hit = data2 & F_DATADIPHIT;
10270 vlan_vld = 0;
10271 } else {
10272 vniy = 0;
10273 dip_hit = 0;
10274 vlan_vld = data2 & F_DATAVIDH2;
10275 ivlan = G_VIDL(val);
10276 }
10277
10278 ctl |= V_CTLXYBITSEL(1);
10279 mtx_lock(&sc->reg_lock);
10280 if (hw_off_limits(sc))
10281 rc = ENXIO;
10282 else {
10283 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10284 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10285 tcamx = G_DMACH(val) << 32;
10286 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10287 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10288 }
10289 mtx_unlock(&sc->reg_lock);
10290 if (rc != 0)
10291 break;
10292
10293 if (lookup_type && lookup_type != M_DATALKPTYPE) {
10294 /* Inner header VNI mask */
10295 vnix = ((data2 & F_DATAVIDH2) << 23) |
10296 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
10297 } else
10298 vnix = 0;
10299
10300 if (tcamx & tcamy)
10301 continue;
10302 tcamxy2valmask(tcamx, tcamy, addr, &mask);
10303
10304 mtx_lock(&sc->reg_lock);
10305 if (hw_off_limits(sc))
10306 rc = ENXIO;
10307 else {
10308 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10309 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10310 }
10311 mtx_unlock(&sc->reg_lock);
10312 if (rc != 0)
10313 break;
10314
10315 if (lookup_type && lookup_type != M_DATALKPTYPE) {
10316 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
10317 "%012jx %06x %06x - - %3c"
10318 " I %4x %3c %#x%4u%4d", i, addr[0],
10319 addr[1], addr[2], addr[3], addr[4], addr[5],
10320 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
10321 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
10322 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
10323 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
10324 } else {
10325 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
10326 "%012jx - - ", i, addr[0], addr[1],
10327 addr[2], addr[3], addr[4], addr[5],
10328 (uintmax_t)mask);
10329
10330 if (vlan_vld)
10331 sbuf_printf(sb, "%4u Y ", ivlan);
10332 else
10333 sbuf_printf(sb, " - N ");
10334
10335 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
10336 lookup_type ? 'I' : 'O', port_num,
10337 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
10338 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
10339 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
10340 }
10341
10342
10343 if (cls_lo & F_T6_REPLICATE) {
10344 struct fw_ldst_cmd ldst_cmd;
10345
10346 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10347 ldst_cmd.op_to_addrspace =
10348 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10349 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10350 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10351 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10352 ldst_cmd.u.mps.rplc.fid_idx =
10353 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10354 V_FW_LDST_CMD_IDX(i));
10355
10356 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10357 "t6mps");
10358 if (rc)
10359 break;
10360 if (hw_off_limits(sc))
10361 rc = ENXIO;
10362 else
10363 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10364 sizeof(ldst_cmd), &ldst_cmd);
10365 end_synchronized_op(sc, 0);
10366 if (rc != 0)
10367 break;
10368 else {
10369 sbuf_printf(sb, " %08x %08x %08x %08x"
10370 " %08x %08x %08x %08x",
10371 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
10372 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
10373 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
10374 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
10375 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10376 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10377 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10378 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10379 }
10380 } else
10381 sbuf_printf(sb, "%72s", "");
10382
10383 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
10384 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
10385 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
10386 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
10387 }
10388
10389 if (rc)
10390 (void) sbuf_finish(sb);
10391 else
10392 rc = sbuf_finish(sb);
10393 sbuf_delete(sb);
10394
10395 return (rc);
10396 }
10397
10398 static int
sysctl_path_mtus(SYSCTL_HANDLER_ARGS)10399 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
10400 {
10401 struct adapter *sc = arg1;
10402 struct sbuf *sb;
10403 int rc;
10404 uint16_t mtus[NMTUS];
10405
10406 rc = sysctl_wire_old_buffer(req, 0);
10407 if (rc != 0)
10408 return (rc);
10409
10410 mtx_lock(&sc->reg_lock);
10411 if (hw_off_limits(sc))
10412 rc = ENXIO;
10413 else
10414 t4_read_mtu_tbl(sc, mtus, NULL);
10415 mtx_unlock(&sc->reg_lock);
10416 if (rc != 0)
10417 return (rc);
10418
10419 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10420 if (sb == NULL)
10421 return (ENOMEM);
10422
10423 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
10424 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
10425 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
10426 mtus[14], mtus[15]);
10427
10428 rc = sbuf_finish(sb);
10429 sbuf_delete(sb);
10430
10431 return (rc);
10432 }
10433
10434 static int
sysctl_pm_stats(SYSCTL_HANDLER_ARGS)10435 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
10436 {
10437 struct adapter *sc = arg1;
10438 struct sbuf *sb;
10439 int rc, i;
10440 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
10441 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
10442 static const char *tx_stats[MAX_PM_NSTATS] = {
10443 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
10444 "Tx FIFO wait", NULL, "Tx latency"
10445 };
10446 static const char *rx_stats[MAX_PM_NSTATS] = {
10447 "Read:", "Write bypass:", "Write mem:", "Flush:",
10448 "Rx FIFO wait", NULL, "Rx latency"
10449 };
10450
10451 rc = sysctl_wire_old_buffer(req, 0);
10452 if (rc != 0)
10453 return (rc);
10454
10455 mtx_lock(&sc->reg_lock);
10456 if (hw_off_limits(sc))
10457 rc = ENXIO;
10458 else {
10459 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
10460 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
10461 }
10462 mtx_unlock(&sc->reg_lock);
10463 if (rc != 0)
10464 return (rc);
10465
10466 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10467 if (sb == NULL)
10468 return (ENOMEM);
10469
10470 sbuf_printf(sb, " Tx pcmds Tx bytes");
10471 for (i = 0; i < 4; i++) {
10472 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
10473 tx_cyc[i]);
10474 }
10475
10476 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
10477 for (i = 0; i < 4; i++) {
10478 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
10479 rx_cyc[i]);
10480 }
10481
10482 if (chip_id(sc) > CHELSIO_T5) {
10483 sbuf_printf(sb,
10484 "\n Total wait Total occupancy");
10485 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
10486 tx_cyc[i]);
10487 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
10488 rx_cyc[i]);
10489
10490 i += 2;
10491 MPASS(i < nitems(tx_stats));
10492
10493 sbuf_printf(sb,
10494 "\n Reads Total wait");
10495 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
10496 tx_cyc[i]);
10497 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
10498 rx_cyc[i]);
10499 }
10500
10501 rc = sbuf_finish(sb);
10502 sbuf_delete(sb);
10503
10504 return (rc);
10505 }
10506
10507 static int
sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)10508 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
10509 {
10510 struct adapter *sc = arg1;
10511 struct sbuf *sb;
10512 int rc;
10513 struct tp_rdma_stats stats;
10514
10515 rc = sysctl_wire_old_buffer(req, 0);
10516 if (rc != 0)
10517 return (rc);
10518
10519 mtx_lock(&sc->reg_lock);
10520 if (hw_off_limits(sc))
10521 rc = ENXIO;
10522 else
10523 t4_tp_get_rdma_stats(sc, &stats, 0);
10524 mtx_unlock(&sc->reg_lock);
10525 if (rc != 0)
10526 return (rc);
10527
10528 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10529 if (sb == NULL)
10530 return (ENOMEM);
10531
10532 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
10533 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
10534
10535 rc = sbuf_finish(sb);
10536 sbuf_delete(sb);
10537
10538 return (rc);
10539 }
10540
10541 static int
sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)10542 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
10543 {
10544 struct adapter *sc = arg1;
10545 struct sbuf *sb;
10546 int rc;
10547 struct tp_tcp_stats v4, v6;
10548
10549 rc = sysctl_wire_old_buffer(req, 0);
10550 if (rc != 0)
10551 return (rc);
10552
10553 mtx_lock(&sc->reg_lock);
10554 if (hw_off_limits(sc))
10555 rc = ENXIO;
10556 else
10557 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
10558 mtx_unlock(&sc->reg_lock);
10559 if (rc != 0)
10560 return (rc);
10561
10562 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10563 if (sb == NULL)
10564 return (ENOMEM);
10565
10566 sbuf_printf(sb,
10567 " IP IPv6\n");
10568 sbuf_printf(sb, "OutRsts: %20u %20u\n",
10569 v4.tcp_out_rsts, v6.tcp_out_rsts);
10570 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
10571 v4.tcp_in_segs, v6.tcp_in_segs);
10572 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
10573 v4.tcp_out_segs, v6.tcp_out_segs);
10574 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
10575 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
10576
10577 rc = sbuf_finish(sb);
10578 sbuf_delete(sb);
10579
10580 return (rc);
10581 }
10582
10583 static int
sysctl_tids(SYSCTL_HANDLER_ARGS)10584 sysctl_tids(SYSCTL_HANDLER_ARGS)
10585 {
10586 struct adapter *sc = arg1;
10587 struct sbuf *sb;
10588 int rc;
10589 uint32_t x, y;
10590 struct tid_info *t = &sc->tids;
10591
10592 rc = sysctl_wire_old_buffer(req, 0);
10593 if (rc != 0)
10594 return (rc);
10595
10596 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10597 if (sb == NULL)
10598 return (ENOMEM);
10599
10600 if (t->natids) {
10601 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
10602 t->atids_in_use);
10603 }
10604
10605 if (t->nhpftids) {
10606 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
10607 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
10608 }
10609
10610 if (t->ntids) {
10611 bool hashen = false;
10612
10613 mtx_lock(&sc->reg_lock);
10614 if (hw_off_limits(sc))
10615 rc = ENXIO;
10616 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
10617 hashen = true;
10618 if (chip_id(sc) <= CHELSIO_T5) {
10619 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
10620 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
10621 } else {
10622 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
10623 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
10624 }
10625 }
10626 mtx_unlock(&sc->reg_lock);
10627 if (rc != 0)
10628 goto done;
10629
10630 sbuf_printf(sb, "TID range: ");
10631 if (hashen) {
10632 if (x)
10633 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1);
10634 sbuf_printf(sb, "%u-%u", y, t->ntids - 1);
10635 } else {
10636 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base +
10637 t->ntids - 1);
10638 }
10639 sbuf_printf(sb, ", in use: %u\n",
10640 atomic_load_acq_int(&t->tids_in_use));
10641 }
10642
10643 if (t->nstids) {
10644 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
10645 t->stid_base + t->nstids - 1, t->stids_in_use);
10646 }
10647
10648 if (t->nftids) {
10649 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
10650 t->ftid_end, t->ftids_in_use);
10651 }
10652
10653 if (t->netids) {
10654 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
10655 t->etid_base + t->netids - 1, t->etids_in_use);
10656 }
10657
10658 mtx_lock(&sc->reg_lock);
10659 if (hw_off_limits(sc))
10660 rc = ENXIO;
10661 else {
10662 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4);
10663 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6);
10664 }
10665 mtx_unlock(&sc->reg_lock);
10666 if (rc != 0)
10667 goto done;
10668 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y);
10669 done:
10670 if (rc == 0)
10671 rc = sbuf_finish(sb);
10672 else
10673 (void)sbuf_finish(sb);
10674 sbuf_delete(sb);
10675
10676 return (rc);
10677 }
10678
10679 static int
sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)10680 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
10681 {
10682 struct adapter *sc = arg1;
10683 struct sbuf *sb;
10684 int rc;
10685 struct tp_err_stats stats;
10686
10687 rc = sysctl_wire_old_buffer(req, 0);
10688 if (rc != 0)
10689 return (rc);
10690
10691 mtx_lock(&sc->reg_lock);
10692 if (hw_off_limits(sc))
10693 rc = ENXIO;
10694 else
10695 t4_tp_get_err_stats(sc, &stats, 0);
10696 mtx_unlock(&sc->reg_lock);
10697 if (rc != 0)
10698 return (rc);
10699
10700 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10701 if (sb == NULL)
10702 return (ENOMEM);
10703
10704 if (sc->chip_params->nchan > 2) {
10705 sbuf_printf(sb, " channel 0 channel 1"
10706 " channel 2 channel 3\n");
10707 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
10708 stats.mac_in_errs[0], stats.mac_in_errs[1],
10709 stats.mac_in_errs[2], stats.mac_in_errs[3]);
10710 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
10711 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
10712 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
10713 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
10714 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
10715 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
10716 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
10717 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
10718 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
10719 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
10720 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
10721 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
10722 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
10723 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
10724 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
10725 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
10726 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
10727 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
10728 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
10729 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
10730 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
10731 } else {
10732 sbuf_printf(sb, " channel 0 channel 1\n");
10733 sbuf_printf(sb, "macInErrs: %10u %10u\n",
10734 stats.mac_in_errs[0], stats.mac_in_errs[1]);
10735 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
10736 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
10737 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
10738 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
10739 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
10740 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
10741 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
10742 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
10743 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
10744 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
10745 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
10746 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
10747 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
10748 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
10749 }
10750
10751 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
10752 stats.ofld_no_neigh, stats.ofld_cong_defer);
10753
10754 rc = sbuf_finish(sb);
10755 sbuf_delete(sb);
10756
10757 return (rc);
10758 }
10759
10760 static int
sysctl_tnl_stats(SYSCTL_HANDLER_ARGS)10761 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS)
10762 {
10763 struct adapter *sc = arg1;
10764 struct sbuf *sb;
10765 int rc;
10766 struct tp_tnl_stats stats;
10767
10768 rc = sysctl_wire_old_buffer(req, 0);
10769 if (rc != 0)
10770 return(rc);
10771
10772 mtx_lock(&sc->reg_lock);
10773 if (hw_off_limits(sc))
10774 rc = ENXIO;
10775 else
10776 t4_tp_get_tnl_stats(sc, &stats, 1);
10777 mtx_unlock(&sc->reg_lock);
10778 if (rc != 0)
10779 return (rc);
10780
10781 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10782 if (sb == NULL)
10783 return (ENOMEM);
10784
10785 if (sc->chip_params->nchan > 2) {
10786 sbuf_printf(sb, " channel 0 channel 1"
10787 " channel 2 channel 3\n");
10788 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n",
10789 stats.out_pkt[0], stats.out_pkt[1],
10790 stats.out_pkt[2], stats.out_pkt[3]);
10791 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u",
10792 stats.in_pkt[0], stats.in_pkt[1],
10793 stats.in_pkt[2], stats.in_pkt[3]);
10794 } else {
10795 sbuf_printf(sb, " channel 0 channel 1\n");
10796 sbuf_printf(sb, "OutPkts: %10u %10u\n",
10797 stats.out_pkt[0], stats.out_pkt[1]);
10798 sbuf_printf(sb, "InPkts: %10u %10u",
10799 stats.in_pkt[0], stats.in_pkt[1]);
10800 }
10801
10802 rc = sbuf_finish(sb);
10803 sbuf_delete(sb);
10804
10805 return (rc);
10806 }
10807
10808 static int
sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)10809 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
10810 {
10811 struct adapter *sc = arg1;
10812 struct tp_params *tpp = &sc->params.tp;
10813 u_int mask;
10814 int rc;
10815
10816 mask = tpp->la_mask >> 16;
10817 rc = sysctl_handle_int(oidp, &mask, 0, req);
10818 if (rc != 0 || req->newptr == NULL)
10819 return (rc);
10820 if (mask > 0xffff)
10821 return (EINVAL);
10822 mtx_lock(&sc->reg_lock);
10823 if (hw_off_limits(sc))
10824 rc = ENXIO;
10825 else {
10826 tpp->la_mask = mask << 16;
10827 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U,
10828 tpp->la_mask);
10829 }
10830 mtx_unlock(&sc->reg_lock);
10831
10832 return (rc);
10833 }
10834
10835 struct field_desc {
10836 const char *name;
10837 u_int start;
10838 u_int width;
10839 };
10840
10841 static void
field_desc_show(struct sbuf * sb,uint64_t v,const struct field_desc * f)10842 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
10843 {
10844 char buf[32];
10845 int line_size = 0;
10846
10847 while (f->name) {
10848 uint64_t mask = (1ULL << f->width) - 1;
10849 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
10850 ((uintmax_t)v >> f->start) & mask);
10851
10852 if (line_size + len >= 79) {
10853 line_size = 8;
10854 sbuf_printf(sb, "\n ");
10855 }
10856 sbuf_printf(sb, "%s ", buf);
10857 line_size += len + 1;
10858 f++;
10859 }
10860 sbuf_printf(sb, "\n");
10861 }
10862
10863 static const struct field_desc tp_la0[] = {
10864 { "RcfOpCodeOut", 60, 4 },
10865 { "State", 56, 4 },
10866 { "WcfState", 52, 4 },
10867 { "RcfOpcSrcOut", 50, 2 },
10868 { "CRxError", 49, 1 },
10869 { "ERxError", 48, 1 },
10870 { "SanityFailed", 47, 1 },
10871 { "SpuriousMsg", 46, 1 },
10872 { "FlushInputMsg", 45, 1 },
10873 { "FlushInputCpl", 44, 1 },
10874 { "RssUpBit", 43, 1 },
10875 { "RssFilterHit", 42, 1 },
10876 { "Tid", 32, 10 },
10877 { "InitTcb", 31, 1 },
10878 { "LineNumber", 24, 7 },
10879 { "Emsg", 23, 1 },
10880 { "EdataOut", 22, 1 },
10881 { "Cmsg", 21, 1 },
10882 { "CdataOut", 20, 1 },
10883 { "EreadPdu", 19, 1 },
10884 { "CreadPdu", 18, 1 },
10885 { "TunnelPkt", 17, 1 },
10886 { "RcfPeerFin", 16, 1 },
10887 { "RcfReasonOut", 12, 4 },
10888 { "TxCchannel", 10, 2 },
10889 { "RcfTxChannel", 8, 2 },
10890 { "RxEchannel", 6, 2 },
10891 { "RcfRxChannel", 5, 1 },
10892 { "RcfDataOutSrdy", 4, 1 },
10893 { "RxDvld", 3, 1 },
10894 { "RxOoDvld", 2, 1 },
10895 { "RxCongestion", 1, 1 },
10896 { "TxCongestion", 0, 1 },
10897 { NULL }
10898 };
10899
10900 static const struct field_desc tp_la1[] = {
10901 { "CplCmdIn", 56, 8 },
10902 { "CplCmdOut", 48, 8 },
10903 { "ESynOut", 47, 1 },
10904 { "EAckOut", 46, 1 },
10905 { "EFinOut", 45, 1 },
10906 { "ERstOut", 44, 1 },
10907 { "SynIn", 43, 1 },
10908 { "AckIn", 42, 1 },
10909 { "FinIn", 41, 1 },
10910 { "RstIn", 40, 1 },
10911 { "DataIn", 39, 1 },
10912 { "DataInVld", 38, 1 },
10913 { "PadIn", 37, 1 },
10914 { "RxBufEmpty", 36, 1 },
10915 { "RxDdp", 35, 1 },
10916 { "RxFbCongestion", 34, 1 },
10917 { "TxFbCongestion", 33, 1 },
10918 { "TxPktSumSrdy", 32, 1 },
10919 { "RcfUlpType", 28, 4 },
10920 { "Eread", 27, 1 },
10921 { "Ebypass", 26, 1 },
10922 { "Esave", 25, 1 },
10923 { "Static0", 24, 1 },
10924 { "Cread", 23, 1 },
10925 { "Cbypass", 22, 1 },
10926 { "Csave", 21, 1 },
10927 { "CPktOut", 20, 1 },
10928 { "RxPagePoolFull", 18, 2 },
10929 { "RxLpbkPkt", 17, 1 },
10930 { "TxLpbkPkt", 16, 1 },
10931 { "RxVfValid", 15, 1 },
10932 { "SynLearned", 14, 1 },
10933 { "SetDelEntry", 13, 1 },
10934 { "SetInvEntry", 12, 1 },
10935 { "CpcmdDvld", 11, 1 },
10936 { "CpcmdSave", 10, 1 },
10937 { "RxPstructsFull", 8, 2 },
10938 { "EpcmdDvld", 7, 1 },
10939 { "EpcmdFlush", 6, 1 },
10940 { "EpcmdTrimPrefix", 5, 1 },
10941 { "EpcmdTrimPostfix", 4, 1 },
10942 { "ERssIp4Pkt", 3, 1 },
10943 { "ERssIp6Pkt", 2, 1 },
10944 { "ERssTcpUdpPkt", 1, 1 },
10945 { "ERssFceFipPkt", 0, 1 },
10946 { NULL }
10947 };
10948
10949 static const struct field_desc tp_la2[] = {
10950 { "CplCmdIn", 56, 8 },
10951 { "MpsVfVld", 55, 1 },
10952 { "MpsPf", 52, 3 },
10953 { "MpsVf", 44, 8 },
10954 { "SynIn", 43, 1 },
10955 { "AckIn", 42, 1 },
10956 { "FinIn", 41, 1 },
10957 { "RstIn", 40, 1 },
10958 { "DataIn", 39, 1 },
10959 { "DataInVld", 38, 1 },
10960 { "PadIn", 37, 1 },
10961 { "RxBufEmpty", 36, 1 },
10962 { "RxDdp", 35, 1 },
10963 { "RxFbCongestion", 34, 1 },
10964 { "TxFbCongestion", 33, 1 },
10965 { "TxPktSumSrdy", 32, 1 },
10966 { "RcfUlpType", 28, 4 },
10967 { "Eread", 27, 1 },
10968 { "Ebypass", 26, 1 },
10969 { "Esave", 25, 1 },
10970 { "Static0", 24, 1 },
10971 { "Cread", 23, 1 },
10972 { "Cbypass", 22, 1 },
10973 { "Csave", 21, 1 },
10974 { "CPktOut", 20, 1 },
10975 { "RxPagePoolFull", 18, 2 },
10976 { "RxLpbkPkt", 17, 1 },
10977 { "TxLpbkPkt", 16, 1 },
10978 { "RxVfValid", 15, 1 },
10979 { "SynLearned", 14, 1 },
10980 { "SetDelEntry", 13, 1 },
10981 { "SetInvEntry", 12, 1 },
10982 { "CpcmdDvld", 11, 1 },
10983 { "CpcmdSave", 10, 1 },
10984 { "RxPstructsFull", 8, 2 },
10985 { "EpcmdDvld", 7, 1 },
10986 { "EpcmdFlush", 6, 1 },
10987 { "EpcmdTrimPrefix", 5, 1 },
10988 { "EpcmdTrimPostfix", 4, 1 },
10989 { "ERssIp4Pkt", 3, 1 },
10990 { "ERssIp6Pkt", 2, 1 },
10991 { "ERssTcpUdpPkt", 1, 1 },
10992 { "ERssFceFipPkt", 0, 1 },
10993 { NULL }
10994 };
10995
10996 static void
tp_la_show(struct sbuf * sb,uint64_t * p,int idx)10997 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
10998 {
10999
11000 field_desc_show(sb, *p, tp_la0);
11001 }
11002
11003 static void
tp_la_show2(struct sbuf * sb,uint64_t * p,int idx)11004 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
11005 {
11006
11007 if (idx)
11008 sbuf_printf(sb, "\n");
11009 field_desc_show(sb, p[0], tp_la0);
11010 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
11011 field_desc_show(sb, p[1], tp_la0);
11012 }
11013
11014 static void
tp_la_show3(struct sbuf * sb,uint64_t * p,int idx)11015 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
11016 {
11017
11018 if (idx)
11019 sbuf_printf(sb, "\n");
11020 field_desc_show(sb, p[0], tp_la0);
11021 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
11022 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
11023 }
11024
11025 static int
sysctl_tp_la(SYSCTL_HANDLER_ARGS)11026 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
11027 {
11028 struct adapter *sc = arg1;
11029 struct sbuf *sb;
11030 uint64_t *buf, *p;
11031 int rc;
11032 u_int i, inc;
11033 void (*show_func)(struct sbuf *, uint64_t *, int);
11034
11035 rc = sysctl_wire_old_buffer(req, 0);
11036 if (rc != 0)
11037 return (rc);
11038
11039 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11040 if (sb == NULL)
11041 return (ENOMEM);
11042
11043 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
11044
11045 mtx_lock(&sc->reg_lock);
11046 if (hw_off_limits(sc))
11047 rc = ENXIO;
11048 else {
11049 t4_tp_read_la(sc, buf, NULL);
11050 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
11051 case 2:
11052 inc = 2;
11053 show_func = tp_la_show2;
11054 break;
11055 case 3:
11056 inc = 2;
11057 show_func = tp_la_show3;
11058 break;
11059 default:
11060 inc = 1;
11061 show_func = tp_la_show;
11062 }
11063 }
11064 mtx_unlock(&sc->reg_lock);
11065 if (rc != 0)
11066 goto done;
11067
11068 p = buf;
11069 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
11070 (*show_func)(sb, p, i);
11071 rc = sbuf_finish(sb);
11072 done:
11073 sbuf_delete(sb);
11074 free(buf, M_CXGBE);
11075 return (rc);
11076 }
11077
11078 static int
sysctl_tx_rate(SYSCTL_HANDLER_ARGS)11079 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
11080 {
11081 struct adapter *sc = arg1;
11082 struct sbuf *sb;
11083 int rc;
11084 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
11085
11086 rc = sysctl_wire_old_buffer(req, 0);
11087 if (rc != 0)
11088 return (rc);
11089
11090 mtx_lock(&sc->reg_lock);
11091 if (hw_off_limits(sc))
11092 rc = ENXIO;
11093 else
11094 t4_get_chan_txrate(sc, nrate, orate);
11095 mtx_unlock(&sc->reg_lock);
11096 if (rc != 0)
11097 return (rc);
11098
11099 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11100 if (sb == NULL)
11101 return (ENOMEM);
11102
11103 if (sc->chip_params->nchan > 2) {
11104 sbuf_printf(sb, " channel 0 channel 1"
11105 " channel 2 channel 3\n");
11106 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
11107 nrate[0], nrate[1], nrate[2], nrate[3]);
11108 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
11109 orate[0], orate[1], orate[2], orate[3]);
11110 } else {
11111 sbuf_printf(sb, " channel 0 channel 1\n");
11112 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
11113 nrate[0], nrate[1]);
11114 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
11115 orate[0], orate[1]);
11116 }
11117
11118 rc = sbuf_finish(sb);
11119 sbuf_delete(sb);
11120
11121 return (rc);
11122 }
11123
11124 static int
sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)11125 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
11126 {
11127 struct adapter *sc = arg1;
11128 struct sbuf *sb;
11129 uint32_t *buf, *p;
11130 int rc, i;
11131
11132 rc = sysctl_wire_old_buffer(req, 0);
11133 if (rc != 0)
11134 return (rc);
11135
11136 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11137 if (sb == NULL)
11138 return (ENOMEM);
11139
11140 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
11141 M_ZERO | M_WAITOK);
11142
11143 mtx_lock(&sc->reg_lock);
11144 if (hw_off_limits(sc))
11145 rc = ENXIO;
11146 else
11147 t4_ulprx_read_la(sc, buf);
11148 mtx_unlock(&sc->reg_lock);
11149 if (rc != 0)
11150 goto done;
11151
11152 p = buf;
11153 sbuf_printf(sb, " Pcmd Type Message"
11154 " Data");
11155 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
11156 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
11157 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
11158 }
11159 rc = sbuf_finish(sb);
11160 done:
11161 sbuf_delete(sb);
11162 free(buf, M_CXGBE);
11163 return (rc);
11164 }
11165
11166 static int
sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)11167 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
11168 {
11169 struct adapter *sc = arg1;
11170 struct sbuf *sb;
11171 int rc;
11172 uint32_t cfg, s1, s2;
11173
11174 MPASS(chip_id(sc) >= CHELSIO_T5);
11175
11176 rc = sysctl_wire_old_buffer(req, 0);
11177 if (rc != 0)
11178 return (rc);
11179
11180 mtx_lock(&sc->reg_lock);
11181 if (hw_off_limits(sc))
11182 rc = ENXIO;
11183 else {
11184 cfg = t4_read_reg(sc, A_SGE_STAT_CFG);
11185 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL);
11186 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH);
11187 }
11188 mtx_unlock(&sc->reg_lock);
11189 if (rc != 0)
11190 return (rc);
11191
11192 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11193 if (sb == NULL)
11194 return (ENOMEM);
11195
11196 if (G_STATSOURCE_T5(cfg) == 7) {
11197 int mode;
11198
11199 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg);
11200 if (mode == 0)
11201 sbuf_printf(sb, "total %d, incomplete %d", s1, s2);
11202 else if (mode == 1)
11203 sbuf_printf(sb, "total %d, data overflow %d", s1, s2);
11204 else
11205 sbuf_printf(sb, "unknown mode %d", mode);
11206 }
11207 rc = sbuf_finish(sb);
11208 sbuf_delete(sb);
11209
11210 return (rc);
11211 }
11212
11213 static int
sysctl_cpus(SYSCTL_HANDLER_ARGS)11214 sysctl_cpus(SYSCTL_HANDLER_ARGS)
11215 {
11216 struct adapter *sc = arg1;
11217 enum cpu_sets op = arg2;
11218 cpuset_t cpuset;
11219 struct sbuf *sb;
11220 int i, rc;
11221
11222 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
11223
11224 CPU_ZERO(&cpuset);
11225 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
11226 if (rc != 0)
11227 return (rc);
11228
11229 rc = sysctl_wire_old_buffer(req, 0);
11230 if (rc != 0)
11231 return (rc);
11232
11233 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11234 if (sb == NULL)
11235 return (ENOMEM);
11236
11237 CPU_FOREACH(i)
11238 sbuf_printf(sb, "%d ", i);
11239 rc = sbuf_finish(sb);
11240 sbuf_delete(sb);
11241
11242 return (rc);
11243 }
11244
11245 static int
sysctl_reset(SYSCTL_HANDLER_ARGS)11246 sysctl_reset(SYSCTL_HANDLER_ARGS)
11247 {
11248 struct adapter *sc = arg1;
11249 u_int val;
11250 int rc;
11251
11252 val = atomic_load_int(&sc->num_resets);
11253 rc = sysctl_handle_int(oidp, &val, 0, req);
11254 if (rc != 0 || req->newptr == NULL)
11255 return (rc);
11256
11257 if (val == 0) {
11258 /* Zero out the counter that tracks reset. */
11259 atomic_store_int(&sc->num_resets, 0);
11260 return (0);
11261 }
11262
11263 if (val != 1)
11264 return (EINVAL); /* 0 or 1 are the only legal values */
11265
11266 if (hw_off_limits(sc)) /* harmless race */
11267 return (EALREADY);
11268
11269 taskqueue_enqueue(reset_tq, &sc->reset_task);
11270 return (0);
11271 }
11272
11273 #ifdef TCP_OFFLOAD
11274 static int
sysctl_tls(SYSCTL_HANDLER_ARGS)11275 sysctl_tls(SYSCTL_HANDLER_ARGS)
11276 {
11277 struct adapter *sc = arg1;
11278 int i, j, v, rc;
11279 struct vi_info *vi;
11280
11281 v = sc->tt.tls;
11282 rc = sysctl_handle_int(oidp, &v, 0, req);
11283 if (rc != 0 || req->newptr == NULL)
11284 return (rc);
11285
11286 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS))
11287 return (ENOTSUP);
11288
11289 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls");
11290 if (rc)
11291 return (rc);
11292 if (hw_off_limits(sc))
11293 rc = ENXIO;
11294 else {
11295 sc->tt.tls = !!v;
11296 for_each_port(sc, i) {
11297 for_each_vi(sc->port[i], j, vi) {
11298 if (vi->flags & VI_INIT_DONE)
11299 t4_update_fl_bufsize(vi->ifp);
11300 }
11301 }
11302 }
11303 end_synchronized_op(sc, 0);
11304
11305 return (rc);
11306
11307 }
11308
11309 static void
unit_conv(char * buf,size_t len,u_int val,u_int factor)11310 unit_conv(char *buf, size_t len, u_int val, u_int factor)
11311 {
11312 u_int rem = val % factor;
11313
11314 if (rem == 0)
11315 snprintf(buf, len, "%u", val / factor);
11316 else {
11317 while (rem % 10 == 0)
11318 rem /= 10;
11319 snprintf(buf, len, "%u.%u", val / factor, rem);
11320 }
11321 }
11322
11323 static int
sysctl_tp_tick(SYSCTL_HANDLER_ARGS)11324 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
11325 {
11326 struct adapter *sc = arg1;
11327 char buf[16];
11328 u_int res, re;
11329 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
11330
11331 mtx_lock(&sc->reg_lock);
11332 if (hw_off_limits(sc))
11333 res = (u_int)-1;
11334 else
11335 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
11336 mtx_unlock(&sc->reg_lock);
11337 if (res == (u_int)-1)
11338 return (ENXIO);
11339
11340 switch (arg2) {
11341 case 0:
11342 /* timer_tick */
11343 re = G_TIMERRESOLUTION(res);
11344 break;
11345 case 1:
11346 /* TCP timestamp tick */
11347 re = G_TIMESTAMPRESOLUTION(res);
11348 break;
11349 case 2:
11350 /* DACK tick */
11351 re = G_DELAYEDACKRESOLUTION(res);
11352 break;
11353 default:
11354 return (EDOOFUS);
11355 }
11356
11357 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
11358
11359 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
11360 }
11361
11362 static int
sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)11363 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
11364 {
11365 struct adapter *sc = arg1;
11366 int rc;
11367 u_int dack_tmr, dack_re, v;
11368 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
11369
11370 mtx_lock(&sc->reg_lock);
11371 if (hw_off_limits(sc))
11372 rc = ENXIO;
11373 else {
11374 rc = 0;
11375 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc,
11376 A_TP_TIMER_RESOLUTION));
11377 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER);
11378 }
11379 mtx_unlock(&sc->reg_lock);
11380 if (rc != 0)
11381 return (rc);
11382
11383 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr;
11384
11385 return (sysctl_handle_int(oidp, &v, 0, req));
11386 }
11387
11388 static int
sysctl_tp_timer(SYSCTL_HANDLER_ARGS)11389 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
11390 {
11391 struct adapter *sc = arg1;
11392 int rc, reg = arg2;
11393 u_int tre;
11394 u_long tp_tick_us, v;
11395 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
11396
11397 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
11398 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
11399 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
11400 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
11401
11402 mtx_lock(&sc->reg_lock);
11403 if (hw_off_limits(sc))
11404 rc = ENXIO;
11405 else {
11406 rc = 0;
11407 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
11408 tp_tick_us = (cclk_ps << tre) / 1000000;
11409 if (reg == A_TP_INIT_SRTT)
11410 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
11411 else
11412 v = tp_tick_us * t4_read_reg(sc, reg);
11413 }
11414 mtx_unlock(&sc->reg_lock);
11415 if (rc != 0)
11416 return (rc);
11417 else
11418 return (sysctl_handle_long(oidp, &v, 0, req));
11419 }
11420
11421 /*
11422 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
11423 * passed to this function.
11424 */
11425 static int
sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)11426 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
11427 {
11428 struct adapter *sc = arg1;
11429 int rc, idx = arg2;
11430 u_int v;
11431
11432 MPASS(idx >= 0 && idx <= 24);
11433
11434 mtx_lock(&sc->reg_lock);
11435 if (hw_off_limits(sc))
11436 rc = ENXIO;
11437 else {
11438 rc = 0;
11439 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
11440 }
11441 mtx_unlock(&sc->reg_lock);
11442 if (rc != 0)
11443 return (rc);
11444 else
11445 return (sysctl_handle_int(oidp, &v, 0, req));
11446 }
11447
11448 static int
sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)11449 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
11450 {
11451 struct adapter *sc = arg1;
11452 int rc, idx = arg2;
11453 u_int shift, v, r;
11454
11455 MPASS(idx >= 0 && idx < 16);
11456
11457 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
11458 shift = (idx & 3) << 3;
11459 mtx_lock(&sc->reg_lock);
11460 if (hw_off_limits(sc))
11461 rc = ENXIO;
11462 else {
11463 rc = 0;
11464 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
11465 }
11466 mtx_unlock(&sc->reg_lock);
11467 if (rc != 0)
11468 return (rc);
11469 else
11470 return (sysctl_handle_int(oidp, &v, 0, req));
11471 }
11472
11473 static int
sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)11474 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
11475 {
11476 struct vi_info *vi = arg1;
11477 struct adapter *sc = vi->adapter;
11478 int idx, rc, i;
11479 struct sge_ofld_rxq *ofld_rxq;
11480 uint8_t v;
11481
11482 idx = vi->ofld_tmr_idx;
11483
11484 rc = sysctl_handle_int(oidp, &idx, 0, req);
11485 if (rc != 0 || req->newptr == NULL)
11486 return (rc);
11487
11488 if (idx < 0 || idx >= SGE_NTIMERS)
11489 return (EINVAL);
11490
11491 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
11492 "t4otmr");
11493 if (rc)
11494 return (rc);
11495
11496 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
11497 for_each_ofld_rxq(vi, i, ofld_rxq) {
11498 #ifdef atomic_store_rel_8
11499 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
11500 #else
11501 ofld_rxq->iq.intr_params = v;
11502 #endif
11503 }
11504 vi->ofld_tmr_idx = idx;
11505
11506 end_synchronized_op(sc, LOCK_HELD);
11507 return (0);
11508 }
11509
11510 static int
sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)11511 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
11512 {
11513 struct vi_info *vi = arg1;
11514 struct adapter *sc = vi->adapter;
11515 int idx, rc;
11516
11517 idx = vi->ofld_pktc_idx;
11518
11519 rc = sysctl_handle_int(oidp, &idx, 0, req);
11520 if (rc != 0 || req->newptr == NULL)
11521 return (rc);
11522
11523 if (idx < -1 || idx >= SGE_NCOUNTERS)
11524 return (EINVAL);
11525
11526 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
11527 "t4opktc");
11528 if (rc)
11529 return (rc);
11530
11531 if (vi->flags & VI_INIT_DONE)
11532 rc = EBUSY; /* cannot be changed once the queues are created */
11533 else
11534 vi->ofld_pktc_idx = idx;
11535
11536 end_synchronized_op(sc, LOCK_HELD);
11537 return (rc);
11538 }
11539 #endif
11540
11541 static int
get_sge_context(struct adapter * sc,struct t4_sge_context * cntxt)11542 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
11543 {
11544 int rc;
11545
11546 if (cntxt->cid > M_CTXTQID)
11547 return (EINVAL);
11548
11549 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
11550 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
11551 return (EINVAL);
11552
11553 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
11554 if (rc)
11555 return (rc);
11556
11557 if (hw_off_limits(sc)) {
11558 rc = ENXIO;
11559 goto done;
11560 }
11561
11562 if (sc->flags & FW_OK) {
11563 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
11564 &cntxt->data[0]);
11565 if (rc == 0)
11566 goto done;
11567 }
11568
11569 /*
11570 * Read via firmware failed or wasn't even attempted. Read directly via
11571 * the backdoor.
11572 */
11573 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
11574 done:
11575 end_synchronized_op(sc, 0);
11576 return (rc);
11577 }
11578
11579 static int
load_fw(struct adapter * sc,struct t4_data * fw)11580 load_fw(struct adapter *sc, struct t4_data *fw)
11581 {
11582 int rc;
11583 uint8_t *fw_data;
11584
11585 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
11586 if (rc)
11587 return (rc);
11588
11589 if (hw_off_limits(sc)) {
11590 rc = ENXIO;
11591 goto done;
11592 }
11593
11594 /*
11595 * The firmware, with the sole exception of the memory parity error
11596 * handler, runs from memory and not flash. It is almost always safe to
11597 * install a new firmware on a running system. Just set bit 1 in
11598 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
11599 */
11600 if (sc->flags & FULL_INIT_DONE &&
11601 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
11602 rc = EBUSY;
11603 goto done;
11604 }
11605
11606 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
11607
11608 rc = copyin(fw->data, fw_data, fw->len);
11609 if (rc == 0)
11610 rc = -t4_load_fw(sc, fw_data, fw->len);
11611
11612 free(fw_data, M_CXGBE);
11613 done:
11614 end_synchronized_op(sc, 0);
11615 return (rc);
11616 }
11617
11618 static int
load_cfg(struct adapter * sc,struct t4_data * cfg)11619 load_cfg(struct adapter *sc, struct t4_data *cfg)
11620 {
11621 int rc;
11622 uint8_t *cfg_data = NULL;
11623
11624 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
11625 if (rc)
11626 return (rc);
11627
11628 if (hw_off_limits(sc)) {
11629 rc = ENXIO;
11630 goto done;
11631 }
11632
11633 if (cfg->len == 0) {
11634 /* clear */
11635 rc = -t4_load_cfg(sc, NULL, 0);
11636 goto done;
11637 }
11638
11639 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
11640
11641 rc = copyin(cfg->data, cfg_data, cfg->len);
11642 if (rc == 0)
11643 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
11644
11645 free(cfg_data, M_CXGBE);
11646 done:
11647 end_synchronized_op(sc, 0);
11648 return (rc);
11649 }
11650
11651 static int
load_boot(struct adapter * sc,struct t4_bootrom * br)11652 load_boot(struct adapter *sc, struct t4_bootrom *br)
11653 {
11654 int rc;
11655 uint8_t *br_data = NULL;
11656 u_int offset;
11657
11658 if (br->len > 1024 * 1024)
11659 return (EFBIG);
11660
11661 if (br->pf_offset == 0) {
11662 /* pfidx */
11663 if (br->pfidx_addr > 7)
11664 return (EINVAL);
11665 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
11666 A_PCIE_PF_EXPROM_OFST)));
11667 } else if (br->pf_offset == 1) {
11668 /* offset */
11669 offset = G_OFFSET(br->pfidx_addr);
11670 } else {
11671 return (EINVAL);
11672 }
11673
11674 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
11675 if (rc)
11676 return (rc);
11677
11678 if (hw_off_limits(sc)) {
11679 rc = ENXIO;
11680 goto done;
11681 }
11682
11683 if (br->len == 0) {
11684 /* clear */
11685 rc = -t4_load_boot(sc, NULL, offset, 0);
11686 goto done;
11687 }
11688
11689 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
11690
11691 rc = copyin(br->data, br_data, br->len);
11692 if (rc == 0)
11693 rc = -t4_load_boot(sc, br_data, offset, br->len);
11694
11695 free(br_data, M_CXGBE);
11696 done:
11697 end_synchronized_op(sc, 0);
11698 return (rc);
11699 }
11700
11701 static int
load_bootcfg(struct adapter * sc,struct t4_data * bc)11702 load_bootcfg(struct adapter *sc, struct t4_data *bc)
11703 {
11704 int rc;
11705 uint8_t *bc_data = NULL;
11706
11707 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
11708 if (rc)
11709 return (rc);
11710
11711 if (hw_off_limits(sc)) {
11712 rc = ENXIO;
11713 goto done;
11714 }
11715
11716 if (bc->len == 0) {
11717 /* clear */
11718 rc = -t4_load_bootcfg(sc, NULL, 0);
11719 goto done;
11720 }
11721
11722 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
11723
11724 rc = copyin(bc->data, bc_data, bc->len);
11725 if (rc == 0)
11726 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
11727
11728 free(bc_data, M_CXGBE);
11729 done:
11730 end_synchronized_op(sc, 0);
11731 return (rc);
11732 }
11733
11734 static int
cudbg_dump(struct adapter * sc,struct t4_cudbg_dump * dump)11735 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
11736 {
11737 int rc;
11738 struct cudbg_init *cudbg;
11739 void *handle, *buf;
11740
11741 /* buf is large, don't block if no memory is available */
11742 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
11743 if (buf == NULL)
11744 return (ENOMEM);
11745
11746 handle = cudbg_alloc_handle();
11747 if (handle == NULL) {
11748 rc = ENOMEM;
11749 goto done;
11750 }
11751
11752 cudbg = cudbg_get_init(handle);
11753 cudbg->adap = sc;
11754 cudbg->print = (cudbg_print_cb)printf;
11755
11756 #ifndef notyet
11757 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
11758 __func__, dump->wr_flash, dump->len, dump->data);
11759 #endif
11760
11761 if (dump->wr_flash)
11762 cudbg->use_flash = 1;
11763 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
11764 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
11765
11766 rc = cudbg_collect(handle, buf, &dump->len);
11767 if (rc != 0)
11768 goto done;
11769
11770 rc = copyout(buf, dump->data, dump->len);
11771 done:
11772 cudbg_free_handle(handle);
11773 free(buf, M_CXGBE);
11774 return (rc);
11775 }
11776
11777 static void
free_offload_policy(struct t4_offload_policy * op)11778 free_offload_policy(struct t4_offload_policy *op)
11779 {
11780 struct offload_rule *r;
11781 int i;
11782
11783 if (op == NULL)
11784 return;
11785
11786 r = &op->rule[0];
11787 for (i = 0; i < op->nrules; i++, r++) {
11788 free(r->bpf_prog.bf_insns, M_CXGBE);
11789 }
11790 free(op->rule, M_CXGBE);
11791 free(op, M_CXGBE);
11792 }
11793
11794 static int
set_offload_policy(struct adapter * sc,struct t4_offload_policy * uop)11795 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
11796 {
11797 int i, rc, len;
11798 struct t4_offload_policy *op, *old;
11799 struct bpf_program *bf;
11800 const struct offload_settings *s;
11801 struct offload_rule *r;
11802 void *u;
11803
11804 if (!is_offload(sc))
11805 return (ENODEV);
11806
11807 if (uop->nrules == 0) {
11808 /* Delete installed policies. */
11809 op = NULL;
11810 goto set_policy;
11811 } else if (uop->nrules > 256) { /* arbitrary */
11812 return (E2BIG);
11813 }
11814
11815 /* Copy userspace offload policy to kernel */
11816 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
11817 op->nrules = uop->nrules;
11818 len = op->nrules * sizeof(struct offload_rule);
11819 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
11820 rc = copyin(uop->rule, op->rule, len);
11821 if (rc) {
11822 free(op->rule, M_CXGBE);
11823 free(op, M_CXGBE);
11824 return (rc);
11825 }
11826
11827 r = &op->rule[0];
11828 for (i = 0; i < op->nrules; i++, r++) {
11829
11830 /* Validate open_type */
11831 if (r->open_type != OPEN_TYPE_LISTEN &&
11832 r->open_type != OPEN_TYPE_ACTIVE &&
11833 r->open_type != OPEN_TYPE_PASSIVE &&
11834 r->open_type != OPEN_TYPE_DONTCARE) {
11835 error:
11836 /*
11837 * Rules 0 to i have malloc'd filters that need to be
11838 * freed. Rules i+1 to nrules have userspace pointers
11839 * and should be left alone.
11840 */
11841 op->nrules = i;
11842 free_offload_policy(op);
11843 return (rc);
11844 }
11845
11846 /* Validate settings */
11847 s = &r->settings;
11848 if ((s->offload != 0 && s->offload != 1) ||
11849 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
11850 s->sched_class < -1 ||
11851 s->sched_class >= sc->params.nsched_cls) {
11852 rc = EINVAL;
11853 goto error;
11854 }
11855
11856 bf = &r->bpf_prog;
11857 u = bf->bf_insns; /* userspace ptr */
11858 bf->bf_insns = NULL;
11859 if (bf->bf_len == 0) {
11860 /* legal, matches everything */
11861 continue;
11862 }
11863 len = bf->bf_len * sizeof(*bf->bf_insns);
11864 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
11865 rc = copyin(u, bf->bf_insns, len);
11866 if (rc != 0)
11867 goto error;
11868
11869 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
11870 rc = EINVAL;
11871 goto error;
11872 }
11873 }
11874 set_policy:
11875 rw_wlock(&sc->policy_lock);
11876 old = sc->policy;
11877 sc->policy = op;
11878 rw_wunlock(&sc->policy_lock);
11879 free_offload_policy(old);
11880
11881 return (0);
11882 }
11883
11884 #define MAX_READ_BUF_SIZE (128 * 1024)
11885 static int
read_card_mem(struct adapter * sc,int win,struct t4_mem_range * mr)11886 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
11887 {
11888 uint32_t addr, remaining, n;
11889 uint32_t *buf;
11890 int rc;
11891 uint8_t *dst;
11892
11893 mtx_lock(&sc->reg_lock);
11894 if (hw_off_limits(sc))
11895 rc = ENXIO;
11896 else
11897 rc = validate_mem_range(sc, mr->addr, mr->len);
11898 mtx_unlock(&sc->reg_lock);
11899 if (rc != 0)
11900 return (rc);
11901
11902 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
11903 addr = mr->addr;
11904 remaining = mr->len;
11905 dst = (void *)mr->data;
11906
11907 while (remaining) {
11908 n = min(remaining, MAX_READ_BUF_SIZE);
11909 mtx_lock(&sc->reg_lock);
11910 if (hw_off_limits(sc))
11911 rc = ENXIO;
11912 else
11913 read_via_memwin(sc, 2, addr, buf, n);
11914 mtx_unlock(&sc->reg_lock);
11915 if (rc != 0)
11916 break;
11917
11918 rc = copyout(buf, dst, n);
11919 if (rc != 0)
11920 break;
11921
11922 dst += n;
11923 remaining -= n;
11924 addr += n;
11925 }
11926
11927 free(buf, M_CXGBE);
11928 return (rc);
11929 }
11930 #undef MAX_READ_BUF_SIZE
11931
11932 static int
read_i2c(struct adapter * sc,struct t4_i2c_data * i2cd)11933 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
11934 {
11935 int rc;
11936
11937 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
11938 return (EINVAL);
11939
11940 if (i2cd->len > sizeof(i2cd->data))
11941 return (EFBIG);
11942
11943 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
11944 if (rc)
11945 return (rc);
11946 if (hw_off_limits(sc))
11947 rc = ENXIO;
11948 else
11949 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
11950 i2cd->offset, i2cd->len, &i2cd->data[0]);
11951 end_synchronized_op(sc, 0);
11952
11953 return (rc);
11954 }
11955
11956 static int
clear_stats(struct adapter * sc,u_int port_id)11957 clear_stats(struct adapter *sc, u_int port_id)
11958 {
11959 int i, v, chan_map;
11960 struct port_info *pi;
11961 struct vi_info *vi;
11962 struct sge_rxq *rxq;
11963 struct sge_txq *txq;
11964 struct sge_wrq *wrq;
11965 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
11966 struct sge_ofld_txq *ofld_txq;
11967 #endif
11968 #ifdef TCP_OFFLOAD
11969 struct sge_ofld_rxq *ofld_rxq;
11970 #endif
11971
11972 if (port_id >= sc->params.nports)
11973 return (EINVAL);
11974 pi = sc->port[port_id];
11975 if (pi == NULL)
11976 return (EIO);
11977
11978 mtx_lock(&sc->reg_lock);
11979 if (!hw_off_limits(sc)) {
11980 /* MAC stats */
11981 t4_clr_port_stats(sc, pi->tx_chan);
11982 if (is_t6(sc)) {
11983 if (pi->fcs_reg != -1)
11984 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg);
11985 else
11986 pi->stats.rx_fcs_err = 0;
11987 }
11988 for_each_vi(pi, v, vi) {
11989 if (vi->flags & VI_INIT_DONE)
11990 t4_clr_vi_stats(sc, vi->vin);
11991 }
11992 chan_map = pi->rx_e_chan_map;
11993 v = 0; /* reuse */
11994 while (chan_map) {
11995 i = ffs(chan_map) - 1;
11996 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
11997 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
11998 chan_map &= ~(1 << i);
11999 }
12000 }
12001 mtx_unlock(&sc->reg_lock);
12002 pi->tx_parse_error = 0;
12003 pi->tnl_cong_drops = 0;
12004
12005 /*
12006 * Since this command accepts a port, clear stats for
12007 * all VIs on this port.
12008 */
12009 for_each_vi(pi, v, vi) {
12010 if (vi->flags & VI_INIT_DONE) {
12011
12012 for_each_rxq(vi, i, rxq) {
12013 #if defined(INET) || defined(INET6)
12014 rxq->lro.lro_queued = 0;
12015 rxq->lro.lro_flushed = 0;
12016 #endif
12017 rxq->rxcsum = 0;
12018 rxq->vlan_extraction = 0;
12019 rxq->vxlan_rxcsum = 0;
12020
12021 rxq->fl.cl_allocated = 0;
12022 rxq->fl.cl_recycled = 0;
12023 rxq->fl.cl_fast_recycled = 0;
12024 }
12025
12026 for_each_txq(vi, i, txq) {
12027 txq->txcsum = 0;
12028 txq->tso_wrs = 0;
12029 txq->vlan_insertion = 0;
12030 txq->imm_wrs = 0;
12031 txq->sgl_wrs = 0;
12032 txq->txpkt_wrs = 0;
12033 txq->txpkts0_wrs = 0;
12034 txq->txpkts1_wrs = 0;
12035 txq->txpkts0_pkts = 0;
12036 txq->txpkts1_pkts = 0;
12037 txq->txpkts_flush = 0;
12038 txq->raw_wrs = 0;
12039 txq->vxlan_tso_wrs = 0;
12040 txq->vxlan_txcsum = 0;
12041 txq->kern_tls_records = 0;
12042 txq->kern_tls_short = 0;
12043 txq->kern_tls_partial = 0;
12044 txq->kern_tls_full = 0;
12045 txq->kern_tls_octets = 0;
12046 txq->kern_tls_waste = 0;
12047 txq->kern_tls_options = 0;
12048 txq->kern_tls_header = 0;
12049 txq->kern_tls_fin = 0;
12050 txq->kern_tls_fin_short = 0;
12051 txq->kern_tls_cbc = 0;
12052 txq->kern_tls_gcm = 0;
12053 mp_ring_reset_stats(txq->r);
12054 }
12055
12056 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12057 for_each_ofld_txq(vi, i, ofld_txq) {
12058 ofld_txq->wrq.tx_wrs_direct = 0;
12059 ofld_txq->wrq.tx_wrs_copied = 0;
12060 counter_u64_zero(ofld_txq->tx_iscsi_pdus);
12061 counter_u64_zero(ofld_txq->tx_iscsi_octets);
12062 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs);
12063 counter_u64_zero(ofld_txq->tx_aio_jobs);
12064 counter_u64_zero(ofld_txq->tx_aio_octets);
12065 counter_u64_zero(ofld_txq->tx_toe_tls_records);
12066 counter_u64_zero(ofld_txq->tx_toe_tls_octets);
12067 }
12068 #endif
12069 #ifdef TCP_OFFLOAD
12070 for_each_ofld_rxq(vi, i, ofld_rxq) {
12071 ofld_rxq->fl.cl_allocated = 0;
12072 ofld_rxq->fl.cl_recycled = 0;
12073 ofld_rxq->fl.cl_fast_recycled = 0;
12074 counter_u64_zero(
12075 ofld_rxq->rx_iscsi_ddp_setup_ok);
12076 counter_u64_zero(
12077 ofld_rxq->rx_iscsi_ddp_setup_error);
12078 ofld_rxq->rx_iscsi_ddp_pdus = 0;
12079 ofld_rxq->rx_iscsi_ddp_octets = 0;
12080 ofld_rxq->rx_iscsi_fl_pdus = 0;
12081 ofld_rxq->rx_iscsi_fl_octets = 0;
12082 ofld_rxq->rx_aio_ddp_jobs = 0;
12083 ofld_rxq->rx_aio_ddp_octets = 0;
12084 ofld_rxq->rx_toe_tls_records = 0;
12085 ofld_rxq->rx_toe_tls_octets = 0;
12086 ofld_rxq->rx_toe_ddp_octets = 0;
12087 counter_u64_zero(ofld_rxq->ddp_buffer_alloc);
12088 counter_u64_zero(ofld_rxq->ddp_buffer_reuse);
12089 counter_u64_zero(ofld_rxq->ddp_buffer_free);
12090 }
12091 #endif
12092
12093 if (IS_MAIN_VI(vi)) {
12094 wrq = &sc->sge.ctrlq[pi->port_id];
12095 wrq->tx_wrs_direct = 0;
12096 wrq->tx_wrs_copied = 0;
12097 }
12098 }
12099 }
12100
12101 return (0);
12102 }
12103
12104 static int
hold_clip_addr(struct adapter * sc,struct t4_clip_addr * ca)12105 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
12106 {
12107 #ifdef INET6
12108 struct in6_addr in6;
12109
12110 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
12111 if (t4_get_clip_entry(sc, &in6, true) != NULL)
12112 return (0);
12113 else
12114 return (EIO);
12115 #else
12116 return (ENOTSUP);
12117 #endif
12118 }
12119
12120 static int
release_clip_addr(struct adapter * sc,struct t4_clip_addr * ca)12121 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
12122 {
12123 #ifdef INET6
12124 struct in6_addr in6;
12125
12126 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
12127 return (t4_release_clip_addr(sc, &in6));
12128 #else
12129 return (ENOTSUP);
12130 #endif
12131 }
12132
12133 int
t4_os_find_pci_capability(struct adapter * sc,int cap)12134 t4_os_find_pci_capability(struct adapter *sc, int cap)
12135 {
12136 int i;
12137
12138 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
12139 }
12140
12141 int
t4_os_pci_save_state(struct adapter * sc)12142 t4_os_pci_save_state(struct adapter *sc)
12143 {
12144 device_t dev;
12145 struct pci_devinfo *dinfo;
12146
12147 dev = sc->dev;
12148 dinfo = device_get_ivars(dev);
12149
12150 pci_cfg_save(dev, dinfo, 0);
12151 return (0);
12152 }
12153
12154 int
t4_os_pci_restore_state(struct adapter * sc)12155 t4_os_pci_restore_state(struct adapter *sc)
12156 {
12157 device_t dev;
12158 struct pci_devinfo *dinfo;
12159
12160 dev = sc->dev;
12161 dinfo = device_get_ivars(dev);
12162
12163 pci_cfg_restore(dev, dinfo);
12164 return (0);
12165 }
12166
12167 void
t4_os_portmod_changed(struct port_info * pi)12168 t4_os_portmod_changed(struct port_info *pi)
12169 {
12170 struct adapter *sc = pi->adapter;
12171 struct vi_info *vi;
12172 if_t ifp;
12173 static const char *mod_str[] = {
12174 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
12175 };
12176
12177 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
12178 ("%s: port_type %u", __func__, pi->port_type));
12179
12180 vi = &pi->vi[0];
12181 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
12182 PORT_LOCK(pi);
12183 build_medialist(pi);
12184 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
12185 fixup_link_config(pi);
12186 apply_link_config(pi);
12187 }
12188 PORT_UNLOCK(pi);
12189 end_synchronized_op(sc, LOCK_HELD);
12190 }
12191
12192 ifp = vi->ifp;
12193 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
12194 if_printf(ifp, "transceiver unplugged.\n");
12195 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
12196 if_printf(ifp, "unknown transceiver inserted.\n");
12197 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
12198 if_printf(ifp, "unsupported transceiver inserted.\n");
12199 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
12200 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
12201 port_top_speed(pi), mod_str[pi->mod_type]);
12202 } else {
12203 if_printf(ifp, "transceiver (type %d) inserted.\n",
12204 pi->mod_type);
12205 }
12206 }
12207
12208 void
t4_os_link_changed(struct port_info * pi)12209 t4_os_link_changed(struct port_info *pi)
12210 {
12211 struct vi_info *vi;
12212 if_t ifp;
12213 struct link_config *lc = &pi->link_cfg;
12214 struct adapter *sc = pi->adapter;
12215 int v;
12216
12217 PORT_LOCK_ASSERT_OWNED(pi);
12218
12219 if (is_t6(sc)) {
12220 if (lc->link_ok) {
12221 if (lc->speed > 25000 ||
12222 (lc->speed == 25000 && lc->fec == FEC_RS)) {
12223 pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
12224 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS);
12225 } else {
12226 pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
12227 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS);
12228 }
12229 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg);
12230 pi->stats.rx_fcs_err = 0;
12231 } else {
12232 pi->fcs_reg = -1;
12233 }
12234 } else {
12235 MPASS(pi->fcs_reg != -1);
12236 MPASS(pi->fcs_base == 0);
12237 }
12238
12239 for_each_vi(pi, v, vi) {
12240 ifp = vi->ifp;
12241 if (ifp == NULL)
12242 continue;
12243
12244 if (lc->link_ok) {
12245 if_setbaudrate(ifp, IF_Mbps(lc->speed));
12246 if_link_state_change(ifp, LINK_STATE_UP);
12247 } else {
12248 if_link_state_change(ifp, LINK_STATE_DOWN);
12249 }
12250 }
12251 }
12252
12253 void
t4_iterate(void (* func)(struct adapter *,void *),void * arg)12254 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
12255 {
12256 struct adapter *sc;
12257
12258 sx_slock(&t4_list_lock);
12259 SLIST_FOREACH(sc, &t4_list, link) {
12260 /*
12261 * func should not make any assumptions about what state sc is
12262 * in - the only guarantee is that sc->sc_lock is a valid lock.
12263 */
12264 func(sc, arg);
12265 }
12266 sx_sunlock(&t4_list_lock);
12267 }
12268
12269 static int
t4_ioctl(struct cdev * dev,unsigned long cmd,caddr_t data,int fflag,struct thread * td)12270 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
12271 struct thread *td)
12272 {
12273 int rc;
12274 struct adapter *sc = dev->si_drv1;
12275
12276 rc = priv_check(td, PRIV_DRIVER);
12277 if (rc != 0)
12278 return (rc);
12279
12280 switch (cmd) {
12281 case CHELSIO_T4_GETREG: {
12282 struct t4_reg *edata = (struct t4_reg *)data;
12283
12284 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
12285 return (EFAULT);
12286
12287 mtx_lock(&sc->reg_lock);
12288 if (hw_off_limits(sc))
12289 rc = ENXIO;
12290 else if (edata->size == 4)
12291 edata->val = t4_read_reg(sc, edata->addr);
12292 else if (edata->size == 8)
12293 edata->val = t4_read_reg64(sc, edata->addr);
12294 else
12295 rc = EINVAL;
12296 mtx_unlock(&sc->reg_lock);
12297
12298 break;
12299 }
12300 case CHELSIO_T4_SETREG: {
12301 struct t4_reg *edata = (struct t4_reg *)data;
12302
12303 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
12304 return (EFAULT);
12305
12306 mtx_lock(&sc->reg_lock);
12307 if (hw_off_limits(sc))
12308 rc = ENXIO;
12309 else if (edata->size == 4) {
12310 if (edata->val & 0xffffffff00000000)
12311 rc = EINVAL;
12312 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
12313 } else if (edata->size == 8)
12314 t4_write_reg64(sc, edata->addr, edata->val);
12315 else
12316 rc = EINVAL;
12317 mtx_unlock(&sc->reg_lock);
12318
12319 break;
12320 }
12321 case CHELSIO_T4_REGDUMP: {
12322 struct t4_regdump *regs = (struct t4_regdump *)data;
12323 int reglen = t4_get_regs_len(sc);
12324 uint8_t *buf;
12325
12326 if (regs->len < reglen) {
12327 regs->len = reglen; /* hint to the caller */
12328 return (ENOBUFS);
12329 }
12330
12331 regs->len = reglen;
12332 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
12333 mtx_lock(&sc->reg_lock);
12334 if (hw_off_limits(sc))
12335 rc = ENXIO;
12336 else
12337 get_regs(sc, regs, buf);
12338 mtx_unlock(&sc->reg_lock);
12339 if (rc == 0)
12340 rc = copyout(buf, regs->data, reglen);
12341 free(buf, M_CXGBE);
12342 break;
12343 }
12344 case CHELSIO_T4_GET_FILTER_MODE:
12345 rc = get_filter_mode(sc, (uint32_t *)data);
12346 break;
12347 case CHELSIO_T4_SET_FILTER_MODE:
12348 rc = set_filter_mode(sc, *(uint32_t *)data);
12349 break;
12350 case CHELSIO_T4_SET_FILTER_MASK:
12351 rc = set_filter_mask(sc, *(uint32_t *)data);
12352 break;
12353 case CHELSIO_T4_GET_FILTER:
12354 rc = get_filter(sc, (struct t4_filter *)data);
12355 break;
12356 case CHELSIO_T4_SET_FILTER:
12357 rc = set_filter(sc, (struct t4_filter *)data);
12358 break;
12359 case CHELSIO_T4_DEL_FILTER:
12360 rc = del_filter(sc, (struct t4_filter *)data);
12361 break;
12362 case CHELSIO_T4_GET_SGE_CONTEXT:
12363 rc = get_sge_context(sc, (struct t4_sge_context *)data);
12364 break;
12365 case CHELSIO_T4_LOAD_FW:
12366 rc = load_fw(sc, (struct t4_data *)data);
12367 break;
12368 case CHELSIO_T4_GET_MEM:
12369 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
12370 break;
12371 case CHELSIO_T4_GET_I2C:
12372 rc = read_i2c(sc, (struct t4_i2c_data *)data);
12373 break;
12374 case CHELSIO_T4_CLEAR_STATS:
12375 rc = clear_stats(sc, *(uint32_t *)data);
12376 break;
12377 case CHELSIO_T4_SCHED_CLASS:
12378 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
12379 break;
12380 case CHELSIO_T4_SCHED_QUEUE:
12381 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
12382 break;
12383 case CHELSIO_T4_GET_TRACER:
12384 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
12385 break;
12386 case CHELSIO_T4_SET_TRACER:
12387 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
12388 break;
12389 case CHELSIO_T4_LOAD_CFG:
12390 rc = load_cfg(sc, (struct t4_data *)data);
12391 break;
12392 case CHELSIO_T4_LOAD_BOOT:
12393 rc = load_boot(sc, (struct t4_bootrom *)data);
12394 break;
12395 case CHELSIO_T4_LOAD_BOOTCFG:
12396 rc = load_bootcfg(sc, (struct t4_data *)data);
12397 break;
12398 case CHELSIO_T4_CUDBG_DUMP:
12399 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
12400 break;
12401 case CHELSIO_T4_SET_OFLD_POLICY:
12402 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
12403 break;
12404 case CHELSIO_T4_HOLD_CLIP_ADDR:
12405 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data);
12406 break;
12407 case CHELSIO_T4_RELEASE_CLIP_ADDR:
12408 rc = release_clip_addr(sc, (struct t4_clip_addr *)data);
12409 break;
12410 default:
12411 rc = ENOTTY;
12412 }
12413
12414 return (rc);
12415 }
12416
12417 #ifdef TCP_OFFLOAD
12418 static int
toe_capability(struct vi_info * vi,bool enable)12419 toe_capability(struct vi_info *vi, bool enable)
12420 {
12421 int rc;
12422 struct port_info *pi = vi->pi;
12423 struct adapter *sc = pi->adapter;
12424
12425 ASSERT_SYNCHRONIZED_OP(sc);
12426
12427 if (!is_offload(sc))
12428 return (ENODEV);
12429 if (hw_off_limits(sc))
12430 return (ENXIO);
12431
12432 if (enable) {
12433 #ifdef KERN_TLS
12434 if (sc->flags & KERN_TLS_ON && is_t6(sc)) {
12435 int i, j, n;
12436 struct port_info *p;
12437 struct vi_info *v;
12438
12439 /*
12440 * Reconfigure hardware for TOE if TXTLS is not enabled
12441 * on any ifnet.
12442 */
12443 n = 0;
12444 for_each_port(sc, i) {
12445 p = sc->port[i];
12446 for_each_vi(p, j, v) {
12447 if (if_getcapenable(v->ifp) & IFCAP_TXTLS) {
12448 CH_WARN(sc,
12449 "%s has NIC TLS enabled.\n",
12450 device_get_nameunit(v->dev));
12451 n++;
12452 }
12453 }
12454 }
12455 if (n > 0) {
12456 CH_WARN(sc, "Disable NIC TLS on all interfaces "
12457 "associated with this adapter before "
12458 "trying to enable TOE.\n");
12459 return (EAGAIN);
12460 }
12461 rc = t6_config_kern_tls(sc, false);
12462 if (rc)
12463 return (rc);
12464 }
12465 #endif
12466 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) {
12467 /* TOE is already enabled. */
12468 return (0);
12469 }
12470
12471 /*
12472 * We need the port's queues around so that we're able to send
12473 * and receive CPLs to/from the TOE even if the ifnet for this
12474 * port has never been UP'd administratively.
12475 */
12476 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
12477 return (rc);
12478 if (!(pi->vi[0].flags & VI_INIT_DONE) &&
12479 ((rc = vi_init(&pi->vi[0])) != 0))
12480 return (rc);
12481
12482 if (isset(&sc->offload_map, pi->port_id)) {
12483 /* TOE is enabled on another VI of this port. */
12484 pi->uld_vis++;
12485 return (0);
12486 }
12487
12488 if (!uld_active(sc, ULD_TOM)) {
12489 rc = t4_activate_uld(sc, ULD_TOM);
12490 if (rc == EAGAIN) {
12491 log(LOG_WARNING,
12492 "You must kldload t4_tom.ko before trying "
12493 "to enable TOE on a cxgbe interface.\n");
12494 }
12495 if (rc != 0)
12496 return (rc);
12497 KASSERT(sc->tom_softc != NULL,
12498 ("%s: TOM activated but softc NULL", __func__));
12499 KASSERT(uld_active(sc, ULD_TOM),
12500 ("%s: TOM activated but flag not set", __func__));
12501 }
12502
12503 /* Activate iWARP and iSCSI too, if the modules are loaded. */
12504 if (!uld_active(sc, ULD_IWARP))
12505 (void) t4_activate_uld(sc, ULD_IWARP);
12506 if (!uld_active(sc, ULD_ISCSI))
12507 (void) t4_activate_uld(sc, ULD_ISCSI);
12508
12509 pi->uld_vis++;
12510 setbit(&sc->offload_map, pi->port_id);
12511 } else {
12512 pi->uld_vis--;
12513
12514 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
12515 return (0);
12516
12517 KASSERT(uld_active(sc, ULD_TOM),
12518 ("%s: TOM never initialized?", __func__));
12519 clrbit(&sc->offload_map, pi->port_id);
12520 }
12521
12522 return (0);
12523 }
12524
12525 /*
12526 * Add an upper layer driver to the global list.
12527 */
12528 int
t4_register_uld(struct uld_info * ui)12529 t4_register_uld(struct uld_info *ui)
12530 {
12531 int rc = 0;
12532 struct uld_info *u;
12533
12534 sx_xlock(&t4_uld_list_lock);
12535 SLIST_FOREACH(u, &t4_uld_list, link) {
12536 if (u->uld_id == ui->uld_id) {
12537 rc = EEXIST;
12538 goto done;
12539 }
12540 }
12541
12542 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
12543 ui->refcount = 0;
12544 done:
12545 sx_xunlock(&t4_uld_list_lock);
12546 return (rc);
12547 }
12548
12549 int
t4_unregister_uld(struct uld_info * ui)12550 t4_unregister_uld(struct uld_info *ui)
12551 {
12552 int rc = EINVAL;
12553 struct uld_info *u;
12554
12555 sx_xlock(&t4_uld_list_lock);
12556
12557 SLIST_FOREACH(u, &t4_uld_list, link) {
12558 if (u == ui) {
12559 if (ui->refcount > 0) {
12560 rc = EBUSY;
12561 goto done;
12562 }
12563
12564 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
12565 rc = 0;
12566 goto done;
12567 }
12568 }
12569 done:
12570 sx_xunlock(&t4_uld_list_lock);
12571 return (rc);
12572 }
12573
12574 int
t4_activate_uld(struct adapter * sc,int id)12575 t4_activate_uld(struct adapter *sc, int id)
12576 {
12577 int rc;
12578 struct uld_info *ui;
12579
12580 ASSERT_SYNCHRONIZED_OP(sc);
12581
12582 if (id < 0 || id > ULD_MAX)
12583 return (EINVAL);
12584 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
12585
12586 sx_slock(&t4_uld_list_lock);
12587
12588 SLIST_FOREACH(ui, &t4_uld_list, link) {
12589 if (ui->uld_id == id) {
12590 if (!(sc->flags & FULL_INIT_DONE)) {
12591 rc = adapter_init(sc);
12592 if (rc != 0)
12593 break;
12594 }
12595
12596 rc = ui->activate(sc);
12597 if (rc == 0) {
12598 setbit(&sc->active_ulds, id);
12599 ui->refcount++;
12600 }
12601 break;
12602 }
12603 }
12604
12605 sx_sunlock(&t4_uld_list_lock);
12606
12607 return (rc);
12608 }
12609
12610 int
t4_deactivate_uld(struct adapter * sc,int id)12611 t4_deactivate_uld(struct adapter *sc, int id)
12612 {
12613 int rc;
12614 struct uld_info *ui;
12615
12616 ASSERT_SYNCHRONIZED_OP(sc);
12617
12618 if (id < 0 || id > ULD_MAX)
12619 return (EINVAL);
12620 rc = ENXIO;
12621
12622 sx_slock(&t4_uld_list_lock);
12623
12624 SLIST_FOREACH(ui, &t4_uld_list, link) {
12625 if (ui->uld_id == id) {
12626 rc = ui->deactivate(sc);
12627 if (rc == 0) {
12628 clrbit(&sc->active_ulds, id);
12629 ui->refcount--;
12630 }
12631 break;
12632 }
12633 }
12634
12635 sx_sunlock(&t4_uld_list_lock);
12636
12637 return (rc);
12638 }
12639
12640 static int
t4_deactivate_all_uld(struct adapter * sc)12641 t4_deactivate_all_uld(struct adapter *sc)
12642 {
12643 int rc;
12644 struct uld_info *ui;
12645
12646 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld");
12647 if (rc != 0)
12648 return (ENXIO);
12649
12650 sx_slock(&t4_uld_list_lock);
12651
12652 SLIST_FOREACH(ui, &t4_uld_list, link) {
12653 if (isset(&sc->active_ulds, ui->uld_id)) {
12654 rc = ui->deactivate(sc);
12655 if (rc != 0)
12656 break;
12657 clrbit(&sc->active_ulds, ui->uld_id);
12658 ui->refcount--;
12659 }
12660 }
12661
12662 sx_sunlock(&t4_uld_list_lock);
12663 end_synchronized_op(sc, 0);
12664
12665 return (rc);
12666 }
12667
12668 static void
t4_async_event(struct adapter * sc)12669 t4_async_event(struct adapter *sc)
12670 {
12671 struct uld_info *ui;
12672
12673 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0)
12674 return;
12675 sx_slock(&t4_uld_list_lock);
12676 SLIST_FOREACH(ui, &t4_uld_list, link) {
12677 if (ui->uld_id == ULD_IWARP) {
12678 ui->async_event(sc);
12679 break;
12680 }
12681 }
12682 sx_sunlock(&t4_uld_list_lock);
12683 end_synchronized_op(sc, 0);
12684 }
12685
12686 int
uld_active(struct adapter * sc,int uld_id)12687 uld_active(struct adapter *sc, int uld_id)
12688 {
12689
12690 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
12691
12692 return (isset(&sc->active_ulds, uld_id));
12693 }
12694 #endif
12695
12696 #ifdef KERN_TLS
12697 static int
ktls_capability(struct adapter * sc,bool enable)12698 ktls_capability(struct adapter *sc, bool enable)
12699 {
12700 ASSERT_SYNCHRONIZED_OP(sc);
12701
12702 if (!is_ktls(sc))
12703 return (ENODEV);
12704 if (!is_t6(sc))
12705 return (0);
12706 if (hw_off_limits(sc))
12707 return (ENXIO);
12708
12709 if (enable) {
12710 if (sc->flags & KERN_TLS_ON)
12711 return (0); /* already on */
12712 if (sc->offload_map != 0) {
12713 CH_WARN(sc,
12714 "Disable TOE on all interfaces associated with "
12715 "this adapter before trying to enable NIC TLS.\n");
12716 return (EAGAIN);
12717 }
12718 return (t6_config_kern_tls(sc, true));
12719 } else {
12720 /*
12721 * Nothing to do for disable. If TOE is enabled sometime later
12722 * then toe_capability will reconfigure the hardware.
12723 */
12724 return (0);
12725 }
12726 }
12727 #endif
12728
12729 /*
12730 * t = ptr to tunable.
12731 * nc = number of CPUs.
12732 * c = compiled in default for that tunable.
12733 */
12734 static void
calculate_nqueues(int * t,int nc,const int c)12735 calculate_nqueues(int *t, int nc, const int c)
12736 {
12737 int nq;
12738
12739 if (*t > 0)
12740 return;
12741 nq = *t < 0 ? -*t : c;
12742 *t = min(nc, nq);
12743 }
12744
12745 /*
12746 * Come up with reasonable defaults for some of the tunables, provided they're
12747 * not set by the user (in which case we'll use the values as is).
12748 */
12749 static void
tweak_tunables(void)12750 tweak_tunables(void)
12751 {
12752 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
12753
12754 if (t4_ntxq < 1) {
12755 #ifdef RSS
12756 t4_ntxq = rss_getnumbuckets();
12757 #else
12758 calculate_nqueues(&t4_ntxq, nc, NTXQ);
12759 #endif
12760 }
12761
12762 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
12763
12764 if (t4_nrxq < 1) {
12765 #ifdef RSS
12766 t4_nrxq = rss_getnumbuckets();
12767 #else
12768 calculate_nqueues(&t4_nrxq, nc, NRXQ);
12769 #endif
12770 }
12771
12772 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
12773
12774 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12775 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
12776 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
12777 #endif
12778 #ifdef TCP_OFFLOAD
12779 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
12780 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
12781 #endif
12782
12783 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
12784 if (t4_toecaps_allowed == -1)
12785 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
12786 #else
12787 if (t4_toecaps_allowed == -1)
12788 t4_toecaps_allowed = 0;
12789 #endif
12790
12791 #ifdef TCP_OFFLOAD
12792 if (t4_rdmacaps_allowed == -1) {
12793 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
12794 FW_CAPS_CONFIG_RDMA_RDMAC;
12795 }
12796
12797 if (t4_iscsicaps_allowed == -1) {
12798 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
12799 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
12800 FW_CAPS_CONFIG_ISCSI_T10DIF;
12801 }
12802
12803 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
12804 t4_tmr_idx_ofld = TMR_IDX_OFLD;
12805
12806 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
12807 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
12808 #else
12809 if (t4_rdmacaps_allowed == -1)
12810 t4_rdmacaps_allowed = 0;
12811
12812 if (t4_iscsicaps_allowed == -1)
12813 t4_iscsicaps_allowed = 0;
12814 #endif
12815
12816 #ifdef DEV_NETMAP
12817 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
12818 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
12819 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
12820 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
12821 #endif
12822
12823 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
12824 t4_tmr_idx = TMR_IDX;
12825
12826 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
12827 t4_pktc_idx = PKTC_IDX;
12828
12829 if (t4_qsize_txq < 128)
12830 t4_qsize_txq = 128;
12831
12832 if (t4_qsize_rxq < 128)
12833 t4_qsize_rxq = 128;
12834 while (t4_qsize_rxq & 7)
12835 t4_qsize_rxq++;
12836
12837 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
12838
12839 /*
12840 * Number of VIs to create per-port. The first VI is the "main" regular
12841 * VI for the port. The rest are additional virtual interfaces on the
12842 * same physical port. Note that the main VI does not have native
12843 * netmap support but the extra VIs do.
12844 *
12845 * Limit the number of VIs per port to the number of available
12846 * MAC addresses per port.
12847 */
12848 if (t4_num_vis < 1)
12849 t4_num_vis = 1;
12850 if (t4_num_vis > nitems(vi_mac_funcs)) {
12851 t4_num_vis = nitems(vi_mac_funcs);
12852 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
12853 }
12854
12855 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
12856 pcie_relaxed_ordering = 1;
12857 #if defined(__i386__) || defined(__amd64__)
12858 if (cpu_vendor_id == CPU_VENDOR_INTEL)
12859 pcie_relaxed_ordering = 0;
12860 #endif
12861 }
12862 }
12863
12864 #ifdef DDB
12865 static void
t4_dump_tcb(struct adapter * sc,int tid)12866 t4_dump_tcb(struct adapter *sc, int tid)
12867 {
12868 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
12869
12870 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
12871 save = t4_read_reg(sc, reg);
12872 base = sc->memwin[2].mw_base;
12873
12874 /* Dump TCB for the tid */
12875 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
12876 tcb_addr += tid * TCB_SIZE;
12877
12878 if (is_t4(sc)) {
12879 pf = 0;
12880 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
12881 } else {
12882 pf = V_PFNUM(sc->pf);
12883 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
12884 }
12885 t4_write_reg(sc, reg, win_pos | pf);
12886 t4_read_reg(sc, reg);
12887
12888 off = tcb_addr - win_pos;
12889 for (i = 0; i < 4; i++) {
12890 uint32_t buf[8];
12891 for (j = 0; j < 8; j++, off += 4)
12892 buf[j] = htonl(t4_read_reg(sc, base + off));
12893
12894 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
12895 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
12896 buf[7]);
12897 }
12898
12899 t4_write_reg(sc, reg, save);
12900 t4_read_reg(sc, reg);
12901 }
12902
12903 static void
t4_dump_devlog(struct adapter * sc)12904 t4_dump_devlog(struct adapter *sc)
12905 {
12906 struct devlog_params *dparams = &sc->params.devlog;
12907 struct fw_devlog_e e;
12908 int i, first, j, m, nentries, rc;
12909 uint64_t ftstamp = UINT64_MAX;
12910
12911 if (dparams->start == 0) {
12912 db_printf("devlog params not valid\n");
12913 return;
12914 }
12915
12916 nentries = dparams->size / sizeof(struct fw_devlog_e);
12917 m = fwmtype_to_hwmtype(dparams->memtype);
12918
12919 /* Find the first entry. */
12920 first = -1;
12921 for (i = 0; i < nentries && !db_pager_quit; i++) {
12922 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
12923 sizeof(e), (void *)&e);
12924 if (rc != 0)
12925 break;
12926
12927 if (e.timestamp == 0)
12928 break;
12929
12930 e.timestamp = be64toh(e.timestamp);
12931 if (e.timestamp < ftstamp) {
12932 ftstamp = e.timestamp;
12933 first = i;
12934 }
12935 }
12936
12937 if (first == -1)
12938 return;
12939
12940 i = first;
12941 do {
12942 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
12943 sizeof(e), (void *)&e);
12944 if (rc != 0)
12945 return;
12946
12947 if (e.timestamp == 0)
12948 return;
12949
12950 e.timestamp = be64toh(e.timestamp);
12951 e.seqno = be32toh(e.seqno);
12952 for (j = 0; j < 8; j++)
12953 e.params[j] = be32toh(e.params[j]);
12954
12955 db_printf("%10d %15ju %8s %8s ",
12956 e.seqno, e.timestamp,
12957 (e.level < nitems(devlog_level_strings) ?
12958 devlog_level_strings[e.level] : "UNKNOWN"),
12959 (e.facility < nitems(devlog_facility_strings) ?
12960 devlog_facility_strings[e.facility] : "UNKNOWN"));
12961 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
12962 e.params[3], e.params[4], e.params[5], e.params[6],
12963 e.params[7]);
12964
12965 if (++i == nentries)
12966 i = 0;
12967 } while (i != first && !db_pager_quit);
12968 }
12969
12970 static DB_DEFINE_TABLE(show, t4, show_t4);
12971
DB_TABLE_COMMAND_FLAGS(show_t4,devlog,db_show_devlog,CS_OWN)12972 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN)
12973 {
12974 device_t dev;
12975 int t;
12976 bool valid;
12977
12978 valid = false;
12979 t = db_read_token();
12980 if (t == tIDENT) {
12981 dev = device_lookup_by_name(db_tok_string);
12982 valid = true;
12983 }
12984 db_skip_to_eol();
12985 if (!valid) {
12986 db_printf("usage: show t4 devlog <nexus>\n");
12987 return;
12988 }
12989
12990 if (dev == NULL) {
12991 db_printf("device not found\n");
12992 return;
12993 }
12994
12995 t4_dump_devlog(device_get_softc(dev));
12996 }
12997
DB_TABLE_COMMAND_FLAGS(show_t4,tcb,db_show_t4tcb,CS_OWN)12998 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN)
12999 {
13000 device_t dev;
13001 int radix, tid, t;
13002 bool valid;
13003
13004 valid = false;
13005 radix = db_radix;
13006 db_radix = 10;
13007 t = db_read_token();
13008 if (t == tIDENT) {
13009 dev = device_lookup_by_name(db_tok_string);
13010 t = db_read_token();
13011 if (t == tNUMBER) {
13012 tid = db_tok_number;
13013 valid = true;
13014 }
13015 }
13016 db_radix = radix;
13017 db_skip_to_eol();
13018 if (!valid) {
13019 db_printf("usage: show t4 tcb <nexus> <tid>\n");
13020 return;
13021 }
13022
13023 if (dev == NULL) {
13024 db_printf("device not found\n");
13025 return;
13026 }
13027 if (tid < 0) {
13028 db_printf("invalid tid\n");
13029 return;
13030 }
13031
13032 t4_dump_tcb(device_get_softc(dev), tid);
13033 }
13034 #endif
13035
13036 static eventhandler_tag vxlan_start_evtag;
13037 static eventhandler_tag vxlan_stop_evtag;
13038
13039 struct vxlan_evargs {
13040 if_t ifp;
13041 uint16_t port;
13042 };
13043
13044 static void
enable_vxlan_rx(struct adapter * sc)13045 enable_vxlan_rx(struct adapter *sc)
13046 {
13047 int i, rc;
13048 struct port_info *pi;
13049 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
13050
13051 ASSERT_SYNCHRONIZED_OP(sc);
13052
13053 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) |
13054 F_VXLAN_EN);
13055 for_each_port(sc, i) {
13056 pi = sc->port[i];
13057 if (pi->vxlan_tcam_entry == true)
13058 continue;
13059 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac,
13060 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
13061 true);
13062 if (rc < 0) {
13063 rc = -rc;
13064 CH_ERR(&pi->vi[0],
13065 "failed to add VXLAN TCAM entry: %d.\n", rc);
13066 } else {
13067 MPASS(rc == sc->rawf_base + pi->port_id);
13068 pi->vxlan_tcam_entry = true;
13069 }
13070 }
13071 }
13072
13073 static void
t4_vxlan_start(struct adapter * sc,void * arg)13074 t4_vxlan_start(struct adapter *sc, void *arg)
13075 {
13076 struct vxlan_evargs *v = arg;
13077
13078 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
13079 return;
13080 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0)
13081 return;
13082
13083 if (sc->vxlan_refcount == 0) {
13084 sc->vxlan_port = v->port;
13085 sc->vxlan_refcount = 1;
13086 if (!hw_off_limits(sc))
13087 enable_vxlan_rx(sc);
13088 } else if (sc->vxlan_port == v->port) {
13089 sc->vxlan_refcount++;
13090 } else {
13091 CH_ERR(sc, "VXLAN already configured on port %d; "
13092 "ignoring attempt to configure it on port %d\n",
13093 sc->vxlan_port, v->port);
13094 }
13095 end_synchronized_op(sc, 0);
13096 }
13097
13098 static void
t4_vxlan_stop(struct adapter * sc,void * arg)13099 t4_vxlan_stop(struct adapter *sc, void *arg)
13100 {
13101 struct vxlan_evargs *v = arg;
13102
13103 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
13104 return;
13105 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0)
13106 return;
13107
13108 /*
13109 * VXLANs may have been configured before the driver was loaded so we
13110 * may see more stops than starts. This is not handled cleanly but at
13111 * least we keep the refcount sane.
13112 */
13113 if (sc->vxlan_port != v->port)
13114 goto done;
13115 if (sc->vxlan_refcount == 0) {
13116 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; "
13117 "ignoring attempt to stop it again.\n", sc->vxlan_port);
13118 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc))
13119 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0);
13120 done:
13121 end_synchronized_op(sc, 0);
13122 }
13123
13124 static void
t4_vxlan_start_handler(void * arg __unused,if_t ifp,sa_family_t family,u_int port)13125 t4_vxlan_start_handler(void *arg __unused, if_t ifp,
13126 sa_family_t family, u_int port)
13127 {
13128 struct vxlan_evargs v;
13129
13130 MPASS(family == AF_INET || family == AF_INET6);
13131 v.ifp = ifp;
13132 v.port = port;
13133
13134 t4_iterate(t4_vxlan_start, &v);
13135 }
13136
13137 static void
t4_vxlan_stop_handler(void * arg __unused,if_t ifp,sa_family_t family,u_int port)13138 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family,
13139 u_int port)
13140 {
13141 struct vxlan_evargs v;
13142
13143 MPASS(family == AF_INET || family == AF_INET6);
13144 v.ifp = ifp;
13145 v.port = port;
13146
13147 t4_iterate(t4_vxlan_stop, &v);
13148 }
13149
13150
13151 static struct sx mlu; /* mod load unload */
13152 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
13153
13154 static int
mod_event(module_t mod,int cmd,void * arg)13155 mod_event(module_t mod, int cmd, void *arg)
13156 {
13157 int rc = 0;
13158 static int loaded = 0;
13159
13160 switch (cmd) {
13161 case MOD_LOAD:
13162 sx_xlock(&mlu);
13163 if (loaded++ == 0) {
13164 t4_sge_modload();
13165 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
13166 t4_filter_rpl, CPL_COOKIE_FILTER);
13167 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
13168 do_l2t_write_rpl, CPL_COOKIE_FILTER);
13169 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
13170 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
13171 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
13172 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
13173 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
13174 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
13175 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
13176 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
13177 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
13178 do_smt_write_rpl);
13179 sx_init(&t4_list_lock, "T4/T5 adapters");
13180 SLIST_INIT(&t4_list);
13181 callout_init(&fatal_callout, 1);
13182 #ifdef TCP_OFFLOAD
13183 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
13184 SLIST_INIT(&t4_uld_list);
13185 #endif
13186 #ifdef INET6
13187 t4_clip_modload();
13188 #endif
13189 #ifdef KERN_TLS
13190 t6_ktls_modload();
13191 #endif
13192 t4_tracer_modload();
13193 tweak_tunables();
13194 vxlan_start_evtag =
13195 EVENTHANDLER_REGISTER(vxlan_start,
13196 t4_vxlan_start_handler, NULL,
13197 EVENTHANDLER_PRI_ANY);
13198 vxlan_stop_evtag =
13199 EVENTHANDLER_REGISTER(vxlan_stop,
13200 t4_vxlan_stop_handler, NULL,
13201 EVENTHANDLER_PRI_ANY);
13202 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK,
13203 taskqueue_thread_enqueue, &reset_tq);
13204 taskqueue_start_threads(&reset_tq, 1, PI_SOFT,
13205 "t4_rst_thr");
13206 }
13207 sx_xunlock(&mlu);
13208 break;
13209
13210 case MOD_UNLOAD:
13211 sx_xlock(&mlu);
13212 if (--loaded == 0) {
13213 int tries;
13214
13215 taskqueue_free(reset_tq);
13216 sx_slock(&t4_list_lock);
13217 if (!SLIST_EMPTY(&t4_list)) {
13218 rc = EBUSY;
13219 sx_sunlock(&t4_list_lock);
13220 goto done_unload;
13221 }
13222 #ifdef TCP_OFFLOAD
13223 sx_slock(&t4_uld_list_lock);
13224 if (!SLIST_EMPTY(&t4_uld_list)) {
13225 rc = EBUSY;
13226 sx_sunlock(&t4_uld_list_lock);
13227 sx_sunlock(&t4_list_lock);
13228 goto done_unload;
13229 }
13230 #endif
13231 tries = 0;
13232 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
13233 uprintf("%ju clusters with custom free routine "
13234 "still is use.\n", t4_sge_extfree_refs());
13235 pause("t4unload", 2 * hz);
13236 }
13237 #ifdef TCP_OFFLOAD
13238 sx_sunlock(&t4_uld_list_lock);
13239 #endif
13240 sx_sunlock(&t4_list_lock);
13241
13242 if (t4_sge_extfree_refs() == 0) {
13243 EVENTHANDLER_DEREGISTER(vxlan_start,
13244 vxlan_start_evtag);
13245 EVENTHANDLER_DEREGISTER(vxlan_stop,
13246 vxlan_stop_evtag);
13247 t4_tracer_modunload();
13248 #ifdef KERN_TLS
13249 t6_ktls_modunload();
13250 #endif
13251 #ifdef INET6
13252 t4_clip_modunload();
13253 #endif
13254 #ifdef TCP_OFFLOAD
13255 sx_destroy(&t4_uld_list_lock);
13256 #endif
13257 sx_destroy(&t4_list_lock);
13258 t4_sge_modunload();
13259 loaded = 0;
13260 } else {
13261 rc = EBUSY;
13262 loaded++; /* undo earlier decrement */
13263 }
13264 }
13265 done_unload:
13266 sx_xunlock(&mlu);
13267 break;
13268 }
13269
13270 return (rc);
13271 }
13272
13273 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0);
13274 MODULE_VERSION(t4nex, 1);
13275 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
13276 #ifdef DEV_NETMAP
13277 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
13278 #endif /* DEV_NETMAP */
13279
13280 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0);
13281 MODULE_VERSION(t5nex, 1);
13282 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
13283 #ifdef DEV_NETMAP
13284 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
13285 #endif /* DEV_NETMAP */
13286
13287 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0);
13288 MODULE_VERSION(t6nex, 1);
13289 MODULE_DEPEND(t6nex, crypto, 1, 1, 1);
13290 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
13291 #ifdef DEV_NETMAP
13292 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
13293 #endif /* DEV_NETMAP */
13294
13295 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0);
13296 MODULE_VERSION(cxgbe, 1);
13297
13298 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0);
13299 MODULE_VERSION(cxl, 1);
13300
13301 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0);
13302 MODULE_VERSION(cc, 1);
13303
13304 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0);
13305 MODULE_VERSION(vcxgbe, 1);
13306
13307 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0);
13308 MODULE_VERSION(vcxl, 1);
13309
13310 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0);
13311 MODULE_VERSION(vcc, 1);
13312