1 /* $NetBSD: be.c,v 1.98 2022/09/25 18:03:04 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Kranenburg.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. The name of the authors may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <sys/cdefs.h>
60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.98 2022/09/25 18:03:04 thorpej Exp $");
61
62 #include "opt_ddb.h"
63 #include "opt_inet.h"
64
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/callout.h>
68 #include <sys/kernel.h>
69 #include <sys/errno.h>
70 #include <sys/ioctl.h>
71 #include <sys/mbuf.h>
72 #include <sys/socket.h>
73 #include <sys/syslog.h>
74 #include <sys/device.h>
75
76 #include <net/if.h>
77 #include <net/if_dl.h>
78 #include <net/if_types.h>
79 #include <net/if_media.h>
80 #include <net/if_ether.h>
81 #include <net/bpf.h>
82
83 #ifdef INET
84 #include <netinet/in.h>
85 #include <netinet/if_inarp.h>
86 #include <netinet/in_systm.h>
87 #include <netinet/in_var.h>
88 #include <netinet/ip.h>
89 #endif
90
91 #include <sys/bus.h>
92 #include <sys/intr.h>
93 #include <machine/autoconf.h>
94
95 #include <dev/mii/mii.h>
96 #include <dev/mii/miivar.h>
97
98 #include <dev/sbus/sbusvar.h>
99 #include <dev/sbus/qecreg.h>
100 #include <dev/sbus/qecvar.h>
101 #include <dev/sbus/bereg.h>
102
103 struct be_softc {
104 device_t sc_dev;
105 bus_space_tag_t sc_bustag; /* bus & DMA tags */
106 bus_dma_tag_t sc_dmatag;
107 bus_dmamap_t sc_dmamap;
108 struct ethercom sc_ethercom;
109 /*struct ifmedia sc_ifmedia; -* interface media */
110 struct mii_data sc_mii; /* MII media control */
111 #define sc_media sc_mii.mii_media/* shorthand */
112 int sc_phys[2]; /* MII instance -> phy */
113
114 struct callout sc_tick_ch;
115
116 /*
117 * Some `mii_softc' items we need to emulate MII operation
118 * for our internal transceiver.
119 */
120 int sc_mii_inst; /* instance of internal phy */
121 int sc_mii_active; /* currently active medium */
122 int sc_mii_ticks; /* tick counter */
123 int sc_mii_flags; /* phy status flags */
124 #define MIIF_HAVELINK 0x04000000
125 int sc_intphy_curspeed; /* Established link speed */
126
127 struct qec_softc *sc_qec; /* QEC parent */
128
129 bus_space_handle_t sc_qr; /* QEC registers */
130 bus_space_handle_t sc_br; /* BE registers */
131 bus_space_handle_t sc_cr; /* channel registers */
132 bus_space_handle_t sc_tr; /* transceiver registers */
133
134 u_int sc_rev;
135
136 int sc_channel; /* channel number */
137 int sc_burst;
138
139 struct qec_ring sc_rb; /* Packet Ring Buffer */
140
141 /* MAC address */
142 uint8_t sc_enaddr[ETHER_ADDR_LEN];
143 #ifdef BEDEBUG
144 int sc_debug;
145 #endif
146 };
147
148 static int bematch(device_t, cfdata_t, void *);
149 static void beattach(device_t, device_t, void *);
150
151 static int beinit(struct ifnet *);
152 static void bestart(struct ifnet *);
153 static void bestop(struct ifnet *, int);
154 static void bewatchdog(struct ifnet *);
155 static int beioctl(struct ifnet *, u_long, void *);
156 static void bereset(struct be_softc *);
157 static void behwreset(struct be_softc *);
158
159 static int beintr(void *);
160 static int berint(struct be_softc *);
161 static int betint(struct be_softc *);
162 static int beqint(struct be_softc *, uint32_t);
163 static int beeint(struct be_softc *, uint32_t);
164
165 static void be_read(struct be_softc *, int, int);
166 static int be_put(struct be_softc *, int, struct mbuf *);
167 static struct mbuf *be_get(struct be_softc *, int, int);
168
169 static void be_pal_gate(struct be_softc *, int);
170
171 /* ifmedia callbacks */
172 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *);
173 static int be_ifmedia_upd(struct ifnet *);
174
175 static void be_mcreset(struct be_softc *);
176
177 /* MII methods & callbacks */
178 static int be_mii_readreg(device_t, int, int, uint16_t *);
179 static int be_mii_writereg(device_t, int, int, uint16_t);
180 static void be_mii_statchg(struct ifnet *);
181
182 /* MII helpers */
183 static void be_mii_sync(struct be_softc *);
184 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int);
185 static int be_mii_reset(struct be_softc *, int);
186 static int be_tcvr_read_bit(struct be_softc *, int);
187 static void be_tcvr_write_bit(struct be_softc *, int, int);
188
189 static void be_tick(void *);
190 #if 0
191 static void be_intphy_auto(struct be_softc *);
192 #endif
193 static void be_intphy_status(struct be_softc *);
194 static int be_intphy_service(struct be_softc *, struct mii_data *, int);
195
196
197 CFATTACH_DECL_NEW(be, sizeof(struct be_softc),
198 bematch, beattach, NULL, NULL);
199
200 int
bematch(device_t parent,cfdata_t cf,void * aux)201 bematch(device_t parent, cfdata_t cf, void *aux)
202 {
203 struct sbus_attach_args *sa = aux;
204
205 return strcmp(cf->cf_name, sa->sa_name) == 0;
206 }
207
208 void
beattach(device_t parent,device_t self,void * aux)209 beattach(device_t parent, device_t self, void *aux)
210 {
211 struct sbus_attach_args *sa = aux;
212 struct qec_softc *qec = device_private(parent);
213 struct be_softc *sc = device_private(self);
214 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
215 struct mii_data *mii = &sc->sc_mii;
216 struct mii_softc *child;
217 int node = sa->sa_node;
218 bus_dma_tag_t dmatag = sa->sa_dmatag;
219 bus_dma_segment_t seg;
220 bus_size_t size;
221 int instance;
222 int rseg, error;
223 uint32_t v;
224
225 sc->sc_dev = self;
226
227 if (sa->sa_nreg < 3) {
228 printf(": only %d register sets\n", sa->sa_nreg);
229 return;
230 }
231
232 if (bus_space_map(sa->sa_bustag,
233 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base),
234 (bus_size_t)sa->sa_reg[0].oa_size,
235 0, &sc->sc_cr) != 0) {
236 printf(": cannot map registers\n");
237 return;
238 }
239
240 if (bus_space_map(sa->sa_bustag,
241 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base),
242 (bus_size_t)sa->sa_reg[1].oa_size,
243 0, &sc->sc_br) != 0) {
244 printf(": cannot map registers\n");
245 return;
246 }
247
248 if (bus_space_map(sa->sa_bustag,
249 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base),
250 (bus_size_t)sa->sa_reg[2].oa_size,
251 0, &sc->sc_tr) != 0) {
252 printf(": cannot map registers\n");
253 return;
254 }
255
256 sc->sc_bustag = sa->sa_bustag;
257 sc->sc_qec = qec;
258 sc->sc_qr = qec->sc_regs;
259
260 sc->sc_rev = prom_getpropint(node, "board-version", -1);
261 printf(": rev %x,", sc->sc_rev);
262
263 callout_init(&sc->sc_tick_ch, 0);
264
265 sc->sc_channel = prom_getpropint(node, "channel#", -1);
266 if (sc->sc_channel == -1)
267 sc->sc_channel = 0;
268
269 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1);
270 if (sc->sc_burst == -1)
271 sc->sc_burst = qec->sc_burst;
272
273 /* Clamp at parent's burst sizes */
274 sc->sc_burst &= qec->sc_burst;
275
276 /* Establish interrupt handler */
277 if (sa->sa_nintr)
278 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET,
279 beintr, sc);
280
281 prom_getether(node, sc->sc_enaddr);
282 printf(" address %s\n", ether_sprintf(sc->sc_enaddr));
283
284 /*
285 * Allocate descriptor ring and buffers.
286 */
287
288 /* for now, allocate as many bufs as there are ring descriptors */
289 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
290 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
291
292 size =
293 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
294 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
295 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ +
296 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ;
297
298 /* Get a DMA handle */
299 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
300 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
301 aprint_error_dev(self, "DMA map create error %d\n", error);
302 return;
303 }
304
305 /* Allocate DMA buffer */
306 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0,
307 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
308 aprint_error_dev(self, "DMA buffer alloc error %d\n", error);
309 return;
310 }
311
312 /* Map DMA memory in CPU addressable space */
313 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size,
314 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
315 aprint_error_dev(self, "DMA buffer map error %d\n", error);
316 bus_dmamem_free(sa->sa_dmatag, &seg, rseg);
317 return;
318 }
319
320 /* Load the buffer */
321 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
322 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) {
323 aprint_error_dev(self, "DMA buffer map load error %d\n", error);
324 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
325 bus_dmamem_free(dmatag, &seg, rseg);
326 return;
327 }
328 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
329
330 /*
331 * Initialize our media structures and MII info.
332 */
333 mii->mii_ifp = ifp;
334 mii->mii_readreg = be_mii_readreg;
335 mii->mii_writereg = be_mii_writereg;
336 mii->mii_statchg = be_mii_statchg;
337
338 sc->sc_ethercom.ec_mii = mii;
339 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts);
340
341 /*
342 * Initialize transceiver and determine which PHY connection to use.
343 */
344 be_mii_sync(sc);
345 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL);
346
347 instance = 0;
348
349 if ((v & MGMT_PAL_EXT_MDIO) != 0) {
350
351 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL,
352 MII_OFFSET_ANY, 0);
353
354 child = LIST_FIRST(&mii->mii_phys);
355 if (child == NULL) {
356 /* No PHY attached */
357 ifmedia_add(&sc->sc_media,
358 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance),
359 0, NULL);
360 ifmedia_set(&sc->sc_media,
361 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance));
362 } else {
363 /*
364 * Note: we support just one PHY on the external
365 * MII connector.
366 */
367 #ifdef DIAGNOSTIC
368 if (LIST_NEXT(child, mii_list) != NULL) {
369 aprint_error_dev(self,
370 "spurious MII device %s attached\n",
371 device_xname(child->mii_dev));
372 }
373 #endif
374 if (child->mii_phy != BE_PHY_EXTERNAL ||
375 child->mii_inst > 0) {
376 aprint_error_dev(self,
377 "cannot accommodate MII device %s"
378 " at phy %d, instance %d\n",
379 device_xname(child->mii_dev),
380 child->mii_phy, child->mii_inst);
381 } else {
382 sc->sc_phys[instance] = child->mii_phy;
383 }
384
385 /*
386 * XXX - we can really do the following ONLY if the
387 * phy indeed has the auto negotiation capability!!
388 */
389 ifmedia_set(&sc->sc_media,
390 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance));
391
392 /* Mark our current media setting */
393 be_pal_gate(sc, BE_PHY_EXTERNAL);
394 instance++;
395 }
396
397 }
398
399 if ((v & MGMT_PAL_INT_MDIO) != 0) {
400 /*
401 * The be internal phy looks vaguely like MII hardware,
402 * but not enough to be able to use the MII device
403 * layer. Hence, we have to take care of media selection
404 * ourselves.
405 */
406
407 sc->sc_mii_inst = instance;
408 sc->sc_phys[instance] = BE_PHY_INTERNAL;
409
410 /* Use `ifm_data' to store BMCR bits */
411 ifmedia_add(&sc->sc_media,
412 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance),
413 0, NULL);
414 ifmedia_add(&sc->sc_media,
415 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance),
416 BMCR_S100, NULL);
417 ifmedia_add(&sc->sc_media,
418 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance),
419 0, NULL);
420
421 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n",
422 device_xname(self));
423
424 be_mii_reset(sc, BE_PHY_INTERNAL);
425 /* Only set default medium here if there's no external PHY */
426 if (instance == 0) {
427 be_pal_gate(sc, BE_PHY_INTERNAL);
428 ifmedia_set(&sc->sc_media,
429 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance));
430 } else
431 be_mii_writereg(self,
432 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO);
433 }
434
435 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
436 ifp->if_softc = sc;
437 ifp->if_start = bestart;
438 ifp->if_ioctl = beioctl;
439 ifp->if_watchdog = bewatchdog;
440 ifp->if_init = beinit;
441 ifp->if_stop = bestop;
442 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
443 IFQ_SET_READY(&ifp->if_snd);
444
445 /* claim 802.1q capability */
446 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
447
448 /* Attach the interface. */
449 if_attach(ifp);
450 ether_ifattach(ifp, sc->sc_enaddr);
451 }
452
453
454 /*
455 * Routine to copy from mbuf chain to transmit buffer in
456 * network buffer memory.
457 */
458 static inline int
be_put(struct be_softc * sc,int idx,struct mbuf * m)459 be_put(struct be_softc *sc, int idx, struct mbuf *m)
460 {
461 struct mbuf *n;
462 int len, tlen = 0, boff = 0;
463 uint8_t *bp;
464
465 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ;
466
467 for (; m; m = n) {
468 len = m->m_len;
469 if (len == 0) {
470 n = m_free(m);
471 continue;
472 }
473 memcpy(bp + boff, mtod(m, void *), len);
474 boff += len;
475 tlen += len;
476 n = m_free(m);
477 }
478 return tlen;
479 }
480
481 /*
482 * Pull data off an interface.
483 * Len is the length of data, with local net header stripped.
484 * We copy the data into mbufs. When full cluster sized units are present,
485 * we copy into clusters.
486 */
487 static inline struct mbuf *
be_get(struct be_softc * sc,int idx,int totlen)488 be_get(struct be_softc *sc, int idx, int totlen)
489 {
490 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
491 struct mbuf *m;
492 struct mbuf *top, **mp;
493 int len, pad, boff = 0;
494 uint8_t *bp;
495
496 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ;
497
498 MGETHDR(m, M_DONTWAIT, MT_DATA);
499 if (m == NULL)
500 return (NULL);
501 m_set_rcvif(m, ifp);
502 m->m_pkthdr.len = totlen;
503
504 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
505 m->m_data += pad;
506 len = MHLEN - pad;
507 top = NULL;
508 mp = ⊤
509
510 while (totlen > 0) {
511 if (top) {
512 MGET(m, M_DONTWAIT, MT_DATA);
513 if (m == NULL) {
514 m_freem(top);
515 return (NULL);
516 }
517 len = MLEN;
518 }
519 if (top && totlen >= MINCLSIZE) {
520 MCLGET(m, M_DONTWAIT);
521 if (m->m_flags & M_EXT)
522 len = MCLBYTES;
523 }
524 m->m_len = len = uimin(totlen, len);
525 memcpy(mtod(m, void *), bp + boff, len);
526 boff += len;
527 totlen -= len;
528 *mp = m;
529 mp = &m->m_next;
530 }
531
532 return top;
533 }
534
535 /*
536 * Pass a packet to the higher levels.
537 */
538 static inline void
be_read(struct be_softc * sc,int idx,int len)539 be_read(struct be_softc *sc, int idx, int len)
540 {
541 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
542 struct mbuf *m;
543
544 if (len <= sizeof(struct ether_header) ||
545 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
546 #ifdef BEDEBUG
547 if (sc->sc_debug)
548 printf("%s: invalid packet size %d; dropping\n",
549 ifp->if_xname, len);
550 #endif
551 if_statinc(ifp, if_ierrors);
552 return;
553 }
554
555 /*
556 * Pull packet off interface.
557 */
558 m = be_get(sc, idx, len);
559 if (m == NULL) {
560 if_statinc(ifp, if_ierrors);
561 return;
562 }
563
564 /* Pass the packet up. */
565 if_percpuq_enqueue(ifp->if_percpuq, m);
566 }
567
568 /*
569 * Start output on interface.
570 * We make an assumption here:
571 * 1) that the current priority is set to splnet _before_ this code
572 * is called *and* is returned to the appropriate priority after
573 * return
574 */
575 void
bestart(struct ifnet * ifp)576 bestart(struct ifnet *ifp)
577 {
578 struct be_softc *sc = ifp->if_softc;
579 struct qec_xd *txd = sc->sc_rb.rb_txd;
580 struct mbuf *m;
581 unsigned int bix, len;
582 unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
583
584 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING)
585 return;
586
587 bix = sc->sc_rb.rb_tdhead;
588
589 while (sc->sc_rb.rb_td_nbusy < ntbuf) {
590 IFQ_DEQUEUE(&ifp->if_snd, m);
591 if (m == 0)
592 break;
593
594 /*
595 * If BPF is listening on this interface, let it see the
596 * packet before we commit it to the wire.
597 */
598 bpf_mtap(ifp, m, BPF_D_OUT);
599
600 /*
601 * Copy the mbuf chain into the transmit buffer.
602 */
603 len = be_put(sc, bix, m);
604
605 /*
606 * Initialize transmit registers and start transmission
607 */
608 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
609 (len & QEC_XD_LENGTH);
610 bus_space_write_4(sc->sc_bustag, sc->sc_cr,
611 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP);
612
613 if (++bix == QEC_XD_RING_MAXSIZE)
614 bix = 0;
615
616 sc->sc_rb.rb_td_nbusy++;
617 }
618
619 sc->sc_rb.rb_tdhead = bix;
620 }
621
622 void
bestop(struct ifnet * ifp,int disable)623 bestop(struct ifnet *ifp, int disable)
624 {
625 struct be_softc *sc = ifp->if_softc;
626
627 callout_stop(&sc->sc_tick_ch);
628
629 /* Down the MII. */
630 mii_down(&sc->sc_mii);
631 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN);
632
633 behwreset(sc);
634 }
635
636 void
behwreset(struct be_softc * sc)637 behwreset(struct be_softc *sc)
638 {
639 int n;
640 bus_space_tag_t t = sc->sc_bustag;
641 bus_space_handle_t br = sc->sc_br;
642
643 /* Stop the transmitter */
644 bus_space_write_4(t, br, BE_BRI_TXCFG, 0);
645 for (n = 32; n > 0; n--) {
646 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0)
647 break;
648 DELAY(20);
649 }
650
651 /* Stop the receiver */
652 bus_space_write_4(t, br, BE_BRI_RXCFG, 0);
653 for (n = 32; n > 0; n--) {
654 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0)
655 break;
656 DELAY(20);
657 }
658 }
659
660 /*
661 * Reset interface.
662 */
663 void
bereset(struct be_softc * sc)664 bereset(struct be_softc *sc)
665 {
666 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
667 int s;
668
669 s = splnet();
670 behwreset(sc);
671 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0)
672 beinit(ifp);
673 splx(s);
674 }
675
676 void
bewatchdog(struct ifnet * ifp)677 bewatchdog(struct ifnet *ifp)
678 {
679 struct be_softc *sc = ifp->if_softc;
680
681 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
682 if_statinc(ifp, if_oerrors);
683
684 bereset(sc);
685 }
686
687 int
beintr(void * arg)688 beintr(void *arg)
689 {
690 struct be_softc *sc = arg;
691 bus_space_tag_t t = sc->sc_bustag;
692 uint32_t whyq, whyb, whyc;
693 int r = 0;
694
695 /* Read QEC status, channel status and BE status */
696 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
697 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT);
698 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT);
699
700 if (whyq & QEC_STAT_BM)
701 r |= beeint(sc, whyb);
702
703 if (whyq & QEC_STAT_ER)
704 r |= beqint(sc, whyc);
705
706 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ)
707 r |= betint(sc);
708
709 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ)
710 r |= berint(sc);
711
712 return r;
713 }
714
715 /*
716 * QEC Interrupt.
717 */
718 int
beqint(struct be_softc * sc,uint32_t why)719 beqint(struct be_softc *sc, uint32_t why)
720 {
721 device_t self = sc->sc_dev;
722 int r = 0, rst = 0;
723
724 if (why & BE_CR_STAT_TXIRQ)
725 r |= 1;
726 if (why & BE_CR_STAT_RXIRQ)
727 r |= 1;
728
729 if (why & BE_CR_STAT_BERROR) {
730 r |= 1;
731 rst = 1;
732 aprint_error_dev(self, "bigmac error\n");
733 }
734
735 if (why & BE_CR_STAT_TXDERR) {
736 r |= 1;
737 rst = 1;
738 aprint_error_dev(self, "bogus tx descriptor\n");
739 }
740
741 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) {
742 r |= 1;
743 rst = 1;
744 aprint_error_dev(self, "tx DMA error ( ");
745 if (why & BE_CR_STAT_TXLERR)
746 printf("Late ");
747 if (why & BE_CR_STAT_TXPERR)
748 printf("Parity ");
749 if (why & BE_CR_STAT_TXSERR)
750 printf("Generic ");
751 printf(")\n");
752 }
753
754 if (why & BE_CR_STAT_RXDROP) {
755 r |= 1;
756 rst = 1;
757 aprint_error_dev(self, "out of rx descriptors\n");
758 }
759
760 if (why & BE_CR_STAT_RXSMALL) {
761 r |= 1;
762 rst = 1;
763 aprint_error_dev(self, "rx descriptor too small\n");
764 }
765
766 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) {
767 r |= 1;
768 rst = 1;
769 aprint_error_dev(self, "rx DMA error ( ");
770 if (why & BE_CR_STAT_RXLERR)
771 printf("Late ");
772 if (why & BE_CR_STAT_RXPERR)
773 printf("Parity ");
774 if (why & BE_CR_STAT_RXSERR)
775 printf("Generic ");
776 printf(")\n");
777 }
778
779 if (!r) {
780 rst = 1;
781 aprint_error_dev(self, "unexpected error interrupt %08x\n",
782 why);
783 }
784
785 if (rst) {
786 printf("%s: resetting\n", device_xname(self));
787 bereset(sc);
788 }
789
790 return r;
791 }
792
793 /*
794 * Error interrupt.
795 */
796 int
beeint(struct be_softc * sc,uint32_t why)797 beeint(struct be_softc *sc, uint32_t why)
798 {
799 device_t self = sc->sc_dev;
800 int r = 0, rst = 0;
801
802 if (why & BE_BR_STAT_RFIFOVF) {
803 r |= 1;
804 rst = 1;
805 aprint_error_dev(self, "receive fifo overrun\n");
806 }
807 if (why & BE_BR_STAT_TFIFO_UND) {
808 r |= 1;
809 rst = 1;
810 aprint_error_dev(self, "transmit fifo underrun\n");
811 }
812 if (why & BE_BR_STAT_MAXPKTERR) {
813 r |= 1;
814 rst = 1;
815 aprint_error_dev(self, "max packet size error\n");
816 }
817
818 if (!r) {
819 rst = 1;
820 aprint_error_dev(self, "unexpected error interrupt %08x\n",
821 why);
822 }
823
824 if (rst) {
825 printf("%s: resetting\n", device_xname(self));
826 bereset(sc);
827 }
828
829 return r;
830 }
831
832 /*
833 * Transmit interrupt.
834 */
835 int
betint(struct be_softc * sc)836 betint(struct be_softc *sc)
837 {
838 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
839 bus_space_tag_t t = sc->sc_bustag;
840 bus_space_handle_t br = sc->sc_br;
841 unsigned int bix, txflags;
842
843 /*
844 * Unload collision counters
845 */
846 if_statadd(ifp, if_collisions,
847 bus_space_read_4(t, br, BE_BRI_NCCNT) +
848 bus_space_read_4(t, br, BE_BRI_FCCNT) +
849 bus_space_read_4(t, br, BE_BRI_EXCNT) +
850 bus_space_read_4(t, br, BE_BRI_LTCNT));
851
852 /*
853 * the clear the hardware counters
854 */
855 bus_space_write_4(t, br, BE_BRI_NCCNT, 0);
856 bus_space_write_4(t, br, BE_BRI_FCCNT, 0);
857 bus_space_write_4(t, br, BE_BRI_EXCNT, 0);
858 bus_space_write_4(t, br, BE_BRI_LTCNT, 0);
859
860 bix = sc->sc_rb.rb_tdtail;
861
862 for (;;) {
863 if (sc->sc_rb.rb_td_nbusy <= 0)
864 break;
865
866 txflags = sc->sc_rb.rb_txd[bix].xd_flags;
867
868 if (txflags & QEC_XD_OWN)
869 break;
870
871 if_statinc(ifp, if_opackets);
872
873 if (++bix == QEC_XD_RING_MAXSIZE)
874 bix = 0;
875
876 --sc->sc_rb.rb_td_nbusy;
877 }
878
879 sc->sc_rb.rb_tdtail = bix;
880
881 bestart(ifp);
882
883 if (sc->sc_rb.rb_td_nbusy == 0)
884 ifp->if_timer = 0;
885
886 return 1;
887 }
888
889 /*
890 * Receive interrupt.
891 */
892 int
berint(struct be_softc * sc)893 berint(struct be_softc *sc)
894 {
895 struct qec_xd *xd = sc->sc_rb.rb_rxd;
896 unsigned int bix, len;
897 unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
898
899 bix = sc->sc_rb.rb_rdtail;
900
901 /*
902 * Process all buffers with valid data.
903 */
904 for (;;) {
905 len = xd[bix].xd_flags;
906 if (len & QEC_XD_OWN)
907 break;
908
909 len &= QEC_XD_LENGTH;
910 be_read(sc, bix, len);
911
912 /* ... */
913 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
914 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH);
915
916 if (++bix == QEC_XD_RING_MAXSIZE)
917 bix = 0;
918 }
919
920 sc->sc_rb.rb_rdtail = bix;
921
922 return 1;
923 }
924
925 int
beioctl(struct ifnet * ifp,u_long cmd,void * data)926 beioctl(struct ifnet *ifp, u_long cmd, void *data)
927 {
928 #ifdef BEDEBUG
929 struct be_softc *sc = ifp->if_softc;
930 #endif
931 struct ifaddr *ifa = data;
932 int s, error = 0;
933
934 s = splnet();
935
936 switch (cmd) {
937 case SIOCINITIFADDR:
938 ifp->if_flags |= IFF_UP;
939 beinit(ifp);
940 switch (ifa->ifa_addr->sa_family) {
941 #ifdef INET
942 case AF_INET:
943 arp_ifinit(ifp, ifa);
944 break;
945 #endif /* INET */
946 default:
947 break;
948 }
949 break;
950
951 case SIOCSIFFLAGS:
952 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
953 break;
954 /* XXX re-use ether_ioctl() */
955 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
956 case IFF_RUNNING:
957 /*
958 * If interface is marked down and it is running, then
959 * stop it.
960 */
961 bestop(ifp, 0);
962 ifp->if_flags &= ~IFF_RUNNING;
963 break;
964 case IFF_UP:
965 /*
966 * If interface is marked up and it is stopped, then
967 * start it.
968 */
969 beinit(ifp);
970 break;
971 default:
972 /*
973 * Reset the interface to pick up changes in any other
974 * flags that affect hardware registers.
975 */
976 bestop(ifp, 0);
977 beinit(ifp);
978 break;
979 }
980 #ifdef BEDEBUG
981 if (ifp->if_flags & IFF_DEBUG)
982 sc->sc_debug = 1;
983 else
984 sc->sc_debug = 0;
985 #endif
986 break;
987
988 default:
989 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
990 /*
991 * Multicast list has changed; set the hardware filter
992 * accordingly.
993 */
994 if (ifp->if_flags & IFF_RUNNING)
995 error = beinit(ifp);
996 else
997 error = 0;
998 }
999 break;
1000 }
1001 splx(s);
1002 return error;
1003 }
1004
1005
1006 int
beinit(struct ifnet * ifp)1007 beinit(struct ifnet *ifp)
1008 {
1009 struct be_softc *sc = ifp->if_softc;
1010 bus_space_tag_t t = sc->sc_bustag;
1011 bus_space_handle_t br = sc->sc_br;
1012 bus_space_handle_t cr = sc->sc_cr;
1013 struct qec_softc *qec = sc->sc_qec;
1014 uint32_t v;
1015 uint32_t qecaddr;
1016 uint8_t *ea;
1017 int rc, s;
1018
1019 s = splnet();
1020
1021 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
1022
1023 bestop(ifp, 1);
1024
1025 ea = sc->sc_enaddr;
1026 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
1027 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
1028 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
1029
1030 /* Clear hash table */
1031 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
1032 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
1033 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
1034 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
1035
1036 /* Re-initialize RX configuration */
1037 v = BE_BR_RXCFG_FIFO;
1038 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1039
1040 be_mcreset(sc);
1041
1042 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
1043
1044 bus_space_write_4(t, br,
1045 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
1046
1047 bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
1048
1049 /*
1050 * Turn off counter expiration interrupts as well as
1051 * 'gotframe' and 'sentframe'
1052 */
1053 bus_space_write_4(t, br, BE_BRI_IMASK,
1054 BE_BR_IMASK_GOTFRAME |
1055 BE_BR_IMASK_RCNTEXP |
1056 BE_BR_IMASK_ACNTEXP |
1057 BE_BR_IMASK_CCNTEXP |
1058 BE_BR_IMASK_LCNTEXP |
1059 BE_BR_IMASK_CVCNTEXP |
1060 BE_BR_IMASK_SENTFRAME |
1061 BE_BR_IMASK_NCNTEXP |
1062 BE_BR_IMASK_ECNTEXP |
1063 BE_BR_IMASK_LCCNTEXP |
1064 BE_BR_IMASK_FCNTEXP |
1065 BE_BR_IMASK_DTIMEXP);
1066
1067 /* Channel registers: */
1068 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma);
1069 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma);
1070
1071 qecaddr = sc->sc_channel * qec->sc_msize;
1072 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
1073 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
1074 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
1075 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
1076
1077 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
1078 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
1079 bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
1080 bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
1081 bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
1082
1083 /* Set max packet length */
1084 v = ETHER_MAX_LEN;
1085 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
1086 v += ETHER_VLAN_ENCAP_LEN;
1087 bus_space_write_4(t, br, BE_BRI_RXMAX, v);
1088 bus_space_write_4(t, br, BE_BRI_TXMAX, v);
1089
1090 /* Enable transmitter */
1091 bus_space_write_4(t, br,
1092 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
1093
1094 /* Enable receiver */
1095 v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1096 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE;
1097 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1098
1099 if ((rc = be_ifmedia_upd(ifp)) != 0)
1100 goto out;
1101
1102 ifp->if_flags |= IFF_RUNNING;
1103
1104 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc);
1105
1106 splx(s);
1107 return 0;
1108 out:
1109 splx(s);
1110 return rc;
1111 }
1112
1113 void
be_mcreset(struct be_softc * sc)1114 be_mcreset(struct be_softc *sc)
1115 {
1116 struct ethercom *ec = &sc->sc_ethercom;
1117 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1118 bus_space_tag_t t = sc->sc_bustag;
1119 bus_space_handle_t br = sc->sc_br;
1120 uint32_t v;
1121 uint32_t crc;
1122 uint16_t hash[4];
1123 struct ether_multi *enm;
1124 struct ether_multistep step;
1125
1126 if (ifp->if_flags & IFF_PROMISC) {
1127 v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1128 v |= BE_BR_RXCFG_PMISC;
1129 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1130 return;
1131 }
1132
1133 if (ifp->if_flags & IFF_ALLMULTI) {
1134 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1135 goto chipit;
1136 }
1137
1138 hash[3] = hash[2] = hash[1] = hash[0] = 0;
1139
1140 ETHER_LOCK(ec);
1141 ETHER_FIRST_MULTI(step, ec, enm);
1142 while (enm != NULL) {
1143 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1144 /*
1145 * We must listen to a range of multicast
1146 * addresses. For now, just accept all
1147 * multicasts, rather than trying to set only
1148 * those filter bits needed to match the range.
1149 * (At this time, the only use of address
1150 * ranges is for IP multicast routing, for
1151 * which the range is big enough to require
1152 * all bits set.)
1153 */
1154 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1155 ifp->if_flags |= IFF_ALLMULTI;
1156 ETHER_UNLOCK(ec);
1157 goto chipit;
1158 }
1159
1160 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1161 /* Just want the 6 most significant bits. */
1162 crc >>= 26;
1163
1164 hash[crc >> 4] |= 1 << (crc & 0xf);
1165 ETHER_NEXT_MULTI(step, enm);
1166 }
1167 ETHER_UNLOCK(ec);
1168
1169 ifp->if_flags &= ~IFF_ALLMULTI;
1170
1171 chipit:
1172 /* Enable the hash filter */
1173 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]);
1174 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]);
1175 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]);
1176 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]);
1177
1178 v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1179 v &= ~BE_BR_RXCFG_PMISC;
1180 v |= BE_BR_RXCFG_HENABLE;
1181 bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1182 }
1183
1184 /*
1185 * Set the tcvr to an idle state
1186 */
1187 void
be_mii_sync(struct be_softc * sc)1188 be_mii_sync(struct be_softc *sc)
1189 {
1190 bus_space_tag_t t = sc->sc_bustag;
1191 bus_space_handle_t tr = sc->sc_tr;
1192 int n = 32;
1193
1194 while (n--) {
1195 bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1196 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB);
1197 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1198 bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1199 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
1200 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK);
1201 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1202 }
1203 }
1204
1205 void
be_pal_gate(struct be_softc * sc,int phy)1206 be_pal_gate(struct be_softc *sc, int phy)
1207 {
1208 bus_space_tag_t t = sc->sc_bustag;
1209 bus_space_handle_t tr = sc->sc_tr;
1210 uint32_t v;
1211
1212 be_mii_sync(sc);
1213
1214 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE);
1215 if (phy == BE_PHY_INTERNAL)
1216 v &= ~TCVR_PAL_SERIAL;
1217
1218 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v);
1219 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
1220 }
1221
1222 static int
be_tcvr_read_bit(struct be_softc * sc,int phy)1223 be_tcvr_read_bit(struct be_softc *sc, int phy)
1224 {
1225 bus_space_tag_t t = sc->sc_bustag;
1226 bus_space_handle_t tr = sc->sc_tr;
1227 int ret;
1228
1229 if (phy == BE_PHY_INTERNAL) {
1230 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO);
1231 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1232 bus_space_write_4(t, tr,
1233 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK);
1234 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1235 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
1236 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT;
1237 } else {
1238 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO);
1239 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1240 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
1241 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT;
1242 bus_space_write_4(t, tr,
1243 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK);
1244 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1245 }
1246
1247 return ret;
1248 }
1249
1250 static void
be_tcvr_write_bit(struct be_softc * sc,int phy,int bit)1251 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit)
1252 {
1253 bus_space_tag_t t = sc->sc_bustag;
1254 bus_space_handle_t tr = sc->sc_tr;
1255 uint32_t v;
1256
1257 if (phy == BE_PHY_INTERNAL) {
1258 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) |
1259 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO;
1260 } else {
1261 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) |
1262 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO;
1263 }
1264 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v);
1265 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1266 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK);
1267 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1268 }
1269
1270 static void
be_mii_sendbits(struct be_softc * sc,int phy,uint32_t data,int nbits)1271 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits)
1272 {
1273 int i;
1274
1275 for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
1276 be_tcvr_write_bit(sc, phy, (data & i) != 0);
1277 }
1278 }
1279
1280 static int
be_mii_readreg(device_t self,int phy,int reg,uint16_t * val)1281 be_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
1282 {
1283 struct be_softc *sc = device_private(self);
1284 int i;
1285 uint16_t data = 0;
1286
1287 /*
1288 * Read the PHY register by manually driving the MII control lines.
1289 */
1290 be_mii_sync(sc);
1291 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
1292 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);
1293 be_mii_sendbits(sc, phy, phy, 5);
1294 be_mii_sendbits(sc, phy, reg, 5);
1295
1296 (void)be_tcvr_read_bit(sc, phy);
1297 (void)be_tcvr_read_bit(sc, phy);
1298
1299 for (i = 15; i >= 0; i--)
1300 data |= (be_tcvr_read_bit(sc, phy) << i);
1301
1302 (void)be_tcvr_read_bit(sc, phy);
1303 (void)be_tcvr_read_bit(sc, phy);
1304 (void)be_tcvr_read_bit(sc, phy);
1305
1306 *val = data;
1307 return 0;
1308 }
1309
1310 int
be_mii_writereg(device_t self,int phy,int reg,uint16_t val)1311 be_mii_writereg(device_t self, int phy, int reg, uint16_t val)
1312 {
1313 struct be_softc *sc = device_private(self);
1314 int i;
1315
1316 /*
1317 * Write the PHY register by manually driving the MII control lines.
1318 */
1319 be_mii_sync(sc);
1320 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
1321 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);
1322 be_mii_sendbits(sc, phy, phy, 5);
1323 be_mii_sendbits(sc, phy, reg, 5);
1324
1325 be_tcvr_write_bit(sc, phy, 1);
1326 be_tcvr_write_bit(sc, phy, 0);
1327
1328 for (i = 15; i >= 0; i--)
1329 be_tcvr_write_bit(sc, phy, (val >> i) & 1);
1330
1331 return 0;
1332 }
1333
1334 int
be_mii_reset(struct be_softc * sc,int phy)1335 be_mii_reset(struct be_softc *sc, int phy)
1336 {
1337 device_t self = sc->sc_dev;
1338 int n;
1339
1340 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO);
1341 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET);
1342
1343 for (n = 16; n >= 0; n--) {
1344 uint16_t bmcr;
1345
1346 be_mii_readreg(self, phy, MII_BMCR, &bmcr);
1347 if ((bmcr & BMCR_RESET) == 0)
1348 break;
1349 DELAY(20);
1350 }
1351 if (n == 0) {
1352 aprint_error_dev(self, "bmcr reset failed\n");
1353 return EIO;
1354 }
1355
1356 return 0;
1357 }
1358
1359 void
be_tick(void * arg)1360 be_tick(void *arg)
1361 {
1362 struct be_softc *sc = arg;
1363 int s = splnet();
1364
1365 mii_tick(&sc->sc_mii);
1366 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK);
1367
1368 splx(s);
1369 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc);
1370 }
1371
1372 void
be_mii_statchg(struct ifnet * ifp)1373 be_mii_statchg(struct ifnet *ifp)
1374 {
1375 struct be_softc *sc = ifp->if_softc;
1376 bus_space_tag_t t = sc->sc_bustag;
1377 bus_space_handle_t br = sc->sc_br;
1378 uint instance;
1379 uint32_t v;
1380
1381 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1382 #ifdef DIAGNOSTIC
1383 if (instance > 1)
1384 panic("be_mii_statchg: instance %d out of range", instance);
1385 #endif
1386
1387 /* Update duplex mode in TX configuration */
1388 v = bus_space_read_4(t, br, BE_BRI_TXCFG);
1389 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
1390 v |= BE_BR_TXCFG_FULLDPLX;
1391 else
1392 v &= ~BE_BR_TXCFG_FULLDPLX;
1393 bus_space_write_4(t, br, BE_BRI_TXCFG, v);
1394
1395 /* Change to appropriate gate in transceiver PAL */
1396 be_pal_gate(sc, sc->sc_phys[instance]);
1397 }
1398
1399 /*
1400 * Get current media settings.
1401 */
1402 void
be_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1403 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1404 {
1405 struct be_softc *sc = ifp->if_softc;
1406
1407 mii_pollstat(&sc->sc_mii);
1408 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT);
1409
1410 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1411 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1412 }
1413
1414 /*
1415 * Set media options.
1416 */
1417 int
be_ifmedia_upd(struct ifnet * ifp)1418 be_ifmedia_upd(struct ifnet *ifp)
1419 {
1420 struct be_softc *sc = ifp->if_softc;
1421 int error;
1422
1423 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO)
1424 error = 0;
1425 else if (error != 0)
1426 return error;
1427
1428 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG);
1429 }
1430
1431 /*
1432 * Service routine for our pseudo-MII internal transceiver.
1433 */
1434 int
be_intphy_service(struct be_softc * sc,struct mii_data * mii,int cmd)1435 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd)
1436 {
1437 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
1438 device_t self = sc->sc_dev;
1439 uint16_t bmcr, bmsr;
1440 int error;
1441
1442 switch (cmd) {
1443 case MII_POLLSTAT:
1444 /*
1445 * If we're not polling our PHY instance, just return.
1446 */
1447 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
1448 return 0;
1449
1450 break;
1451
1452 case MII_MEDIACHG:
1453
1454 /*
1455 * If the media indicates a different PHY instance,
1456 * isolate ourselves.
1457 */
1458 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) {
1459 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1460 be_mii_writereg(self,
1461 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
1462 sc->sc_mii_flags &= ~MIIF_HAVELINK;
1463 sc->sc_intphy_curspeed = 0;
1464 return 0;
1465 }
1466
1467
1468 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0)
1469 return error;
1470
1471 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1472
1473 /*
1474 * Select the new mode and take out of isolation
1475 */
1476 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
1477 bmcr |= BMCR_S100;
1478 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T)
1479 bmcr &= ~BMCR_S100;
1480 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
1481 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) {
1482 bmcr &= ~BMCR_S100;
1483 bmcr |= sc->sc_intphy_curspeed;
1484 } else {
1485 /* Keep isolated until link is up */
1486 bmcr |= BMCR_ISO;
1487 sc->sc_mii_flags |= MIIF_DOINGAUTO;
1488 }
1489 }
1490
1491 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0)
1492 bmcr |= BMCR_FDX;
1493 else
1494 bmcr &= ~BMCR_FDX;
1495
1496 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr);
1497 break;
1498
1499 case MII_TICK:
1500 /*
1501 * If we're not currently selected, just return.
1502 */
1503 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
1504 return 0;
1505
1506 /* Is the interface even up? */
1507 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
1508 return 0;
1509
1510 /* Only used for automatic media selection */
1511 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
1512 break;
1513
1514 /*
1515 * Check link status; if we don't have a link, try another
1516 * speed. We can't detect duplex mode, so half-duplex is
1517 * what we have to settle for.
1518 */
1519
1520 /* Read twice in case the register is latched */
1521 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr);
1522 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr);
1523
1524 if ((bmsr & BMSR_LINK) != 0) {
1525 /* We have a carrier */
1526 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1527
1528 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) {
1529 be_mii_readreg(self,
1530 BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1531
1532 sc->sc_mii_flags |= MIIF_HAVELINK;
1533 sc->sc_intphy_curspeed = (bmcr & BMCR_S100);
1534 sc->sc_mii_flags &= ~MIIF_DOINGAUTO;
1535
1536 bmcr &= ~BMCR_ISO;
1537 be_mii_writereg(self,
1538 BE_PHY_INTERNAL, MII_BMCR, bmcr);
1539
1540 printf("%s: link up at %s Mbps\n",
1541 device_xname(self),
1542 (bmcr & BMCR_S100) ? "100" : "10");
1543 }
1544 break;
1545 }
1546
1547 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) {
1548 sc->sc_mii_flags |= MIIF_DOINGAUTO;
1549 sc->sc_mii_flags &= ~MIIF_HAVELINK;
1550 sc->sc_intphy_curspeed = 0;
1551 printf("%s: link down\n", device_xname(self));
1552 }
1553
1554 /* Only retry autonegotiation every 5 seconds. */
1555 if (++sc->sc_mii_ticks < 5)
1556 return 0;
1557
1558 sc->sc_mii_ticks = 0;
1559 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1560 /* Just flip the fast speed bit */
1561 bmcr ^= BMCR_S100;
1562 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr);
1563
1564 break;
1565
1566 case MII_DOWN:
1567 /* Isolate this phy */
1568 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1569 be_mii_writereg(self,
1570 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
1571 return 0;
1572 }
1573
1574 /* Update the media status. */
1575 be_intphy_status(sc);
1576
1577 /* Callback if something changed. */
1578 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
1579 (*mii->mii_statchg)(mii->mii_ifp);
1580 sc->sc_mii_active = mii->mii_media_active;
1581 }
1582 return 0;
1583 }
1584
1585 /*
1586 * Determine status of internal transceiver
1587 */
1588 void
be_intphy_status(struct be_softc * sc)1589 be_intphy_status(struct be_softc *sc)
1590 {
1591 struct mii_data *mii = &sc->sc_mii;
1592 device_t self = sc->sc_dev;
1593 int media_active, media_status;
1594 uint16_t bmcr, bmsr;
1595
1596 media_status = IFM_AVALID;
1597 media_active = 0;
1598
1599 /*
1600 * Internal transceiver; do the work here.
1601 */
1602 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr);
1603
1604 switch (bmcr & (BMCR_S100 | BMCR_FDX)) {
1605 case (BMCR_S100 | BMCR_FDX):
1606 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1607 break;
1608 case BMCR_S100:
1609 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1610 break;
1611 case BMCR_FDX:
1612 media_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1613 break;
1614 case 0:
1615 media_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1616 break;
1617 }
1618
1619 /* Read twice in case the register is latched */
1620 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr);
1621 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr);
1622 if (bmsr & BMSR_LINK)
1623 media_status |= IFM_ACTIVE;
1624
1625 mii->mii_media_status = media_status;
1626 mii->mii_media_active = media_active;
1627 }
1628