1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
84
85 #include <net/debugnet.h>
86 #include <net/if.h>
87 #include <net/if_var.h>
88 #include <net/if_arp.h>
89 #include <net/ethernet.h>
90 #include <net/if_dl.h>
91 #include <net/if_media.h>
92
93 #include <net/bpf.h>
94
95 #include <net/if_types.h>
96 #include <net/if_vlan_var.h>
97
98 #include <netinet/in_systm.h>
99 #include <netinet/in.h>
100 #include <netinet/ip.h>
101 #include <netinet/tcp.h>
102
103 #include <machine/bus.h>
104 #include <machine/resource.h>
105 #include <sys/bus.h>
106 #include <sys/rman.h>
107
108 #include <dev/mii/mii.h>
109 #include <dev/mii/miivar.h>
110 #include "miidevs.h"
111 #include <dev/mii/brgphyreg.h>
112
113 #include <dev/pci/pcireg.h>
114 #include <dev/pci/pcivar.h>
115
116 #include <dev/bge/if_bgereg.h>
117
118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
119 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
120
121 MODULE_DEPEND(bge, pci, 1, 1, 1);
122 MODULE_DEPEND(bge, ether, 1, 1, 1);
123 MODULE_DEPEND(bge, miibus, 1, 1, 1);
124
125 /* "device miibus" required. See GENERIC if you get errors here. */
126 #include "miibus_if.h"
127
128 /*
129 * Various supported device vendors/types and their names. Note: the
130 * spec seems to indicate that the hardware still has Alteon's vendor
131 * ID burned into it, though it will always be overridden by the vendor
132 * ID in the EEPROM. Just to be safe, we cover all possibilities.
133 */
134 static const struct bge_type {
135 uint16_t bge_vid;
136 uint16_t bge_did;
137 } bge_devs[] = {
138 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
139 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
140
141 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
142 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
143 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
144
145 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
146
147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
233
234 { SK_VENDORID, SK_DEVICEID_ALTIMA },
235
236 { TC_VENDORID, TC_DEVICEID_3C996 },
237
238 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
239 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
240 { 0, 0 }
241 };
242
243 static const struct bge_vendor {
244 uint16_t v_id;
245 const char *v_name;
246 } bge_vendors[] = {
247 { ALTEON_VENDORID, "Alteon" },
248 { ALTIMA_VENDORID, "Altima" },
249 { APPLE_VENDORID, "Apple" },
250 { BCOM_VENDORID, "Broadcom" },
251 { SK_VENDORID, "SysKonnect" },
252 { TC_VENDORID, "3Com" },
253 { FJTSU_VENDORID, "Fujitsu" },
254 { 0, NULL }
255 };
256
257 static const struct bge_revision {
258 uint32_t br_chipid;
259 const char *br_name;
260 } bge_revisions[] = {
261 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
262 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
263 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
264 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
265 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
266 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
267 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
268 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
269 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
270 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
271 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
272 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
273 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
274 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
275 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
276 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
277 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
278 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
279 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
280 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
281 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
282 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
283 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
284 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
285 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
286 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
287 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
288 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
289 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
290 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
291 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
292 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
293 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
294 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
295 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
296 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
297 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
298 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
299 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
300 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
301 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
302 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
303 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
304 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
305 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
306 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" },
307 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
308 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
309 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
310 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
311 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
312 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
313 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
314 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
315 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
316 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
317 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
318 /* 5754 and 5787 share the same ASIC ID */
319 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
320 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
321 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
322 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
323 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
324 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
325 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
326 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
327 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
328 { 0, NULL }
329 };
330
331 /*
332 * Some defaults for major revisions, so that newer steppings
333 * that we don't know about have a shot at working.
334 */
335 static const struct bge_revision bge_majorrevs[] = {
336 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
337 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
338 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
339 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
340 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
341 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
342 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
343 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
344 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
345 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
346 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
347 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
348 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
349 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
350 /* 5754 and 5787 share the same ASIC ID */
351 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
352 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
353 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
354 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
355 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
356 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
357 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
358 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
359 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
360 { 0, NULL }
361 };
362
363 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
364 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
365 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
366 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
367 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
368 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
369 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
370 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
371
372 static uint32_t bge_chipid(device_t);
373 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
374 static const struct bge_revision * bge_lookup_rev(uint32_t);
375
376 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
377
378 static int bge_probe(device_t);
379 static int bge_attach(device_t);
380 static int bge_detach(device_t);
381 static int bge_suspend(device_t);
382 static int bge_resume(device_t);
383 static void bge_release_resources(struct bge_softc *);
384 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
385 static int bge_dma_alloc(struct bge_softc *);
386 static void bge_dma_free(struct bge_softc *);
387 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
388 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
389
390 static void bge_devinfo(struct bge_softc *);
391 static int bge_mbox_reorder(struct bge_softc *);
392
393 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
394 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
395 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
396 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
397 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
398
399 static void bge_txeof(struct bge_softc *, uint16_t);
400 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
401 static int bge_rxeof(struct bge_softc *, uint16_t, int);
402
403 static void bge_asf_driver_up (struct bge_softc *);
404 static void bge_tick(void *);
405 static void bge_stats_clear_regs(struct bge_softc *);
406 static void bge_stats_update(struct bge_softc *);
407 static void bge_stats_update_regs(struct bge_softc *);
408 static struct mbuf *bge_check_short_dma(struct mbuf *);
409 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
410 uint16_t *, uint16_t *);
411 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
412
413 static void bge_intr(void *);
414 static int bge_msi_intr(void *);
415 static void bge_intr_task(void *, int);
416 static void bge_start(if_t);
417 static void bge_start_locked(if_t);
418 static void bge_start_tx(struct bge_softc *, uint32_t);
419 static int bge_ioctl(if_t, u_long, caddr_t);
420 static void bge_init_locked(struct bge_softc *);
421 static void bge_init(void *);
422 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
423 static void bge_stop(struct bge_softc *);
424 static void bge_watchdog(struct bge_softc *);
425 static int bge_shutdown(device_t);
426 static int bge_ifmedia_upd_locked(if_t);
427 static int bge_ifmedia_upd(if_t);
428 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
429 static uint64_t bge_get_counter(if_t, ift_counter);
430
431 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
432 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
433
434 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
435 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
436
437 static void bge_setpromisc(struct bge_softc *);
438 static void bge_setmulti(struct bge_softc *);
439 static void bge_setvlan(struct bge_softc *);
440
441 static __inline void bge_rxreuse_std(struct bge_softc *, int);
442 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
443 static int bge_newbuf_std(struct bge_softc *, int);
444 static int bge_newbuf_jumbo(struct bge_softc *, int);
445 static int bge_init_rx_ring_std(struct bge_softc *);
446 static void bge_free_rx_ring_std(struct bge_softc *);
447 static int bge_init_rx_ring_jumbo(struct bge_softc *);
448 static void bge_free_rx_ring_jumbo(struct bge_softc *);
449 static void bge_free_tx_ring(struct bge_softc *);
450 static int bge_init_tx_ring(struct bge_softc *);
451
452 static int bge_chipinit(struct bge_softc *);
453 static int bge_blockinit(struct bge_softc *);
454 static uint32_t bge_dma_swap_options(struct bge_softc *);
455
456 static int bge_has_eaddr(struct bge_softc *);
457 static uint32_t bge_readmem_ind(struct bge_softc *, int);
458 static void bge_writemem_ind(struct bge_softc *, int, int);
459 static void bge_writembx(struct bge_softc *, int, int);
460 #ifdef notdef
461 static uint32_t bge_readreg_ind(struct bge_softc *, int);
462 #endif
463 static void bge_writemem_direct(struct bge_softc *, int, int);
464 static void bge_writereg_ind(struct bge_softc *, int, int);
465
466 static int bge_miibus_readreg(device_t, int, int);
467 static int bge_miibus_writereg(device_t, int, int, int);
468 static void bge_miibus_statchg(device_t);
469 #ifdef DEVICE_POLLING
470 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
471 #endif
472
473 #define BGE_RESET_SHUTDOWN 0
474 #define BGE_RESET_START 1
475 #define BGE_RESET_SUSPEND 2
476 static void bge_sig_post_reset(struct bge_softc *, int);
477 static void bge_sig_legacy(struct bge_softc *, int);
478 static void bge_sig_pre_reset(struct bge_softc *, int);
479 static void bge_stop_fw(struct bge_softc *);
480 static int bge_reset(struct bge_softc *);
481 static void bge_link_upd(struct bge_softc *);
482
483 static void bge_ape_lock_init(struct bge_softc *);
484 static void bge_ape_read_fw_ver(struct bge_softc *);
485 static int bge_ape_lock(struct bge_softc *, int);
486 static void bge_ape_unlock(struct bge_softc *, int);
487 static void bge_ape_send_event(struct bge_softc *, uint32_t);
488 static void bge_ape_driver_state_change(struct bge_softc *, int);
489
490 /*
491 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
492 * leak information to untrusted users. It is also known to cause alignment
493 * traps on certain architectures.
494 */
495 #ifdef BGE_REGISTER_DEBUG
496 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
497 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
498 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
499 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
500 #endif
501 static void bge_add_sysctls(struct bge_softc *);
502 static void bge_add_sysctl_stats_regs(struct bge_softc *,
503 struct sysctl_ctx_list *, struct sysctl_oid_list *);
504 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
505 struct sysctl_oid_list *);
506 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
507
508 DEBUGNET_DEFINE(bge);
509
510 static device_method_t bge_methods[] = {
511 /* Device interface */
512 DEVMETHOD(device_probe, bge_probe),
513 DEVMETHOD(device_attach, bge_attach),
514 DEVMETHOD(device_detach, bge_detach),
515 DEVMETHOD(device_shutdown, bge_shutdown),
516 DEVMETHOD(device_suspend, bge_suspend),
517 DEVMETHOD(device_resume, bge_resume),
518
519 /* MII interface */
520 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
521 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
522 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
523
524 DEVMETHOD_END
525 };
526
527 static driver_t bge_driver = {
528 "bge",
529 bge_methods,
530 sizeof(struct bge_softc)
531 };
532
533 DRIVER_MODULE(bge, pci, bge_driver, 0, 0);
534 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
535 nitems(bge_devs) - 1);
536 DRIVER_MODULE(miibus, bge, miibus_driver, 0, 0);
537
538 static int bge_allow_asf = 1;
539
540 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
541 "BGE driver parameters");
542 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
543 "Allow ASF mode if available");
544
545 static int
bge_has_eaddr(struct bge_softc * sc)546 bge_has_eaddr(struct bge_softc *sc)
547 {
548 return (1);
549 }
550
551 static uint32_t
bge_readmem_ind(struct bge_softc * sc,int off)552 bge_readmem_ind(struct bge_softc *sc, int off)
553 {
554 device_t dev;
555 uint32_t val;
556
557 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
558 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
559 return (0);
560
561 dev = sc->bge_dev;
562
563 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
564 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
565 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
566 return (val);
567 }
568
569 static void
bge_writemem_ind(struct bge_softc * sc,int off,int val)570 bge_writemem_ind(struct bge_softc *sc, int off, int val)
571 {
572 device_t dev;
573
574 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
575 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
576 return;
577
578 dev = sc->bge_dev;
579
580 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
581 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
582 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
583 }
584
585 #ifdef notdef
586 static uint32_t
bge_readreg_ind(struct bge_softc * sc,int off)587 bge_readreg_ind(struct bge_softc *sc, int off)
588 {
589 device_t dev;
590
591 dev = sc->bge_dev;
592
593 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
594 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
595 }
596 #endif
597
598 static void
bge_writereg_ind(struct bge_softc * sc,int off,int val)599 bge_writereg_ind(struct bge_softc *sc, int off, int val)
600 {
601 device_t dev;
602
603 dev = sc->bge_dev;
604
605 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
606 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
607 }
608
609 static void
bge_writemem_direct(struct bge_softc * sc,int off,int val)610 bge_writemem_direct(struct bge_softc *sc, int off, int val)
611 {
612 CSR_WRITE_4(sc, off, val);
613 }
614
615 static void
bge_writembx(struct bge_softc * sc,int off,int val)616 bge_writembx(struct bge_softc *sc, int off, int val)
617 {
618 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
619 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
620
621 CSR_WRITE_4(sc, off, val);
622 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
623 CSR_READ_4(sc, off);
624 }
625
626 /*
627 * Clear all stale locks and select the lock for this driver instance.
628 */
629 static void
bge_ape_lock_init(struct bge_softc * sc)630 bge_ape_lock_init(struct bge_softc *sc)
631 {
632 uint32_t bit, regbase;
633 int i;
634
635 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
636 regbase = BGE_APE_LOCK_GRANT;
637 else
638 regbase = BGE_APE_PER_LOCK_GRANT;
639
640 /* Clear any stale locks. */
641 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
642 switch (i) {
643 case BGE_APE_LOCK_PHY0:
644 case BGE_APE_LOCK_PHY1:
645 case BGE_APE_LOCK_PHY2:
646 case BGE_APE_LOCK_PHY3:
647 bit = BGE_APE_LOCK_GRANT_DRIVER0;
648 break;
649 default:
650 if (sc->bge_func_addr == 0)
651 bit = BGE_APE_LOCK_GRANT_DRIVER0;
652 else
653 bit = (1 << sc->bge_func_addr);
654 }
655 APE_WRITE_4(sc, regbase + 4 * i, bit);
656 }
657
658 /* Select the PHY lock based on the device's function number. */
659 switch (sc->bge_func_addr) {
660 case 0:
661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
662 break;
663 case 1:
664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
665 break;
666 case 2:
667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
668 break;
669 case 3:
670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
671 break;
672 default:
673 device_printf(sc->bge_dev,
674 "PHY lock not supported on this function\n");
675 }
676 }
677
678 /*
679 * Check for APE firmware, set flags, and print version info.
680 */
681 static void
bge_ape_read_fw_ver(struct bge_softc * sc)682 bge_ape_read_fw_ver(struct bge_softc *sc)
683 {
684 const char *fwtype;
685 uint32_t apedata, features;
686
687 /* Check for a valid APE signature in shared memory. */
688 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
689 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
690 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
691 return;
692 }
693
694 /* Check if APE firmware is running. */
695 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
696 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
697 device_printf(sc->bge_dev, "APE signature found "
698 "but FW status not ready! 0x%08x\n", apedata);
699 return;
700 }
701
702 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
703
704 /* Fetch the APE firmware type and version. */
705 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
706 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
707 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
708 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
709 fwtype = "NCSI";
710 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
711 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
712 fwtype = "DASH";
713 } else
714 fwtype = "UNKN";
715
716 /* Print the APE firmware version. */
717 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
718 fwtype,
719 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
720 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
721 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
722 (apedata & BGE_APE_FW_VERSION_BLDMSK));
723 }
724
725 static int
bge_ape_lock(struct bge_softc * sc,int locknum)726 bge_ape_lock(struct bge_softc *sc, int locknum)
727 {
728 uint32_t bit, gnt, req, status;
729 int i, off;
730
731 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
732 return (0);
733
734 /* Lock request/grant registers have different bases. */
735 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
736 req = BGE_APE_LOCK_REQ;
737 gnt = BGE_APE_LOCK_GRANT;
738 } else {
739 req = BGE_APE_PER_LOCK_REQ;
740 gnt = BGE_APE_PER_LOCK_GRANT;
741 }
742
743 off = 4 * locknum;
744
745 switch (locknum) {
746 case BGE_APE_LOCK_GPIO:
747 /* Lock required when using GPIO. */
748 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
749 return (0);
750 if (sc->bge_func_addr == 0)
751 bit = BGE_APE_LOCK_REQ_DRIVER0;
752 else
753 bit = (1 << sc->bge_func_addr);
754 break;
755 case BGE_APE_LOCK_GRC:
756 /* Lock required to reset the device. */
757 if (sc->bge_func_addr == 0)
758 bit = BGE_APE_LOCK_REQ_DRIVER0;
759 else
760 bit = (1 << sc->bge_func_addr);
761 break;
762 case BGE_APE_LOCK_MEM:
763 /* Lock required when accessing certain APE memory. */
764 if (sc->bge_func_addr == 0)
765 bit = BGE_APE_LOCK_REQ_DRIVER0;
766 else
767 bit = (1 << sc->bge_func_addr);
768 break;
769 case BGE_APE_LOCK_PHY0:
770 case BGE_APE_LOCK_PHY1:
771 case BGE_APE_LOCK_PHY2:
772 case BGE_APE_LOCK_PHY3:
773 /* Lock required when accessing PHYs. */
774 bit = BGE_APE_LOCK_REQ_DRIVER0;
775 break;
776 default:
777 return (EINVAL);
778 }
779
780 /* Request a lock. */
781 APE_WRITE_4(sc, req + off, bit);
782
783 /* Wait up to 1 second to acquire lock. */
784 for (i = 0; i < 20000; i++) {
785 status = APE_READ_4(sc, gnt + off);
786 if (status == bit)
787 break;
788 DELAY(50);
789 }
790
791 /* Handle any errors. */
792 if (status != bit) {
793 device_printf(sc->bge_dev, "APE lock %d request failed! "
794 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
795 locknum, req + off, bit & 0xFFFF, gnt + off,
796 status & 0xFFFF);
797 /* Revoke the lock request. */
798 APE_WRITE_4(sc, gnt + off, bit);
799 return (EBUSY);
800 }
801
802 return (0);
803 }
804
805 static void
bge_ape_unlock(struct bge_softc * sc,int locknum)806 bge_ape_unlock(struct bge_softc *sc, int locknum)
807 {
808 uint32_t bit, gnt;
809 int off;
810
811 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
812 return;
813
814 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
815 gnt = BGE_APE_LOCK_GRANT;
816 else
817 gnt = BGE_APE_PER_LOCK_GRANT;
818
819 off = 4 * locknum;
820
821 switch (locknum) {
822 case BGE_APE_LOCK_GPIO:
823 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
824 return;
825 if (sc->bge_func_addr == 0)
826 bit = BGE_APE_LOCK_GRANT_DRIVER0;
827 else
828 bit = (1 << sc->bge_func_addr);
829 break;
830 case BGE_APE_LOCK_GRC:
831 if (sc->bge_func_addr == 0)
832 bit = BGE_APE_LOCK_GRANT_DRIVER0;
833 else
834 bit = (1 << sc->bge_func_addr);
835 break;
836 case BGE_APE_LOCK_MEM:
837 if (sc->bge_func_addr == 0)
838 bit = BGE_APE_LOCK_GRANT_DRIVER0;
839 else
840 bit = (1 << sc->bge_func_addr);
841 break;
842 case BGE_APE_LOCK_PHY0:
843 case BGE_APE_LOCK_PHY1:
844 case BGE_APE_LOCK_PHY2:
845 case BGE_APE_LOCK_PHY3:
846 bit = BGE_APE_LOCK_GRANT_DRIVER0;
847 break;
848 default:
849 return;
850 }
851
852 APE_WRITE_4(sc, gnt + off, bit);
853 }
854
855 /*
856 * Send an event to the APE firmware.
857 */
858 static void
bge_ape_send_event(struct bge_softc * sc,uint32_t event)859 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
860 {
861 uint32_t apedata;
862 int i;
863
864 /* NCSI does not support APE events. */
865 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
866 return;
867
868 /* Wait up to 1ms for APE to service previous event. */
869 for (i = 10; i > 0; i--) {
870 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
871 break;
872 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
873 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
874 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
875 BGE_APE_EVENT_STATUS_EVENT_PENDING);
876 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
877 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
878 break;
879 }
880 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
881 DELAY(100);
882 }
883 if (i == 0)
884 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
885 event);
886 }
887
888 static void
bge_ape_driver_state_change(struct bge_softc * sc,int kind)889 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
890 {
891 uint32_t apedata, event;
892
893 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
894 return;
895
896 switch (kind) {
897 case BGE_RESET_START:
898 /* If this is the first load, clear the load counter. */
899 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
900 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
901 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
902 else {
903 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
904 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
905 }
906 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
907 BGE_APE_HOST_SEG_SIG_MAGIC);
908 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
909 BGE_APE_HOST_SEG_LEN_MAGIC);
910
911 /* Add some version info if bge(4) supports it. */
912 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
913 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
914 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
915 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
916 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
917 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
918 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
919 BGE_APE_HOST_DRVR_STATE_START);
920 event = BGE_APE_EVENT_STATUS_STATE_START;
921 break;
922 case BGE_RESET_SHUTDOWN:
923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
924 BGE_APE_HOST_DRVR_STATE_UNLOAD);
925 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
926 break;
927 case BGE_RESET_SUSPEND:
928 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
929 break;
930 default:
931 return;
932 }
933
934 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
935 BGE_APE_EVENT_STATUS_STATE_CHNGE);
936 }
937
938 /*
939 * Map a single buffer address.
940 */
941
942 static void
bge_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)943 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
944 {
945 struct bge_dmamap_arg *ctx;
946
947 if (error)
948 return;
949
950 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
951
952 ctx = arg;
953 ctx->bge_busaddr = segs->ds_addr;
954 }
955
956 static uint8_t
bge_nvram_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)957 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
958 {
959 uint32_t access, byte = 0;
960 int i;
961
962 /* Lock. */
963 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
964 for (i = 0; i < 8000; i++) {
965 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
966 break;
967 DELAY(20);
968 }
969 if (i == 8000)
970 return (1);
971
972 /* Enable access. */
973 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
974 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
975
976 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
977 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
978 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
979 DELAY(10);
980 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
981 DELAY(10);
982 break;
983 }
984 }
985
986 if (i == BGE_TIMEOUT * 10) {
987 if_printf(sc->bge_ifp, "nvram read timed out\n");
988 return (1);
989 }
990
991 /* Get result. */
992 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
993
994 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
995
996 /* Disable access. */
997 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
998
999 /* Unlock. */
1000 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1001 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1002
1003 return (0);
1004 }
1005
1006 /*
1007 * Read a sequence of bytes from NVRAM.
1008 */
1009 static int
bge_read_nvram(struct bge_softc * sc,caddr_t dest,int off,int cnt)1010 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1011 {
1012 int err = 0, i;
1013 uint8_t byte = 0;
1014
1015 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1016 return (1);
1017
1018 for (i = 0; i < cnt; i++) {
1019 err = bge_nvram_getbyte(sc, off + i, &byte);
1020 if (err)
1021 break;
1022 *(dest + i) = byte;
1023 }
1024
1025 return (err ? 1 : 0);
1026 }
1027
1028 /*
1029 * Read a byte of data stored in the EEPROM at address 'addr.' The
1030 * BCM570x supports both the traditional bitbang interface and an
1031 * auto access interface for reading the EEPROM. We use the auto
1032 * access method.
1033 */
1034 static uint8_t
bge_eeprom_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)1035 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1036 {
1037 int i;
1038 uint32_t byte = 0;
1039
1040 /*
1041 * Enable use of auto EEPROM access so we can avoid
1042 * having to use the bitbang method.
1043 */
1044 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1045
1046 /* Reset the EEPROM, load the clock period. */
1047 CSR_WRITE_4(sc, BGE_EE_ADDR,
1048 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1049 DELAY(20);
1050
1051 /* Issue the read EEPROM command. */
1052 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1053
1054 /* Wait for completion */
1055 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1056 DELAY(10);
1057 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1058 break;
1059 }
1060
1061 if (i == BGE_TIMEOUT * 10) {
1062 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1063 return (1);
1064 }
1065
1066 /* Get result. */
1067 byte = CSR_READ_4(sc, BGE_EE_DATA);
1068
1069 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1070
1071 return (0);
1072 }
1073
1074 /*
1075 * Read a sequence of bytes from the EEPROM.
1076 */
1077 static int
bge_read_eeprom(struct bge_softc * sc,caddr_t dest,int off,int cnt)1078 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1079 {
1080 int i, error = 0;
1081 uint8_t byte = 0;
1082
1083 for (i = 0; i < cnt; i++) {
1084 error = bge_eeprom_getbyte(sc, off + i, &byte);
1085 if (error)
1086 break;
1087 *(dest + i) = byte;
1088 }
1089
1090 return (error ? 1 : 0);
1091 }
1092
1093 static int
bge_miibus_readreg(device_t dev,int phy,int reg)1094 bge_miibus_readreg(device_t dev, int phy, int reg)
1095 {
1096 struct bge_softc *sc;
1097 uint32_t val;
1098 int i;
1099
1100 sc = device_get_softc(dev);
1101
1102 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1103 return (0);
1104
1105 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1106 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1107 CSR_WRITE_4(sc, BGE_MI_MODE,
1108 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1109 DELAY(80);
1110 }
1111
1112 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1113 BGE_MIPHY(phy) | BGE_MIREG(reg));
1114
1115 /* Poll for the PHY register access to complete. */
1116 for (i = 0; i < BGE_TIMEOUT; i++) {
1117 DELAY(10);
1118 val = CSR_READ_4(sc, BGE_MI_COMM);
1119 if ((val & BGE_MICOMM_BUSY) == 0) {
1120 DELAY(5);
1121 val = CSR_READ_4(sc, BGE_MI_COMM);
1122 break;
1123 }
1124 }
1125
1126 if (i == BGE_TIMEOUT) {
1127 device_printf(sc->bge_dev,
1128 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1129 phy, reg, val);
1130 val = 0;
1131 }
1132
1133 /* Restore the autopoll bit if necessary. */
1134 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1135 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1136 DELAY(80);
1137 }
1138
1139 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1140
1141 if (val & BGE_MICOMM_READFAIL)
1142 return (0);
1143
1144 return (val & 0xFFFF);
1145 }
1146
1147 static int
bge_miibus_writereg(device_t dev,int phy,int reg,int val)1148 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1149 {
1150 struct bge_softc *sc;
1151 int i;
1152
1153 sc = device_get_softc(dev);
1154
1155 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1156 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1157 return (0);
1158
1159 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1160 return (0);
1161
1162 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1163 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1164 CSR_WRITE_4(sc, BGE_MI_MODE,
1165 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1166 DELAY(80);
1167 }
1168
1169 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1170 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1171
1172 for (i = 0; i < BGE_TIMEOUT; i++) {
1173 DELAY(10);
1174 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1175 DELAY(5);
1176 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1177 break;
1178 }
1179 }
1180
1181 /* Restore the autopoll bit if necessary. */
1182 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1183 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1184 DELAY(80);
1185 }
1186
1187 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1188
1189 if (i == BGE_TIMEOUT)
1190 device_printf(sc->bge_dev,
1191 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1192 phy, reg, val);
1193
1194 return (0);
1195 }
1196
1197 static void
bge_miibus_statchg(device_t dev)1198 bge_miibus_statchg(device_t dev)
1199 {
1200 struct bge_softc *sc;
1201 struct mii_data *mii;
1202 uint32_t mac_mode, rx_mode, tx_mode;
1203
1204 sc = device_get_softc(dev);
1205 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1206 return;
1207 mii = device_get_softc(sc->bge_miibus);
1208
1209 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1210 (IFM_ACTIVE | IFM_AVALID)) {
1211 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1212 case IFM_10_T:
1213 case IFM_100_TX:
1214 sc->bge_link = 1;
1215 break;
1216 case IFM_1000_T:
1217 case IFM_1000_SX:
1218 case IFM_2500_SX:
1219 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1220 sc->bge_link = 1;
1221 else
1222 sc->bge_link = 0;
1223 break;
1224 default:
1225 sc->bge_link = 0;
1226 break;
1227 }
1228 } else
1229 sc->bge_link = 0;
1230 if (sc->bge_link == 0)
1231 return;
1232
1233 /*
1234 * APE firmware touches these registers to keep the MAC
1235 * connected to the outside world. Try to keep the
1236 * accesses atomic.
1237 */
1238
1239 /* Set the port mode (MII/GMII) to match the link speed. */
1240 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1241 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1242 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1243 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1244
1245 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1246 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1247 mac_mode |= BGE_PORTMODE_GMII;
1248 else
1249 mac_mode |= BGE_PORTMODE_MII;
1250
1251 /* Set MAC flow control behavior to match link flow control settings. */
1252 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1253 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1254 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1255 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1256 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1257 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1258 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1259 } else
1260 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1261
1262 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1263 DELAY(40);
1264 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1265 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1266 }
1267
1268 /*
1269 * Intialize a standard receive ring descriptor.
1270 */
1271 static int
bge_newbuf_std(struct bge_softc * sc,int i)1272 bge_newbuf_std(struct bge_softc *sc, int i)
1273 {
1274 struct mbuf *m;
1275 struct bge_rx_bd *r;
1276 bus_dma_segment_t segs[1];
1277 bus_dmamap_t map;
1278 int error, nsegs;
1279
1280 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1281 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1282 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1283 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1284 if (m == NULL)
1285 return (ENOBUFS);
1286 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1287 } else {
1288 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1289 if (m == NULL)
1290 return (ENOBUFS);
1291 m->m_len = m->m_pkthdr.len = MCLBYTES;
1292 }
1293 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1294 m_adj(m, ETHER_ALIGN);
1295
1296 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1297 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1298 if (error != 0) {
1299 m_freem(m);
1300 return (error);
1301 }
1302 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1303 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1304 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1305 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1306 sc->bge_cdata.bge_rx_std_dmamap[i]);
1307 }
1308 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1309 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1310 sc->bge_cdata.bge_rx_std_sparemap = map;
1311 sc->bge_cdata.bge_rx_std_chain[i] = m;
1312 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1313 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1314 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1315 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1316 r->bge_flags = BGE_RXBDFLAG_END;
1317 r->bge_len = segs[0].ds_len;
1318 r->bge_idx = i;
1319
1320 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1321 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1322
1323 return (0);
1324 }
1325
1326 /*
1327 * Initialize a jumbo receive ring descriptor. This allocates
1328 * a jumbo buffer from the pool managed internally by the driver.
1329 */
1330 static int
bge_newbuf_jumbo(struct bge_softc * sc,int i)1331 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1332 {
1333 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1334 bus_dmamap_t map;
1335 struct bge_extrx_bd *r;
1336 struct mbuf *m;
1337 int error, nsegs;
1338
1339 MGETHDR(m, M_NOWAIT, MT_DATA);
1340 if (m == NULL)
1341 return (ENOBUFS);
1342
1343 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1344 m_freem(m);
1345 return (ENOBUFS);
1346 }
1347 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1348 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1349 m_adj(m, ETHER_ALIGN);
1350
1351 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1352 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1353 if (error != 0) {
1354 m_freem(m);
1355 return (error);
1356 }
1357
1358 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1359 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1360 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1361 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1362 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1363 }
1364 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1365 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1366 sc->bge_cdata.bge_rx_jumbo_sparemap;
1367 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1368 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1369 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1370 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1371 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1372 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1373
1374 /*
1375 * Fill in the extended RX buffer descriptor.
1376 */
1377 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1378 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1379 r->bge_idx = i;
1380 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1381 switch (nsegs) {
1382 case 4:
1383 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1384 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1385 r->bge_len3 = segs[3].ds_len;
1386 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1387 case 3:
1388 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1389 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1390 r->bge_len2 = segs[2].ds_len;
1391 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1392 case 2:
1393 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1394 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1395 r->bge_len1 = segs[1].ds_len;
1396 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1397 case 1:
1398 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1399 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1400 r->bge_len0 = segs[0].ds_len;
1401 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1402 break;
1403 default:
1404 panic("%s: %d segments\n", __func__, nsegs);
1405 }
1406
1407 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1408 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1409
1410 return (0);
1411 }
1412
1413 static int
bge_init_rx_ring_std(struct bge_softc * sc)1414 bge_init_rx_ring_std(struct bge_softc *sc)
1415 {
1416 int error, i;
1417
1418 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1419 sc->bge_std = 0;
1420 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1421 if ((error = bge_newbuf_std(sc, i)) != 0)
1422 return (error);
1423 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1424 }
1425
1426 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1427 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1428
1429 sc->bge_std = 0;
1430 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1431
1432 return (0);
1433 }
1434
1435 static void
bge_free_rx_ring_std(struct bge_softc * sc)1436 bge_free_rx_ring_std(struct bge_softc *sc)
1437 {
1438 int i;
1439
1440 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1441 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1442 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1443 sc->bge_cdata.bge_rx_std_dmamap[i],
1444 BUS_DMASYNC_POSTREAD);
1445 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1446 sc->bge_cdata.bge_rx_std_dmamap[i]);
1447 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1448 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1449 }
1450 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1451 sizeof(struct bge_rx_bd));
1452 }
1453 }
1454
1455 static int
bge_init_rx_ring_jumbo(struct bge_softc * sc)1456 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1457 {
1458 struct bge_rcb *rcb;
1459 int error, i;
1460
1461 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1462 sc->bge_jumbo = 0;
1463 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1464 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1465 return (error);
1466 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1467 }
1468
1469 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1470 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1471
1472 sc->bge_jumbo = 0;
1473
1474 /* Enable the jumbo receive producer ring. */
1475 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1476 rcb->bge_maxlen_flags =
1477 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1478 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1479
1480 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1481
1482 return (0);
1483 }
1484
1485 static void
bge_free_rx_ring_jumbo(struct bge_softc * sc)1486 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1487 {
1488 int i;
1489
1490 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1491 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1492 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1493 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1494 BUS_DMASYNC_POSTREAD);
1495 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1496 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1497 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1498 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1499 }
1500 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1501 sizeof(struct bge_extrx_bd));
1502 }
1503 }
1504
1505 static void
bge_free_tx_ring(struct bge_softc * sc)1506 bge_free_tx_ring(struct bge_softc *sc)
1507 {
1508 int i;
1509
1510 if (sc->bge_ldata.bge_tx_ring == NULL)
1511 return;
1512
1513 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1514 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1515 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1516 sc->bge_cdata.bge_tx_dmamap[i],
1517 BUS_DMASYNC_POSTWRITE);
1518 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1519 sc->bge_cdata.bge_tx_dmamap[i]);
1520 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1521 sc->bge_cdata.bge_tx_chain[i] = NULL;
1522 }
1523 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1524 sizeof(struct bge_tx_bd));
1525 }
1526 }
1527
1528 static int
bge_init_tx_ring(struct bge_softc * sc)1529 bge_init_tx_ring(struct bge_softc *sc)
1530 {
1531 sc->bge_txcnt = 0;
1532 sc->bge_tx_saved_considx = 0;
1533
1534 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1535 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1536 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1537
1538 /* Initialize transmit producer index for host-memory send ring. */
1539 sc->bge_tx_prodidx = 0;
1540 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1541
1542 /* 5700 b2 errata */
1543 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1544 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1545
1546 /* NIC-memory send ring not used; initialize to zero. */
1547 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1548 /* 5700 b2 errata */
1549 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1550 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1551
1552 return (0);
1553 }
1554
1555 static void
bge_setpromisc(struct bge_softc * sc)1556 bge_setpromisc(struct bge_softc *sc)
1557 {
1558 if_t ifp;
1559
1560 BGE_LOCK_ASSERT(sc);
1561
1562 ifp = sc->bge_ifp;
1563
1564 /* Enable or disable promiscuous mode as needed. */
1565 if (if_getflags(ifp) & IFF_PROMISC)
1566 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1567 else
1568 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1569 }
1570
1571 static u_int
bge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1572 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1573 {
1574 uint32_t *hashes = arg;
1575 int h;
1576
1577 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F;
1578 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1579
1580 return (1);
1581 }
1582
1583 static void
bge_setmulti(struct bge_softc * sc)1584 bge_setmulti(struct bge_softc *sc)
1585 {
1586 if_t ifp;
1587 uint32_t hashes[4] = { 0, 0, 0, 0 };
1588 int i;
1589
1590 BGE_LOCK_ASSERT(sc);
1591
1592 ifp = sc->bge_ifp;
1593
1594 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1595 for (i = 0; i < 4; i++)
1596 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1597 return;
1598 }
1599
1600 /* First, zot all the existing filters. */
1601 for (i = 0; i < 4; i++)
1602 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1603
1604 if_foreach_llmaddr(ifp, bge_hash_maddr, hashes);
1605
1606 for (i = 0; i < 4; i++)
1607 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1608 }
1609
1610 static void
bge_setvlan(struct bge_softc * sc)1611 bge_setvlan(struct bge_softc *sc)
1612 {
1613 if_t ifp;
1614
1615 BGE_LOCK_ASSERT(sc);
1616
1617 ifp = sc->bge_ifp;
1618
1619 /* Enable or disable VLAN tag stripping as needed. */
1620 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1621 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1622 else
1623 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1624 }
1625
1626 static void
bge_sig_pre_reset(struct bge_softc * sc,int type)1627 bge_sig_pre_reset(struct bge_softc *sc, int type)
1628 {
1629
1630 /*
1631 * Some chips don't like this so only do this if ASF is enabled
1632 */
1633 if (sc->bge_asf_mode)
1634 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1635
1636 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1637 switch (type) {
1638 case BGE_RESET_START:
1639 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1640 BGE_FW_DRV_STATE_START);
1641 break;
1642 case BGE_RESET_SHUTDOWN:
1643 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1644 BGE_FW_DRV_STATE_UNLOAD);
1645 break;
1646 case BGE_RESET_SUSPEND:
1647 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1648 BGE_FW_DRV_STATE_SUSPEND);
1649 break;
1650 }
1651 }
1652
1653 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1654 bge_ape_driver_state_change(sc, type);
1655 }
1656
1657 static void
bge_sig_post_reset(struct bge_softc * sc,int type)1658 bge_sig_post_reset(struct bge_softc *sc, int type)
1659 {
1660
1661 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1662 switch (type) {
1663 case BGE_RESET_START:
1664 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1665 BGE_FW_DRV_STATE_START_DONE);
1666 /* START DONE */
1667 break;
1668 case BGE_RESET_SHUTDOWN:
1669 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1670 BGE_FW_DRV_STATE_UNLOAD_DONE);
1671 break;
1672 }
1673 }
1674 if (type == BGE_RESET_SHUTDOWN)
1675 bge_ape_driver_state_change(sc, type);
1676 }
1677
1678 static void
bge_sig_legacy(struct bge_softc * sc,int type)1679 bge_sig_legacy(struct bge_softc *sc, int type)
1680 {
1681
1682 if (sc->bge_asf_mode) {
1683 switch (type) {
1684 case BGE_RESET_START:
1685 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1686 BGE_FW_DRV_STATE_START);
1687 break;
1688 case BGE_RESET_SHUTDOWN:
1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1690 BGE_FW_DRV_STATE_UNLOAD);
1691 break;
1692 }
1693 }
1694 }
1695
1696 static void
bge_stop_fw(struct bge_softc * sc)1697 bge_stop_fw(struct bge_softc *sc)
1698 {
1699 int i;
1700
1701 if (sc->bge_asf_mode) {
1702 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1703 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1704 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1705
1706 for (i = 0; i < 100; i++ ) {
1707 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1708 BGE_RX_CPU_DRV_EVENT))
1709 break;
1710 DELAY(10);
1711 }
1712 }
1713 }
1714
1715 static uint32_t
bge_dma_swap_options(struct bge_softc * sc)1716 bge_dma_swap_options(struct bge_softc *sc)
1717 {
1718 uint32_t dma_options;
1719
1720 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1721 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1722 #if BYTE_ORDER == BIG_ENDIAN
1723 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1724 #endif
1725 return (dma_options);
1726 }
1727
1728 /*
1729 * Do endian, PCI and DMA initialization.
1730 */
1731 static int
bge_chipinit(struct bge_softc * sc)1732 bge_chipinit(struct bge_softc *sc)
1733 {
1734 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1735 uint16_t val;
1736 int i;
1737
1738 /* Set endianness before we access any non-PCI registers. */
1739 misc_ctl = BGE_INIT;
1740 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1741 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1742 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1743
1744 /*
1745 * Clear the MAC statistics block in the NIC's
1746 * internal memory.
1747 */
1748 for (i = BGE_STATS_BLOCK;
1749 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1750 BGE_MEMWIN_WRITE(sc, i, 0);
1751
1752 for (i = BGE_STATUS_BLOCK;
1753 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1754 BGE_MEMWIN_WRITE(sc, i, 0);
1755
1756 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1757 /*
1758 * Fix data corruption caused by non-qword write with WB.
1759 * Fix master abort in PCI mode.
1760 * Fix PCI latency timer.
1761 */
1762 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1763 val |= (1 << 10) | (1 << 12) | (1 << 13);
1764 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1765 }
1766
1767 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1768 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1769 /*
1770 * For the 57766 and non Ax versions of 57765, bootcode
1771 * needs to setup the PCIE Fast Training Sequence (FTS)
1772 * value to prevent transmit hangs.
1773 */
1774 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1775 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1776 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1777 BGE_CPMU_PADRNG_CTL_RDIV2);
1778 }
1779 }
1780
1781 /*
1782 * Set up the PCI DMA control register.
1783 */
1784 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1785 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1786 if (sc->bge_flags & BGE_FLAG_PCIE) {
1787 if (sc->bge_mps >= 256)
1788 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1789 else
1790 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1791 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1792 if (BGE_IS_5714_FAMILY(sc)) {
1793 /* 256 bytes for read and write. */
1794 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1795 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1796 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1797 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1798 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1799 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1800 /*
1801 * In the BCM5703, the DMA read watermark should
1802 * be set to less than or equal to the maximum
1803 * memory read byte count of the PCI-X command
1804 * register.
1805 */
1806 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1807 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1808 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1809 /* 1536 bytes for read, 384 bytes for write. */
1810 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1811 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1812 } else {
1813 /* 384 bytes for read and write. */
1814 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1815 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1816 0x0F;
1817 }
1818 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1819 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1820 uint32_t tmp;
1821
1822 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1823 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1824 if (tmp == 6 || tmp == 7)
1825 dma_rw_ctl |=
1826 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1827
1828 /* Set PCI-X DMA write workaround. */
1829 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1830 }
1831 } else {
1832 /* Conventional PCI bus: 256 bytes for read and write. */
1833 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1834 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1835
1836 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1837 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1838 dma_rw_ctl |= 0x0F;
1839 }
1840 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1841 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1842 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1843 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1844 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1845 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1846 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1847 if (BGE_IS_5717_PLUS(sc)) {
1848 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1849 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1850 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1851 /*
1852 * Enable HW workaround for controllers that misinterpret
1853 * a status tag update and leave interrupts permanently
1854 * disabled.
1855 */
1856 if (!BGE_IS_57765_PLUS(sc) &&
1857 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1858 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1859 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1860 }
1861 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1862
1863 /*
1864 * Set up general mode register.
1865 */
1866 mode_ctl = bge_dma_swap_options(sc);
1867 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1868 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1869 /* Retain Host-2-BMC settings written by APE firmware. */
1870 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1871 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1872 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1873 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1874 }
1875 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1876 BGE_MODECTL_TX_NO_PHDR_CSUM;
1877
1878 /*
1879 * BCM5701 B5 have a bug causing data corruption when using
1880 * 64-bit DMA reads, which can be terminated early and then
1881 * completed later as 32-bit accesses, in combination with
1882 * certain bridges.
1883 */
1884 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1885 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1886 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1887
1888 /*
1889 * Tell the firmware the driver is running
1890 */
1891 if (sc->bge_asf_mode & ASF_STACKUP)
1892 mode_ctl |= BGE_MODECTL_STACKUP;
1893
1894 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1895
1896 /*
1897 * Disable memory write invalidate. Apparently it is not supported
1898 * properly by these devices.
1899 */
1900 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1901
1902 /* Set the timer prescaler (always 66 MHz). */
1903 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1904
1905 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1906 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1907 DELAY(40); /* XXX */
1908
1909 /* Put PHY into ready state */
1910 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1911 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1912 DELAY(40);
1913 }
1914
1915 return (0);
1916 }
1917
1918 static int
bge_blockinit(struct bge_softc * sc)1919 bge_blockinit(struct bge_softc *sc)
1920 {
1921 struct bge_rcb *rcb;
1922 bus_size_t vrcb;
1923 caddr_t lladdr;
1924 bge_hostaddr taddr;
1925 uint32_t dmactl, rdmareg, val;
1926 int i, limit;
1927
1928 /*
1929 * Initialize the memory window pointer register so that
1930 * we can access the first 32K of internal NIC RAM. This will
1931 * allow us to set up the TX send ring RCBs and the RX return
1932 * ring RCBs, plus other things which live in NIC memory.
1933 */
1934 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1935
1936 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1937
1938 if (!(BGE_IS_5705_PLUS(sc))) {
1939 /* Configure mbuf memory pool */
1940 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1941 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1942 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1943 else
1944 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1945
1946 /* Configure DMA resource pool */
1947 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1948 BGE_DMA_DESCRIPTORS);
1949 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1950 }
1951
1952 /* Configure mbuf pool watermarks */
1953 if (BGE_IS_5717_PLUS(sc)) {
1954 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1955 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
1956 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1958 } else {
1959 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1961 }
1962 } else if (!BGE_IS_5705_PLUS(sc)) {
1963 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1964 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1965 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1966 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1967 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1969 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1970 } else {
1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1974 }
1975
1976 /* Configure DMA resource watermarks */
1977 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1978 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1979
1980 /* Enable buffer manager */
1981 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1982 /*
1983 * Change the arbitration algorithm of TXMBUF read request to
1984 * round-robin instead of priority based for BCM5719. When
1985 * TXFIFO is almost empty, RDMA will hold its request until
1986 * TXFIFO is not almost empty.
1987 */
1988 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1989 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1990 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1991
1992 /* Poll for buffer manager start indication */
1993 for (i = 0; i < BGE_TIMEOUT; i++) {
1994 DELAY(10);
1995 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1996 break;
1997 }
1998
1999 if (i == BGE_TIMEOUT) {
2000 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2001 return (ENXIO);
2002 }
2003
2004 /* Enable flow-through queues */
2005 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2006 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2007
2008 /* Wait until queue initialization is complete */
2009 for (i = 0; i < BGE_TIMEOUT; i++) {
2010 DELAY(10);
2011 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2012 break;
2013 }
2014
2015 if (i == BGE_TIMEOUT) {
2016 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2017 return (ENXIO);
2018 }
2019
2020 /*
2021 * Summary of rings supported by the controller:
2022 *
2023 * Standard Receive Producer Ring
2024 * - This ring is used to feed receive buffers for "standard"
2025 * sized frames (typically 1536 bytes) to the controller.
2026 *
2027 * Jumbo Receive Producer Ring
2028 * - This ring is used to feed receive buffers for jumbo sized
2029 * frames (i.e. anything bigger than the "standard" frames)
2030 * to the controller.
2031 *
2032 * Mini Receive Producer Ring
2033 * - This ring is used to feed receive buffers for "mini"
2034 * sized frames to the controller.
2035 * - This feature required external memory for the controller
2036 * but was never used in a production system. Should always
2037 * be disabled.
2038 *
2039 * Receive Return Ring
2040 * - After the controller has placed an incoming frame into a
2041 * receive buffer that buffer is moved into a receive return
2042 * ring. The driver is then responsible to passing the
2043 * buffer up to the stack. Many versions of the controller
2044 * support multiple RR rings.
2045 *
2046 * Send Ring
2047 * - This ring is used for outgoing frames. Many versions of
2048 * the controller support multiple send rings.
2049 */
2050
2051 /* Initialize the standard receive producer ring control block. */
2052 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2053 rcb->bge_hostaddr.bge_addr_lo =
2054 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2055 rcb->bge_hostaddr.bge_addr_hi =
2056 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2057 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2058 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2059 if (BGE_IS_5717_PLUS(sc)) {
2060 /*
2061 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2062 * Bits 15-2 : Maximum RX frame size
2063 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2064 * Bit 0 : Reserved
2065 */
2066 rcb->bge_maxlen_flags =
2067 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2068 } else if (BGE_IS_5705_PLUS(sc)) {
2069 /*
2070 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2071 * Bits 15-2 : Reserved (should be 0)
2072 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2073 * Bit 0 : Reserved
2074 */
2075 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2076 } else {
2077 /*
2078 * Ring size is always XXX entries
2079 * Bits 31-16: Maximum RX frame size
2080 * Bits 15-2 : Reserved (should be 0)
2081 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2082 * Bit 0 : Reserved
2083 */
2084 rcb->bge_maxlen_flags =
2085 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2086 }
2087 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2088 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2089 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2090 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2091 else
2092 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2093 /* Write the standard receive producer ring control block. */
2094 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2095 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2096 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2097 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2098
2099 /* Reset the standard receive producer ring producer index. */
2100 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2101
2102 /*
2103 * Initialize the jumbo RX producer ring control
2104 * block. We set the 'ring disabled' bit in the
2105 * flags field until we're actually ready to start
2106 * using this ring (i.e. once we set the MTU
2107 * high enough to require it).
2108 */
2109 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2110 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2111 /* Get the jumbo receive producer ring RCB parameters. */
2112 rcb->bge_hostaddr.bge_addr_lo =
2113 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2114 rcb->bge_hostaddr.bge_addr_hi =
2115 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2116 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2117 sc->bge_cdata.bge_rx_jumbo_ring_map,
2118 BUS_DMASYNC_PREREAD);
2119 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2120 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2121 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2122 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2123 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2124 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2125 else
2126 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2127 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2128 rcb->bge_hostaddr.bge_addr_hi);
2129 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2130 rcb->bge_hostaddr.bge_addr_lo);
2131 /* Program the jumbo receive producer ring RCB parameters. */
2132 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2133 rcb->bge_maxlen_flags);
2134 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2135 /* Reset the jumbo receive producer ring producer index. */
2136 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2137 }
2138
2139 /* Disable the mini receive producer ring RCB. */
2140 if (BGE_IS_5700_FAMILY(sc)) {
2141 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2142 rcb->bge_maxlen_flags =
2143 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2144 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2145 rcb->bge_maxlen_flags);
2146 /* Reset the mini receive producer ring producer index. */
2147 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2148 }
2149
2150 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2151 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2152 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2153 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2154 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2155 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2156 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2157 }
2158 /*
2159 * The BD ring replenish thresholds control how often the
2160 * hardware fetches new BD's from the producer rings in host
2161 * memory. Setting the value too low on a busy system can
2162 * starve the hardware and reduce the throughput.
2163 *
2164 * Set the BD ring replentish thresholds. The recommended
2165 * values are 1/8th the number of descriptors allocated to
2166 * each ring.
2167 * XXX The 5754 requires a lower threshold, so it might be a
2168 * requirement of all 575x family chips. The Linux driver sets
2169 * the lower threshold for all 5705 family chips as well, but there
2170 * are reports that it might not need to be so strict.
2171 *
2172 * XXX Linux does some extra fiddling here for the 5906 parts as
2173 * well.
2174 */
2175 if (BGE_IS_5705_PLUS(sc))
2176 val = 8;
2177 else
2178 val = BGE_STD_RX_RING_CNT / 8;
2179 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2180 if (BGE_IS_JUMBO_CAPABLE(sc))
2181 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2182 BGE_JUMBO_RX_RING_CNT/8);
2183 if (BGE_IS_5717_PLUS(sc)) {
2184 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2185 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2186 }
2187
2188 /*
2189 * Disable all send rings by setting the 'ring disabled' bit
2190 * in the flags field of all the TX send ring control blocks,
2191 * located in NIC memory.
2192 */
2193 if (!BGE_IS_5705_PLUS(sc))
2194 /* 5700 to 5704 had 16 send rings. */
2195 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2196 else if (BGE_IS_57765_PLUS(sc) ||
2197 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2198 limit = 2;
2199 else if (BGE_IS_5717_PLUS(sc))
2200 limit = 4;
2201 else
2202 limit = 1;
2203 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2204 for (i = 0; i < limit; i++) {
2205 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2206 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2207 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2208 vrcb += sizeof(struct bge_rcb);
2209 }
2210
2211 /* Configure send ring RCB 0 (we use only the first ring) */
2212 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2213 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2214 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2215 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2216 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2217 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2218 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2219 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2220 else
2221 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2222 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2223 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2224 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2225
2226 /*
2227 * Disable all receive return rings by setting the
2228 * 'ring diabled' bit in the flags field of all the receive
2229 * return ring control blocks, located in NIC memory.
2230 */
2231 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2232 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2233 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2234 /* Should be 17, use 16 until we get an SRAM map. */
2235 limit = 16;
2236 } else if (!BGE_IS_5705_PLUS(sc))
2237 limit = BGE_RX_RINGS_MAX;
2238 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2239 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2240 BGE_IS_57765_PLUS(sc))
2241 limit = 4;
2242 else
2243 limit = 1;
2244 /* Disable all receive return rings. */
2245 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2246 for (i = 0; i < limit; i++) {
2247 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2248 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2249 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2250 BGE_RCB_FLAG_RING_DISABLED);
2251 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2252 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2253 (i * (sizeof(uint64_t))), 0);
2254 vrcb += sizeof(struct bge_rcb);
2255 }
2256
2257 /*
2258 * Set up receive return ring 0. Note that the NIC address
2259 * for RX return rings is 0x0. The return rings live entirely
2260 * within the host, so the nicaddr field in the RCB isn't used.
2261 */
2262 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2263 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2264 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2265 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2266 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2267 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2268 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2269
2270 lladdr = if_getlladdr(sc->bge_ifp);
2271 /* Set random backoff seed for TX */
2272 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2273 (lladdr[0] + lladdr[1] +
2274 lladdr[2] + lladdr[3] +
2275 lladdr[4] + lladdr[5]) &
2276 BGE_TX_BACKOFF_SEED_MASK);
2277
2278 /* Set inter-packet gap */
2279 val = 0x2620;
2280 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2281 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2282 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2283 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2284 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2285
2286 /*
2287 * Specify which ring to use for packets that don't match
2288 * any RX rules.
2289 */
2290 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2291
2292 /*
2293 * Configure number of RX lists. One interrupt distribution
2294 * list, sixteen active lists, one bad frames class.
2295 */
2296 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2297
2298 /* Initialize RX list placement stats mask. */
2299 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2300 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2301
2302 /* Disable host coalescing until we get it set up */
2303 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2304
2305 /* Poll to make sure it's shut down. */
2306 for (i = 0; i < BGE_TIMEOUT; i++) {
2307 DELAY(10);
2308 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2309 break;
2310 }
2311
2312 if (i == BGE_TIMEOUT) {
2313 device_printf(sc->bge_dev,
2314 "host coalescing engine failed to idle\n");
2315 return (ENXIO);
2316 }
2317
2318 /* Set up host coalescing defaults */
2319 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2320 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2321 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2322 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2323 if (!(BGE_IS_5705_PLUS(sc))) {
2324 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2325 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2326 }
2327 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2328 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2329
2330 /* Set up address of statistics block */
2331 if (!(BGE_IS_5705_PLUS(sc))) {
2332 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2333 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2334 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2335 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2336 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2337 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2338 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2339 }
2340
2341 /* Set up address of status block */
2342 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2343 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2344 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2345 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2346
2347 /* Set up status block size. */
2348 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2349 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2350 val = BGE_STATBLKSZ_FULL;
2351 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2352 } else {
2353 val = BGE_STATBLKSZ_32BYTE;
2354 bzero(sc->bge_ldata.bge_status_block, 32);
2355 }
2356 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2357 sc->bge_cdata.bge_status_map,
2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2359
2360 /* Turn on host coalescing state machine */
2361 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2362
2363 /* Turn on RX BD completion state machine and enable attentions */
2364 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2365 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2366
2367 /* Turn on RX list placement state machine */
2368 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2369
2370 /* Turn on RX list selector state machine. */
2371 if (!(BGE_IS_5705_PLUS(sc)))
2372 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2373
2374 /* Turn on DMA, clear stats. */
2375 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2376 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2377 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2378 BGE_MACMODE_FRMHDR_DMA_ENB;
2379
2380 if (sc->bge_flags & BGE_FLAG_TBI)
2381 val |= BGE_PORTMODE_TBI;
2382 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2383 val |= BGE_PORTMODE_GMII;
2384 else
2385 val |= BGE_PORTMODE_MII;
2386
2387 /* Allow APE to send/receive frames. */
2388 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2389 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2390
2391 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2392 DELAY(40);
2393
2394 /* Set misc. local control, enable interrupts on attentions */
2395 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2396
2397 #ifdef notdef
2398 /* Assert GPIO pins for PHY reset */
2399 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2400 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2401 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2402 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2403 #endif
2404
2405 /* Turn on DMA completion state machine */
2406 if (!(BGE_IS_5705_PLUS(sc)))
2407 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2408
2409 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2410
2411 /* Enable host coalescing bug fix. */
2412 if (BGE_IS_5755_PLUS(sc))
2413 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2414
2415 /* Request larger DMA burst size to get better performance. */
2416 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2417 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2418
2419 /* Turn on write DMA state machine */
2420 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2421 DELAY(40);
2422
2423 /* Turn on read DMA state machine */
2424 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2425
2426 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2427 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2428
2429 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2430 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2431 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2432 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2433 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2434 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2435 if (sc->bge_flags & BGE_FLAG_PCIE)
2436 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2437 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2438 val |= BGE_RDMAMODE_TSO4_ENABLE;
2439 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2440 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2441 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2442 val |= BGE_RDMAMODE_TSO6_ENABLE;
2443 }
2444
2445 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2446 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2447 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2448 BGE_RDMAMODE_H2BNC_VLAN_DET;
2449 /*
2450 * Allow multiple outstanding read requests from
2451 * non-LSO read DMA engine.
2452 */
2453 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2454 }
2455
2456 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2457 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2458 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2459 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2460 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2461 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2462 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2463 else
2464 rdmareg = BGE_RDMA_RSRVCTRL;
2465 dmactl = CSR_READ_4(sc, rdmareg);
2466 /*
2467 * Adjust tx margin to prevent TX data corruption and
2468 * fix internal FIFO overflow.
2469 */
2470 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2471 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2472 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2473 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2474 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2475 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2476 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2477 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2478 }
2479 /*
2480 * Enable fix for read DMA FIFO overruns.
2481 * The fix is to limit the number of RX BDs
2482 * the hardware would fetch at a fime.
2483 */
2484 CSR_WRITE_4(sc, rdmareg, dmactl |
2485 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2486 }
2487
2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2489 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2490 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2491 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2492 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2493 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2494 /*
2495 * Allow 4KB burst length reads for non-LSO frames.
2496 * Enable 512B burst length reads for buffer descriptors.
2497 */
2498 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2499 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2500 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2501 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2502 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2503 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2504 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2505 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2506 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2507 }
2508
2509 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2510 DELAY(40);
2511
2512 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2513 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2514 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2515 if ((val & 0xFFFF) > BGE_FRAMELEN)
2516 break;
2517 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2518 break;
2519 }
2520 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2521 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2522 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2523 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2524 else
2525 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2526 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2527 }
2528 }
2529
2530 /* Turn on RX data completion state machine */
2531 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2532
2533 /* Turn on RX BD initiator state machine */
2534 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2535
2536 /* Turn on RX data and RX BD initiator state machine */
2537 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2538
2539 /* Turn on Mbuf cluster free state machine */
2540 if (!(BGE_IS_5705_PLUS(sc)))
2541 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2542
2543 /* Turn on send BD completion state machine */
2544 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2545
2546 /* Turn on send data completion state machine */
2547 val = BGE_SDCMODE_ENABLE;
2548 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2549 val |= BGE_SDCMODE_CDELAY;
2550 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2551
2552 /* Turn on send data initiator state machine */
2553 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2554 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2555 BGE_SDIMODE_HW_LSO_PRE_DMA);
2556 else
2557 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2558
2559 /* Turn on send BD initiator state machine */
2560 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2561
2562 /* Turn on send BD selector state machine */
2563 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2564
2565 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2566 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2567 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2568
2569 /* ack/clear link change events */
2570 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2571 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2572 BGE_MACSTAT_LINK_CHANGED);
2573 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2574
2575 /*
2576 * Enable attention when the link has changed state for
2577 * devices that use auto polling.
2578 */
2579 if (sc->bge_flags & BGE_FLAG_TBI) {
2580 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2581 } else {
2582 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2583 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2584 DELAY(80);
2585 }
2586 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2587 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2588 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2589 BGE_EVTENB_MI_INTERRUPT);
2590 }
2591
2592 /*
2593 * Clear any pending link state attention.
2594 * Otherwise some link state change events may be lost until attention
2595 * is cleared by bge_intr() -> bge_link_upd() sequence.
2596 * It's not necessary on newer BCM chips - perhaps enabling link
2597 * state change attentions implies clearing pending attention.
2598 */
2599 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2600 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2601 BGE_MACSTAT_LINK_CHANGED);
2602
2603 /* Enable link state change attentions. */
2604 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2605
2606 return (0);
2607 }
2608
2609 static const struct bge_revision *
bge_lookup_rev(uint32_t chipid)2610 bge_lookup_rev(uint32_t chipid)
2611 {
2612 const struct bge_revision *br;
2613
2614 for (br = bge_revisions; br->br_name != NULL; br++) {
2615 if (br->br_chipid == chipid)
2616 return (br);
2617 }
2618
2619 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2620 if (br->br_chipid == BGE_ASICREV(chipid))
2621 return (br);
2622 }
2623
2624 return (NULL);
2625 }
2626
2627 static const struct bge_vendor *
bge_lookup_vendor(uint16_t vid)2628 bge_lookup_vendor(uint16_t vid)
2629 {
2630 const struct bge_vendor *v;
2631
2632 for (v = bge_vendors; v->v_name != NULL; v++)
2633 if (v->v_id == vid)
2634 return (v);
2635
2636 return (NULL);
2637 }
2638
2639 static uint32_t
bge_chipid(device_t dev)2640 bge_chipid(device_t dev)
2641 {
2642 uint32_t id;
2643
2644 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2645 BGE_PCIMISCCTL_ASICREV_SHIFT;
2646 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2647 /*
2648 * Find the ASCI revision. Different chips use different
2649 * registers.
2650 */
2651 switch (pci_get_device(dev)) {
2652 case BCOM_DEVICEID_BCM5717C:
2653 /* 5717 C0 seems to belong to 5720 line. */
2654 id = BGE_CHIPID_BCM5720_A0;
2655 break;
2656 case BCOM_DEVICEID_BCM5717:
2657 case BCOM_DEVICEID_BCM5718:
2658 case BCOM_DEVICEID_BCM5719:
2659 case BCOM_DEVICEID_BCM5720:
2660 case BCOM_DEVICEID_BCM5725:
2661 case BCOM_DEVICEID_BCM5727:
2662 case BCOM_DEVICEID_BCM5762:
2663 case BCOM_DEVICEID_BCM57764:
2664 case BCOM_DEVICEID_BCM57767:
2665 case BCOM_DEVICEID_BCM57787:
2666 id = pci_read_config(dev,
2667 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2668 break;
2669 case BCOM_DEVICEID_BCM57761:
2670 case BCOM_DEVICEID_BCM57762:
2671 case BCOM_DEVICEID_BCM57765:
2672 case BCOM_DEVICEID_BCM57766:
2673 case BCOM_DEVICEID_BCM57781:
2674 case BCOM_DEVICEID_BCM57782:
2675 case BCOM_DEVICEID_BCM57785:
2676 case BCOM_DEVICEID_BCM57786:
2677 case BCOM_DEVICEID_BCM57791:
2678 case BCOM_DEVICEID_BCM57795:
2679 id = pci_read_config(dev,
2680 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2681 break;
2682 default:
2683 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2684 }
2685 }
2686 return (id);
2687 }
2688
2689 /*
2690 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2691 * against our list and return its name if we find a match.
2692 *
2693 * Note that since the Broadcom controller contains VPD support, we
2694 * try to get the device name string from the controller itself instead
2695 * of the compiled-in string. It guarantees we'll always announce the
2696 * right product name. We fall back to the compiled-in string when
2697 * VPD is unavailable or corrupt.
2698 */
2699 static int
bge_probe(device_t dev)2700 bge_probe(device_t dev)
2701 {
2702 char model[64];
2703 const struct bge_revision *br;
2704 const char *pname;
2705 struct bge_softc *sc;
2706 const struct bge_type *t = bge_devs;
2707 const struct bge_vendor *v;
2708 uint32_t id;
2709 uint16_t did, vid;
2710
2711 sc = device_get_softc(dev);
2712 sc->bge_dev = dev;
2713 vid = pci_get_vendor(dev);
2714 did = pci_get_device(dev);
2715 while(t->bge_vid != 0) {
2716 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2717 id = bge_chipid(dev);
2718 br = bge_lookup_rev(id);
2719 if (bge_has_eaddr(sc) &&
2720 pci_get_vpd_ident(dev, &pname) == 0)
2721 snprintf(model, sizeof(model), "%s", pname);
2722 else {
2723 v = bge_lookup_vendor(vid);
2724 snprintf(model, sizeof(model), "%s %s",
2725 v != NULL ? v->v_name : "Unknown",
2726 br != NULL ? br->br_name :
2727 "NetXtreme/NetLink Ethernet Controller");
2728 }
2729 device_set_descf(dev, "%s, %sASIC rev. %#08x",
2730 model, br != NULL ? "" : "unknown ", id);
2731 return (BUS_PROBE_DEFAULT);
2732 }
2733 t++;
2734 }
2735
2736 return (ENXIO);
2737 }
2738
2739 static void
bge_dma_free(struct bge_softc * sc)2740 bge_dma_free(struct bge_softc *sc)
2741 {
2742 int i;
2743
2744 /* Destroy DMA maps for RX buffers. */
2745 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2746 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2747 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2748 sc->bge_cdata.bge_rx_std_dmamap[i]);
2749 }
2750 if (sc->bge_cdata.bge_rx_std_sparemap)
2751 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2752 sc->bge_cdata.bge_rx_std_sparemap);
2753
2754 /* Destroy DMA maps for jumbo RX buffers. */
2755 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2756 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2757 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2758 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2759 }
2760 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2761 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2762 sc->bge_cdata.bge_rx_jumbo_sparemap);
2763
2764 /* Destroy DMA maps for TX buffers. */
2765 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2766 if (sc->bge_cdata.bge_tx_dmamap[i])
2767 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2768 sc->bge_cdata.bge_tx_dmamap[i]);
2769 }
2770
2771 if (sc->bge_cdata.bge_rx_mtag)
2772 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2773 if (sc->bge_cdata.bge_mtag_jumbo)
2774 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2775 if (sc->bge_cdata.bge_tx_mtag)
2776 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2777
2778 /* Destroy standard RX ring. */
2779 if (sc->bge_ldata.bge_rx_std_ring_paddr)
2780 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2781 sc->bge_cdata.bge_rx_std_ring_map);
2782 if (sc->bge_ldata.bge_rx_std_ring)
2783 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2784 sc->bge_ldata.bge_rx_std_ring,
2785 sc->bge_cdata.bge_rx_std_ring_map);
2786
2787 if (sc->bge_cdata.bge_rx_std_ring_tag)
2788 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2789
2790 /* Destroy jumbo RX ring. */
2791 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2792 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2793 sc->bge_cdata.bge_rx_jumbo_ring_map);
2794
2795 if (sc->bge_ldata.bge_rx_jumbo_ring)
2796 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2797 sc->bge_ldata.bge_rx_jumbo_ring,
2798 sc->bge_cdata.bge_rx_jumbo_ring_map);
2799
2800 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2801 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2802
2803 /* Destroy RX return ring. */
2804 if (sc->bge_ldata.bge_rx_return_ring_paddr)
2805 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2806 sc->bge_cdata.bge_rx_return_ring_map);
2807
2808 if (sc->bge_ldata.bge_rx_return_ring)
2809 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2810 sc->bge_ldata.bge_rx_return_ring,
2811 sc->bge_cdata.bge_rx_return_ring_map);
2812
2813 if (sc->bge_cdata.bge_rx_return_ring_tag)
2814 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2815
2816 /* Destroy TX ring. */
2817 if (sc->bge_ldata.bge_tx_ring_paddr)
2818 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2819 sc->bge_cdata.bge_tx_ring_map);
2820
2821 if (sc->bge_ldata.bge_tx_ring)
2822 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2823 sc->bge_ldata.bge_tx_ring,
2824 sc->bge_cdata.bge_tx_ring_map);
2825
2826 if (sc->bge_cdata.bge_tx_ring_tag)
2827 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2828
2829 /* Destroy status block. */
2830 if (sc->bge_ldata.bge_status_block_paddr)
2831 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2832 sc->bge_cdata.bge_status_map);
2833
2834 if (sc->bge_ldata.bge_status_block)
2835 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2836 sc->bge_ldata.bge_status_block,
2837 sc->bge_cdata.bge_status_map);
2838
2839 if (sc->bge_cdata.bge_status_tag)
2840 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2841
2842 /* Destroy statistics block. */
2843 if (sc->bge_ldata.bge_stats_paddr)
2844 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2845 sc->bge_cdata.bge_stats_map);
2846
2847 if (sc->bge_ldata.bge_stats)
2848 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2849 sc->bge_ldata.bge_stats,
2850 sc->bge_cdata.bge_stats_map);
2851
2852 if (sc->bge_cdata.bge_stats_tag)
2853 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2854
2855 if (sc->bge_cdata.bge_buffer_tag)
2856 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2857
2858 /* Destroy the parent tag. */
2859 if (sc->bge_cdata.bge_parent_tag)
2860 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2861 }
2862
2863 static int
bge_dma_ring_alloc(struct bge_softc * sc,bus_size_t alignment,bus_size_t maxsize,bus_dma_tag_t * tag,uint8_t ** ring,bus_dmamap_t * map,bus_addr_t * paddr,const char * msg)2864 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2865 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2866 bus_addr_t *paddr, const char *msg)
2867 {
2868 struct bge_dmamap_arg ctx;
2869 bus_addr_t lowaddr;
2870 bus_size_t ring_end;
2871 int error;
2872
2873 lowaddr = BUS_SPACE_MAXADDR;
2874 again:
2875 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2876 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2877 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2878 if (error != 0) {
2879 device_printf(sc->bge_dev,
2880 "could not create %s dma tag\n", msg);
2881 return (ENOMEM);
2882 }
2883 /* Allocate DMA'able memory for ring. */
2884 error = bus_dmamem_alloc(*tag, (void **)ring,
2885 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2886 if (error != 0) {
2887 device_printf(sc->bge_dev,
2888 "could not allocate DMA'able memory for %s\n", msg);
2889 return (ENOMEM);
2890 }
2891 /* Load the address of the ring. */
2892 ctx.bge_busaddr = 0;
2893 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2894 &ctx, BUS_DMA_NOWAIT);
2895 if (error != 0) {
2896 device_printf(sc->bge_dev,
2897 "could not load DMA'able memory for %s\n", msg);
2898 return (ENOMEM);
2899 }
2900 *paddr = ctx.bge_busaddr;
2901 ring_end = *paddr + maxsize;
2902 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2903 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2904 /*
2905 * 4GB boundary crossed. Limit maximum allowable DMA
2906 * address space to 32bit and try again.
2907 */
2908 bus_dmamap_unload(*tag, *map);
2909 bus_dmamem_free(*tag, *ring, *map);
2910 bus_dma_tag_destroy(*tag);
2911 if (bootverbose)
2912 device_printf(sc->bge_dev, "4GB boundary crossed, "
2913 "limit DMA address space to 32bit for %s\n", msg);
2914 *ring = NULL;
2915 *tag = NULL;
2916 *map = NULL;
2917 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2918 goto again;
2919 }
2920 return (0);
2921 }
2922
2923 static int
bge_dma_alloc(struct bge_softc * sc)2924 bge_dma_alloc(struct bge_softc *sc)
2925 {
2926 bus_addr_t lowaddr;
2927 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2928 int i, error;
2929
2930 lowaddr = BUS_SPACE_MAXADDR;
2931 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2932 lowaddr = BGE_DMA_MAXADDR;
2933 /*
2934 * Allocate the parent bus DMA tag appropriate for PCI.
2935 */
2936 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2937 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2938 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2939 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2940 if (error != 0) {
2941 device_printf(sc->bge_dev,
2942 "could not allocate parent dma tag\n");
2943 return (ENOMEM);
2944 }
2945
2946 /* Create tag for standard RX ring. */
2947 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2948 &sc->bge_cdata.bge_rx_std_ring_tag,
2949 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2950 &sc->bge_cdata.bge_rx_std_ring_map,
2951 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2952 if (error)
2953 return (error);
2954
2955 /* Create tag for RX return ring. */
2956 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2957 &sc->bge_cdata.bge_rx_return_ring_tag,
2958 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2959 &sc->bge_cdata.bge_rx_return_ring_map,
2960 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2961 if (error)
2962 return (error);
2963
2964 /* Create tag for TX ring. */
2965 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2966 &sc->bge_cdata.bge_tx_ring_tag,
2967 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2968 &sc->bge_cdata.bge_tx_ring_map,
2969 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2970 if (error)
2971 return (error);
2972
2973 /*
2974 * Create tag for status block.
2975 * Because we only use single Tx/Rx/Rx return ring, use
2976 * minimum status block size except BCM5700 AX/BX which
2977 * seems to want to see full status block size regardless
2978 * of configured number of ring.
2979 */
2980 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2981 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2982 sbsz = BGE_STATUS_BLK_SZ;
2983 else
2984 sbsz = 32;
2985 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2986 &sc->bge_cdata.bge_status_tag,
2987 (uint8_t **)&sc->bge_ldata.bge_status_block,
2988 &sc->bge_cdata.bge_status_map,
2989 &sc->bge_ldata.bge_status_block_paddr, "status block");
2990 if (error)
2991 return (error);
2992
2993 /* Create tag for statistics block. */
2994 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2995 &sc->bge_cdata.bge_stats_tag,
2996 (uint8_t **)&sc->bge_ldata.bge_stats,
2997 &sc->bge_cdata.bge_stats_map,
2998 &sc->bge_ldata.bge_stats_paddr, "statistics block");
2999 if (error)
3000 return (error);
3001
3002 /* Create tag for jumbo RX ring. */
3003 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3004 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3005 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3006 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3007 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3008 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3009 if (error)
3010 return (error);
3011 }
3012
3013 /* Create parent tag for buffers. */
3014 boundary = 0;
3015 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3016 boundary = BGE_DMA_BNDRY;
3017 /*
3018 * XXX
3019 * watchdog timeout issue was observed on BCM5704 which
3020 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3021 * Both limiting DMA address space to 32bits and flushing
3022 * mailbox write seem to address the issue.
3023 */
3024 if (sc->bge_pcixcap != 0)
3025 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3026 }
3027 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3028 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
3029 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3030 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3031 if (error != 0) {
3032 device_printf(sc->bge_dev,
3033 "could not allocate buffer dma tag\n");
3034 return (ENOMEM);
3035 }
3036 /* Create tag for Tx mbufs. */
3037 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3038 txsegsz = BGE_TSOSEG_SZ;
3039 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3040 } else {
3041 txsegsz = MCLBYTES;
3042 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3043 }
3044 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3045 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3046 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3047 &sc->bge_cdata.bge_tx_mtag);
3048
3049 if (error) {
3050 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3051 return (ENOMEM);
3052 }
3053
3054 /* Create tag for Rx mbufs. */
3055 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3056 rxmaxsegsz = MJUM9BYTES;
3057 else
3058 rxmaxsegsz = MCLBYTES;
3059 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3060 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3061 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3062
3063 if (error) {
3064 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3065 return (ENOMEM);
3066 }
3067
3068 /* Create DMA maps for RX buffers. */
3069 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3070 &sc->bge_cdata.bge_rx_std_sparemap);
3071 if (error) {
3072 device_printf(sc->bge_dev,
3073 "can't create spare DMA map for RX\n");
3074 return (ENOMEM);
3075 }
3076 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3077 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3078 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3079 if (error) {
3080 device_printf(sc->bge_dev,
3081 "can't create DMA map for RX\n");
3082 return (ENOMEM);
3083 }
3084 }
3085
3086 /* Create DMA maps for TX buffers. */
3087 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3088 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3089 &sc->bge_cdata.bge_tx_dmamap[i]);
3090 if (error) {
3091 device_printf(sc->bge_dev,
3092 "can't create DMA map for TX\n");
3093 return (ENOMEM);
3094 }
3095 }
3096
3097 /* Create tags for jumbo RX buffers. */
3098 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3099 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3100 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3101 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3102 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3103 if (error) {
3104 device_printf(sc->bge_dev,
3105 "could not allocate jumbo dma tag\n");
3106 return (ENOMEM);
3107 }
3108 /* Create DMA maps for jumbo RX buffers. */
3109 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3110 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3111 if (error) {
3112 device_printf(sc->bge_dev,
3113 "can't create spare DMA map for jumbo RX\n");
3114 return (ENOMEM);
3115 }
3116 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3117 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3118 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3119 if (error) {
3120 device_printf(sc->bge_dev,
3121 "can't create DMA map for jumbo RX\n");
3122 return (ENOMEM);
3123 }
3124 }
3125 }
3126
3127 return (0);
3128 }
3129
3130 /*
3131 * Return true if this device has more than one port.
3132 */
3133 static int
bge_has_multiple_ports(struct bge_softc * sc)3134 bge_has_multiple_ports(struct bge_softc *sc)
3135 {
3136 device_t dev = sc->bge_dev;
3137 u_int b, d, f, fscan, s;
3138
3139 d = pci_get_domain(dev);
3140 b = pci_get_bus(dev);
3141 s = pci_get_slot(dev);
3142 f = pci_get_function(dev);
3143 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3144 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3145 return (1);
3146 return (0);
3147 }
3148
3149 /*
3150 * Return true if MSI can be used with this device.
3151 */
3152 static int
bge_can_use_msi(struct bge_softc * sc)3153 bge_can_use_msi(struct bge_softc *sc)
3154 {
3155 int can_use_msi = 0;
3156
3157 if (sc->bge_msi == 0)
3158 return (0);
3159
3160 /* Disable MSI for polling(4). */
3161 #ifdef DEVICE_POLLING
3162 return (0);
3163 #endif
3164 switch (sc->bge_asicrev) {
3165 case BGE_ASICREV_BCM5714_A0:
3166 case BGE_ASICREV_BCM5714:
3167 /*
3168 * Apparently, MSI doesn't work when these chips are
3169 * configured in single-port mode.
3170 */
3171 if (bge_has_multiple_ports(sc))
3172 can_use_msi = 1;
3173 break;
3174 case BGE_ASICREV_BCM5750:
3175 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3176 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3177 can_use_msi = 1;
3178 break;
3179 case BGE_ASICREV_BCM5784:
3180 /*
3181 * Prevent infinite "watchdog timeout" errors
3182 * in some MacBook Pro and make it work out-of-the-box.
3183 */
3184 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3185 break;
3186 /* FALLTHROUGH */
3187 default:
3188 if (BGE_IS_575X_PLUS(sc))
3189 can_use_msi = 1;
3190 }
3191 return (can_use_msi);
3192 }
3193
3194 static int
bge_mbox_reorder(struct bge_softc * sc)3195 bge_mbox_reorder(struct bge_softc *sc)
3196 {
3197 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3198 static const struct mbox_reorder {
3199 const uint16_t vendor;
3200 const uint16_t device;
3201 const char *desc;
3202 } mbox_reorder_lists[] = {
3203 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3204 };
3205 devclass_t pci, pcib;
3206 device_t bus, dev;
3207 int i;
3208
3209 pci = devclass_find("pci");
3210 pcib = devclass_find("pcib");
3211 dev = sc->bge_dev;
3212 bus = device_get_parent(dev);
3213 for (;;) {
3214 dev = device_get_parent(bus);
3215 bus = device_get_parent(dev);
3216 if (device_get_devclass(dev) != pcib)
3217 break;
3218 if (device_get_devclass(bus) != pci)
3219 break;
3220 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3221 if (pci_get_vendor(dev) ==
3222 mbox_reorder_lists[i].vendor &&
3223 pci_get_device(dev) ==
3224 mbox_reorder_lists[i].device) {
3225 device_printf(sc->bge_dev,
3226 "enabling MBOX workaround for %s\n",
3227 mbox_reorder_lists[i].desc);
3228 return (1);
3229 }
3230 }
3231 }
3232 return (0);
3233 }
3234
3235 static void
bge_devinfo(struct bge_softc * sc)3236 bge_devinfo(struct bge_softc *sc)
3237 {
3238 uint32_t cfg, clk;
3239
3240 device_printf(sc->bge_dev,
3241 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3242 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3243 if (sc->bge_flags & BGE_FLAG_PCIE)
3244 printf("PCI-E\n");
3245 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3246 printf("PCI-X ");
3247 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3248 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3249 clk = 133;
3250 else {
3251 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3252 switch (clk) {
3253 case 0:
3254 clk = 33;
3255 break;
3256 case 2:
3257 clk = 50;
3258 break;
3259 case 4:
3260 clk = 66;
3261 break;
3262 case 6:
3263 clk = 100;
3264 break;
3265 case 7:
3266 clk = 133;
3267 break;
3268 }
3269 }
3270 printf("%u MHz\n", clk);
3271 } else {
3272 if (sc->bge_pcixcap != 0)
3273 printf("PCI on PCI-X ");
3274 else
3275 printf("PCI ");
3276 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3277 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3278 clk = 66;
3279 else
3280 clk = 33;
3281 if (cfg & BGE_PCISTATE_32BIT_BUS)
3282 printf("%u MHz; 32bit\n", clk);
3283 else
3284 printf("%u MHz; 64bit\n", clk);
3285 }
3286 }
3287
3288 static int
bge_attach(device_t dev)3289 bge_attach(device_t dev)
3290 {
3291 if_t ifp;
3292 struct bge_softc *sc;
3293 uint32_t hwcfg = 0, misccfg, pcistate;
3294 u_char eaddr[ETHER_ADDR_LEN];
3295 int capmask, error, reg, rid, trys;
3296
3297 sc = device_get_softc(dev);
3298 sc->bge_dev = dev;
3299
3300 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3301 NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3302 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3303
3304 pci_enable_busmaster(dev);
3305
3306 /*
3307 * Allocate control/status registers.
3308 */
3309 rid = PCIR_BAR(0);
3310 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3311 RF_ACTIVE);
3312
3313 if (sc->bge_res == NULL) {
3314 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3315 error = ENXIO;
3316 goto fail;
3317 }
3318
3319 /* Save various chip information. */
3320 sc->bge_func_addr = pci_get_function(dev);
3321 sc->bge_chipid = bge_chipid(dev);
3322 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3323 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3324
3325 /* Set default PHY address. */
3326 sc->bge_phy_addr = 1;
3327 /*
3328 * PHY address mapping for various devices.
3329 *
3330 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3331 * ---------+-------+-------+-------+-------+
3332 * BCM57XX | 1 | X | X | X |
3333 * BCM5704 | 1 | X | 1 | X |
3334 * BCM5717 | 1 | 8 | 2 | 9 |
3335 * BCM5719 | 1 | 8 | 2 | 9 |
3336 * BCM5720 | 1 | 8 | 2 | 9 |
3337 *
3338 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3339 * ---------+-------+-------+-------+-------+
3340 * BCM57XX | X | X | X | X |
3341 * BCM5704 | X | X | X | X |
3342 * BCM5717 | X | X | X | X |
3343 * BCM5719 | 3 | 10 | 4 | 11 |
3344 * BCM5720 | X | X | X | X |
3345 *
3346 * Other addresses may respond but they are not
3347 * IEEE compliant PHYs and should be ignored.
3348 */
3349 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3350 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3351 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3352 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3353 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3354 BGE_SGDIGSTS_IS_SERDES)
3355 sc->bge_phy_addr = sc->bge_func_addr + 8;
3356 else
3357 sc->bge_phy_addr = sc->bge_func_addr + 1;
3358 } else {
3359 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3360 BGE_CPMU_PHY_STRAP_IS_SERDES)
3361 sc->bge_phy_addr = sc->bge_func_addr + 8;
3362 else
3363 sc->bge_phy_addr = sc->bge_func_addr + 1;
3364 }
3365 }
3366
3367 if (bge_has_eaddr(sc))
3368 sc->bge_flags |= BGE_FLAG_EADDR;
3369
3370 /* Save chipset family. */
3371 switch (sc->bge_asicrev) {
3372 case BGE_ASICREV_BCM5762:
3373 case BGE_ASICREV_BCM57765:
3374 case BGE_ASICREV_BCM57766:
3375 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3376 /* FALLTHROUGH */
3377 case BGE_ASICREV_BCM5717:
3378 case BGE_ASICREV_BCM5719:
3379 case BGE_ASICREV_BCM5720:
3380 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3381 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3382 BGE_FLAG_JUMBO_FRAME;
3383 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3384 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3385 /*
3386 * Enable work around for DMA engine miscalculation
3387 * of TXMBUF available space.
3388 */
3389 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3390 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3391 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3392 /* Jumbo frame on BCM5719 A0 does not work. */
3393 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3394 }
3395 }
3396 break;
3397 case BGE_ASICREV_BCM5755:
3398 case BGE_ASICREV_BCM5761:
3399 case BGE_ASICREV_BCM5784:
3400 case BGE_ASICREV_BCM5785:
3401 case BGE_ASICREV_BCM5787:
3402 case BGE_ASICREV_BCM57780:
3403 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3404 BGE_FLAG_5705_PLUS;
3405 break;
3406 case BGE_ASICREV_BCM5700:
3407 case BGE_ASICREV_BCM5701:
3408 case BGE_ASICREV_BCM5703:
3409 case BGE_ASICREV_BCM5704:
3410 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3411 break;
3412 case BGE_ASICREV_BCM5714_A0:
3413 case BGE_ASICREV_BCM5780:
3414 case BGE_ASICREV_BCM5714:
3415 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3416 /* FALLTHROUGH */
3417 case BGE_ASICREV_BCM5750:
3418 case BGE_ASICREV_BCM5752:
3419 case BGE_ASICREV_BCM5906:
3420 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3421 /* FALLTHROUGH */
3422 case BGE_ASICREV_BCM5705:
3423 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3424 break;
3425 }
3426
3427 /* Identify chips with APE processor. */
3428 switch (sc->bge_asicrev) {
3429 case BGE_ASICREV_BCM5717:
3430 case BGE_ASICREV_BCM5719:
3431 case BGE_ASICREV_BCM5720:
3432 case BGE_ASICREV_BCM5761:
3433 case BGE_ASICREV_BCM5762:
3434 sc->bge_flags |= BGE_FLAG_APE;
3435 break;
3436 }
3437
3438 /* Chips with APE need BAR2 access for APE registers/memory. */
3439 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3440 rid = PCIR_BAR(2);
3441 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3442 RF_ACTIVE);
3443 if (sc->bge_res2 == NULL) {
3444 device_printf (sc->bge_dev,
3445 "couldn't map BAR2 memory\n");
3446 error = ENXIO;
3447 goto fail;
3448 }
3449
3450 /* Enable APE register/memory access by host driver. */
3451 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3452 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3453 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3454 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3455 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3456
3457 bge_ape_lock_init(sc);
3458 bge_ape_read_fw_ver(sc);
3459 }
3460
3461 /* Add SYSCTLs, requires the chipset family to be set. */
3462 bge_add_sysctls(sc);
3463
3464 /* Identify the chips that use an CPMU. */
3465 if (BGE_IS_5717_PLUS(sc) ||
3466 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3467 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3468 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3469 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3470 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3471 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3472 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3473 else
3474 sc->bge_mi_mode = BGE_MIMODE_BASE;
3475 /* Enable auto polling for BCM570[0-5]. */
3476 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3477 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3478
3479 /*
3480 * All Broadcom controllers have 4GB boundary DMA bug.
3481 * Whenever an address crosses a multiple of the 4GB boundary
3482 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3483 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3484 * state machine will lockup and cause the device to hang.
3485 */
3486 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3487
3488 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3489 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3490 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3491
3492 /*
3493 * BCM5719 cannot handle DMA requests for DMA segments that
3494 * have larger than 4KB in size. However the maximum DMA
3495 * segment size created in DMA tag is 4KB for TSO, so we
3496 * wouldn't encounter the issue here.
3497 */
3498 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3499 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3500
3501 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3502 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3503 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3504 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3505 sc->bge_flags |= BGE_FLAG_5788;
3506 }
3507
3508 capmask = BMSR_DEFCAPMASK;
3509 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3510 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3511 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3512 pci_get_vendor(dev) == BCOM_VENDORID &&
3513 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3514 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3515 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3516 (pci_get_vendor(dev) == BCOM_VENDORID &&
3517 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3518 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3519 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3520 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3521 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3522 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3523 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3524 /* These chips are 10/100 only. */
3525 capmask &= ~BMSR_EXTSTAT;
3526 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3527 }
3528
3529 /*
3530 * Some controllers seem to require a special firmware to use
3531 * TSO. But the firmware is not available to FreeBSD and Linux
3532 * claims that the TSO performed by the firmware is slower than
3533 * hardware based TSO. Moreover the firmware based TSO has one
3534 * known bug which can't handle TSO if Ethernet header + IP/TCP
3535 * header is greater than 80 bytes. A workaround for the TSO
3536 * bug exist but it seems it's too expensive than not using
3537 * TSO at all. Some hardware also have the TSO bug so limit
3538 * the TSO to the controllers that are not affected TSO issues
3539 * (e.g. 5755 or higher).
3540 */
3541 if (BGE_IS_5717_PLUS(sc)) {
3542 /* BCM5717 requires different TSO configuration. */
3543 sc->bge_flags |= BGE_FLAG_TSO3;
3544 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3545 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3546 /* TSO on BCM5719 A0 does not work. */
3547 sc->bge_flags &= ~BGE_FLAG_TSO3;
3548 }
3549 } else if (BGE_IS_5755_PLUS(sc)) {
3550 /*
3551 * BCM5754 and BCM5787 shares the same ASIC id so
3552 * explicit device id check is required.
3553 * Due to unknown reason TSO does not work on BCM5755M.
3554 */
3555 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3556 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3557 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3558 sc->bge_flags |= BGE_FLAG_TSO;
3559 }
3560
3561 /*
3562 * Check if this is a PCI-X or PCI Express device.
3563 */
3564 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3565 /*
3566 * Found a PCI Express capabilities register, this
3567 * must be a PCI Express device.
3568 */
3569 sc->bge_flags |= BGE_FLAG_PCIE;
3570 sc->bge_expcap = reg;
3571 /* Extract supported maximum payload size. */
3572 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3573 PCIER_DEVICE_CAP, 2);
3574 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3575 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3576 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3577 sc->bge_expmrq = 2048;
3578 else
3579 sc->bge_expmrq = 4096;
3580 pci_set_max_read_req(dev, sc->bge_expmrq);
3581 } else {
3582 /*
3583 * Check if the device is in PCI-X Mode.
3584 * (This bit is not valid on PCI Express controllers.)
3585 */
3586 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3587 sc->bge_pcixcap = reg;
3588 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3589 BGE_PCISTATE_PCI_BUSMODE) == 0)
3590 sc->bge_flags |= BGE_FLAG_PCIX;
3591 }
3592
3593 /*
3594 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3595 * not actually a MAC controller bug but an issue with the embedded
3596 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3597 */
3598 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3599 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3600 /*
3601 * Some PCI-X bridges are known to trigger write reordering to
3602 * the mailbox registers. Typical phenomena is watchdog timeouts
3603 * caused by out-of-order TX completions. Enable workaround for
3604 * PCI-X devices that live behind these bridges.
3605 * Note, PCI-X controllers can run in PCI mode so we can't use
3606 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3607 */
3608 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3609 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3610 /*
3611 * Allocate the interrupt, using MSI if possible. These devices
3612 * support 8 MSI messages, but only the first one is used in
3613 * normal operation.
3614 */
3615 rid = 0;
3616 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3617 sc->bge_msicap = reg;
3618 reg = 1;
3619 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3620 rid = 1;
3621 sc->bge_flags |= BGE_FLAG_MSI;
3622 }
3623 }
3624
3625 /*
3626 * All controllers except BCM5700 supports tagged status but
3627 * we use tagged status only for MSI case on BCM5717. Otherwise
3628 * MSI on BCM5717 does not work.
3629 */
3630 #ifndef DEVICE_POLLING
3631 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3632 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3633 #endif
3634
3635 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3636 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3637
3638 if (sc->bge_irq == NULL) {
3639 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3640 error = ENXIO;
3641 goto fail;
3642 }
3643
3644 bge_devinfo(sc);
3645
3646 sc->bge_asf_mode = 0;
3647 /* No ASF if APE present. */
3648 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3649 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3650 BGE_SRAM_DATA_SIG_MAGIC)) {
3651 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3652 BGE_HWCFG_ASF) {
3653 sc->bge_asf_mode |= ASF_ENABLE;
3654 sc->bge_asf_mode |= ASF_STACKUP;
3655 if (BGE_IS_575X_PLUS(sc))
3656 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3657 }
3658 }
3659 }
3660
3661 bge_stop_fw(sc);
3662 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3663 if (bge_reset(sc)) {
3664 device_printf(sc->bge_dev, "chip reset failed\n");
3665 error = ENXIO;
3666 goto fail;
3667 }
3668
3669 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3670 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3671
3672 if (bge_chipinit(sc)) {
3673 device_printf(sc->bge_dev, "chip initialization failed\n");
3674 error = ENXIO;
3675 goto fail;
3676 }
3677
3678 error = bge_get_eaddr(sc, eaddr);
3679 if (error) {
3680 device_printf(sc->bge_dev,
3681 "failed to read station address\n");
3682 error = ENXIO;
3683 goto fail;
3684 }
3685
3686 /* 5705 limits RX return ring to 512 entries. */
3687 if (BGE_IS_5717_PLUS(sc))
3688 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3689 else if (BGE_IS_5705_PLUS(sc))
3690 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3691 else
3692 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3693
3694 if (bge_dma_alloc(sc)) {
3695 device_printf(sc->bge_dev,
3696 "failed to allocate DMA resources\n");
3697 error = ENXIO;
3698 goto fail;
3699 }
3700
3701 /* Set default tuneable values. */
3702 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3703 sc->bge_rx_coal_ticks = 150;
3704 sc->bge_tx_coal_ticks = 150;
3705 sc->bge_rx_max_coal_bds = 10;
3706 sc->bge_tx_max_coal_bds = 10;
3707
3708 /* Initialize checksum features to use. */
3709 sc->bge_csum_features = BGE_CSUM_FEATURES;
3710 if (sc->bge_forced_udpcsum != 0)
3711 sc->bge_csum_features |= CSUM_UDP;
3712
3713 /* Set up ifnet structure */
3714 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3715 if_setsoftc(ifp, sc);
3716 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3717 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3718 if_setioctlfn(ifp, bge_ioctl);
3719 if_setstartfn(ifp, bge_start);
3720 if_setinitfn(ifp, bge_init);
3721 if_setgetcounterfn(ifp, bge_get_counter);
3722 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3723 if_setsendqready(ifp);
3724 if_sethwassist(ifp, sc->bge_csum_features);
3725 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3726 IFCAP_VLAN_MTU);
3727 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3728 if_sethwassistbits(ifp, CSUM_TSO, 0);
3729 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3730 }
3731 #ifdef IFCAP_VLAN_HWCSUM
3732 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3733 #endif
3734 if_setcapenable(ifp, if_getcapabilities(ifp));
3735 #ifdef DEVICE_POLLING
3736 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3737 #endif
3738
3739 /*
3740 * 5700 B0 chips do not support checksumming correctly due
3741 * to hardware bugs.
3742 */
3743 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3744 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3745 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3746 if_sethwassist(ifp, 0);
3747 }
3748
3749 /*
3750 * Figure out what sort of media we have by checking the
3751 * hardware config word in the first 32k of NIC internal memory,
3752 * or fall back to examining the EEPROM if necessary.
3753 * Note: on some BCM5700 cards, this value appears to be unset.
3754 * If that's the case, we have to rely on identifying the NIC
3755 * by its PCI subsystem ID, as we do below for the SysKonnect
3756 * SK-9D41.
3757 */
3758 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3759 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3760 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3761 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3762 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3763 sizeof(hwcfg))) {
3764 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3765 error = ENXIO;
3766 goto fail;
3767 }
3768 hwcfg = ntohl(hwcfg);
3769 }
3770
3771 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3772 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3773 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3774 if (BGE_IS_5705_PLUS(sc)) {
3775 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3776 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3777 } else
3778 sc->bge_flags |= BGE_FLAG_TBI;
3779 }
3780
3781 /* Set various PHY bug flags. */
3782 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3783 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3784 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3785 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3786 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3787 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3788 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3789 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3790 if (pci_get_subvendor(dev) == DELL_VENDORID)
3791 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3792 if ((BGE_IS_5705_PLUS(sc)) &&
3793 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3794 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3795 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3796 !BGE_IS_5717_PLUS(sc)) {
3797 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3798 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3799 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3800 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3801 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3802 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3803 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3804 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3805 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3806 } else
3807 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3808 }
3809
3810 /*
3811 * Don't enable Ethernet@WireSpeed for the 5700 or the
3812 * 5705 A0 and A1 chips.
3813 */
3814 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3815 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3816 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3817 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3818 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3819
3820 if (sc->bge_flags & BGE_FLAG_TBI) {
3821 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3822 bge_ifmedia_sts);
3823 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3824 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3825 0, NULL);
3826 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3827 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3828 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3829 } else {
3830 /*
3831 * Do transceiver setup and tell the firmware the
3832 * driver is down so we can try to get access the
3833 * probe if ASF is running. Retry a couple of times
3834 * if we get a conflict with the ASF firmware accessing
3835 * the PHY.
3836 */
3837 trys = 0;
3838 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3839 again:
3840 bge_asf_driver_up(sc);
3841
3842 error = mii_attach(dev, &sc->bge_miibus, ifp,
3843 (ifm_change_cb_t)bge_ifmedia_upd,
3844 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3845 MII_OFFSET_ANY, MIIF_DOPAUSE);
3846 if (error != 0) {
3847 if (trys++ < 4) {
3848 device_printf(sc->bge_dev, "Try again\n");
3849 bge_miibus_writereg(sc->bge_dev,
3850 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3851 goto again;
3852 }
3853 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3854 goto fail;
3855 }
3856
3857 /*
3858 * Now tell the firmware we are going up after probing the PHY
3859 */
3860 if (sc->bge_asf_mode & ASF_STACKUP)
3861 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3862 }
3863
3864 /*
3865 * When using the BCM5701 in PCI-X mode, data corruption has
3866 * been observed in the first few bytes of some received packets.
3867 * Aligning the packet buffer in memory eliminates the corruption.
3868 * Unfortunately, this misaligns the packet payloads. On platforms
3869 * which do not support unaligned accesses, we will realign the
3870 * payloads by copying the received packets.
3871 */
3872 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3873 sc->bge_flags & BGE_FLAG_PCIX)
3874 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3875
3876 /*
3877 * Call MI attach routine.
3878 */
3879 ether_ifattach(ifp, eaddr);
3880
3881 /* Tell upper layer we support long frames. */
3882 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3883
3884 /*
3885 * Hookup IRQ last.
3886 */
3887 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3888 /* Take advantage of single-shot MSI. */
3889 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3890 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3891 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3892 taskqueue_thread_enqueue, &sc->bge_tq);
3893 if (sc->bge_tq == NULL) {
3894 device_printf(dev, "could not create taskqueue.\n");
3895 ether_ifdetach(ifp);
3896 error = ENOMEM;
3897 goto fail;
3898 }
3899 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3900 "%s taskq", device_get_nameunit(sc->bge_dev));
3901 if (error != 0) {
3902 device_printf(dev, "could not start threads.\n");
3903 ether_ifdetach(ifp);
3904 goto fail;
3905 }
3906 error = bus_setup_intr(dev, sc->bge_irq,
3907 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3908 &sc->bge_intrhand);
3909 } else
3910 error = bus_setup_intr(dev, sc->bge_irq,
3911 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3912 &sc->bge_intrhand);
3913
3914 if (error) {
3915 ether_ifdetach(ifp);
3916 device_printf(sc->bge_dev, "couldn't set up irq\n");
3917 goto fail;
3918 }
3919
3920 /* Attach driver debugnet methods. */
3921 DEBUGNET_SET(ifp, bge);
3922
3923 fail:
3924 if (error)
3925 bge_detach(dev);
3926 return (error);
3927 }
3928
3929 static int
bge_detach(device_t dev)3930 bge_detach(device_t dev)
3931 {
3932 struct bge_softc *sc;
3933 if_t ifp;
3934
3935 sc = device_get_softc(dev);
3936 ifp = sc->bge_ifp;
3937
3938 #ifdef DEVICE_POLLING
3939 if (if_getcapenable(ifp) & IFCAP_POLLING)
3940 ether_poll_deregister(ifp);
3941 #endif
3942
3943 if (device_is_attached(dev)) {
3944 ether_ifdetach(ifp);
3945 BGE_LOCK(sc);
3946 bge_stop(sc);
3947 BGE_UNLOCK(sc);
3948 callout_drain(&sc->bge_stat_ch);
3949 }
3950
3951 if (sc->bge_tq)
3952 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3953
3954 if (sc->bge_flags & BGE_FLAG_TBI)
3955 ifmedia_removeall(&sc->bge_ifmedia);
3956 else if (sc->bge_miibus != NULL) {
3957 bus_generic_detach(dev);
3958 device_delete_child(dev, sc->bge_miibus);
3959 }
3960
3961 bge_release_resources(sc);
3962
3963 return (0);
3964 }
3965
3966 static void
bge_release_resources(struct bge_softc * sc)3967 bge_release_resources(struct bge_softc *sc)
3968 {
3969 device_t dev;
3970
3971 dev = sc->bge_dev;
3972
3973 if (sc->bge_tq != NULL)
3974 taskqueue_free(sc->bge_tq);
3975
3976 if (sc->bge_intrhand != NULL)
3977 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3978
3979 if (sc->bge_irq != NULL) {
3980 bus_release_resource(dev, SYS_RES_IRQ,
3981 rman_get_rid(sc->bge_irq), sc->bge_irq);
3982 pci_release_msi(dev);
3983 }
3984
3985 if (sc->bge_res != NULL)
3986 bus_release_resource(dev, SYS_RES_MEMORY,
3987 rman_get_rid(sc->bge_res), sc->bge_res);
3988
3989 if (sc->bge_res2 != NULL)
3990 bus_release_resource(dev, SYS_RES_MEMORY,
3991 rman_get_rid(sc->bge_res2), sc->bge_res2);
3992
3993 if (sc->bge_ifp != NULL)
3994 if_free(sc->bge_ifp);
3995
3996 bge_dma_free(sc);
3997
3998 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3999 BGE_LOCK_DESTROY(sc);
4000 }
4001
4002 static int
bge_reset(struct bge_softc * sc)4003 bge_reset(struct bge_softc *sc)
4004 {
4005 device_t dev;
4006 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4007 void (*write_op)(struct bge_softc *, int, int);
4008 uint16_t devctl;
4009 int i;
4010
4011 dev = sc->bge_dev;
4012
4013 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4014 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4015 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4016 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4017
4018 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4019 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4020 if (sc->bge_flags & BGE_FLAG_PCIE)
4021 write_op = bge_writemem_direct;
4022 else
4023 write_op = bge_writemem_ind;
4024 } else
4025 write_op = bge_writereg_ind;
4026
4027 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4028 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4029 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4030 for (i = 0; i < 8000; i++) {
4031 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4032 BGE_NVRAMSWARB_GNT1)
4033 break;
4034 DELAY(20);
4035 }
4036 if (i == 8000) {
4037 if (bootverbose)
4038 device_printf(dev, "NVRAM lock timedout!\n");
4039 }
4040 }
4041 /* Take APE lock when performing reset. */
4042 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4043
4044 /* Save some important PCI state. */
4045 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4046 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4047
4048 pci_write_config(dev, BGE_PCI_MISC_CTL,
4049 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4050 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4051
4052 /* Disable fastboot on controllers that support it. */
4053 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4054 BGE_IS_5755_PLUS(sc)) {
4055 if (bootverbose)
4056 device_printf(dev, "Disabling fastboot\n");
4057 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4058 }
4059
4060 /*
4061 * Write the magic number to SRAM at offset 0xB50.
4062 * When firmware finishes its initialization it will
4063 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4064 */
4065 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4066
4067 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4068
4069 /* XXX: Broadcom Linux driver. */
4070 if (sc->bge_flags & BGE_FLAG_PCIE) {
4071 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4072 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4073 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4074 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4075 }
4076 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4077 /* Prevent PCIE link training during global reset */
4078 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4079 reset |= 1 << 29;
4080 }
4081 }
4082
4083 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4084 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4085 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4086 val | BGE_VCPU_STATUS_DRV_RESET);
4087 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4088 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4089 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4090 }
4091
4092 /*
4093 * Set GPHY Power Down Override to leave GPHY
4094 * powered up in D0 uninitialized.
4095 */
4096 if (BGE_IS_5705_PLUS(sc) &&
4097 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4098 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4099
4100 /* Issue global reset */
4101 write_op(sc, BGE_MISC_CFG, reset);
4102
4103 if (sc->bge_flags & BGE_FLAG_PCIE)
4104 DELAY(100 * 1000);
4105 else
4106 DELAY(1000);
4107
4108 /* XXX: Broadcom Linux driver. */
4109 if (sc->bge_flags & BGE_FLAG_PCIE) {
4110 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4111 DELAY(500000); /* wait for link training to complete */
4112 val = pci_read_config(dev, 0xC4, 4);
4113 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4114 }
4115 devctl = pci_read_config(dev,
4116 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4117 /* Clear enable no snoop and disable relaxed ordering. */
4118 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4119 PCIEM_CTL_NOSNOOP_ENABLE);
4120 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4121 devctl, 2);
4122 pci_set_max_read_req(dev, sc->bge_expmrq);
4123 /* Clear error status. */
4124 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4125 PCIEM_STA_CORRECTABLE_ERROR |
4126 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4127 PCIEM_STA_UNSUPPORTED_REQ, 2);
4128 }
4129
4130 /* Reset some of the PCI state that got zapped by reset. */
4131 pci_write_config(dev, BGE_PCI_MISC_CTL,
4132 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4133 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4134 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4135 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4136 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4137 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4138 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4139 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4140 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4141 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4142 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4143 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4144 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4145 /*
4146 * Disable PCI-X relaxed ordering to ensure status block update
4147 * comes first then packet buffer DMA. Otherwise driver may
4148 * read stale status block.
4149 */
4150 if (sc->bge_flags & BGE_FLAG_PCIX) {
4151 devctl = pci_read_config(dev,
4152 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4153 devctl &= ~PCIXM_COMMAND_ERO;
4154 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4155 devctl &= ~PCIXM_COMMAND_MAX_READ;
4156 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4157 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4158 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4159 PCIXM_COMMAND_MAX_READ);
4160 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4161 }
4162 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4163 devctl, 2);
4164 }
4165 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4166 if (BGE_IS_5714_FAMILY(sc)) {
4167 /* This chip disables MSI on reset. */
4168 if (sc->bge_flags & BGE_FLAG_MSI) {
4169 val = pci_read_config(dev,
4170 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4171 pci_write_config(dev,
4172 sc->bge_msicap + PCIR_MSI_CTRL,
4173 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4174 val = CSR_READ_4(sc, BGE_MSI_MODE);
4175 CSR_WRITE_4(sc, BGE_MSI_MODE,
4176 val | BGE_MSIMODE_ENABLE);
4177 }
4178 val = CSR_READ_4(sc, BGE_MARB_MODE);
4179 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4180 } else
4181 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4182
4183 /* Fix up byte swapping. */
4184 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4185
4186 val = CSR_READ_4(sc, BGE_MAC_MODE);
4187 val = (val & ~mac_mode_mask) | mac_mode;
4188 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4189 DELAY(40);
4190
4191 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4192
4193 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4194 for (i = 0; i < BGE_TIMEOUT; i++) {
4195 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4196 if (val & BGE_VCPU_STATUS_INIT_DONE)
4197 break;
4198 DELAY(100);
4199 }
4200 if (i == BGE_TIMEOUT) {
4201 device_printf(dev, "reset timed out\n");
4202 return (1);
4203 }
4204 } else {
4205 /*
4206 * Poll until we see the 1's complement of the magic number.
4207 * This indicates that the firmware initialization is complete.
4208 * We expect this to fail if no chip containing the Ethernet
4209 * address is fitted though.
4210 */
4211 for (i = 0; i < BGE_TIMEOUT; i++) {
4212 DELAY(10);
4213 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4214 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4215 break;
4216 }
4217
4218 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4219 device_printf(dev,
4220 "firmware handshake timed out, found 0x%08x\n",
4221 val);
4222 /* BCM57765 A0 needs additional time before accessing. */
4223 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4224 DELAY(10 * 1000); /* XXX */
4225 }
4226
4227 /*
4228 * The 5704 in TBI mode apparently needs some special
4229 * adjustment to insure the SERDES drive level is set
4230 * to 1.2V.
4231 */
4232 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4233 sc->bge_flags & BGE_FLAG_TBI) {
4234 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4235 val = (val & ~0xFFF) | 0x880;
4236 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4237 }
4238
4239 /* XXX: Broadcom Linux driver. */
4240 if (sc->bge_flags & BGE_FLAG_PCIE &&
4241 !BGE_IS_5717_PLUS(sc) &&
4242 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4243 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4244 /* Enable Data FIFO protection. */
4245 val = CSR_READ_4(sc, 0x7C00);
4246 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4247 }
4248
4249 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4250 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4251 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4252
4253 return (0);
4254 }
4255
4256 static __inline void
bge_rxreuse_std(struct bge_softc * sc,int i)4257 bge_rxreuse_std(struct bge_softc *sc, int i)
4258 {
4259 struct bge_rx_bd *r;
4260
4261 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4262 r->bge_flags = BGE_RXBDFLAG_END;
4263 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4264 r->bge_idx = i;
4265 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4266 }
4267
4268 static __inline void
bge_rxreuse_jumbo(struct bge_softc * sc,int i)4269 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4270 {
4271 struct bge_extrx_bd *r;
4272
4273 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4274 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4275 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4276 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4277 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4278 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4279 r->bge_idx = i;
4280 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4281 }
4282
4283 /*
4284 * Frame reception handling. This is called if there's a frame
4285 * on the receive return list.
4286 *
4287 * Note: we have to be able to handle two possibilities here:
4288 * 1) the frame is from the jumbo receive ring
4289 * 2) the frame is from the standard receive ring
4290 */
4291
4292 static int
bge_rxeof(struct bge_softc * sc,uint16_t rx_prod,int holdlck)4293 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4294 {
4295 if_t ifp;
4296 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4297 uint16_t rx_cons;
4298
4299 rx_cons = sc->bge_rx_saved_considx;
4300
4301 /* Nothing to do. */
4302 if (rx_cons == rx_prod)
4303 return (rx_npkts);
4304
4305 ifp = sc->bge_ifp;
4306
4307 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4308 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4309 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4310 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4311 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4312 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4313 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4314 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4315 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4316
4317 while (rx_cons != rx_prod) {
4318 struct bge_rx_bd *cur_rx;
4319 uint32_t rxidx;
4320 struct mbuf *m = NULL;
4321 uint16_t vlan_tag = 0;
4322 int have_tag = 0;
4323
4324 #ifdef DEVICE_POLLING
4325 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4326 if (sc->rxcycles <= 0)
4327 break;
4328 sc->rxcycles--;
4329 }
4330 #endif
4331
4332 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4333
4334 rxidx = cur_rx->bge_idx;
4335 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4336
4337 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4338 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4339 have_tag = 1;
4340 vlan_tag = cur_rx->bge_vlan_tag;
4341 }
4342
4343 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4344 jumbocnt++;
4345 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4346 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4347 bge_rxreuse_jumbo(sc, rxidx);
4348 continue;
4349 }
4350 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4351 bge_rxreuse_jumbo(sc, rxidx);
4352 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4353 continue;
4354 }
4355 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4356 } else {
4357 stdcnt++;
4358 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4359 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4360 bge_rxreuse_std(sc, rxidx);
4361 continue;
4362 }
4363 if (bge_newbuf_std(sc, rxidx) != 0) {
4364 bge_rxreuse_std(sc, rxidx);
4365 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4366 continue;
4367 }
4368 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4369 }
4370
4371 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4372 #ifndef __NO_STRICT_ALIGNMENT
4373 /*
4374 * For architectures with strict alignment we must make sure
4375 * the payload is aligned.
4376 */
4377 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4378 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4379 cur_rx->bge_len);
4380 m->m_data += ETHER_ALIGN;
4381 }
4382 #endif
4383 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4384 m->m_pkthdr.rcvif = ifp;
4385
4386 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4387 bge_rxcsum(sc, cur_rx, m);
4388
4389 /*
4390 * If we received a packet with a vlan tag,
4391 * attach that information to the packet.
4392 */
4393 if (have_tag) {
4394 m->m_pkthdr.ether_vtag = vlan_tag;
4395 m->m_flags |= M_VLANTAG;
4396 }
4397
4398 if (holdlck != 0) {
4399 BGE_UNLOCK(sc);
4400 if_input(ifp, m);
4401 BGE_LOCK(sc);
4402 } else
4403 if_input(ifp, m);
4404 rx_npkts++;
4405
4406 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4407 return (rx_npkts);
4408 }
4409
4410 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4411 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4412 if (stdcnt > 0)
4413 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4414 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4415
4416 if (jumbocnt > 0)
4417 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4418 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4419
4420 sc->bge_rx_saved_considx = rx_cons;
4421 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4422 if (stdcnt)
4423 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4424 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4425 if (jumbocnt)
4426 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4427 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4428 #ifdef notyet
4429 /*
4430 * This register wraps very quickly under heavy packet drops.
4431 * If you need correct statistics, you can enable this check.
4432 */
4433 if (BGE_IS_5705_PLUS(sc))
4434 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4435 #endif
4436 return (rx_npkts);
4437 }
4438
4439 static void
bge_rxcsum(struct bge_softc * sc,struct bge_rx_bd * cur_rx,struct mbuf * m)4440 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4441 {
4442
4443 if (BGE_IS_5717_PLUS(sc)) {
4444 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4445 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4446 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4447 if ((cur_rx->bge_error_flag &
4448 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4449 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4450 }
4451 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4452 m->m_pkthdr.csum_data =
4453 cur_rx->bge_tcp_udp_csum;
4454 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4455 CSUM_PSEUDO_HDR;
4456 }
4457 }
4458 } else {
4459 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4460 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4461 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4462 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4463 }
4464 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4465 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4466 m->m_pkthdr.csum_data =
4467 cur_rx->bge_tcp_udp_csum;
4468 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4469 CSUM_PSEUDO_HDR;
4470 }
4471 }
4472 }
4473
4474 static void
bge_txeof(struct bge_softc * sc,uint16_t tx_cons)4475 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4476 {
4477 struct bge_tx_bd *cur_tx;
4478 if_t ifp;
4479
4480 BGE_LOCK_ASSERT(sc);
4481
4482 /* Nothing to do. */
4483 if (sc->bge_tx_saved_considx == tx_cons)
4484 return;
4485
4486 ifp = sc->bge_ifp;
4487
4488 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4489 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4490 /*
4491 * Go through our tx ring and free mbufs for those
4492 * frames that have been sent.
4493 */
4494 while (sc->bge_tx_saved_considx != tx_cons) {
4495 uint32_t idx;
4496
4497 idx = sc->bge_tx_saved_considx;
4498 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4499 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4500 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4501 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4502 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4503 sc->bge_cdata.bge_tx_dmamap[idx],
4504 BUS_DMASYNC_POSTWRITE);
4505 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4506 sc->bge_cdata.bge_tx_dmamap[idx]);
4507 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4508 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4509 }
4510 sc->bge_txcnt--;
4511 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4512 }
4513
4514 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4515 if (sc->bge_txcnt == 0)
4516 sc->bge_timer = 0;
4517 }
4518
4519 #ifdef DEVICE_POLLING
4520 static int
bge_poll(if_t ifp,enum poll_cmd cmd,int count)4521 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4522 {
4523 struct bge_softc *sc = if_getsoftc(ifp);
4524 uint16_t rx_prod, tx_cons;
4525 uint32_t statusword;
4526 int rx_npkts = 0;
4527
4528 BGE_LOCK(sc);
4529 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4530 BGE_UNLOCK(sc);
4531 return (rx_npkts);
4532 }
4533
4534 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4535 sc->bge_cdata.bge_status_map,
4536 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4537 /* Fetch updates from the status block. */
4538 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4539 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4540
4541 statusword = sc->bge_ldata.bge_status_block->bge_status;
4542 /* Clear the status so the next pass only sees the changes. */
4543 sc->bge_ldata.bge_status_block->bge_status = 0;
4544
4545 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4546 sc->bge_cdata.bge_status_map,
4547 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4548
4549 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4550 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4551 sc->bge_link_evt++;
4552
4553 if (cmd == POLL_AND_CHECK_STATUS)
4554 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4555 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4556 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4557 bge_link_upd(sc);
4558
4559 sc->rxcycles = count;
4560 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4561 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4562 BGE_UNLOCK(sc);
4563 return (rx_npkts);
4564 }
4565 bge_txeof(sc, tx_cons);
4566 if (!if_sendq_empty(ifp))
4567 bge_start_locked(ifp);
4568
4569 BGE_UNLOCK(sc);
4570 return (rx_npkts);
4571 }
4572 #endif /* DEVICE_POLLING */
4573
4574 static int
bge_msi_intr(void * arg)4575 bge_msi_intr(void *arg)
4576 {
4577 struct bge_softc *sc;
4578
4579 sc = (struct bge_softc *)arg;
4580 /*
4581 * This interrupt is not shared and controller already
4582 * disabled further interrupt.
4583 */
4584 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4585 return (FILTER_HANDLED);
4586 }
4587
4588 static void
bge_intr_task(void * arg,int pending)4589 bge_intr_task(void *arg, int pending)
4590 {
4591 struct bge_softc *sc;
4592 if_t ifp;
4593 uint32_t status, status_tag;
4594 uint16_t rx_prod, tx_cons;
4595
4596 sc = (struct bge_softc *)arg;
4597 ifp = sc->bge_ifp;
4598
4599 BGE_LOCK(sc);
4600 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4601 BGE_UNLOCK(sc);
4602 return;
4603 }
4604
4605 /* Get updated status block. */
4606 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4607 sc->bge_cdata.bge_status_map,
4608 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4609
4610 /* Save producer/consumer indices. */
4611 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4612 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4613 status = sc->bge_ldata.bge_status_block->bge_status;
4614 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4615 /* Dirty the status flag. */
4616 sc->bge_ldata.bge_status_block->bge_status = 0;
4617 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4618 sc->bge_cdata.bge_status_map,
4619 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4620 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4621 status_tag = 0;
4622
4623 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4624 bge_link_upd(sc);
4625
4626 /* Let controller work. */
4627 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4628
4629 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4630 sc->bge_rx_saved_considx != rx_prod) {
4631 /* Check RX return ring producer/consumer. */
4632 BGE_UNLOCK(sc);
4633 bge_rxeof(sc, rx_prod, 0);
4634 BGE_LOCK(sc);
4635 }
4636 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4637 /* Check TX ring producer/consumer. */
4638 bge_txeof(sc, tx_cons);
4639 if (!if_sendq_empty(ifp))
4640 bge_start_locked(ifp);
4641 }
4642 BGE_UNLOCK(sc);
4643 }
4644
4645 static void
bge_intr(void * xsc)4646 bge_intr(void *xsc)
4647 {
4648 struct bge_softc *sc;
4649 if_t ifp;
4650 uint32_t statusword;
4651 uint16_t rx_prod, tx_cons;
4652
4653 sc = xsc;
4654
4655 BGE_LOCK(sc);
4656
4657 ifp = sc->bge_ifp;
4658
4659 #ifdef DEVICE_POLLING
4660 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4661 BGE_UNLOCK(sc);
4662 return;
4663 }
4664 #endif
4665
4666 /*
4667 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4668 * disable interrupts by writing nonzero like we used to, since with
4669 * our current organization this just gives complications and
4670 * pessimizations for re-enabling interrupts. We used to have races
4671 * instead of the necessary complications. Disabling interrupts
4672 * would just reduce the chance of a status update while we are
4673 * running (by switching to the interrupt-mode coalescence
4674 * parameters), but this chance is already very low so it is more
4675 * efficient to get another interrupt than prevent it.
4676 *
4677 * We do the ack first to ensure another interrupt if there is a
4678 * status update after the ack. We don't check for the status
4679 * changing later because it is more efficient to get another
4680 * interrupt than prevent it, not quite as above (not checking is
4681 * a smaller optimization than not toggling the interrupt enable,
4682 * since checking doesn't involve PCI accesses and toggling require
4683 * the status check). So toggling would probably be a pessimization
4684 * even with MSI. It would only be needed for using a task queue.
4685 */
4686 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4687
4688 /*
4689 * Do the mandatory PCI flush as well as get the link status.
4690 */
4691 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4692
4693 /* Make sure the descriptor ring indexes are coherent. */
4694 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4695 sc->bge_cdata.bge_status_map,
4696 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4697 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4698 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4699 sc->bge_ldata.bge_status_block->bge_status = 0;
4700 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4701 sc->bge_cdata.bge_status_map,
4702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4703
4704 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4705 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4706 statusword || sc->bge_link_evt)
4707 bge_link_upd(sc);
4708
4709 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4710 /* Check RX return ring producer/consumer. */
4711 bge_rxeof(sc, rx_prod, 1);
4712 }
4713
4714 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4715 /* Check TX ring producer/consumer. */
4716 bge_txeof(sc, tx_cons);
4717 }
4718
4719 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4720 !if_sendq_empty(ifp))
4721 bge_start_locked(ifp);
4722
4723 BGE_UNLOCK(sc);
4724 }
4725
4726 static void
bge_asf_driver_up(struct bge_softc * sc)4727 bge_asf_driver_up(struct bge_softc *sc)
4728 {
4729 if (sc->bge_asf_mode & ASF_STACKUP) {
4730 /* Send ASF heartbeat aprox. every 2s */
4731 if (sc->bge_asf_count)
4732 sc->bge_asf_count --;
4733 else {
4734 sc->bge_asf_count = 2;
4735 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4736 BGE_FW_CMD_DRV_ALIVE);
4737 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4738 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4739 BGE_FW_HB_TIMEOUT_SEC);
4740 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4741 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4742 BGE_RX_CPU_DRV_EVENT);
4743 }
4744 }
4745 }
4746
4747 static void
bge_tick(void * xsc)4748 bge_tick(void *xsc)
4749 {
4750 struct bge_softc *sc = xsc;
4751 struct mii_data *mii = NULL;
4752
4753 BGE_LOCK_ASSERT(sc);
4754
4755 /* Synchronize with possible callout reset/stop. */
4756 if (callout_pending(&sc->bge_stat_ch) ||
4757 !callout_active(&sc->bge_stat_ch))
4758 return;
4759
4760 if (BGE_IS_5705_PLUS(sc))
4761 bge_stats_update_regs(sc);
4762 else
4763 bge_stats_update(sc);
4764
4765 /* XXX Add APE heartbeat check here? */
4766
4767 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4768 mii = device_get_softc(sc->bge_miibus);
4769 /*
4770 * Do not touch PHY if we have link up. This could break
4771 * IPMI/ASF mode or produce extra input errors
4772 * (extra errors was reported for bcm5701 & bcm5704).
4773 */
4774 if (!sc->bge_link)
4775 mii_tick(mii);
4776 } else {
4777 /*
4778 * Since in TBI mode auto-polling can't be used we should poll
4779 * link status manually. Here we register pending link event
4780 * and trigger interrupt.
4781 */
4782 #ifdef DEVICE_POLLING
4783 /* In polling mode we poll link state in bge_poll(). */
4784 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4785 #endif
4786 {
4787 sc->bge_link_evt++;
4788 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4789 sc->bge_flags & BGE_FLAG_5788)
4790 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4791 else
4792 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4793 }
4794 }
4795
4796 bge_asf_driver_up(sc);
4797 bge_watchdog(sc);
4798
4799 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4800 }
4801
4802 static void
bge_stats_update_regs(struct bge_softc * sc)4803 bge_stats_update_regs(struct bge_softc *sc)
4804 {
4805 struct bge_mac_stats *stats;
4806 uint32_t val;
4807
4808 stats = &sc->bge_mac_stats;
4809
4810 stats->ifHCOutOctets +=
4811 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4812 stats->etherStatsCollisions +=
4813 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4814 stats->outXonSent +=
4815 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4816 stats->outXoffSent +=
4817 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4818 stats->dot3StatsInternalMacTransmitErrors +=
4819 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4820 stats->dot3StatsSingleCollisionFrames +=
4821 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4822 stats->dot3StatsMultipleCollisionFrames +=
4823 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4824 stats->dot3StatsDeferredTransmissions +=
4825 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4826 stats->dot3StatsExcessiveCollisions +=
4827 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4828 stats->dot3StatsLateCollisions +=
4829 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4830 stats->ifHCOutUcastPkts +=
4831 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4832 stats->ifHCOutMulticastPkts +=
4833 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4834 stats->ifHCOutBroadcastPkts +=
4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4836
4837 stats->ifHCInOctets +=
4838 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4839 stats->etherStatsFragments +=
4840 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4841 stats->ifHCInUcastPkts +=
4842 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4843 stats->ifHCInMulticastPkts +=
4844 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4845 stats->ifHCInBroadcastPkts +=
4846 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4847 stats->dot3StatsFCSErrors +=
4848 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4849 stats->dot3StatsAlignmentErrors +=
4850 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4851 stats->xonPauseFramesReceived +=
4852 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4853 stats->xoffPauseFramesReceived +=
4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4855 stats->macControlFramesReceived +=
4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4857 stats->xoffStateEntered +=
4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4859 stats->dot3StatsFramesTooLong +=
4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4861 stats->etherStatsJabbers +=
4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4863 stats->etherStatsUndersizePkts +=
4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4865
4866 stats->FramesDroppedDueToFilters +=
4867 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4868 stats->DmaWriteQueueFull +=
4869 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4870 stats->DmaWriteHighPriQueueFull +=
4871 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4872 stats->NoMoreRxBDs +=
4873 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4874 /*
4875 * XXX
4876 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4877 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4878 * includes number of unwanted multicast frames. This comes
4879 * from silicon bug and known workaround to get rough(not
4880 * exact) counter is to enable interrupt on MBUF low water
4881 * attention. This can be accomplished by setting
4882 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4883 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4884 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4885 * However that change would generate more interrupts and
4886 * there are still possibilities of losing multiple frames
4887 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4888 * Given that the workaround still would not get correct
4889 * counter I don't think it's worth to implement it. So
4890 * ignore reading the counter on controllers that have the
4891 * silicon bug.
4892 */
4893 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4894 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4895 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4896 stats->InputDiscards +=
4897 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4898 stats->InputErrors +=
4899 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4900 stats->RecvThresholdHit +=
4901 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4902
4903 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4904 /*
4905 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4906 * frames, it's safe to disable workaround for DMA engine's
4907 * miscalculation of TXMBUF space.
4908 */
4909 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4910 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4911 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4912 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4913 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4914 else
4915 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4916 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4917 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4918 }
4919 }
4920 }
4921
4922 static void
bge_stats_clear_regs(struct bge_softc * sc)4923 bge_stats_clear_regs(struct bge_softc *sc)
4924 {
4925
4926 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4927 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4928 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4929 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4930 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4931 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4932 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4933 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4934 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4935 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4936 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4937 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4938 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4939
4940 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4941 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4942 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4943 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4944 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4945 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4946 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4947 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4948 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4949 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4950 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4951 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4952 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4953 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4954
4955 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4956 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4957 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4958 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4959 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4960 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4961 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4962 }
4963
4964 static void
bge_stats_update(struct bge_softc * sc)4965 bge_stats_update(struct bge_softc *sc)
4966 {
4967 if_t ifp;
4968 bus_size_t stats;
4969 uint32_t cnt; /* current register value */
4970
4971 ifp = sc->bge_ifp;
4972
4973 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4974
4975 #define READ_STAT(sc, stats, stat) \
4976 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4977
4978 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4979 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4980 sc->bge_tx_collisions = cnt;
4981
4982 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4983 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
4984 sc->bge_rx_nobds = cnt;
4985 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4986 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
4987 sc->bge_rx_inerrs = cnt;
4988 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4989 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
4990 sc->bge_rx_discards = cnt;
4991
4992 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4993 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
4994 sc->bge_tx_discards = cnt;
4995
4996 #undef READ_STAT
4997 }
4998
4999 /*
5000 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5001 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5002 * but when such padded frames employ the bge IP/TCP checksum offload,
5003 * the hardware checksum assist gives incorrect results (possibly
5004 * from incorporating its own padding into the UDP/TCP checksum; who knows).
5005 * If we pad such runts with zeros, the onboard checksum comes out correct.
5006 */
5007 static __inline int
bge_cksum_pad(struct mbuf * m)5008 bge_cksum_pad(struct mbuf *m)
5009 {
5010 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5011 struct mbuf *last;
5012
5013 /* If there's only the packet-header and we can pad there, use it. */
5014 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5015 M_TRAILINGSPACE(m) >= padlen) {
5016 last = m;
5017 } else {
5018 /*
5019 * Walk packet chain to find last mbuf. We will either
5020 * pad there, or append a new mbuf and pad it.
5021 */
5022 for (last = m; last->m_next != NULL; last = last->m_next);
5023 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5024 /* Allocate new empty mbuf, pad it. Compact later. */
5025 struct mbuf *n;
5026
5027 MGET(n, M_NOWAIT, MT_DATA);
5028 if (n == NULL)
5029 return (ENOBUFS);
5030 n->m_len = 0;
5031 last->m_next = n;
5032 last = n;
5033 }
5034 }
5035
5036 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5037 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5038 last->m_len += padlen;
5039 m->m_pkthdr.len += padlen;
5040
5041 return (0);
5042 }
5043
5044 static struct mbuf *
bge_check_short_dma(struct mbuf * m)5045 bge_check_short_dma(struct mbuf *m)
5046 {
5047 struct mbuf *n;
5048 int found;
5049
5050 /*
5051 * If device receive two back-to-back send BDs with less than
5052 * or equal to 8 total bytes then the device may hang. The two
5053 * back-to-back send BDs must in the same frame for this failure
5054 * to occur. Scan mbuf chains and see whether two back-to-back
5055 * send BDs are there. If this is the case, allocate new mbuf
5056 * and copy the frame to workaround the silicon bug.
5057 */
5058 for (n = m, found = 0; n != NULL; n = n->m_next) {
5059 if (n->m_len < 8) {
5060 found++;
5061 if (found > 1)
5062 break;
5063 continue;
5064 }
5065 found = 0;
5066 }
5067
5068 if (found > 1) {
5069 n = m_defrag(m, M_NOWAIT);
5070 if (n == NULL)
5071 m_freem(m);
5072 } else
5073 n = m;
5074 return (n);
5075 }
5076
5077 static struct mbuf *
bge_setup_tso(struct bge_softc * sc,struct mbuf * m,uint16_t * mss,uint16_t * flags)5078 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5079 uint16_t *flags)
5080 {
5081 struct ip *ip;
5082 struct tcphdr *tcp;
5083 struct mbuf *n;
5084 uint16_t hlen;
5085 uint32_t poff;
5086
5087 if (M_WRITABLE(m) == 0) {
5088 /* Get a writable copy. */
5089 n = m_dup(m, M_NOWAIT);
5090 m_freem(m);
5091 if (n == NULL)
5092 return (NULL);
5093 m = n;
5094 }
5095 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5096 if (m == NULL)
5097 return (NULL);
5098 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5099 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5100 m = m_pullup(m, poff + sizeof(struct tcphdr));
5101 if (m == NULL)
5102 return (NULL);
5103 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5104 m = m_pullup(m, poff + (tcp->th_off << 2));
5105 if (m == NULL)
5106 return (NULL);
5107 /*
5108 * It seems controller doesn't modify IP length and TCP pseudo
5109 * checksum. These checksum computed by upper stack should be 0.
5110 */
5111 *mss = m->m_pkthdr.tso_segsz;
5112 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5113 ip->ip_sum = 0;
5114 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5115 /* Clear pseudo checksum computed by TCP stack. */
5116 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5117 tcp->th_sum = 0;
5118 /*
5119 * Broadcom controllers uses different descriptor format for
5120 * TSO depending on ASIC revision. Due to TSO-capable firmware
5121 * license issue and lower performance of firmware based TSO
5122 * we only support hardware based TSO.
5123 */
5124 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5125 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5126 if (sc->bge_flags & BGE_FLAG_TSO3) {
5127 /*
5128 * For BCM5717 and newer controllers, hardware based TSO
5129 * uses the 14 lower bits of the bge_mss field to store the
5130 * MSS and the upper 2 bits to store the lowest 2 bits of
5131 * the IP/TCP header length. The upper 6 bits of the header
5132 * length are stored in the bge_flags[14:10,4] field. Jumbo
5133 * frames are supported.
5134 */
5135 *mss |= ((hlen & 0x3) << 14);
5136 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5137 } else {
5138 /*
5139 * For BCM5755 and newer controllers, hardware based TSO uses
5140 * the lower 11 bits to store the MSS and the upper 5 bits to
5141 * store the IP/TCP header length. Jumbo frames are not
5142 * supported.
5143 */
5144 *mss |= (hlen << 11);
5145 }
5146 return (m);
5147 }
5148
5149 /*
5150 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5151 * pointers to descriptors.
5152 */
5153 static int
bge_encap(struct bge_softc * sc,struct mbuf ** m_head,uint32_t * txidx)5154 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5155 {
5156 bus_dma_segment_t segs[BGE_NSEG_NEW];
5157 bus_dmamap_t map;
5158 struct bge_tx_bd *d;
5159 struct mbuf *m = *m_head;
5160 uint32_t idx = *txidx;
5161 uint16_t csum_flags, mss, vlan_tag;
5162 int nsegs, i, error;
5163
5164 csum_flags = 0;
5165 mss = 0;
5166 vlan_tag = 0;
5167 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5168 m->m_next != NULL) {
5169 *m_head = bge_check_short_dma(m);
5170 if (*m_head == NULL)
5171 return (ENOBUFS);
5172 m = *m_head;
5173 }
5174 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5175 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5176 if (*m_head == NULL)
5177 return (ENOBUFS);
5178 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5179 BGE_TXBDFLAG_CPU_POST_DMA;
5180 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5181 if (m->m_pkthdr.csum_flags & CSUM_IP)
5182 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5183 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5184 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5185 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5186 (error = bge_cksum_pad(m)) != 0) {
5187 m_freem(m);
5188 *m_head = NULL;
5189 return (error);
5190 }
5191 }
5192 }
5193
5194 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5195 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5196 m->m_pkthdr.len > ETHER_MAX_LEN)
5197 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5198 if (sc->bge_forced_collapse > 0 &&
5199 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5200 /*
5201 * Forcedly collapse mbuf chains to overcome hardware
5202 * limitation which only support a single outstanding
5203 * DMA read operation.
5204 */
5205 if (sc->bge_forced_collapse == 1)
5206 m = m_defrag(m, M_NOWAIT);
5207 else
5208 m = m_collapse(m, M_NOWAIT,
5209 sc->bge_forced_collapse);
5210 if (m == NULL)
5211 m = *m_head;
5212 *m_head = m;
5213 }
5214 }
5215
5216 map = sc->bge_cdata.bge_tx_dmamap[idx];
5217 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5218 &nsegs, BUS_DMA_NOWAIT);
5219 if (error == EFBIG) {
5220 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5221 if (m == NULL) {
5222 m_freem(*m_head);
5223 *m_head = NULL;
5224 return (ENOBUFS);
5225 }
5226 *m_head = m;
5227 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5228 m, segs, &nsegs, BUS_DMA_NOWAIT);
5229 if (error) {
5230 m_freem(m);
5231 *m_head = NULL;
5232 return (error);
5233 }
5234 } else if (error != 0)
5235 return (error);
5236
5237 /* Check if we have enough free send BDs. */
5238 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5239 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5240 return (ENOBUFS);
5241 }
5242
5243 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5244
5245 if (m->m_flags & M_VLANTAG) {
5246 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5247 vlan_tag = m->m_pkthdr.ether_vtag;
5248 }
5249
5250 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5251 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5252 /*
5253 * 5725 family of devices corrupts TSO packets when TSO DMA
5254 * buffers cross into regions which are within MSS bytes of
5255 * a 4GB boundary. If we encounter the condition, drop the
5256 * packet.
5257 */
5258 for (i = 0; ; i++) {
5259 d = &sc->bge_ldata.bge_tx_ring[idx];
5260 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5261 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5262 d->bge_len = segs[i].ds_len;
5263 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5264 d->bge_addr.bge_addr_lo)
5265 break;
5266 d->bge_flags = csum_flags;
5267 d->bge_vlan_tag = vlan_tag;
5268 d->bge_mss = mss;
5269 if (i == nsegs - 1)
5270 break;
5271 BGE_INC(idx, BGE_TX_RING_CNT);
5272 }
5273 if (i != nsegs - 1) {
5274 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5275 BUS_DMASYNC_POSTWRITE);
5276 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5277 m_freem(*m_head);
5278 *m_head = NULL;
5279 return (EIO);
5280 }
5281 } else {
5282 for (i = 0; ; i++) {
5283 d = &sc->bge_ldata.bge_tx_ring[idx];
5284 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5285 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5286 d->bge_len = segs[i].ds_len;
5287 d->bge_flags = csum_flags;
5288 d->bge_vlan_tag = vlan_tag;
5289 d->bge_mss = mss;
5290 if (i == nsegs - 1)
5291 break;
5292 BGE_INC(idx, BGE_TX_RING_CNT);
5293 }
5294 }
5295
5296 /* Mark the last segment as end of packet... */
5297 d->bge_flags |= BGE_TXBDFLAG_END;
5298
5299 /*
5300 * Insure that the map for this transmission
5301 * is placed at the array index of the last descriptor
5302 * in this chain.
5303 */
5304 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5305 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5306 sc->bge_cdata.bge_tx_chain[idx] = m;
5307 sc->bge_txcnt += nsegs;
5308
5309 BGE_INC(idx, BGE_TX_RING_CNT);
5310 *txidx = idx;
5311
5312 return (0);
5313 }
5314
5315 /*
5316 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5317 * to the mbuf data regions directly in the transmit descriptors.
5318 */
5319 static void
bge_start_locked(if_t ifp)5320 bge_start_locked(if_t ifp)
5321 {
5322 struct bge_softc *sc;
5323 struct mbuf *m_head;
5324 uint32_t prodidx;
5325 int count;
5326
5327 sc = if_getsoftc(ifp);
5328 BGE_LOCK_ASSERT(sc);
5329
5330 if (!sc->bge_link ||
5331 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5332 IFF_DRV_RUNNING)
5333 return;
5334
5335 prodidx = sc->bge_tx_prodidx;
5336
5337 for (count = 0; !if_sendq_empty(ifp);) {
5338 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5339 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5340 break;
5341 }
5342 m_head = if_dequeue(ifp);
5343 if (m_head == NULL)
5344 break;
5345
5346 /*
5347 * Pack the data into the transmit ring. If we
5348 * don't have room, set the OACTIVE flag and wait
5349 * for the NIC to drain the ring.
5350 */
5351 if (bge_encap(sc, &m_head, &prodidx)) {
5352 if (m_head == NULL)
5353 break;
5354 if_sendq_prepend(ifp, m_head);
5355 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5356 break;
5357 }
5358 ++count;
5359
5360 /*
5361 * If there's a BPF listener, bounce a copy of this frame
5362 * to him.
5363 */
5364 bpf_mtap_if(ifp, m_head);
5365 }
5366
5367 if (count > 0)
5368 bge_start_tx(sc, prodidx);
5369 }
5370
5371 static void
bge_start_tx(struct bge_softc * sc,uint32_t prodidx)5372 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5373 {
5374
5375 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5376 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5377 /* Transmit. */
5378 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5379 /* 5700 b2 errata */
5380 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5381 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5382
5383 sc->bge_tx_prodidx = prodidx;
5384
5385 /* Set a timeout in case the chip goes out to lunch. */
5386 sc->bge_timer = BGE_TX_TIMEOUT;
5387 }
5388
5389 /*
5390 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5391 * to the mbuf data regions directly in the transmit descriptors.
5392 */
5393 static void
bge_start(if_t ifp)5394 bge_start(if_t ifp)
5395 {
5396 struct bge_softc *sc;
5397
5398 sc = if_getsoftc(ifp);
5399 BGE_LOCK(sc);
5400 bge_start_locked(ifp);
5401 BGE_UNLOCK(sc);
5402 }
5403
5404 static void
bge_init_locked(struct bge_softc * sc)5405 bge_init_locked(struct bge_softc *sc)
5406 {
5407 if_t ifp;
5408 uint16_t *m;
5409 uint32_t mode;
5410
5411 BGE_LOCK_ASSERT(sc);
5412
5413 ifp = sc->bge_ifp;
5414
5415 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5416 return;
5417
5418 /* Cancel pending I/O and flush buffers. */
5419 bge_stop(sc);
5420
5421 bge_stop_fw(sc);
5422 bge_sig_pre_reset(sc, BGE_RESET_START);
5423 bge_reset(sc);
5424 bge_sig_legacy(sc, BGE_RESET_START);
5425 bge_sig_post_reset(sc, BGE_RESET_START);
5426
5427 bge_chipinit(sc);
5428
5429 /*
5430 * Init the various state machines, ring
5431 * control blocks and firmware.
5432 */
5433 if (bge_blockinit(sc)) {
5434 device_printf(sc->bge_dev, "initialization failure\n");
5435 return;
5436 }
5437
5438 ifp = sc->bge_ifp;
5439
5440 /* Specify MTU. */
5441 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5442 ETHER_HDR_LEN + ETHER_CRC_LEN +
5443 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5444
5445 /* Load our MAC address. */
5446 m = (uint16_t *)if_getlladdr(sc->bge_ifp);
5447 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5448 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5449
5450 /* Program promiscuous mode. */
5451 bge_setpromisc(sc);
5452
5453 /* Program multicast filter. */
5454 bge_setmulti(sc);
5455
5456 /* Program VLAN tag stripping. */
5457 bge_setvlan(sc);
5458
5459 /* Override UDP checksum offloading. */
5460 if (sc->bge_forced_udpcsum == 0)
5461 sc->bge_csum_features &= ~CSUM_UDP;
5462 else
5463 sc->bge_csum_features |= CSUM_UDP;
5464 if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5465 if_getcapenable(ifp) & IFCAP_TXCSUM) {
5466 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5467 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5468 }
5469
5470 /* Init RX ring. */
5471 if (bge_init_rx_ring_std(sc) != 0) {
5472 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5473 bge_stop(sc);
5474 return;
5475 }
5476
5477 /*
5478 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5479 * memory to insure that the chip has in fact read the first
5480 * entry of the ring.
5481 */
5482 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5483 uint32_t v, i;
5484 for (i = 0; i < 10; i++) {
5485 DELAY(20);
5486 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5487 if (v == (MCLBYTES - ETHER_ALIGN))
5488 break;
5489 }
5490 if (i == 10)
5491 device_printf (sc->bge_dev,
5492 "5705 A0 chip failed to load RX ring\n");
5493 }
5494
5495 /* Init jumbo RX ring. */
5496 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5497 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5498 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5499 if (bge_init_rx_ring_jumbo(sc) != 0) {
5500 device_printf(sc->bge_dev,
5501 "no memory for jumbo Rx buffers.\n");
5502 bge_stop(sc);
5503 return;
5504 }
5505 }
5506
5507 /* Init our RX return ring index. */
5508 sc->bge_rx_saved_considx = 0;
5509
5510 /* Init our RX/TX stat counters. */
5511 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5512
5513 /* Init TX ring. */
5514 bge_init_tx_ring(sc);
5515
5516 /* Enable TX MAC state machine lockup fix. */
5517 mode = CSR_READ_4(sc, BGE_TX_MODE);
5518 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5519 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5520 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5521 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5522 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5523 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5524 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5525 }
5526 /* Turn on transmitter. */
5527 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5528 DELAY(100);
5529
5530 /* Turn on receiver. */
5531 mode = CSR_READ_4(sc, BGE_RX_MODE);
5532 if (BGE_IS_5755_PLUS(sc))
5533 mode |= BGE_RXMODE_IPV6_ENABLE;
5534 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5535 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5536 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5537 DELAY(10);
5538
5539 /*
5540 * Set the number of good frames to receive after RX MBUF
5541 * Low Watermark has been reached. After the RX MAC receives
5542 * this number of frames, it will drop subsequent incoming
5543 * frames until the MBUF High Watermark is reached.
5544 */
5545 if (BGE_IS_57765_PLUS(sc))
5546 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5547 else
5548 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5549
5550 /* Clear MAC statistics. */
5551 if (BGE_IS_5705_PLUS(sc))
5552 bge_stats_clear_regs(sc);
5553
5554 /* Tell firmware we're alive. */
5555 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5556
5557 #ifdef DEVICE_POLLING
5558 /* Disable interrupts if we are polling. */
5559 if (if_getcapenable(ifp) & IFCAP_POLLING) {
5560 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5561 BGE_PCIMISCCTL_MASK_PCI_INTR);
5562 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5563 } else
5564 #endif
5565
5566 /* Enable host interrupts. */
5567 {
5568 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5569 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5570 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5571 }
5572
5573 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5574 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5575
5576 bge_ifmedia_upd_locked(ifp);
5577
5578 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5579 }
5580
5581 static void
bge_init(void * xsc)5582 bge_init(void *xsc)
5583 {
5584 struct bge_softc *sc = xsc;
5585
5586 BGE_LOCK(sc);
5587 bge_init_locked(sc);
5588 BGE_UNLOCK(sc);
5589 }
5590
5591 /*
5592 * Set media options.
5593 */
5594 static int
bge_ifmedia_upd(if_t ifp)5595 bge_ifmedia_upd(if_t ifp)
5596 {
5597 struct bge_softc *sc = if_getsoftc(ifp);
5598 int res;
5599
5600 BGE_LOCK(sc);
5601 res = bge_ifmedia_upd_locked(ifp);
5602 BGE_UNLOCK(sc);
5603
5604 return (res);
5605 }
5606
5607 static int
bge_ifmedia_upd_locked(if_t ifp)5608 bge_ifmedia_upd_locked(if_t ifp)
5609 {
5610 struct bge_softc *sc = if_getsoftc(ifp);
5611 struct mii_data *mii;
5612 struct mii_softc *miisc;
5613 struct ifmedia *ifm;
5614
5615 BGE_LOCK_ASSERT(sc);
5616
5617 ifm = &sc->bge_ifmedia;
5618
5619 /* If this is a 1000baseX NIC, enable the TBI port. */
5620 if (sc->bge_flags & BGE_FLAG_TBI) {
5621 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5622 return (EINVAL);
5623 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5624 case IFM_AUTO:
5625 /*
5626 * The BCM5704 ASIC appears to have a special
5627 * mechanism for programming the autoneg
5628 * advertisement registers in TBI mode.
5629 */
5630 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5631 uint32_t sgdig;
5632 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5633 if (sgdig & BGE_SGDIGSTS_DONE) {
5634 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5635 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5636 sgdig |= BGE_SGDIGCFG_AUTO |
5637 BGE_SGDIGCFG_PAUSE_CAP |
5638 BGE_SGDIGCFG_ASYM_PAUSE;
5639 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5640 sgdig | BGE_SGDIGCFG_SEND);
5641 DELAY(5);
5642 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5643 }
5644 }
5645 break;
5646 case IFM_1000_SX:
5647 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5648 BGE_CLRBIT(sc, BGE_MAC_MODE,
5649 BGE_MACMODE_HALF_DUPLEX);
5650 } else {
5651 BGE_SETBIT(sc, BGE_MAC_MODE,
5652 BGE_MACMODE_HALF_DUPLEX);
5653 }
5654 DELAY(40);
5655 break;
5656 default:
5657 return (EINVAL);
5658 }
5659 return (0);
5660 }
5661
5662 sc->bge_link_evt++;
5663 mii = device_get_softc(sc->bge_miibus);
5664 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5665 PHY_RESET(miisc);
5666 mii_mediachg(mii);
5667
5668 /*
5669 * Force an interrupt so that we will call bge_link_upd
5670 * if needed and clear any pending link state attention.
5671 * Without this we are not getting any further interrupts
5672 * for link state changes and thus will not UP the link and
5673 * not be able to send in bge_start_locked. The only
5674 * way to get things working was to receive a packet and
5675 * get an RX intr.
5676 * bge_tick should help for fiber cards and we might not
5677 * need to do this here if BGE_FLAG_TBI is set but as
5678 * we poll for fiber anyway it should not harm.
5679 */
5680 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5681 sc->bge_flags & BGE_FLAG_5788)
5682 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5683 else
5684 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5685
5686 return (0);
5687 }
5688
5689 /*
5690 * Report current media status.
5691 */
5692 static void
bge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)5693 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5694 {
5695 struct bge_softc *sc = if_getsoftc(ifp);
5696 struct mii_data *mii;
5697
5698 BGE_LOCK(sc);
5699
5700 if ((if_getflags(ifp) & IFF_UP) == 0) {
5701 BGE_UNLOCK(sc);
5702 return;
5703 }
5704 if (sc->bge_flags & BGE_FLAG_TBI) {
5705 ifmr->ifm_status = IFM_AVALID;
5706 ifmr->ifm_active = IFM_ETHER;
5707 if (CSR_READ_4(sc, BGE_MAC_STS) &
5708 BGE_MACSTAT_TBI_PCS_SYNCHED)
5709 ifmr->ifm_status |= IFM_ACTIVE;
5710 else {
5711 ifmr->ifm_active |= IFM_NONE;
5712 BGE_UNLOCK(sc);
5713 return;
5714 }
5715 ifmr->ifm_active |= IFM_1000_SX;
5716 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5717 ifmr->ifm_active |= IFM_HDX;
5718 else
5719 ifmr->ifm_active |= IFM_FDX;
5720 BGE_UNLOCK(sc);
5721 return;
5722 }
5723
5724 mii = device_get_softc(sc->bge_miibus);
5725 mii_pollstat(mii);
5726 ifmr->ifm_active = mii->mii_media_active;
5727 ifmr->ifm_status = mii->mii_media_status;
5728
5729 BGE_UNLOCK(sc);
5730 }
5731
5732 static int
bge_ioctl(if_t ifp,u_long command,caddr_t data)5733 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5734 {
5735 struct bge_softc *sc = if_getsoftc(ifp);
5736 struct ifreq *ifr = (struct ifreq *) data;
5737 struct mii_data *mii;
5738 int flags, mask, error = 0;
5739
5740 switch (command) {
5741 case SIOCSIFMTU:
5742 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5743 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5744 if (ifr->ifr_mtu < ETHERMIN ||
5745 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5746 error = EINVAL;
5747 break;
5748 }
5749 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5750 error = EINVAL;
5751 break;
5752 }
5753 BGE_LOCK(sc);
5754 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5755 if_setmtu(ifp, ifr->ifr_mtu);
5756 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5757 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5758 bge_init_locked(sc);
5759 }
5760 }
5761 BGE_UNLOCK(sc);
5762 break;
5763 case SIOCSIFFLAGS:
5764 BGE_LOCK(sc);
5765 if (if_getflags(ifp) & IFF_UP) {
5766 /*
5767 * If only the state of the PROMISC flag changed,
5768 * then just use the 'set promisc mode' command
5769 * instead of reinitializing the entire NIC. Doing
5770 * a full re-init means reloading the firmware and
5771 * waiting for it to start up, which may take a
5772 * second or two. Similarly for ALLMULTI.
5773 */
5774 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5775 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5776 if (flags & IFF_PROMISC)
5777 bge_setpromisc(sc);
5778 if (flags & IFF_ALLMULTI)
5779 bge_setmulti(sc);
5780 } else
5781 bge_init_locked(sc);
5782 } else {
5783 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5784 bge_stop(sc);
5785 }
5786 }
5787 sc->bge_if_flags = if_getflags(ifp);
5788 BGE_UNLOCK(sc);
5789 error = 0;
5790 break;
5791 case SIOCADDMULTI:
5792 case SIOCDELMULTI:
5793 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5794 BGE_LOCK(sc);
5795 bge_setmulti(sc);
5796 BGE_UNLOCK(sc);
5797 error = 0;
5798 }
5799 break;
5800 case SIOCSIFMEDIA:
5801 case SIOCGIFMEDIA:
5802 if (sc->bge_flags & BGE_FLAG_TBI) {
5803 error = ifmedia_ioctl(ifp, ifr,
5804 &sc->bge_ifmedia, command);
5805 } else {
5806 mii = device_get_softc(sc->bge_miibus);
5807 error = ifmedia_ioctl(ifp, ifr,
5808 &mii->mii_media, command);
5809 }
5810 break;
5811 case SIOCSIFCAP:
5812 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5813 #ifdef DEVICE_POLLING
5814 if (mask & IFCAP_POLLING) {
5815 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5816 error = ether_poll_register(bge_poll, ifp);
5817 if (error)
5818 return (error);
5819 BGE_LOCK(sc);
5820 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5821 BGE_PCIMISCCTL_MASK_PCI_INTR);
5822 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5823 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5824 BGE_UNLOCK(sc);
5825 } else {
5826 error = ether_poll_deregister(ifp);
5827 /* Enable interrupt even in error case */
5828 BGE_LOCK(sc);
5829 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5830 BGE_PCIMISCCTL_MASK_PCI_INTR);
5831 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5832 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5833 BGE_UNLOCK(sc);
5834 }
5835 }
5836 #endif
5837 if ((mask & IFCAP_TXCSUM) != 0 &&
5838 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5839 if_togglecapenable(ifp, IFCAP_TXCSUM);
5840 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5841 if_sethwassistbits(ifp,
5842 sc->bge_csum_features, 0);
5843 else
5844 if_sethwassistbits(ifp, 0,
5845 sc->bge_csum_features);
5846 }
5847
5848 if ((mask & IFCAP_RXCSUM) != 0 &&
5849 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5850 if_togglecapenable(ifp, IFCAP_RXCSUM);
5851
5852 if ((mask & IFCAP_TSO4) != 0 &&
5853 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5854 if_togglecapenable(ifp, IFCAP_TSO4);
5855 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5856 if_sethwassistbits(ifp, CSUM_TSO, 0);
5857 else
5858 if_sethwassistbits(ifp, 0, CSUM_TSO);
5859 }
5860
5861 if (mask & IFCAP_VLAN_MTU) {
5862 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5863 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5864 bge_init(sc);
5865 }
5866
5867 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5868 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5869 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5870 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5871 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5872 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5873 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5874 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5875 BGE_LOCK(sc);
5876 bge_setvlan(sc);
5877 BGE_UNLOCK(sc);
5878 }
5879 #ifdef VLAN_CAPABILITIES
5880 if_vlancap(ifp);
5881 #endif
5882 break;
5883 default:
5884 error = ether_ioctl(ifp, command, data);
5885 break;
5886 }
5887
5888 return (error);
5889 }
5890
5891 static void
bge_watchdog(struct bge_softc * sc)5892 bge_watchdog(struct bge_softc *sc)
5893 {
5894 if_t ifp;
5895 uint32_t status;
5896
5897 BGE_LOCK_ASSERT(sc);
5898
5899 if (sc->bge_timer == 0 || --sc->bge_timer)
5900 return;
5901
5902 /* If pause frames are active then don't reset the hardware. */
5903 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5904 status = CSR_READ_4(sc, BGE_RX_STS);
5905 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5906 /*
5907 * If link partner has us in XOFF state then wait for
5908 * the condition to clear.
5909 */
5910 CSR_WRITE_4(sc, BGE_RX_STS, status);
5911 sc->bge_timer = BGE_TX_TIMEOUT;
5912 return;
5913 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5914 (status & BGE_RXSTAT_RCVD_XON) != 0) {
5915 /*
5916 * If link partner has us in XOFF state then wait for
5917 * the condition to clear.
5918 */
5919 CSR_WRITE_4(sc, BGE_RX_STS, status);
5920 sc->bge_timer = BGE_TX_TIMEOUT;
5921 return;
5922 }
5923 /*
5924 * Any other condition is unexpected and the controller
5925 * should be reset.
5926 */
5927 }
5928
5929 ifp = sc->bge_ifp;
5930
5931 if_printf(ifp, "watchdog timeout -- resetting\n");
5932
5933 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5934 bge_init_locked(sc);
5935
5936 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5937 }
5938
5939 static void
bge_stop_block(struct bge_softc * sc,bus_size_t reg,uint32_t bit)5940 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5941 {
5942 int i;
5943
5944 BGE_CLRBIT(sc, reg, bit);
5945
5946 for (i = 0; i < BGE_TIMEOUT; i++) {
5947 if ((CSR_READ_4(sc, reg) & bit) == 0)
5948 return;
5949 DELAY(100);
5950 }
5951 }
5952
5953 /*
5954 * Stop the adapter and free any mbufs allocated to the
5955 * RX and TX lists.
5956 */
5957 static void
bge_stop(struct bge_softc * sc)5958 bge_stop(struct bge_softc *sc)
5959 {
5960 if_t ifp;
5961
5962 BGE_LOCK_ASSERT(sc);
5963
5964 ifp = sc->bge_ifp;
5965
5966 callout_stop(&sc->bge_stat_ch);
5967
5968 /* Disable host interrupts. */
5969 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5970 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5971
5972 /*
5973 * Tell firmware we're shutting down.
5974 */
5975 bge_stop_fw(sc);
5976 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5977
5978 /*
5979 * Disable all of the receiver blocks.
5980 */
5981 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5982 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5983 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5984 if (BGE_IS_5700_FAMILY(sc))
5985 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5986 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5987 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5988 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5989
5990 /*
5991 * Disable all of the transmit blocks.
5992 */
5993 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5994 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5995 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5996 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5997 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5998 if (BGE_IS_5700_FAMILY(sc))
5999 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6000 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6001
6002 /*
6003 * Shut down all of the memory managers and related
6004 * state machines.
6005 */
6006 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6007 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6008 if (BGE_IS_5700_FAMILY(sc))
6009 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6010
6011 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6012 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6013 if (!(BGE_IS_5705_PLUS(sc))) {
6014 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6015 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6016 }
6017 /* Update MAC statistics. */
6018 if (BGE_IS_5705_PLUS(sc))
6019 bge_stats_update_regs(sc);
6020
6021 bge_reset(sc);
6022 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6023 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6024
6025 /*
6026 * Keep the ASF firmware running if up.
6027 */
6028 if (sc->bge_asf_mode & ASF_STACKUP)
6029 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6030 else
6031 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6032
6033 /* Free the RX lists. */
6034 bge_free_rx_ring_std(sc);
6035
6036 /* Free jumbo RX list. */
6037 if (BGE_IS_JUMBO_CAPABLE(sc))
6038 bge_free_rx_ring_jumbo(sc);
6039
6040 /* Free TX buffers. */
6041 bge_free_tx_ring(sc);
6042
6043 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6044
6045 /* Clear MAC's link state (PHY may still have link UP). */
6046 if (bootverbose && sc->bge_link)
6047 if_printf(sc->bge_ifp, "link DOWN\n");
6048 sc->bge_link = 0;
6049
6050 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6051 }
6052
6053 /*
6054 * Stop all chip I/O so that the kernel's probe routines don't
6055 * get confused by errant DMAs when rebooting.
6056 */
6057 static int
bge_shutdown(device_t dev)6058 bge_shutdown(device_t dev)
6059 {
6060 struct bge_softc *sc;
6061
6062 sc = device_get_softc(dev);
6063 BGE_LOCK(sc);
6064 bge_stop(sc);
6065 BGE_UNLOCK(sc);
6066
6067 return (0);
6068 }
6069
6070 static int
bge_suspend(device_t dev)6071 bge_suspend(device_t dev)
6072 {
6073 struct bge_softc *sc;
6074
6075 sc = device_get_softc(dev);
6076 BGE_LOCK(sc);
6077 bge_stop(sc);
6078 BGE_UNLOCK(sc);
6079
6080 return (0);
6081 }
6082
6083 static int
bge_resume(device_t dev)6084 bge_resume(device_t dev)
6085 {
6086 struct bge_softc *sc;
6087 if_t ifp;
6088
6089 sc = device_get_softc(dev);
6090 BGE_LOCK(sc);
6091 ifp = sc->bge_ifp;
6092 if (if_getflags(ifp) & IFF_UP) {
6093 bge_init_locked(sc);
6094 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6095 bge_start_locked(ifp);
6096 }
6097 BGE_UNLOCK(sc);
6098
6099 return (0);
6100 }
6101
6102 static void
bge_link_upd(struct bge_softc * sc)6103 bge_link_upd(struct bge_softc *sc)
6104 {
6105 struct mii_data *mii;
6106 uint32_t link, status;
6107
6108 BGE_LOCK_ASSERT(sc);
6109
6110 /* Clear 'pending link event' flag. */
6111 sc->bge_link_evt = 0;
6112
6113 /*
6114 * Process link state changes.
6115 * Grrr. The link status word in the status block does
6116 * not work correctly on the BCM5700 rev AX and BX chips,
6117 * according to all available information. Hence, we have
6118 * to enable MII interrupts in order to properly obtain
6119 * async link changes. Unfortunately, this also means that
6120 * we have to read the MAC status register to detect link
6121 * changes, thereby adding an additional register access to
6122 * the interrupt handler.
6123 *
6124 * XXX: perhaps link state detection procedure used for
6125 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6126 */
6127
6128 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6129 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6130 status = CSR_READ_4(sc, BGE_MAC_STS);
6131 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6132 mii = device_get_softc(sc->bge_miibus);
6133 mii_pollstat(mii);
6134 if (!sc->bge_link &&
6135 mii->mii_media_status & IFM_ACTIVE &&
6136 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6137 sc->bge_link++;
6138 if (bootverbose)
6139 if_printf(sc->bge_ifp, "link UP\n");
6140 } else if (sc->bge_link &&
6141 (!(mii->mii_media_status & IFM_ACTIVE) ||
6142 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6143 sc->bge_link = 0;
6144 if (bootverbose)
6145 if_printf(sc->bge_ifp, "link DOWN\n");
6146 }
6147
6148 /* Clear the interrupt. */
6149 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6150 BGE_EVTENB_MI_INTERRUPT);
6151 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6152 BRGPHY_MII_ISR);
6153 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6154 BRGPHY_MII_IMR, BRGPHY_INTRS);
6155 }
6156 return;
6157 }
6158
6159 if (sc->bge_flags & BGE_FLAG_TBI) {
6160 status = CSR_READ_4(sc, BGE_MAC_STS);
6161 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6162 if (!sc->bge_link) {
6163 sc->bge_link++;
6164 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6165 BGE_CLRBIT(sc, BGE_MAC_MODE,
6166 BGE_MACMODE_TBI_SEND_CFGS);
6167 DELAY(40);
6168 }
6169 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6170 if (bootverbose)
6171 if_printf(sc->bge_ifp, "link UP\n");
6172 if_link_state_change(sc->bge_ifp,
6173 LINK_STATE_UP);
6174 }
6175 } else if (sc->bge_link) {
6176 sc->bge_link = 0;
6177 if (bootverbose)
6178 if_printf(sc->bge_ifp, "link DOWN\n");
6179 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6180 }
6181 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6182 /*
6183 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6184 * in status word always set. Workaround this bug by reading
6185 * PHY link status directly.
6186 */
6187 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6188
6189 if (link != sc->bge_link ||
6190 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6191 mii = device_get_softc(sc->bge_miibus);
6192 mii_pollstat(mii);
6193 if (!sc->bge_link &&
6194 mii->mii_media_status & IFM_ACTIVE &&
6195 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6196 sc->bge_link++;
6197 if (bootverbose)
6198 if_printf(sc->bge_ifp, "link UP\n");
6199 } else if (sc->bge_link &&
6200 (!(mii->mii_media_status & IFM_ACTIVE) ||
6201 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6202 sc->bge_link = 0;
6203 if (bootverbose)
6204 if_printf(sc->bge_ifp, "link DOWN\n");
6205 }
6206 }
6207 } else {
6208 /*
6209 * For controllers that call mii_tick, we have to poll
6210 * link status.
6211 */
6212 mii = device_get_softc(sc->bge_miibus);
6213 mii_pollstat(mii);
6214 bge_miibus_statchg(sc->bge_dev);
6215 }
6216
6217 /* Disable MAC attention when link is up. */
6218 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6219 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6220 BGE_MACSTAT_LINK_CHANGED);
6221 }
6222
6223 static void
bge_add_sysctls(struct bge_softc * sc)6224 bge_add_sysctls(struct bge_softc *sc)
6225 {
6226 struct sysctl_ctx_list *ctx;
6227 struct sysctl_oid_list *children;
6228
6229 ctx = device_get_sysctl_ctx(sc->bge_dev);
6230 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6231
6232 #ifdef BGE_REGISTER_DEBUG
6233 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6234 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6235 bge_sysctl_debug_info, "I", "Debug Information");
6236
6237 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6238 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6239 bge_sysctl_reg_read, "I", "MAC Register Read");
6240
6241 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6242 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6243 bge_sysctl_ape_read, "I", "APE Register Read");
6244
6245 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6246 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6247 bge_sysctl_mem_read, "I", "Memory Read");
6248
6249 #endif
6250
6251 /*
6252 * A common design characteristic for many Broadcom client controllers
6253 * is that they only support a single outstanding DMA read operation
6254 * on the PCIe bus. This means that it will take twice as long to fetch
6255 * a TX frame that is split into header and payload buffers as it does
6256 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6257 * these controllers, coalescing buffers to reduce the number of memory
6258 * reads is effective way to get maximum performance(about 940Mbps).
6259 * Without collapsing TX buffers the maximum TCP bulk transfer
6260 * performance is about 850Mbps. However forcing coalescing mbufs
6261 * consumes a lot of CPU cycles, so leave it off by default.
6262 */
6263 sc->bge_forced_collapse = 0;
6264 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6265 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6266 "Number of fragmented TX buffers of a frame allowed before "
6267 "forced collapsing");
6268
6269 sc->bge_msi = 1;
6270 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6271 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6272
6273 /*
6274 * It seems all Broadcom controllers have a bug that can generate UDP
6275 * datagrams with checksum value 0 when TX UDP checksum offloading is
6276 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6277 * Even though the probability of generating such UDP datagrams is
6278 * low, I don't want to see FreeBSD boxes to inject such datagrams
6279 * into network so disable UDP checksum offloading by default. Users
6280 * still override this behavior by setting a sysctl variable,
6281 * dev.bge.0.forced_udpcsum.
6282 */
6283 sc->bge_forced_udpcsum = 0;
6284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6285 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6286 "Enable UDP checksum offloading even if controller can "
6287 "generate UDP checksum value 0");
6288
6289 if (BGE_IS_5705_PLUS(sc))
6290 bge_add_sysctl_stats_regs(sc, ctx, children);
6291 else
6292 bge_add_sysctl_stats(sc, ctx, children);
6293 }
6294
6295 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6296 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, \
6297 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \
6298 offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", desc)
6299
6300 static void
bge_add_sysctl_stats(struct bge_softc * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent)6301 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6302 struct sysctl_oid_list *parent)
6303 {
6304 struct sysctl_oid *tree;
6305 struct sysctl_oid_list *children, *schildren;
6306
6307 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6308 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6309 schildren = children = SYSCTL_CHILDREN(tree);
6310 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6311 children, COSFramesDroppedDueToFilters,
6312 "FramesDroppedDueToFilters");
6313 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6314 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6315 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6316 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6317 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6318 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6319 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6320 children, ifInDiscards, "InputDiscards");
6321 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6322 children, ifInErrors, "InputErrors");
6323 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6324 children, nicRecvThresholdHit, "RecvThresholdHit");
6325 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6326 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6327 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6328 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6329 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6330 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6331 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6332 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6333 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6334 children, nicRingStatusUpdate, "RingStatusUpdate");
6335 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6336 children, nicInterrupts, "Interrupts");
6337 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6338 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6339 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6340 children, nicSendThresholdHit, "SendThresholdHit");
6341
6342 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx",
6343 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6344 children = SYSCTL_CHILDREN(tree);
6345 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6346 children, rxstats.ifHCInOctets, "ifHCInOctets");
6347 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6348 children, rxstats.etherStatsFragments, "Fragments");
6349 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6350 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6351 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6352 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6353 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6354 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6355 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6356 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6357 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6358 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6359 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6360 children, rxstats.xoffPauseFramesReceived,
6361 "xoffPauseFramesReceived");
6362 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6363 children, rxstats.macControlFramesReceived,
6364 "ControlFramesReceived");
6365 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6366 children, rxstats.xoffStateEntered, "xoffStateEntered");
6367 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6368 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6369 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6370 children, rxstats.etherStatsJabbers, "Jabbers");
6371 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6372 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6373 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6374 children, rxstats.inRangeLengthError, "inRangeLengthError");
6375 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6376 children, rxstats.outRangeLengthError, "outRangeLengthError");
6377
6378 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx",
6379 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6380 children = SYSCTL_CHILDREN(tree);
6381 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6382 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6383 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6384 children, txstats.etherStatsCollisions, "Collisions");
6385 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6386 children, txstats.outXonSent, "XonSent");
6387 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6388 children, txstats.outXoffSent, "XoffSent");
6389 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6390 children, txstats.flowControlDone, "flowControlDone");
6391 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6392 children, txstats.dot3StatsInternalMacTransmitErrors,
6393 "InternalMacTransmitErrors");
6394 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6395 children, txstats.dot3StatsSingleCollisionFrames,
6396 "SingleCollisionFrames");
6397 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6398 children, txstats.dot3StatsMultipleCollisionFrames,
6399 "MultipleCollisionFrames");
6400 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6401 children, txstats.dot3StatsDeferredTransmissions,
6402 "DeferredTransmissions");
6403 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6404 children, txstats.dot3StatsExcessiveCollisions,
6405 "ExcessiveCollisions");
6406 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6407 children, txstats.dot3StatsLateCollisions,
6408 "LateCollisions");
6409 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6410 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6411 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6412 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6413 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6414 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6415 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6416 children, txstats.dot3StatsCarrierSenseErrors,
6417 "CarrierSenseErrors");
6418 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6419 children, txstats.ifOutDiscards, "Discards");
6420 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6421 children, txstats.ifOutErrors, "Errors");
6422 }
6423
6424 #undef BGE_SYSCTL_STAT
6425
6426 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6427 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6428
6429 static void
bge_add_sysctl_stats_regs(struct bge_softc * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent)6430 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6431 struct sysctl_oid_list *parent)
6432 {
6433 struct sysctl_oid *tree;
6434 struct sysctl_oid_list *child, *schild;
6435 struct bge_mac_stats *stats;
6436
6437 stats = &sc->bge_mac_stats;
6438 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6439 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6440 schild = child = SYSCTL_CHILDREN(tree);
6441 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6442 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6443 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6444 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6445 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6446 &stats->DmaWriteHighPriQueueFull,
6447 "NIC DMA Write High Priority Queue Full");
6448 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6449 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6450 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6451 &stats->InputDiscards, "Discarded Input Frames");
6452 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6453 &stats->InputErrors, "Input Errors");
6454 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6455 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6456
6457 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
6458 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6459 child = SYSCTL_CHILDREN(tree);
6460 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6461 &stats->ifHCInOctets, "Inbound Octets");
6462 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6463 &stats->etherStatsFragments, "Fragments");
6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6465 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6467 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6469 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6470 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6471 &stats->dot3StatsFCSErrors, "FCS Errors");
6472 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6473 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6474 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6475 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6477 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6478 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6479 &stats->macControlFramesReceived, "MAC Control Frames Received");
6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6481 &stats->xoffStateEntered, "XOFF State Entered");
6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6483 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6485 &stats->etherStatsJabbers, "Jabbers");
6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6487 &stats->etherStatsUndersizePkts, "Undersized Packets");
6488
6489 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
6490 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6491 child = SYSCTL_CHILDREN(tree);
6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6493 &stats->ifHCOutOctets, "Outbound Octets");
6494 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6495 &stats->etherStatsCollisions, "TX Collisions");
6496 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6497 &stats->outXonSent, "XON Sent");
6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6499 &stats->outXoffSent, "XOFF Sent");
6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6501 &stats->dot3StatsInternalMacTransmitErrors,
6502 "Internal MAC TX Errors");
6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6504 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6506 &stats->dot3StatsMultipleCollisionFrames,
6507 "Multiple Collision Frames");
6508 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6509 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6510 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6511 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6513 &stats->dot3StatsLateCollisions, "Late Collisions");
6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6515 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6516 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6517 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6518 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6519 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6520 }
6521
6522 #undef BGE_SYSCTL_STAT_ADD64
6523
6524 static int
bge_sysctl_stats(SYSCTL_HANDLER_ARGS)6525 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6526 {
6527 struct bge_softc *sc;
6528 uint32_t result;
6529 int offset;
6530
6531 sc = (struct bge_softc *)arg1;
6532 offset = arg2;
6533 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6534 offsetof(bge_hostaddr, bge_addr_lo));
6535 return (sysctl_handle_int(oidp, &result, 0, req));
6536 }
6537
6538 #ifdef BGE_REGISTER_DEBUG
6539 static int
bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)6540 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6541 {
6542 struct bge_softc *sc;
6543 uint16_t *sbdata;
6544 int error, result, sbsz;
6545 int i, j;
6546
6547 result = -1;
6548 error = sysctl_handle_int(oidp, &result, 0, req);
6549 if (error || (req->newptr == NULL))
6550 return (error);
6551
6552 if (result == 1) {
6553 sc = (struct bge_softc *)arg1;
6554
6555 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6556 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6557 sbsz = BGE_STATUS_BLK_SZ;
6558 else
6559 sbsz = 32;
6560 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6561 printf("Status Block:\n");
6562 BGE_LOCK(sc);
6563 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6564 sc->bge_cdata.bge_status_map,
6565 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6566 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6567 printf("%06x:", i);
6568 for (j = 0; j < 8; j++)
6569 printf(" %04x", sbdata[i++]);
6570 printf("\n");
6571 }
6572
6573 printf("Registers:\n");
6574 for (i = 0x800; i < 0xA00; ) {
6575 printf("%06x:", i);
6576 for (j = 0; j < 8; j++) {
6577 printf(" %08x", CSR_READ_4(sc, i));
6578 i += 4;
6579 }
6580 printf("\n");
6581 }
6582 BGE_UNLOCK(sc);
6583
6584 printf("Hardware Flags:\n");
6585 if (BGE_IS_5717_PLUS(sc))
6586 printf(" - 5717 Plus\n");
6587 if (BGE_IS_5755_PLUS(sc))
6588 printf(" - 5755 Plus\n");
6589 if (BGE_IS_575X_PLUS(sc))
6590 printf(" - 575X Plus\n");
6591 if (BGE_IS_5705_PLUS(sc))
6592 printf(" - 5705 Plus\n");
6593 if (BGE_IS_5714_FAMILY(sc))
6594 printf(" - 5714 Family\n");
6595 if (BGE_IS_5700_FAMILY(sc))
6596 printf(" - 5700 Family\n");
6597 if (sc->bge_flags & BGE_FLAG_JUMBO)
6598 printf(" - Supports Jumbo Frames\n");
6599 if (sc->bge_flags & BGE_FLAG_PCIX)
6600 printf(" - PCI-X Bus\n");
6601 if (sc->bge_flags & BGE_FLAG_PCIE)
6602 printf(" - PCI Express Bus\n");
6603 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6604 printf(" - No 3 LEDs\n");
6605 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6606 printf(" - RX Alignment Bug\n");
6607 }
6608
6609 return (error);
6610 }
6611
6612 static int
bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)6613 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6614 {
6615 struct bge_softc *sc;
6616 int error;
6617 uint16_t result;
6618 uint32_t val;
6619
6620 result = -1;
6621 error = sysctl_handle_int(oidp, &result, 0, req);
6622 if (error || (req->newptr == NULL))
6623 return (error);
6624
6625 if (result < 0x8000) {
6626 sc = (struct bge_softc *)arg1;
6627 val = CSR_READ_4(sc, result);
6628 printf("reg 0x%06X = 0x%08X\n", result, val);
6629 }
6630
6631 return (error);
6632 }
6633
6634 static int
bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)6635 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6636 {
6637 struct bge_softc *sc;
6638 int error;
6639 uint16_t result;
6640 uint32_t val;
6641
6642 result = -1;
6643 error = sysctl_handle_int(oidp, &result, 0, req);
6644 if (error || (req->newptr == NULL))
6645 return (error);
6646
6647 if (result < 0x8000) {
6648 sc = (struct bge_softc *)arg1;
6649 val = APE_READ_4(sc, result);
6650 printf("reg 0x%06X = 0x%08X\n", result, val);
6651 }
6652
6653 return (error);
6654 }
6655
6656 static int
bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)6657 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6658 {
6659 struct bge_softc *sc;
6660 int error;
6661 uint16_t result;
6662 uint32_t val;
6663
6664 result = -1;
6665 error = sysctl_handle_int(oidp, &result, 0, req);
6666 if (error || (req->newptr == NULL))
6667 return (error);
6668
6669 if (result < 0x8000) {
6670 sc = (struct bge_softc *)arg1;
6671 val = bge_readmem_ind(sc, result);
6672 printf("mem 0x%06X = 0x%08X\n", result, val);
6673 }
6674
6675 return (error);
6676 }
6677 #endif
6678
6679 static int
bge_get_eaddr_fw(struct bge_softc * sc,uint8_t ether_addr[])6680 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6681 {
6682 return (1);
6683 }
6684
6685 static int
bge_get_eaddr_mem(struct bge_softc * sc,uint8_t ether_addr[])6686 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6687 {
6688 uint32_t mac_addr;
6689
6690 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6691 if ((mac_addr >> 16) == 0x484b) {
6692 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6693 ether_addr[1] = (uint8_t)mac_addr;
6694 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6695 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6696 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6697 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6698 ether_addr[5] = (uint8_t)mac_addr;
6699 return (0);
6700 }
6701 return (1);
6702 }
6703
6704 static int
bge_get_eaddr_nvram(struct bge_softc * sc,uint8_t ether_addr[])6705 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6706 {
6707 int mac_offset = BGE_EE_MAC_OFFSET;
6708
6709 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6710 mac_offset = BGE_EE_MAC_OFFSET_5906;
6711
6712 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6713 ETHER_ADDR_LEN));
6714 }
6715
6716 static int
bge_get_eaddr_eeprom(struct bge_softc * sc,uint8_t ether_addr[])6717 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6718 {
6719
6720 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6721 return (1);
6722
6723 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6724 ETHER_ADDR_LEN));
6725 }
6726
6727 static int
bge_get_eaddr(struct bge_softc * sc,uint8_t eaddr[])6728 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6729 {
6730 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6731 /* NOTE: Order is critical */
6732 bge_get_eaddr_fw,
6733 bge_get_eaddr_mem,
6734 bge_get_eaddr_nvram,
6735 bge_get_eaddr_eeprom,
6736 NULL
6737 };
6738 const bge_eaddr_fcn_t *func;
6739
6740 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6741 if ((*func)(sc, eaddr) == 0)
6742 break;
6743 }
6744 return (*func == NULL ? ENXIO : 0);
6745 }
6746
6747 static uint64_t
bge_get_counter(if_t ifp,ift_counter cnt)6748 bge_get_counter(if_t ifp, ift_counter cnt)
6749 {
6750 struct bge_softc *sc;
6751 struct bge_mac_stats *stats;
6752
6753 sc = if_getsoftc(ifp);
6754 if (!BGE_IS_5705_PLUS(sc))
6755 return (if_get_counter_default(ifp, cnt));
6756 stats = &sc->bge_mac_stats;
6757
6758 switch (cnt) {
6759 case IFCOUNTER_IERRORS:
6760 return (stats->NoMoreRxBDs + stats->InputDiscards +
6761 stats->InputErrors);
6762 case IFCOUNTER_COLLISIONS:
6763 return (stats->etherStatsCollisions);
6764 default:
6765 return (if_get_counter_default(ifp, cnt));
6766 }
6767 }
6768
6769 #ifdef DEBUGNET
6770 static void
bge_debugnet_init(if_t ifp,int * nrxr,int * ncl,int * clsize)6771 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6772 {
6773 struct bge_softc *sc;
6774
6775 sc = if_getsoftc(ifp);
6776 BGE_LOCK(sc);
6777 /*
6778 * There is only one logical receive ring, but it is backed
6779 * by two actual rings, for cluster- and jumbo-sized mbufs.
6780 * Debugnet expects only one size, so if jumbo is in use,
6781 * this says we have two rings of jumbo mbufs, but that's
6782 * only a little wasteful.
6783 */
6784 *nrxr = 2;
6785 *ncl = DEBUGNET_MAX_IN_FLIGHT;
6786 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6787 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6788 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6789 *clsize = MJUM9BYTES;
6790 else
6791 *clsize = MCLBYTES;
6792 BGE_UNLOCK(sc);
6793 }
6794
6795 static void
bge_debugnet_event(if_t ifp __unused,enum debugnet_ev event __unused)6796 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
6797 {
6798 }
6799
6800 static int
bge_debugnet_transmit(if_t ifp,struct mbuf * m)6801 bge_debugnet_transmit(if_t ifp, struct mbuf *m)
6802 {
6803 struct bge_softc *sc;
6804 uint32_t prodidx;
6805 int error;
6806
6807 sc = if_getsoftc(ifp);
6808 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6809 IFF_DRV_RUNNING)
6810 return (1);
6811
6812 prodidx = sc->bge_tx_prodidx;
6813 error = bge_encap(sc, &m, &prodidx);
6814 if (error == 0)
6815 bge_start_tx(sc, prodidx);
6816 return (error);
6817 }
6818
6819 static int
bge_debugnet_poll(if_t ifp,int count)6820 bge_debugnet_poll(if_t ifp, int count)
6821 {
6822 struct bge_softc *sc;
6823 uint32_t rx_prod, tx_cons;
6824
6825 sc = if_getsoftc(ifp);
6826 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6827 IFF_DRV_RUNNING)
6828 return (1);
6829
6830 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6831 sc->bge_cdata.bge_status_map,
6832 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6833
6834 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6835 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6836
6837 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6838 sc->bge_cdata.bge_status_map,
6839 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6840
6841 (void)bge_rxeof(sc, rx_prod, 0);
6842 bge_txeof(sc, tx_cons);
6843 return (0);
6844 }
6845 #endif /* DEBUGNET */
6846