1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
17 *
18 * NO WARRANTY
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
30 */
31
32 #include <sys/cdefs.h>
33 /*
34 * Broadcom Common PCI/PCIe Support.
35 *
36 * This base driver implementation is shared by the bhnd_pcib (root complex)
37 * and bhnd_pci_hostb (host bridge) drivers.
38 */
39
40 #include <sys/param.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/bus.h>
44 #include <sys/module.h>
45 #include <sys/systm.h>
46
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <machine/resource.h>
50
51 #include <dev/bhnd/bhnd.h>
52 #include <dev/mdio/mdio.h>
53
54 #include "bhnd_pcireg.h"
55 #include "bhnd_pcivar.h"
56
57 static int bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc);
58 static int bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd);
59 static int bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc);
60 static void bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc);
61 static int bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc,
62 uint32_t cmd);
63 static int bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
64 uint16_t *data_read);
65
66 static struct bhnd_device_quirk bhnd_pci_quirks[];
67 static struct bhnd_device_quirk bhnd_pcie_quirks[];
68
69 #define BHND_PCI_QUIRKS bhnd_pci_quirks
70 #define BHND_PCIE_QUIRKS bhnd_pcie_quirks
71 #define BHND_PCI_DEV(_core, _desc, ...) \
72 { BHND_DEVICE(BCM, _core, _desc, BHND_ ## _core ## _QUIRKS, \
73 ## __VA_ARGS__), BHND_PCI_REGFMT_ ## _core }
74
75 static const struct bhnd_pci_device {
76 struct bhnd_device device;
77 bhnd_pci_regfmt_t regfmt; /**< register format */
78 } bhnd_pci_devs[] = {
79 BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB),
80 BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC),
81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB),
82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC),
83 { BHND_DEVICE_END, 0 }
84 };
85
86 /* Device quirks tables */
87 static struct bhnd_device_quirk bhnd_pci_quirks[] = { BHND_DEVICE_QUIRK_END };
88 static struct bhnd_device_quirk bhnd_pcie_quirks[] = {
89 BHND_CORE_QUIRK(HWREV_GTE(10), BHND_PCI_QUIRK_SD_C22_EXTADDR),
90
91 BHND_DEVICE_QUIRK_END
92 };
93
94 #define BHND_PCIE_MDIO_CTL_DELAY 10 /**< usec delay required between
95 * MDIO_CTL/MDIO_DATA accesses. */
96 #define BHND_PCIE_MDIO_RETRY_DELAY 2000 /**< usec delay before retrying
97 * BHND_PCIE_MDIOCTL_DONE. */
98 #define BHND_PCIE_MDIO_RETRY_COUNT 200 /**< number of times to loop waiting
99 * for BHND_PCIE_MDIOCTL_DONE. */
100
101 #define BHND_PCI_READ_4(_sc, _reg) \
102 bhnd_bus_read_4((_sc)->mem_res, (_reg))
103 #define BHND_PCI_WRITE_4(_sc, _reg, _val) \
104 bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val))
105
106 #define BHND_PCIE_ASSERT(sc) \
107 KASSERT(bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE, \
108 ("not a pcie device!"));
109
110 int
bhnd_pci_generic_probe(device_t dev)111 bhnd_pci_generic_probe(device_t dev)
112 {
113 const struct bhnd_device *id;
114
115 id = bhnd_device_lookup(dev, &bhnd_pci_devs[0].device,
116 sizeof(bhnd_pci_devs[0]));
117 if (id == NULL)
118 return (ENXIO);
119
120 bhnd_set_custom_core_desc(dev, id->desc);
121 return (BUS_PROBE_DEFAULT);
122 }
123
124 int
bhnd_pci_generic_attach(device_t dev)125 bhnd_pci_generic_attach(device_t dev)
126 {
127 struct bhnd_pci_softc *sc;
128 int error;
129
130 sc = device_get_softc(dev);
131 sc->dev = dev;
132 sc->quirks = bhnd_device_quirks(dev, &bhnd_pci_devs[0].device,
133 sizeof(bhnd_pci_devs[0]));
134
135 /* Allocate bus resources */
136 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
137 RF_ACTIVE);
138 if (sc->mem_res == NULL)
139 return (ENXIO);
140
141 BHND_PCI_LOCK_INIT(sc);
142
143 /* Probe and attach children */
144 if ((error = bus_generic_attach(dev)))
145 goto cleanup;
146
147 return (0);
148
149 cleanup:
150 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
151 BHND_PCI_LOCK_DESTROY(sc);
152
153 return (error);
154 }
155
156 int
bhnd_pci_generic_detach(device_t dev)157 bhnd_pci_generic_detach(device_t dev)
158 {
159 struct bhnd_pci_softc *sc;
160 int error;
161
162 sc = device_get_softc(dev);
163
164 if ((error = bus_generic_detach(dev)))
165 return (error);
166
167 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
168
169 BHND_PCI_LOCK_DESTROY(sc);
170
171 return (0);
172 }
173
174 static struct resource_list *
bhnd_pci_get_resource_list(device_t dev,device_t child)175 bhnd_pci_get_resource_list(device_t dev, device_t child)
176 {
177 struct bhnd_pci_devinfo *dinfo;
178
179 if (device_get_parent(child) != dev)
180 return (NULL);
181
182 dinfo = device_get_ivars(child);
183 return (&dinfo->resources);
184 }
185
186 static device_t
bhnd_pci_add_child(device_t dev,u_int order,const char * name,int unit)187 bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
188 {
189 struct bhnd_pci_devinfo *dinfo;
190 device_t child;
191
192 child = device_add_child_ordered(dev, order, name, unit);
193 if (child == NULL)
194 return (NULL);
195
196 dinfo = malloc(sizeof(struct bhnd_pci_devinfo), M_DEVBUF, M_NOWAIT);
197 if (dinfo == NULL) {
198 device_delete_child(dev, child);
199 return (NULL);
200 }
201
202 resource_list_init(&dinfo->resources);
203
204 device_set_ivars(child, dinfo);
205 return (child);
206 }
207
208 static void
bhnd_pci_child_deleted(device_t dev,device_t child)209 bhnd_pci_child_deleted(device_t dev, device_t child)
210 {
211 struct bhnd_pci_devinfo *dinfo;
212
213 if (device_get_parent(child) != dev)
214 return;
215
216 dinfo = device_get_ivars(child);
217 if (dinfo != NULL) {
218 resource_list_free(&dinfo->resources);
219 free(dinfo, M_DEVBUF);
220 }
221
222 device_set_ivars(child, NULL);
223 }
224
225 int
bhnd_pci_generic_suspend(device_t dev)226 bhnd_pci_generic_suspend(device_t dev)
227 {
228 return (bus_generic_suspend(dev));
229 }
230
231 int
bhnd_pci_generic_resume(device_t dev)232 bhnd_pci_generic_resume(device_t dev)
233 {
234 return (bus_generic_resume(dev));
235 }
236
237 /**
238 * Read a 32-bit PCIe TLP/DLLP/PLP protocol register.
239 *
240 * @param sc The bhndb_pci driver state.
241 * @param addr The protocol register offset.
242 */
243 uint32_t
bhnd_pcie_read_proto_reg(struct bhnd_pci_softc * sc,uint32_t addr)244 bhnd_pcie_read_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr)
245 {
246 uint32_t val;
247
248 BHND_PCIE_ASSERT(sc);
249
250 BHND_PCI_LOCK(sc);
251 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr);
252 val = BHND_PCI_READ_4(sc, BHND_PCIE_IND_DATA);
253 BHND_PCI_UNLOCK(sc);
254
255 return (val);
256 }
257
258 /**
259 * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value.
260 *
261 * @param sc The bhndb_pci driver state.
262 * @param addr The protocol register offset.
263 * @param val The value to write to @p addr.
264 */
265 void
bhnd_pcie_write_proto_reg(struct bhnd_pci_softc * sc,uint32_t addr,uint32_t val)266 bhnd_pcie_write_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr,
267 uint32_t val)
268 {
269 BHND_PCIE_ASSERT(sc);
270
271 BHND_PCI_LOCK(sc);
272 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr);
273 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_DATA, val);
274 BHND_PCI_UNLOCK(sc);
275 }
276
277 /* Spin until the MDIO device reports itself as idle, or timeout is reached. */
278 static int
bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc * sc)279 bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc)
280 {
281 uint32_t ctl;
282
283 /* Spin waiting for the BUSY flag to clear */
284 for (int i = 0; i < BHND_PCIE_MDIO_RETRY_COUNT; i++) {
285 ctl = BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_CTL);
286 if ((ctl & BHND_PCIE_MDIOCTL_DONE))
287 return (0);
288
289 DELAY(BHND_PCIE_MDIO_RETRY_DELAY);
290 }
291
292 return (ETIMEDOUT);
293 }
294
295 /**
296 * Write an MDIO IOCTL and wait for completion.
297 */
298 static int
bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc * sc,uint32_t cmd)299 bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd)
300 {
301 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
302
303 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_CTL, cmd);
304 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
305 return (0);
306 }
307
308 /**
309 * Enable MDIO device
310 */
311 static int
bhnd_pcie_mdio_enable(struct bhnd_pci_softc * sc)312 bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc)
313 {
314 uint32_t ctl;
315
316 BHND_PCIE_ASSERT(sc);
317
318 /* Enable MDIO clock and preamble mode */
319 ctl = BHND_PCIE_MDIOCTL_PREAM_EN|BHND_PCIE_MDIOCTL_DIVISOR_VAL;
320 return (bhnd_pcie_mdio_ioctl(sc, ctl));
321 }
322
323 /**
324 * Disable MDIO device.
325 */
326 static void
bhnd_pcie_mdio_disable(struct bhnd_pci_softc * sc)327 bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc)
328 {
329 if (bhnd_pcie_mdio_ioctl(sc, 0))
330 device_printf(sc->dev, "failed to disable MDIO clock\n");
331 }
332
333 /**
334 * Issue a write command and wait for completion
335 */
336 static int
bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc * sc,uint32_t cmd)337 bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, uint32_t cmd)
338 {
339 int error;
340
341 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
342
343 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_WRITE;
344
345 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd);
346 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
347
348 if ((error = bhnd_pcie_mdio_wait_idle(sc)))
349 return (error);
350
351 return (0);
352 }
353
354 /**
355 * Issue an MDIO read command, wait for completion, and return
356 * the result in @p data_read.
357 */
358 static int
bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc * sc,uint32_t cmd,uint16_t * data_read)359 bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
360 uint16_t *data_read)
361 {
362 int error;
363
364 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
365
366 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_READ;
367 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd);
368 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
369
370 if ((error = bhnd_pcie_mdio_wait_idle(sc)))
371 return (error);
372
373 *data_read = (BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_DATA) &
374 BHND_PCIE_MDIODATA_DATA_MASK);
375 return (0);
376 }
377
378 int
bhnd_pcie_mdio_read(struct bhnd_pci_softc * sc,int phy,int reg)379 bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)
380 {
381 uint32_t cmd;
382 uint16_t val;
383 int error;
384
385 /* Enable MDIO access */
386 BHND_PCI_LOCK(sc);
387 bhnd_pcie_mdio_enable(sc);
388
389 /* Issue the read */
390 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);
391 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val);
392
393 /* Disable MDIO access */
394 bhnd_pcie_mdio_disable(sc);
395 BHND_PCI_UNLOCK(sc);
396
397 if (error)
398 return (~0U);
399
400 return (val);
401 }
402
403 int
bhnd_pcie_mdio_write(struct bhnd_pci_softc * sc,int phy,int reg,int val)404 bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val)
405 {
406 uint32_t cmd;
407 int error;
408
409 /* Enable MDIO access */
410 BHND_PCI_LOCK(sc);
411 bhnd_pcie_mdio_enable(sc);
412
413 /* Issue the write */
414 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK);
415 error = bhnd_pcie_mdio_cmd_write(sc, cmd);
416
417 /* Disable MDIO access */
418 bhnd_pcie_mdio_disable(sc);
419 BHND_PCI_UNLOCK(sc);
420
421 return (error);
422 }
423
424 int
bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc * sc,int phy,int devaddr,int reg)425 bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,
426 int reg)
427 {
428 uint32_t cmd;
429 uint16_t val;
430 int error;
431
432 if (devaddr == MDIO_DEVADDR_NONE)
433 return (bhnd_pcie_mdio_read(sc, phy, reg));
434
435 /* Extended register access is only supported for the SerDes device,
436 * using the non-standard C22 extended address mechanism */
437 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) ||
438 phy != BHND_PCIE_PHYADDR_SD)
439 {
440 return (~0U);
441 }
442
443 /* Enable MDIO access */
444 BHND_PCI_LOCK(sc);
445 bhnd_pcie_mdio_enable(sc);
446
447 /* Write the block address to the address extension register */
448 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;
449 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd)))
450 goto cleanup;
451
452 /* Issue the read */
453 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);
454 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val);
455
456 cleanup:
457 bhnd_pcie_mdio_disable(sc);
458 BHND_PCI_UNLOCK(sc);
459
460 if (error)
461 return (~0U);
462
463 return (val);
464 }
465
466 int
bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc * sc,int phy,int devaddr,int reg,int val)467 bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,
468 int reg, int val)
469 {
470 uint32_t cmd;
471 int error;
472
473 if (devaddr == MDIO_DEVADDR_NONE)
474 return (bhnd_pcie_mdio_write(sc, phy, reg, val));
475
476 /* Extended register access is only supported for the SerDes device,
477 * using the non-standard C22 extended address mechanism */
478 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) ||
479 phy != BHND_PCIE_PHYADDR_SD)
480 {
481 return (~0U);
482 }
483
484 /* Enable MDIO access */
485 BHND_PCI_LOCK(sc);
486 bhnd_pcie_mdio_enable(sc);
487
488 /* Write the block address to the address extension register */
489 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;
490 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd)))
491 goto cleanup;
492
493 /* Issue the write */
494 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) |
495 (val & BHND_PCIE_MDIODATA_DATA_MASK);
496 error = bhnd_pcie_mdio_cmd_write(sc, cmd);
497
498 cleanup:
499 bhnd_pcie_mdio_disable(sc);
500 BHND_PCI_UNLOCK(sc);
501
502 return (error);
503 }
504
505 static device_method_t bhnd_pci_methods[] = {
506 /* Device interface */
507 DEVMETHOD(device_probe, bhnd_pci_generic_probe),
508 DEVMETHOD(device_attach, bhnd_pci_generic_attach),
509 DEVMETHOD(device_detach, bhnd_pci_generic_detach),
510 DEVMETHOD(device_suspend, bhnd_pci_generic_suspend),
511 DEVMETHOD(device_resume, bhnd_pci_generic_resume),
512
513 /* Bus interface */
514 DEVMETHOD(bus_add_child, bhnd_pci_add_child),
515 DEVMETHOD(bus_child_deleted, bhnd_pci_child_deleted),
516 DEVMETHOD(bus_print_child, bus_generic_print_child),
517 DEVMETHOD(bus_get_resource_list, bhnd_pci_get_resource_list),
518 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
519 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
520 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
521
522 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
523 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
524 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
525 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
526 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
527
528 DEVMETHOD_END
529 };
530
531 DEFINE_CLASS_0(bhnd_pci, bhnd_pci_driver, bhnd_pci_methods, sizeof(struct bhnd_pci_softc));
532 MODULE_DEPEND(bhnd_pci, bhnd, 1, 1, 1);
533 MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1);
534 MODULE_VERSION(bhnd_pci, 1);
535