1 /* $OpenBSD: gdtvar.h,v 1.27 2024/09/01 03:08:56 jsg Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * This driver would not have written if it was not for the hardware donations
29 * from both ICP-Vortex and �ko.neT. I want to thank them for their support.
30 */
31
32 #define DEVNAME(s) ((s)->sc_dev.dv_xname)
33 #define GDT_CMD_RESERVE 4 /* Internal driver cmd reserve. */
34
35 #define GDT_SCRATCH_SZ 4096
36
37 #ifdef _KERNEL
38
39 /* Debugging */
40 /* #define GDT_DEBUG GDT_D_IOCTL | GDT_D_INFO */
41 #ifdef GDT_DEBUG
42 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
43 #define GDT_D_INTR 0x01
44 #define GDT_D_MISC 0x02
45 #define GDT_D_CMD 0x04
46 #define GDT_D_QUEUE 0x08
47 #define GDT_D_IO 0x10
48 #define GDT_D_IOCTL 0x20
49 #define GDT_D_INFO 0x40
50 extern int gdt_debug;
51 #else
52 #define GDT_DPRINTF(mask, args)
53 #endif
54
55 /* Miscellaneous constants */
56 #define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
57 #define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
58 #define GDT_POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
59 #define GDT_WATCH_TIMEOUT 10000 /* 10000 * 1ms = 10s */
60
61 /* Context structure for interrupt services */
62 struct gdt_intr_ctx {
63 u_int32_t info, info2;
64 u_int16_t cmd_status, service;
65 u_int8_t istatus;
66 };
67
68 /*
69 * A command control block, one for each corresponding command index of the
70 * controller.
71 */
72 struct gdt_ccb {
73 TAILQ_ENTRY(gdt_ccb) gc_chain;
74 struct scsi_xfer *gc_xs;
75 bus_dmamap_t gc_dmamap_xfer;
76 int gc_timeout;
77 u_int32_t gc_info;
78 u_int32_t gc_blockno;
79 u_int32_t gc_blockcnt;
80 u_int16_t gc_status;
81 u_int8_t gc_service;
82 u_int8_t gc_cmd_index;
83 u_int8_t gc_flags;
84 #define GDT_GCF_CMD_MASK 0x3
85 #define GDT_GCF_UNUSED 0
86 #define GDT_GCF_INTERNAL 1
87 #define GDT_GCF_SCREEN 2
88 #define GDT_GCF_SCSI 3
89 #define GDT_GCF_WATCHDOG 0x4
90 };
91
92 static inline int gdt_ccb_set_cmd(struct gdt_ccb *, int);
93 static inline int
gdt_ccb_set_cmd(struct gdt_ccb * ccb,int flag)94 gdt_ccb_set_cmd(struct gdt_ccb *ccb, int flag)
95 {
96 int rv = ccb->gc_flags & GDT_GCF_CMD_MASK;
97
98 ccb->gc_flags &= ~GDT_GCF_CMD_MASK;
99 ccb->gc_flags |= flag;
100 return (rv);
101 }
102
103 struct gdt_softc {
104 struct device sc_dev;
105 void *sc_ih;
106
107 int sc_class; /* Controller class */
108 #define GDT_ISA 0x01
109 #define GDT_EISA 0x02
110 #define GDT_PCI 0x03
111 #define GDT_PCINEW 0x04
112 #define GDT_MPR 0x05
113 #define GDT_CLASS_MASK 0x07
114 #define GDT_FC 0x10
115 #define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
116
117 bus_space_tag_t sc_dpmemt;
118 bus_space_handle_t sc_dpmemh;
119 bus_addr_t sc_dpmembase;
120 bus_dma_tag_t sc_dmat;
121
122 /* XXX These could go into a class-dependent opaque struct instead */
123 bus_space_tag_t sc_iot;
124 bus_space_handle_t sc_ioh;
125 bus_addr_t sc_iobase;
126
127 u_int16_t sc_ic_all_size;
128
129 struct gdt_ccb sc_ccbs[GDT_MAXCMDS];
130 TAILQ_HEAD(, gdt_ccb) sc_free_ccb, sc_ccbq;
131 struct scsi_xfer_list sc_queue;
132
133 struct mutex sc_ccb_mtx;
134 struct scsi_iopool sc_iopool;
135
136 int sc_ndevs;
137
138 u_int16_t sc_cmd_len;
139 u_int16_t sc_cmd_off;
140 u_int16_t sc_cmd_cnt;
141 u_int8_t sc_cmd[GDT_CMD_SZ];
142
143 u_int32_t sc_info;
144 u_int32_t sc_info2;
145 bus_dma_segment_t sc_scratch_seg;
146 caddr_t sc_scratch;
147 u_int16_t sc_status;
148
149 u_int8_t sc_bus_cnt;
150 u_int8_t sc_bus_id[GDT_MAXBUS];
151 u_int8_t sc_more_proc;
152
153 u_int32_t sc_total_disks;
154
155 struct {
156 u_int8_t hd_present;
157 u_int8_t hd_is_logdrv;
158 u_int8_t hd_is_arraydrv;
159 u_int8_t hd_is_master;
160 u_int8_t hd_is_parity;
161 u_int8_t hd_is_hotfix;
162 u_int8_t hd_master_no;
163 u_int8_t hd_lock;
164 u_int8_t hd_heads;
165 u_int8_t hd_secs;
166 u_int16_t hd_devtype;
167 u_int32_t hd_size;
168 u_int8_t hd_ldr_no;
169 u_int8_t hd_rw_attribs;
170 u_int32_t hd_start_sec;
171 } sc_hdr[GDT_MAX_HDRIVES];
172
173 struct {
174 u_int8_t ra_lock; /* chan locked? (hot plug */
175 u_int8_t ra_phys_cnt; /* physical disk count */
176 u_int8_t ra_local_no; /* local channel number */
177 u_int8_t ra_io_cnt[GDT_MAXID]; /* current IO count */
178 u_int32_t ra_address; /* channel address */
179 u_int32_t ra_id_list[GDT_MAXID]; /* IDs of phys disks */
180 } sc_raw[GDT_MAXBUS]; /* SCSI channels */
181
182 struct {
183 u_int32_t cp_version;
184 u_int16_t cp_state;
185 u_int16_t cp_strategy;
186 u_int16_t cp_write_back;
187 u_int16_t cp_block_size;
188 } sc_cpar;
189
190 struct {
191 u_int32_t bi_ser_no; /* serial number */
192 u_int8_t bi_oem_id[2]; /* u_int8_t OEM ID */
193 u_int16_t bi_ep_flags; /* eprom flags */
194 u_int32_t bi_proc_id; /* processor ID */
195 u_int32_t bi_memsize; /* memory size (bytes) */
196 u_int8_t bi_mem_banks; /* memory banks */
197 u_int8_t bi_chan_type; /* channel type */
198 u_int8_t bi_chan_count; /* channel count */
199 u_int8_t bi_rdongle_pres; /* dongle present */
200 u_int32_t bi_epr_fw_ver; /* (eprom) firmware ver */
201 u_int32_t bi_upd_fw_ver; /* (update) firmware ver */
202 u_int32_t bi_upd_revision; /* update revision */
203 char bi_type_string[16]; /* char controller name */
204 char bi_raid_string[16]; /* char RAID firmware name */
205 u_int8_t bi_update_pres; /* update present? */
206 u_int8_t bi_xor_pres; /* XOR engine present */
207 u_int8_t bi_prom_type; /* ROM type (eprom/flash) */
208 u_int8_t bi_prom_count; /* number of ROM devices */
209 u_int32_t bi_dup_pres; /* duplexing module pres? */
210 u_int32_t bi_chan_pres; /* # of exp. channels */
211 u_int32_t bi_mem_pres; /* memory expansion inst? */
212 u_int8_t bi_ft_bus_system; /* fault bus supported? */
213 u_int8_t bi_subtype_valid; /* board_subtype valid */
214 u_int8_t bi_board_subtype; /* subtype/hardware level */
215 u_int8_t bi_rampar_pres; /* RAM parity check hw? */
216 } sc_binfo;
217
218 struct {
219 u_int8_t bf_chaining; /* chaining supported */
220 u_int8_t bf_striping; /* striping (RAID-0) supported */
221 u_int8_t bf_mirroring; /* mirroring (RAID-1) supported */
222 u_int8_t bf_raid; /* RAID-4/5/10 supported */
223 } sc_bfeat;
224
225 u_int16_t sc_raw_feat;
226 u_int16_t sc_cache_feat;
227
228 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
229 u_int8_t (*sc_get_status)(struct gdt_softc *);
230 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
231 void (*sc_release_event)(struct gdt_softc *, struct gdt_ccb *);
232 void (*sc_set_sema0)(struct gdt_softc *);
233 int (*sc_test_busy)(struct gdt_softc *);
234 };
235
236 int gdt_attach(struct gdt_softc *);
237 int gdt_intr(void *);
238
239 /* These all require correctly aligned buffers */
240 static inline void gdt_enc16(u_int8_t *, u_int16_t);
241 static inline void gdt_enc32(u_int8_t *, u_int32_t);
242 static inline u_int8_t gdt_dec8(u_int8_t *);
243 static inline u_int16_t gdt_dec16(u_int8_t *);
244 static inline u_int32_t gdt_dec32(u_int8_t *);
245
246 static inline void
gdt_enc16(u_int8_t * addr,u_int16_t value)247 gdt_enc16(u_int8_t *addr, u_int16_t value)
248 {
249 *(u_int16_t *)addr = htole16(value);
250 }
251
252 static inline void
gdt_enc32(u_int8_t * addr,u_int32_t value)253 gdt_enc32(u_int8_t *addr, u_int32_t value)
254 {
255 *(u_int32_t *)addr = htole32(value);
256 }
257
258 static inline u_int8_t
gdt_dec8(u_int8_t * addr)259 gdt_dec8(u_int8_t *addr)
260 {
261 return *(u_int8_t *)addr;
262 }
263
264 static inline u_int16_t
gdt_dec16(u_int8_t * addr)265 gdt_dec16(u_int8_t *addr)
266 {
267 return letoh16(*(u_int16_t *)addr);
268 }
269
270 static inline u_int32_t
gdt_dec32(u_int8_t * addr)271 gdt_dec32(u_int8_t *addr)
272 {
273 return letoh32(*(u_int32_t *)addr);
274 }
275
276 extern u_int8_t gdt_polling;
277
278 #endif
279