| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/net/wireshark-lite/wireshark-3.6.1/epan/dissectors/ |
| H A D | packet-stat.c | 34 { STATPROC_UNMON, "UNMON" },
35 { STATPROC_UNMON_ALL, "UNMON_ALL" },
45 static header_field_info hfi_stat_mon_name STAT_HFI_INIT = {
53 static const value_string stat_res[] =
81 "My ID", "stat.my_id", FT_NONE,BASE_NONE,
82 NULL, 0, "My_ID structure", HFILL };
105 "Status Change", "stat.stat_chge", FT_NONE, BASE_NONE,
106 NULL, 0, "Status Change structure", HFILL };
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/include/linux/ |
| H A D | wait_bit.h | 21 #define __WAIT_BIT_KEY_INITIALIZER(word, bit) \ argument
38 #define DEFINE_WAIT_BIT(name, word, bit) \ argument
71 wait_on_bit(unsigned long *word, int bit, unsigned mode) in wait_on_bit()
96 wait_on_bit_io(unsigned long *word, int bit, unsigned mode) in wait_on_bit_io()
122 wait_on_bit_timeout(unsigned long *word, int bit, unsigned mode, in wait_on_bit_timeout()
150 wait_on_bit_action(unsigned long *word, int bit, wait_bit_action_f *action, in wait_on_bit_action()
179 wait_on_bit_lock(unsigned long *word, int bit, unsigned mode) in wait_on_bit_lock()
203 wait_on_bit_lock_io(unsigned long *word, int bit, unsigned mode) in wait_on_bit_lock_io()
229 wait_on_bit_lock_action(unsigned long *word, int bit, wait_bit_action_f *action, in wait_on_bit_lock_action()
330 static inline void clear_and_wake_up_bit(int bit, void *word) in clear_and_wake_up_bit()
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
45 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
82 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
83 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
106 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
107 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/multimedia/libv4l/linux-5.13-rc2/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
45 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
82 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
83 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
106 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
107 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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