| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
45 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
82 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
83 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
106 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
107 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/include/linux/ |
| H A D | wait_bit.h | 21 #define __WAIT_BIT_KEY_INITIALIZER(word, bit) \ argument
38 #define DEFINE_WAIT_BIT(name, word, bit) \ argument
71 wait_on_bit(unsigned long *word, int bit, unsigned mode) in wait_on_bit()
96 wait_on_bit_io(unsigned long *word, int bit, unsigned mode) in wait_on_bit_io()
122 wait_on_bit_timeout(unsigned long *word, int bit, unsigned mode, in wait_on_bit_timeout()
150 wait_on_bit_action(unsigned long *word, int bit, wait_bit_action_f *action, in wait_on_bit_action()
179 wait_on_bit_lock(unsigned long *word, int bit, unsigned mode) in wait_on_bit_lock()
203 wait_on_bit_lock_io(unsigned long *word, int bit, unsigned mode) in wait_on_bit_lock_io()
229 wait_on_bit_lock_action(unsigned long *word, int bit, wait_bit_action_f *action, in wait_on_bit_lock_action()
330 static inline void clear_and_wake_up_bit(int bit, void *word) in clear_and_wake_up_bit()
|
| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
|
| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
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