xref: /dragonfly/sys/dev/drm/i915/intel_huc.c (revision 3f2dd94a)
1 /*
2  * Copyright © 2016-2017 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/types.h>
26 
27 #include "intel_huc.h"
28 #include "i915_drv.h"
29 
30 /**
31  * DOC: HuC Firmware
32  *
33  * Motivation:
34  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
35  * Efficiency Video Coding) operations. Userspace can use the firmware
36  * capabilities by adding HuC specific commands to batch buffers.
37  *
38  * Implementation:
39  * The same firmware loader is used as the GuC. However, the actual
40  * loading to HW is deferred until GEM initialization is done.
41  *
42  * Note that HuC firmware loading must be done before GuC loading.
43  */
44 
45 #define BXT_HUC_FW_MAJOR 01
46 #define BXT_HUC_FW_MINOR 07
47 #define BXT_BLD_NUM 1398
48 
49 #define SKL_HUC_FW_MAJOR 01
50 #define SKL_HUC_FW_MINOR 07
51 #define SKL_BLD_NUM 1398
52 
53 #define KBL_HUC_FW_MAJOR 02
54 #define KBL_HUC_FW_MINOR 00
55 #define KBL_BLD_NUM 1810
56 
57 #define HUC_FW_PATH(platform, major, minor, bld_num) \
58 	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
59 	__stringify(minor) "_" __stringify(bld_num) ".bin"
60 
61 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
62 	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
63 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
64 
65 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
66 	BXT_HUC_FW_MINOR, BXT_BLD_NUM)
67 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
68 
69 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
70 	KBL_HUC_FW_MINOR, KBL_BLD_NUM)
71 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
72 
73 /**
74  * intel_huc_select_fw() - selects HuC firmware for loading
75  * @huc:	intel_huc struct
76  */
intel_huc_select_fw(struct intel_huc * huc)77 void intel_huc_select_fw(struct intel_huc *huc)
78 {
79 	struct drm_i915_private *dev_priv = huc_to_i915(huc);
80 
81 	intel_uc_fw_init(&huc->fw, INTEL_UC_FW_TYPE_HUC);
82 
83 	if (i915_modparams.huc_firmware_path) {
84 		huc->fw.path = i915_modparams.huc_firmware_path;
85 		huc->fw.major_ver_wanted = 0;
86 		huc->fw.minor_ver_wanted = 0;
87 	} else if (IS_SKYLAKE(dev_priv)) {
88 		huc->fw.path = I915_SKL_HUC_UCODE;
89 		huc->fw.major_ver_wanted = SKL_HUC_FW_MAJOR;
90 		huc->fw.minor_ver_wanted = SKL_HUC_FW_MINOR;
91 	} else if (IS_BROXTON(dev_priv)) {
92 		huc->fw.path = I915_BXT_HUC_UCODE;
93 		huc->fw.major_ver_wanted = BXT_HUC_FW_MAJOR;
94 		huc->fw.minor_ver_wanted = BXT_HUC_FW_MINOR;
95 	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
96 		huc->fw.path = I915_KBL_HUC_UCODE;
97 		huc->fw.major_ver_wanted = KBL_HUC_FW_MAJOR;
98 		huc->fw.minor_ver_wanted = KBL_HUC_FW_MINOR;
99 	} else {
100 		DRM_ERROR("No HuC firmware known for platform with HuC!\n");
101 		return;
102 	}
103 }
104 
105 /**
106  * huc_ucode_xfer() - DMA's the firmware
107  * @dev_priv: the drm_i915_private device
108  *
109  * Transfer the firmware image to RAM for execution by the microcontroller.
110  *
111  * Return: 0 on success, non-zero on failure
112  */
huc_ucode_xfer(struct intel_uc_fw * huc_fw,struct i915_vma * vma)113 static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
114 {
115 	struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
116 	struct drm_i915_private *dev_priv = huc_to_i915(huc);
117 	unsigned long offset = 0;
118 	u32 size;
119 	int ret;
120 
121 	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
122 
123 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
124 
125 	/* Set the source address for the uCode */
126 	offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
127 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
128 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
129 
130 	/* Hardware doesn't look at destination address for HuC. Set it to 0,
131 	 * but still program the correct address space.
132 	 */
133 	I915_WRITE(DMA_ADDR_1_LOW, 0);
134 	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
135 
136 	size = huc_fw->header_size + huc_fw->ucode_size;
137 	I915_WRITE(DMA_COPY_SIZE, size);
138 
139 	/* Start the DMA */
140 	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
141 
142 	/* Wait for DMA to finish */
143 	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
144 
145 	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
146 
147 	/* Disable the bits once DMA is over */
148 	I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
149 
150 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
151 
152 	return ret;
153 }
154 
155 /**
156  * intel_huc_init_hw() - load HuC uCode to device
157  * @huc: intel_huc structure
158  *
159  * Called from guc_setup() during driver loading and also after a GPU reset.
160  * Be note that HuC loading must be done before GuC loading.
161  *
162  * The firmware image should have already been fetched into memory by the
163  * earlier call to intel_huc_init(), so here we need only check that
164  * is succeeded, and then transfer the image to the h/w.
165  *
166  */
intel_huc_init_hw(struct intel_huc * huc)167 void intel_huc_init_hw(struct intel_huc *huc)
168 {
169 	intel_uc_fw_upload(&huc->fw, huc_ucode_xfer);
170 }
171 
172 /**
173  * intel_huc_auth() - Authenticate HuC uCode
174  * @huc: intel_huc structure
175  *
176  * Called after HuC and GuC firmware loading during intel_uc_init_hw().
177  *
178  * This function pins HuC firmware image object into GGTT.
179  * Then it invokes GuC action to authenticate passing the offset to RSA
180  * signature through intel_guc_auth_huc(). It then waits for 50ms for
181  * firmware verification ACK and unpins the object.
182  */
intel_huc_auth(struct intel_huc * huc)183 void intel_huc_auth(struct intel_huc *huc)
184 {
185 	struct drm_i915_private *i915 = huc_to_i915(huc);
186 	struct intel_guc *guc = &i915->guc;
187 	struct i915_vma *vma;
188 	int ret;
189 
190 	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
191 		return;
192 
193 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
194 				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
195 	if (IS_ERR(vma)) {
196 		DRM_ERROR("failed to pin huc fw object %d\n",
197 				(int)PTR_ERR(vma));
198 		return;
199 	}
200 
201 	ret = intel_guc_auth_huc(guc,
202 				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
203 	if (ret) {
204 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
205 		goto out;
206 	}
207 
208 	/* Check authentication status, it should be done by now */
209 	ret = intel_wait_for_register(i915,
210 				      HUC_STATUS2,
211 				      HUC_FW_VERIFIED,
212 				      HUC_FW_VERIFIED,
213 				      50);
214 	if (ret) {
215 		DRM_ERROR("HuC: Authentication failed %d\n", ret);
216 		goto out;
217 	}
218 
219 out:
220 	i915_vma_unpin(vma);
221 }
222