1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 struct abm_save_restore; 50 51 /* forward declaration */ 52 struct aux_payload; 53 struct set_config_cmd_payload; 54 struct dmub_notification; 55 56 #define DC_VER "3.2.281" 57 58 #define MAX_SURFACES 3 59 #define MAX_PLANES 6 60 #define MAX_STREAMS 6 61 #define MIN_VIEWPORT_SIZE 12 62 #define MAX_NUM_EDP 2 63 64 /* Display Core Interfaces */ 65 struct dc_versions { 66 const char *dc_ver; 67 struct dmcu_version dmcu_version; 68 }; 69 70 enum dp_protocol_version { 71 DP_VERSION_1_4 = 0, 72 DP_VERSION_2_1, 73 DP_VERSION_UNKNOWN, 74 }; 75 76 enum dc_plane_type { 77 DC_PLANE_TYPE_INVALID, 78 DC_PLANE_TYPE_DCE_RGB, 79 DC_PLANE_TYPE_DCE_UNDERLAY, 80 DC_PLANE_TYPE_DCN_UNIVERSAL, 81 }; 82 83 // Sizes defined as multiples of 64KB 84 enum det_size { 85 DET_SIZE_DEFAULT = 0, 86 DET_SIZE_192KB = 3, 87 DET_SIZE_256KB = 4, 88 DET_SIZE_320KB = 5, 89 DET_SIZE_384KB = 6 90 }; 91 92 93 struct dc_plane_cap { 94 enum dc_plane_type type; 95 uint32_t per_pixel_alpha : 1; 96 struct { 97 uint32_t argb8888 : 1; 98 uint32_t nv12 : 1; 99 uint32_t fp16 : 1; 100 uint32_t p010 : 1; 101 uint32_t ayuv : 1; 102 } pixel_format_support; 103 // max upscaling factor x1000 104 // upscaling factors are always >= 1 105 // for example, 1080p -> 8K is 4.0, or 4000 raw value 106 struct { 107 uint32_t argb8888; 108 uint32_t nv12; 109 uint32_t fp16; 110 } max_upscale_factor; 111 // max downscale factor x1000 112 // downscale factors are always <= 1 113 // for example, 8K -> 1080p is 0.25, or 250 raw value 114 struct { 115 uint32_t argb8888; 116 uint32_t nv12; 117 uint32_t fp16; 118 } max_downscale_factor; 119 // minimal width/height 120 uint32_t min_width; 121 uint32_t min_height; 122 }; 123 124 /** 125 * DOC: color-management-caps 126 * 127 * **Color management caps (DPP and MPC)** 128 * 129 * Modules/color calculates various color operations which are translated to 130 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 131 * DCN1, every new generation comes with fairly major differences in color 132 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 133 * decide mapping to HW block based on logical capabilities. 134 */ 135 136 /** 137 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 138 * @srgb: RGB color space transfer func 139 * @bt2020: BT.2020 transfer func 140 * @gamma2_2: standard gamma 141 * @pq: perceptual quantizer transfer function 142 * @hlg: hybrid log–gamma transfer function 143 */ 144 struct rom_curve_caps { 145 uint16_t srgb : 1; 146 uint16_t bt2020 : 1; 147 uint16_t gamma2_2 : 1; 148 uint16_t pq : 1; 149 uint16_t hlg : 1; 150 }; 151 152 /** 153 * struct dpp_color_caps - color pipeline capabilities for display pipe and 154 * plane blocks 155 * 156 * @dcn_arch: all DCE generations treated the same 157 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 158 * just plain 256-entry lookup 159 * @icsc: input color space conversion 160 * @dgam_ram: programmable degamma LUT 161 * @post_csc: post color space conversion, before gamut remap 162 * @gamma_corr: degamma correction 163 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 164 * with MPC by setting mpc:shared_3d_lut flag 165 * @ogam_ram: programmable out/blend gamma LUT 166 * @ocsc: output color space conversion 167 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 168 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 169 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 170 * 171 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 172 */ 173 struct dpp_color_caps { 174 uint16_t dcn_arch : 1; 175 uint16_t input_lut_shared : 1; 176 uint16_t icsc : 1; 177 uint16_t dgam_ram : 1; 178 uint16_t post_csc : 1; 179 uint16_t gamma_corr : 1; 180 uint16_t hw_3d_lut : 1; 181 uint16_t ogam_ram : 1; 182 uint16_t ocsc : 1; 183 uint16_t dgam_rom_for_yuv : 1; 184 struct rom_curve_caps dgam_rom_caps; 185 struct rom_curve_caps ogam_rom_caps; 186 }; 187 188 /** 189 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 190 * plane combined blocks 191 * 192 * @gamut_remap: color transformation matrix 193 * @ogam_ram: programmable out gamma LUT 194 * @ocsc: output color space conversion matrix 195 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 196 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 197 * instance 198 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 199 */ 200 struct mpc_color_caps { 201 uint16_t gamut_remap : 1; 202 uint16_t ogam_ram : 1; 203 uint16_t ocsc : 1; 204 uint16_t num_3dluts : 3; 205 uint16_t shared_3d_lut:1; 206 struct rom_curve_caps ogam_rom_caps; 207 }; 208 209 /** 210 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 211 * @dpp: color pipes caps for DPP 212 * @mpc: color pipes caps for MPC 213 */ 214 struct dc_color_caps { 215 struct dpp_color_caps dpp; 216 struct mpc_color_caps mpc; 217 }; 218 219 struct dc_dmub_caps { 220 bool psr; 221 bool mclk_sw; 222 bool subvp_psr; 223 bool gecc_enable; 224 uint8_t fams_ver; 225 }; 226 227 struct dc_caps { 228 uint32_t max_streams; 229 uint32_t max_links; 230 uint32_t max_audios; 231 uint32_t max_slave_planes; 232 uint32_t max_slave_yuv_planes; 233 uint32_t max_slave_rgb_planes; 234 uint32_t max_planes; 235 uint32_t max_downscale_ratio; 236 uint32_t i2c_speed_in_khz; 237 uint32_t i2c_speed_in_khz_hdcp; 238 uint32_t dmdata_alloc_size; 239 unsigned int max_cursor_size; 240 unsigned int max_video_width; 241 /* 242 * max video plane width that can be safely assumed to be always 243 * supported by single DPP pipe. 244 */ 245 unsigned int max_optimizable_video_width; 246 unsigned int min_horizontal_blanking_period; 247 int linear_pitch_alignment; 248 bool dcc_const_color; 249 bool dynamic_audio; 250 bool is_apu; 251 bool dual_link_dvi; 252 bool post_blend_color_processing; 253 bool force_dp_tps4_for_cp2520; 254 bool disable_dp_clk_share; 255 bool psp_setup_panel_mode; 256 bool extended_aux_timeout_support; 257 bool dmcub_support; 258 bool zstate_support; 259 bool ips_support; 260 uint32_t num_of_internal_disp; 261 enum dp_protocol_version max_dp_protocol_version; 262 unsigned int mall_size_per_mem_channel; 263 unsigned int mall_size_total; 264 unsigned int cursor_cache_size; 265 struct dc_plane_cap planes[MAX_PLANES]; 266 struct dc_color_caps color; 267 struct dc_dmub_caps dmub_caps; 268 bool dp_hpo; 269 bool dp_hdmi21_pcon_support; 270 bool edp_dsc_support; 271 bool vbios_lttpr_aware; 272 bool vbios_lttpr_enable; 273 uint32_t max_otg_num; 274 uint32_t max_cab_allocation_bytes; 275 uint32_t cache_line_size; 276 uint32_t cache_num_ways; 277 uint16_t subvp_fw_processing_delay_us; 278 uint8_t subvp_drr_max_vblank_margin_us; 279 uint16_t subvp_prefetch_end_to_mall_start_us; 280 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 281 uint16_t subvp_pstate_allow_width_us; 282 uint16_t subvp_vertical_int_margin_us; 283 bool seamless_odm; 284 uint32_t max_v_total; 285 uint32_t max_disp_clock_khz_at_vmin; 286 uint8_t subvp_drr_vblank_start_margin_us; 287 }; 288 289 struct dc_bug_wa { 290 bool no_connect_phy_config; 291 bool dedcn20_305_wa; 292 bool skip_clock_update; 293 bool lt_early_cr_pattern; 294 struct { 295 uint8_t uclk : 1; 296 uint8_t fclk : 1; 297 uint8_t dcfclk : 1; 298 uint8_t dcfclk_ds: 1; 299 } clock_update_disable_mask; 300 }; 301 struct dc_dcc_surface_param { 302 struct dc_size surface_size; 303 enum surface_pixel_format format; 304 enum swizzle_mode_values swizzle_mode; 305 enum dc_scan_direction scan; 306 }; 307 308 struct dc_dcc_setting { 309 unsigned int max_compressed_blk_size; 310 unsigned int max_uncompressed_blk_size; 311 bool independent_64b_blks; 312 //These bitfields to be used starting with DCN 3.0 313 struct { 314 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 315 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 316 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 317 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 318 } dcc_controls; 319 }; 320 321 struct dc_surface_dcc_cap { 322 union { 323 struct { 324 struct dc_dcc_setting rgb; 325 } grph; 326 327 struct { 328 struct dc_dcc_setting luma; 329 struct dc_dcc_setting chroma; 330 } video; 331 }; 332 333 bool capable; 334 bool const_color_support; 335 }; 336 337 struct dc_static_screen_params { 338 struct { 339 bool force_trigger; 340 bool cursor_update; 341 bool surface_update; 342 bool overlay_update; 343 } triggers; 344 unsigned int num_frames; 345 }; 346 347 348 /* Surface update type is used by dc_update_surfaces_and_stream 349 * The update type is determined at the very beginning of the function based 350 * on parameters passed in and decides how much programming (or updating) is 351 * going to be done during the call. 352 * 353 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 354 * logical calculations or hardware register programming. This update MUST be 355 * ISR safe on windows. Currently fast update will only be used to flip surface 356 * address. 357 * 358 * UPDATE_TYPE_MED is used for slower updates which require significant hw 359 * re-programming however do not affect bandwidth consumption or clock 360 * requirements. At present, this is the level at which front end updates 361 * that do not require us to run bw_calcs happen. These are in/out transfer func 362 * updates, viewport offset changes, recout size changes and pixel depth changes. 363 * This update can be done at ISR, but we want to minimize how often this happens. 364 * 365 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 366 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 367 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 368 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 369 * a full update. This cannot be done at ISR level and should be a rare event. 370 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 371 * underscan we don't expect to see this call at all. 372 */ 373 374 enum surface_update_type { 375 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 376 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 377 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 378 }; 379 380 /* Forward declaration*/ 381 struct dc; 382 struct dc_plane_state; 383 struct dc_state; 384 385 386 struct dc_cap_funcs { 387 bool (*get_dcc_compression_cap)(const struct dc *dc, 388 const struct dc_dcc_surface_param *input, 389 struct dc_surface_dcc_cap *output); 390 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 391 }; 392 393 struct link_training_settings; 394 395 union allow_lttpr_non_transparent_mode { 396 struct { 397 bool DP1_4A : 1; 398 bool DP2_0 : 1; 399 } bits; 400 unsigned char raw; 401 }; 402 403 /* Structure to hold configuration flags set by dm at dc creation. */ 404 struct dc_config { 405 bool gpu_vm_support; 406 bool disable_disp_pll_sharing; 407 bool fbc_support; 408 bool disable_fractional_pwm; 409 bool allow_seamless_boot_optimization; 410 bool seamless_boot_edp_requested; 411 bool edp_not_connected; 412 bool edp_no_power_sequencing; 413 bool force_enum_edp; 414 bool forced_clocks; 415 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 416 bool multi_mon_pp_mclk_switch; 417 bool disable_dmcu; 418 bool enable_4to1MPC; 419 bool enable_windowed_mpo_odm; 420 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 421 uint32_t allow_edp_hotplug_detection; 422 bool clamp_min_dcfclk; 423 uint64_t vblank_alignment_dto_params; 424 uint8_t vblank_alignment_max_frame_time_diff; 425 bool is_asymmetric_memory; 426 bool is_single_rank_dimm; 427 bool is_vmin_only_asic; 428 bool use_pipe_ctx_sync_logic; 429 bool ignore_dpref_ss; 430 bool enable_mipi_converter_optimization; 431 bool use_default_clock_table; 432 bool force_bios_enable_lttpr; 433 uint8_t force_bios_fixed_vs; 434 int sdpif_request_limit_words_per_umc; 435 bool dc_mode_clk_limit_support; 436 bool EnableMinDispClkODM; 437 bool enable_auto_dpm_test_logs; 438 unsigned int disable_ips; 439 unsigned int disable_ips_in_vpb; 440 bool usb4_bw_alloc_support; 441 bool allow_0_dtb_clk; 442 bool use_assr_psp_message; 443 bool support_edp0_on_dp1; 444 }; 445 446 enum visual_confirm { 447 VISUAL_CONFIRM_DISABLE = 0, 448 VISUAL_CONFIRM_SURFACE = 1, 449 VISUAL_CONFIRM_HDR = 2, 450 VISUAL_CONFIRM_MPCTREE = 4, 451 VISUAL_CONFIRM_PSR = 5, 452 VISUAL_CONFIRM_SWAPCHAIN = 6, 453 VISUAL_CONFIRM_FAMS = 7, 454 VISUAL_CONFIRM_SWIZZLE = 9, 455 VISUAL_CONFIRM_REPLAY = 12, 456 VISUAL_CONFIRM_SUBVP = 14, 457 VISUAL_CONFIRM_MCLK_SWITCH = 16, 458 }; 459 460 enum dc_psr_power_opts { 461 psr_power_opt_invalid = 0x0, 462 psr_power_opt_smu_opt_static_screen = 0x1, 463 psr_power_opt_z10_static_screen = 0x10, 464 psr_power_opt_ds_disable_allow = 0x100, 465 }; 466 467 enum dml_hostvm_override_opts { 468 DML_HOSTVM_NO_OVERRIDE = 0x0, 469 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 470 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 471 }; 472 473 enum dc_replay_power_opts { 474 replay_power_opt_invalid = 0x0, 475 replay_power_opt_smu_opt_static_screen = 0x1, 476 replay_power_opt_z10_static_screen = 0x10, 477 }; 478 479 enum dcc_option { 480 DCC_ENABLE = 0, 481 DCC_DISABLE = 1, 482 DCC_HALF_REQ_DISALBE = 2, 483 }; 484 485 /** 486 * enum pipe_split_policy - Pipe split strategy supported by DCN 487 * 488 * This enum is used to define the pipe split policy supported by DCN. By 489 * default, DC favors MPC_SPLIT_DYNAMIC. 490 */ 491 enum pipe_split_policy { 492 /** 493 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 494 * pipe in order to bring the best trade-off between performance and 495 * power consumption. This is the recommended option. 496 */ 497 MPC_SPLIT_DYNAMIC = 0, 498 499 /** 500 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 501 * try any sort of split optimization. 502 */ 503 MPC_SPLIT_AVOID = 1, 504 505 /** 506 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 507 * optimize the pipe utilization when using a single display; if the 508 * user connects to a second display, DC will avoid pipe split. 509 */ 510 MPC_SPLIT_AVOID_MULT_DISP = 2, 511 }; 512 513 enum wm_report_mode { 514 WM_REPORT_DEFAULT = 0, 515 WM_REPORT_OVERRIDE = 1, 516 }; 517 enum dtm_pstate{ 518 dtm_level_p0 = 0,/*highest voltage*/ 519 dtm_level_p1, 520 dtm_level_p2, 521 dtm_level_p3, 522 dtm_level_p4,/*when active_display_count = 0*/ 523 }; 524 525 enum dcn_pwr_state { 526 DCN_PWR_STATE_UNKNOWN = -1, 527 DCN_PWR_STATE_MISSION_MODE = 0, 528 DCN_PWR_STATE_LOW_POWER = 3, 529 }; 530 531 enum dcn_zstate_support_state { 532 DCN_ZSTATE_SUPPORT_UNKNOWN, 533 DCN_ZSTATE_SUPPORT_ALLOW, 534 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 535 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 536 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 537 DCN_ZSTATE_SUPPORT_DISALLOW, 538 }; 539 540 /* 541 * struct dc_clocks - DC pipe clocks 542 * 543 * For any clocks that may differ per pipe only the max is stored in this 544 * structure 545 */ 546 struct dc_clocks { 547 int dispclk_khz; 548 int actual_dispclk_khz; 549 int dppclk_khz; 550 int actual_dppclk_khz; 551 int disp_dpp_voltage_level_khz; 552 int dcfclk_khz; 553 int socclk_khz; 554 int dcfclk_deep_sleep_khz; 555 int fclk_khz; 556 int phyclk_khz; 557 int dramclk_khz; 558 bool p_state_change_support; 559 enum dcn_zstate_support_state zstate_support; 560 bool dtbclk_en; 561 int ref_dtbclk_khz; 562 bool fclk_p_state_change_support; 563 enum dcn_pwr_state pwr_state; 564 /* 565 * Elements below are not compared for the purposes of 566 * optimization required 567 */ 568 bool prev_p_state_change_support; 569 bool fclk_prev_p_state_change_support; 570 int num_ways; 571 572 /* 573 * @fw_based_mclk_switching 574 * 575 * DC has a mechanism that leverage the variable refresh rate to switch 576 * memory clock in cases that we have a large latency to achieve the 577 * memory clock change and a short vblank window. DC has some 578 * requirements to enable this feature, and this field describes if the 579 * system support or not such a feature. 580 */ 581 bool fw_based_mclk_switching; 582 bool fw_based_mclk_switching_shut_down; 583 int prev_num_ways; 584 enum dtm_pstate dtm_level; 585 int max_supported_dppclk_khz; 586 int max_supported_dispclk_khz; 587 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 588 int bw_dispclk_khz; 589 }; 590 591 struct dc_bw_validation_profile { 592 bool enable; 593 594 unsigned long long total_ticks; 595 unsigned long long voltage_level_ticks; 596 unsigned long long watermark_ticks; 597 unsigned long long rq_dlg_ticks; 598 599 unsigned long long total_count; 600 unsigned long long skip_fast_count; 601 unsigned long long skip_pass_count; 602 unsigned long long skip_fail_count; 603 }; 604 605 #define BW_VAL_TRACE_SETUP() \ 606 unsigned long long end_tick = 0; \ 607 unsigned long long voltage_level_tick = 0; \ 608 unsigned long long watermark_tick = 0; \ 609 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 610 dm_get_timestamp(dc->ctx) : 0 611 612 #define BW_VAL_TRACE_COUNT() \ 613 if (dc->debug.bw_val_profile.enable) \ 614 dc->debug.bw_val_profile.total_count++ 615 616 #define BW_VAL_TRACE_SKIP(status) \ 617 if (dc->debug.bw_val_profile.enable) { \ 618 if (!voltage_level_tick) \ 619 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 620 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 621 } 622 623 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 624 if (dc->debug.bw_val_profile.enable) \ 625 voltage_level_tick = dm_get_timestamp(dc->ctx) 626 627 #define BW_VAL_TRACE_END_WATERMARKS() \ 628 if (dc->debug.bw_val_profile.enable) \ 629 watermark_tick = dm_get_timestamp(dc->ctx) 630 631 #define BW_VAL_TRACE_FINISH() \ 632 if (dc->debug.bw_val_profile.enable) { \ 633 end_tick = dm_get_timestamp(dc->ctx); \ 634 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 635 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 636 if (watermark_tick) { \ 637 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 638 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 639 } \ 640 } 641 642 union mem_low_power_enable_options { 643 struct { 644 bool vga: 1; 645 bool i2c: 1; 646 bool dmcu: 1; 647 bool dscl: 1; 648 bool cm: 1; 649 bool mpc: 1; 650 bool optc: 1; 651 bool vpg: 1; 652 bool afmt: 1; 653 } bits; 654 uint32_t u32All; 655 }; 656 657 union root_clock_optimization_options { 658 struct { 659 bool dpp: 1; 660 bool dsc: 1; 661 bool hdmistream: 1; 662 bool hdmichar: 1; 663 bool dpstream: 1; 664 bool symclk32_se: 1; 665 bool symclk32_le: 1; 666 bool symclk_fe: 1; 667 bool physymclk: 1; 668 bool dpiasymclk: 1; 669 uint32_t reserved: 22; 670 } bits; 671 uint32_t u32All; 672 }; 673 674 union fine_grain_clock_gating_enable_options { 675 struct { 676 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 677 bool dchub : 1; /* Display controller hub */ 678 bool dchubbub : 1; 679 bool dpp : 1; /* Display pipes and planes */ 680 bool opp : 1; /* Output pixel processing */ 681 bool optc : 1; /* Output pipe timing combiner */ 682 bool dio : 1; /* Display output */ 683 bool dwb : 1; /* Display writeback */ 684 bool mmhubbub : 1; /* Multimedia hub */ 685 bool dmu : 1; /* Display core management unit */ 686 bool az : 1; /* Azalia */ 687 bool dchvm : 1; 688 bool dsc : 1; /* Display stream compression */ 689 690 uint32_t reserved : 19; 691 } bits; 692 uint32_t u32All; 693 }; 694 695 enum pg_hw_pipe_resources { 696 PG_HUBP = 0, 697 PG_DPP, 698 PG_DSC, 699 PG_MPCC, 700 PG_OPP, 701 PG_OPTC, 702 PG_DPSTREAM, 703 PG_HDMISTREAM, 704 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 705 }; 706 707 enum pg_hw_resources { 708 PG_DCCG = 0, 709 PG_DCIO, 710 PG_DIO, 711 PG_DCHUBBUB, 712 PG_DCHVM, 713 PG_DWB, 714 PG_HPO, 715 PG_HW_RESOURCES_NUM_ELEMENT 716 }; 717 718 struct pg_block_update { 719 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 720 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 721 }; 722 723 union dpia_debug_options { 724 struct { 725 uint32_t disable_dpia:1; /* bit 0 */ 726 uint32_t force_non_lttpr:1; /* bit 1 */ 727 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 728 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 729 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 730 uint32_t reserved:27; 731 } bits; 732 uint32_t raw; 733 }; 734 735 /* AUX wake work around options 736 * 0: enable/disable work around 737 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 738 * 15-2: reserved 739 * 31-16: timeout in ms 740 */ 741 union aux_wake_wa_options { 742 struct { 743 uint32_t enable_wa : 1; 744 uint32_t use_default_timeout : 1; 745 uint32_t rsvd: 14; 746 uint32_t timeout_ms : 16; 747 } bits; 748 uint32_t raw; 749 }; 750 751 struct dc_debug_data { 752 uint32_t ltFailCount; 753 uint32_t i2cErrorCount; 754 uint32_t auxErrorCount; 755 }; 756 757 struct dc_phy_addr_space_config { 758 struct { 759 uint64_t start_addr; 760 uint64_t end_addr; 761 uint64_t fb_top; 762 uint64_t fb_offset; 763 uint64_t fb_base; 764 uint64_t agp_top; 765 uint64_t agp_bot; 766 uint64_t agp_base; 767 } system_aperture; 768 769 struct { 770 uint64_t page_table_start_addr; 771 uint64_t page_table_end_addr; 772 uint64_t page_table_base_addr; 773 bool base_addr_is_mc_addr; 774 } gart_config; 775 776 bool valid; 777 bool is_hvm_enabled; 778 uint64_t page_table_default_page_addr; 779 }; 780 781 struct dc_virtual_addr_space_config { 782 uint64_t page_table_base_addr; 783 uint64_t page_table_start_addr; 784 uint64_t page_table_end_addr; 785 uint32_t page_table_block_size_in_bytes; 786 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 787 }; 788 789 struct dc_bounding_box_overrides { 790 int sr_exit_time_ns; 791 int sr_enter_plus_exit_time_ns; 792 int sr_exit_z8_time_ns; 793 int sr_enter_plus_exit_z8_time_ns; 794 int urgent_latency_ns; 795 int percent_of_ideal_drambw; 796 int dram_clock_change_latency_ns; 797 int dummy_clock_change_latency_ns; 798 int fclk_clock_change_latency_ns; 799 /* This forces a hard min on the DCFCLK we use 800 * for DML. Unlike the debug option for forcing 801 * DCFCLK, this override affects watermark calculations 802 */ 803 int min_dcfclk_mhz; 804 }; 805 806 struct dc_state; 807 struct resource_pool; 808 struct dce_hwseq; 809 struct link_service; 810 811 /* 812 * struct dc_debug_options - DC debug struct 813 * 814 * This struct provides a simple mechanism for developers to change some 815 * configurations, enable/disable features, and activate extra debug options. 816 * This can be very handy to narrow down whether some specific feature is 817 * causing an issue or not. 818 */ 819 struct dc_debug_options { 820 bool native422_support; 821 bool disable_dsc; 822 enum visual_confirm visual_confirm; 823 int visual_confirm_rect_height; 824 825 bool sanity_checks; 826 bool max_disp_clk; 827 bool surface_trace; 828 bool timing_trace; 829 bool clock_trace; 830 bool validation_trace; 831 bool bandwidth_calcs_trace; 832 int max_downscale_src_width; 833 834 /* stutter efficiency related */ 835 bool disable_stutter; 836 bool use_max_lb; 837 enum dcc_option disable_dcc; 838 839 /* 840 * @pipe_split_policy: Define which pipe split policy is used by the 841 * display core. 842 */ 843 enum pipe_split_policy pipe_split_policy; 844 bool force_single_disp_pipe_split; 845 bool voltage_align_fclk; 846 bool disable_min_fclk; 847 848 bool disable_dfs_bypass; 849 bool disable_dpp_power_gate; 850 bool disable_hubp_power_gate; 851 bool disable_dsc_power_gate; 852 bool disable_optc_power_gate; 853 bool disable_hpo_power_gate; 854 int dsc_min_slice_height_override; 855 int dsc_bpp_increment_div; 856 bool disable_pplib_wm_range; 857 enum wm_report_mode pplib_wm_report_mode; 858 unsigned int min_disp_clk_khz; 859 unsigned int min_dpp_clk_khz; 860 unsigned int min_dram_clk_khz; 861 int sr_exit_time_dpm0_ns; 862 int sr_enter_plus_exit_time_dpm0_ns; 863 int sr_exit_time_ns; 864 int sr_enter_plus_exit_time_ns; 865 int sr_exit_z8_time_ns; 866 int sr_enter_plus_exit_z8_time_ns; 867 int urgent_latency_ns; 868 uint32_t underflow_assert_delay_us; 869 int percent_of_ideal_drambw; 870 int dram_clock_change_latency_ns; 871 bool optimized_watermark; 872 int always_scale; 873 bool disable_pplib_clock_request; 874 bool disable_clock_gate; 875 bool disable_mem_low_power; 876 bool pstate_enabled; 877 bool disable_dmcu; 878 bool force_abm_enable; 879 bool disable_stereo_support; 880 bool vsr_support; 881 bool performance_trace; 882 bool az_endpoint_mute_only; 883 bool always_use_regamma; 884 bool recovery_enabled; 885 bool avoid_vbios_exec_table; 886 bool scl_reset_length10; 887 bool hdmi20_disable; 888 bool skip_detection_link_training; 889 uint32_t edid_read_retry_times; 890 unsigned int force_odm_combine; //bit vector based on otg inst 891 unsigned int seamless_boot_odm_combine; 892 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 893 int minimum_z8_residency_time; 894 int minimum_z10_residency_time; 895 bool disable_z9_mpc; 896 unsigned int force_fclk_khz; 897 bool enable_tri_buf; 898 bool dmub_offload_enabled; 899 bool dmcub_emulation; 900 bool disable_idle_power_optimizations; 901 unsigned int mall_size_override; 902 unsigned int mall_additional_timer_percent; 903 bool mall_error_as_fatal; 904 bool dmub_command_table; /* for testing only */ 905 struct dc_bw_validation_profile bw_val_profile; 906 bool disable_fec; 907 bool disable_48mhz_pwrdwn; 908 /* This forces a hard min on the DCFCLK requested to SMU/PP 909 * watermarks are not affected. 910 */ 911 unsigned int force_min_dcfclk_mhz; 912 int dwb_fi_phase; 913 bool disable_timing_sync; 914 bool cm_in_bypass; 915 int force_clock_mode;/*every mode change.*/ 916 917 bool disable_dram_clock_change_vactive_support; 918 bool validate_dml_output; 919 bool enable_dmcub_surface_flip; 920 bool usbc_combo_phy_reset_wa; 921 bool enable_dram_clock_change_one_display_vactive; 922 /* TODO - remove once tested */ 923 bool legacy_dp2_lt; 924 bool set_mst_en_for_sst; 925 bool disable_uhbr; 926 bool force_dp2_lt_fallback_method; 927 bool ignore_cable_id; 928 union mem_low_power_enable_options enable_mem_low_power; 929 union root_clock_optimization_options root_clock_optimization; 930 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 931 bool hpo_optimization; 932 bool force_vblank_alignment; 933 934 /* Enable dmub aux for legacy ddc */ 935 bool enable_dmub_aux_for_legacy_ddc; 936 bool disable_fams; 937 bool disable_fams_gaming; 938 /* FEC/PSR1 sequence enable delay in 100us */ 939 uint8_t fec_enable_delay_in100us; 940 bool enable_driver_sequence_debug; 941 enum det_size crb_alloc_policy; 942 int crb_alloc_policy_min_disp_count; 943 bool disable_z10; 944 bool enable_z9_disable_interface; 945 bool psr_skip_crtc_disable; 946 union dpia_debug_options dpia_debug; 947 bool disable_fixed_vs_aux_timeout_wa; 948 uint32_t fixed_vs_aux_delay_config_wa; 949 bool force_disable_subvp; 950 bool force_subvp_mclk_switch; 951 bool allow_sw_cursor_fallback; 952 unsigned int force_subvp_num_ways; 953 unsigned int force_mall_ss_num_ways; 954 bool alloc_extra_way_for_cursor; 955 uint32_t subvp_extra_lines; 956 bool force_usr_allow; 957 /* uses value at boot and disables switch */ 958 bool disable_dtb_ref_clk_switch; 959 bool extended_blank_optimization; 960 union aux_wake_wa_options aux_wake_wa; 961 uint32_t mst_start_top_delay; 962 uint8_t psr_power_use_phy_fsm; 963 enum dml_hostvm_override_opts dml_hostvm_override; 964 bool dml_disallow_alternate_prefetch_modes; 965 bool use_legacy_soc_bb_mechanism; 966 bool exit_idle_opt_for_cursor_updates; 967 bool using_dml2; 968 bool enable_single_display_2to1_odm_policy; 969 bool enable_double_buffered_dsc_pg_support; 970 bool enable_dp_dig_pixel_rate_div_policy; 971 enum lttpr_mode lttpr_mode_override; 972 unsigned int dsc_delay_factor_wa_x1000; 973 unsigned int min_prefetch_in_strobe_ns; 974 bool disable_unbounded_requesting; 975 bool dig_fifo_off_in_blank; 976 bool override_dispclk_programming; 977 bool otg_crc_db; 978 bool disallow_dispclk_dppclk_ds; 979 bool disable_fpo_optimizations; 980 bool support_eDP1_5; 981 uint32_t fpo_vactive_margin_us; 982 bool disable_fpo_vactive; 983 bool disable_boot_optimizations; 984 bool override_odm_optimization; 985 bool minimize_dispclk_using_odm; 986 bool disable_subvp_high_refresh; 987 bool disable_dp_plus_plus_wa; 988 uint32_t fpo_vactive_min_active_margin_us; 989 uint32_t fpo_vactive_max_blank_us; 990 bool enable_hpo_pg_support; 991 bool enable_legacy_fast_update; 992 bool disable_dc_mode_overwrite; 993 bool replay_skip_crtc_disabled; 994 bool ignore_pg;/*do nothing, let pmfw control it*/ 995 bool psp_disabled_wa; 996 unsigned int ips2_eval_delay_us; 997 unsigned int ips2_entry_delay_us; 998 bool optimize_ips_handshake; 999 bool disable_dmub_reallow_idle; 1000 bool disable_timeout; 1001 bool disable_extblankadj; 1002 bool enable_idle_reg_checks; 1003 unsigned int static_screen_wait_frames; 1004 bool force_chroma_subsampling_1tap; 1005 bool disable_422_left_edge_pixel; 1006 unsigned int force_cositing; 1007 }; 1008 1009 1010 /* Generic structure that can be used to query properties of DC. More fields 1011 * can be added as required. 1012 */ 1013 struct dc_current_properties { 1014 unsigned int cursor_size_limit; 1015 }; 1016 1017 enum frame_buffer_mode { 1018 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1019 FRAME_BUFFER_MODE_ZFB_ONLY, 1020 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1021 } ; 1022 1023 struct dchub_init_data { 1024 int64_t zfb_phys_addr_base; 1025 int64_t zfb_mc_base_addr; 1026 uint64_t zfb_size_in_byte; 1027 enum frame_buffer_mode fb_mode; 1028 bool dchub_initialzied; 1029 bool dchub_info_valid; 1030 }; 1031 1032 struct dc_init_data { 1033 struct hw_asic_id asic_id; 1034 void *driver; /* ctx */ 1035 struct cgs_device *cgs_device; 1036 struct dc_bounding_box_overrides bb_overrides; 1037 1038 int num_virtual_links; 1039 /* 1040 * If 'vbios_override' not NULL, it will be called instead 1041 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1042 */ 1043 struct dc_bios *vbios_override; 1044 enum dce_environment dce_environment; 1045 1046 struct dmub_offload_funcs *dmub_if; 1047 struct dc_reg_helper_state *dmub_offload; 1048 1049 struct dc_config flags; 1050 uint64_t log_mask; 1051 1052 struct dpcd_vendor_signature vendor_signature; 1053 bool force_smu_not_present; 1054 /* 1055 * IP offset for run time initializaion of register addresses 1056 * 1057 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1058 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1059 * before them. 1060 */ 1061 uint32_t *dcn_reg_offsets; 1062 uint32_t *nbio_reg_offsets; 1063 uint32_t *clk_reg_offsets; 1064 }; 1065 1066 struct dc_callback_init { 1067 struct cp_psp cp_psp; 1068 }; 1069 1070 struct dc *dc_create(const struct dc_init_data *init_params); 1071 void dc_hardware_init(struct dc *dc); 1072 1073 int dc_get_vmid_use_vector(struct dc *dc); 1074 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1075 /* Returns the number of vmids supported */ 1076 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1077 void dc_init_callbacks(struct dc *dc, 1078 const struct dc_callback_init *init_params); 1079 void dc_deinit_callbacks(struct dc *dc); 1080 void dc_destroy(struct dc **dc); 1081 1082 /* Surface Interfaces */ 1083 1084 enum { 1085 TRANSFER_FUNC_POINTS = 1025 1086 }; 1087 1088 struct dc_hdr_static_metadata { 1089 /* display chromaticities and white point in units of 0.00001 */ 1090 unsigned int chromaticity_green_x; 1091 unsigned int chromaticity_green_y; 1092 unsigned int chromaticity_blue_x; 1093 unsigned int chromaticity_blue_y; 1094 unsigned int chromaticity_red_x; 1095 unsigned int chromaticity_red_y; 1096 unsigned int chromaticity_white_point_x; 1097 unsigned int chromaticity_white_point_y; 1098 1099 uint32_t min_luminance; 1100 uint32_t max_luminance; 1101 uint32_t maximum_content_light_level; 1102 uint32_t maximum_frame_average_light_level; 1103 }; 1104 1105 enum dc_transfer_func_type { 1106 TF_TYPE_PREDEFINED, 1107 TF_TYPE_DISTRIBUTED_POINTS, 1108 TF_TYPE_BYPASS, 1109 TF_TYPE_HWPWL 1110 }; 1111 1112 struct dc_transfer_func_distributed_points { 1113 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1114 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1115 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1116 1117 uint16_t end_exponent; 1118 uint16_t x_point_at_y1_red; 1119 uint16_t x_point_at_y1_green; 1120 uint16_t x_point_at_y1_blue; 1121 }; 1122 1123 enum dc_transfer_func_predefined { 1124 TRANSFER_FUNCTION_SRGB, 1125 TRANSFER_FUNCTION_BT709, 1126 TRANSFER_FUNCTION_PQ, 1127 TRANSFER_FUNCTION_LINEAR, 1128 TRANSFER_FUNCTION_UNITY, 1129 TRANSFER_FUNCTION_HLG, 1130 TRANSFER_FUNCTION_HLG12, 1131 TRANSFER_FUNCTION_GAMMA22, 1132 TRANSFER_FUNCTION_GAMMA24, 1133 TRANSFER_FUNCTION_GAMMA26 1134 }; 1135 1136 1137 struct dc_transfer_func { 1138 struct kref refcount; 1139 enum dc_transfer_func_type type; 1140 enum dc_transfer_func_predefined tf; 1141 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1142 uint32_t sdr_ref_white_level; 1143 union { 1144 struct pwl_params pwl; 1145 struct dc_transfer_func_distributed_points tf_pts; 1146 }; 1147 }; 1148 1149 1150 union dc_3dlut_state { 1151 struct { 1152 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1153 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1154 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1155 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1156 uint32_t mpc_rmu1_mux:4; 1157 uint32_t mpc_rmu2_mux:4; 1158 uint32_t reserved:15; 1159 } bits; 1160 uint32_t raw; 1161 }; 1162 1163 1164 struct dc_3dlut { 1165 struct kref refcount; 1166 struct tetrahedral_params lut_3d; 1167 struct fixed31_32 hdr_multiplier; 1168 union dc_3dlut_state state; 1169 }; 1170 /* 1171 * This structure is filled in by dc_surface_get_status and contains 1172 * the last requested address and the currently active address so the called 1173 * can determine if there are any outstanding flips 1174 */ 1175 struct dc_plane_status { 1176 struct dc_plane_address requested_address; 1177 struct dc_plane_address current_address; 1178 bool is_flip_pending; 1179 bool is_right_eye; 1180 }; 1181 1182 union surface_update_flags { 1183 1184 struct { 1185 uint32_t addr_update:1; 1186 /* Medium updates */ 1187 uint32_t dcc_change:1; 1188 uint32_t color_space_change:1; 1189 uint32_t horizontal_mirror_change:1; 1190 uint32_t per_pixel_alpha_change:1; 1191 uint32_t global_alpha_change:1; 1192 uint32_t hdr_mult:1; 1193 uint32_t rotation_change:1; 1194 uint32_t swizzle_change:1; 1195 uint32_t scaling_change:1; 1196 uint32_t clip_size_change: 1; 1197 uint32_t position_change:1; 1198 uint32_t in_transfer_func_change:1; 1199 uint32_t input_csc_change:1; 1200 uint32_t coeff_reduction_change:1; 1201 uint32_t output_tf_change:1; 1202 uint32_t pixel_format_change:1; 1203 uint32_t plane_size_change:1; 1204 uint32_t gamut_remap_change:1; 1205 1206 /* Full updates */ 1207 uint32_t new_plane:1; 1208 uint32_t bpp_change:1; 1209 uint32_t gamma_change:1; 1210 uint32_t bandwidth_change:1; 1211 uint32_t clock_change:1; 1212 uint32_t stereo_format_change:1; 1213 uint32_t lut_3d:1; 1214 uint32_t tmz_changed:1; 1215 uint32_t full_update:1; 1216 } bits; 1217 1218 uint32_t raw; 1219 }; 1220 1221 #define DC_REMOVE_PLANE_POINTERS 1 1222 1223 struct dc_plane_state { 1224 struct dc_plane_address address; 1225 struct dc_plane_flip_time time; 1226 bool triplebuffer_flips; 1227 struct scaling_taps scaling_quality; 1228 struct rect src_rect; 1229 struct rect dst_rect; 1230 struct rect clip_rect; 1231 1232 struct plane_size plane_size; 1233 union dc_tiling_info tiling_info; 1234 1235 struct dc_plane_dcc_param dcc; 1236 1237 struct dc_gamma gamma_correction; 1238 struct dc_transfer_func in_transfer_func; 1239 struct dc_bias_and_scale *bias_and_scale; 1240 struct dc_csc_transform input_csc_color_matrix; 1241 struct fixed31_32 coeff_reduction_factor; 1242 struct fixed31_32 hdr_mult; 1243 struct colorspace_transform gamut_remap_matrix; 1244 1245 // TODO: No longer used, remove 1246 struct dc_hdr_static_metadata hdr_static_ctx; 1247 1248 enum dc_color_space color_space; 1249 1250 struct dc_3dlut lut3d_func; 1251 struct dc_transfer_func in_shaper_func; 1252 struct dc_transfer_func blend_tf; 1253 1254 struct dc_transfer_func *gamcor_tf; 1255 enum surface_pixel_format format; 1256 enum dc_rotation_angle rotation; 1257 enum plane_stereo_format stereo_format; 1258 1259 bool is_tiling_rotated; 1260 bool per_pixel_alpha; 1261 bool pre_multiplied_alpha; 1262 bool global_alpha; 1263 int global_alpha_value; 1264 bool visible; 1265 bool flip_immediate; 1266 bool horizontal_mirror; 1267 int layer_index; 1268 1269 union surface_update_flags update_flags; 1270 bool flip_int_enabled; 1271 bool skip_manual_trigger; 1272 1273 /* private to DC core */ 1274 struct dc_plane_status status; 1275 struct dc_context *ctx; 1276 1277 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1278 bool force_full_update; 1279 1280 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1281 1282 /* private to dc_surface.c */ 1283 enum dc_irq_source irq_source; 1284 struct kref refcount; 1285 struct tg_color visual_confirm_color; 1286 1287 bool is_statically_allocated; 1288 enum chroma_cositing cositing; 1289 }; 1290 1291 struct dc_plane_info { 1292 struct plane_size plane_size; 1293 union dc_tiling_info tiling_info; 1294 struct dc_plane_dcc_param dcc; 1295 enum surface_pixel_format format; 1296 enum dc_rotation_angle rotation; 1297 enum plane_stereo_format stereo_format; 1298 enum dc_color_space color_space; 1299 bool horizontal_mirror; 1300 bool visible; 1301 bool per_pixel_alpha; 1302 bool pre_multiplied_alpha; 1303 bool global_alpha; 1304 int global_alpha_value; 1305 bool input_csc_enabled; 1306 int layer_index; 1307 enum chroma_cositing cositing; 1308 }; 1309 1310 #include "dc_stream.h" 1311 1312 struct dc_scratch_space { 1313 /* used to temporarily backup plane states of a stream during 1314 * dc update. The reason is that plane states are overwritten 1315 * with surface updates in dc update. Once they are overwritten 1316 * current state is no longer valid. We want to temporarily 1317 * store current value in plane states so we can still recover 1318 * a valid current state during dc update. 1319 */ 1320 struct dc_plane_state plane_states[MAX_SURFACE_NUM]; 1321 1322 struct dc_stream_state stream_state; 1323 }; 1324 1325 struct dc { 1326 struct dc_debug_options debug; 1327 struct dc_versions versions; 1328 struct dc_caps caps; 1329 struct dc_cap_funcs cap_funcs; 1330 struct dc_config config; 1331 struct dc_bounding_box_overrides bb_overrides; 1332 struct dc_bug_wa work_arounds; 1333 struct dc_context *ctx; 1334 struct dc_phy_addr_space_config vm_pa_config; 1335 1336 uint8_t link_count; 1337 struct dc_link *links[MAX_LINKS]; 1338 struct link_service *link_srv; 1339 1340 struct dc_state *current_state; 1341 struct resource_pool *res_pool; 1342 1343 struct clk_mgr *clk_mgr; 1344 1345 /* Display Engine Clock levels */ 1346 struct dm_pp_clock_levels sclk_lvls; 1347 1348 /* Inputs into BW and WM calculations. */ 1349 struct bw_calcs_dceip *bw_dceip; 1350 struct bw_calcs_vbios *bw_vbios; 1351 struct dcn_soc_bounding_box *dcn_soc; 1352 struct dcn_ip_params *dcn_ip; 1353 struct display_mode_lib dml; 1354 1355 /* HW functions */ 1356 struct hw_sequencer_funcs hwss; 1357 struct dce_hwseq *hwseq; 1358 1359 /* Require to optimize clocks and bandwidth for added/removed planes */ 1360 bool optimized_required; 1361 bool wm_optimized_required; 1362 bool idle_optimizations_allowed; 1363 bool enable_c20_dtm_b0; 1364 1365 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1366 1367 /* FBC compressor */ 1368 struct compressor *fbc_compressor; 1369 1370 struct dc_debug_data debug_data; 1371 struct dpcd_vendor_signature vendor_signature; 1372 1373 const char *build_id; 1374 struct vm_helper *vm_helper; 1375 1376 uint32_t *dcn_reg_offsets; 1377 uint32_t *nbio_reg_offsets; 1378 uint32_t *clk_reg_offsets; 1379 1380 /* Scratch memory */ 1381 struct { 1382 struct { 1383 /* 1384 * For matching clock_limits table in driver with table 1385 * from PMFW. 1386 */ 1387 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1388 } update_bw_bounding_box; 1389 struct dc_scratch_space current_state; 1390 struct dc_scratch_space new_state; 1391 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1392 } scratch; 1393 1394 struct dml2_configuration_options dml2_options; 1395 enum dc_acpi_cm_power_state power_state; 1396 1397 }; 1398 1399 struct dc_scaling_info { 1400 struct rect src_rect; 1401 struct rect dst_rect; 1402 struct rect clip_rect; 1403 struct scaling_taps scaling_quality; 1404 }; 1405 1406 struct dc_fast_update { 1407 const struct dc_flip_addrs *flip_addr; 1408 const struct dc_gamma *gamma; 1409 const struct colorspace_transform *gamut_remap_matrix; 1410 const struct dc_csc_transform *input_csc_color_matrix; 1411 const struct fixed31_32 *coeff_reduction_factor; 1412 struct dc_transfer_func *out_transfer_func; 1413 struct dc_csc_transform *output_csc_transform; 1414 }; 1415 1416 struct dc_surface_update { 1417 struct dc_plane_state *surface; 1418 1419 /* isr safe update parameters. null means no updates */ 1420 const struct dc_flip_addrs *flip_addr; 1421 const struct dc_plane_info *plane_info; 1422 const struct dc_scaling_info *scaling_info; 1423 struct fixed31_32 hdr_mult; 1424 /* following updates require alloc/sleep/spin that is not isr safe, 1425 * null means no updates 1426 */ 1427 const struct dc_gamma *gamma; 1428 const struct dc_transfer_func *in_transfer_func; 1429 1430 const struct dc_csc_transform *input_csc_color_matrix; 1431 const struct fixed31_32 *coeff_reduction_factor; 1432 const struct dc_transfer_func *func_shaper; 1433 const struct dc_3dlut *lut3d_func; 1434 const struct dc_transfer_func *blend_tf; 1435 const struct colorspace_transform *gamut_remap_matrix; 1436 }; 1437 1438 /* 1439 * Create a new surface with default parameters; 1440 */ 1441 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1442 void dc_gamma_release(struct dc_gamma **dc_gamma); 1443 struct dc_gamma *dc_create_gamma(void); 1444 1445 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1446 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1447 struct dc_transfer_func *dc_create_transfer_func(void); 1448 1449 struct dc_3dlut *dc_create_3dlut_func(void); 1450 void dc_3dlut_func_release(struct dc_3dlut *lut); 1451 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1452 1453 void dc_post_update_surfaces_to_stream( 1454 struct dc *dc); 1455 1456 #include "dc_stream.h" 1457 1458 /** 1459 * struct dc_validation_set - Struct to store surface/stream associations for validation 1460 */ 1461 struct dc_validation_set { 1462 /** 1463 * @stream: Stream state properties 1464 */ 1465 struct dc_stream_state *stream; 1466 1467 /** 1468 * @plane_states: Surface state 1469 */ 1470 struct dc_plane_state *plane_states[MAX_SURFACES]; 1471 1472 /** 1473 * @plane_count: Total of active planes 1474 */ 1475 uint8_t plane_count; 1476 }; 1477 1478 bool dc_validate_boot_timing(const struct dc *dc, 1479 const struct dc_sink *sink, 1480 struct dc_crtc_timing *crtc_timing); 1481 1482 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1483 1484 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1485 1486 enum dc_status dc_validate_with_context(struct dc *dc, 1487 const struct dc_validation_set set[], 1488 int set_count, 1489 struct dc_state *context, 1490 bool fast_validate); 1491 1492 bool dc_set_generic_gpio_for_stereo(bool enable, 1493 struct gpio_service *gpio_service); 1494 1495 /* 1496 * fast_validate: we return after determining if we can support the new state, 1497 * but before we populate the programming info 1498 */ 1499 enum dc_status dc_validate_global_state( 1500 struct dc *dc, 1501 struct dc_state *new_ctx, 1502 bool fast_validate); 1503 1504 bool dc_acquire_release_mpc_3dlut( 1505 struct dc *dc, bool acquire, 1506 struct dc_stream_state *stream, 1507 struct dc_3dlut **lut, 1508 struct dc_transfer_func **shaper); 1509 1510 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1511 void get_audio_check(struct audio_info *aud_modes, 1512 struct audio_check *aud_chk); 1513 /* 1514 * Set up streams and links associated to drive sinks 1515 * The streams parameter is an absolute set of all active streams. 1516 * 1517 * After this call: 1518 * Phy, Encoder, Timing Generator are programmed and enabled. 1519 * New streams are enabled with blank stream; no memory read. 1520 */ 1521 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1522 1523 1524 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1525 struct dc_stream_state *stream, 1526 int mpcc_inst); 1527 1528 1529 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1530 1531 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1532 1533 /* The function returns minimum bandwidth required to drive a given timing 1534 * return - minimum required timing bandwidth in kbps. 1535 */ 1536 uint32_t dc_bandwidth_in_kbps_from_timing( 1537 const struct dc_crtc_timing *timing, 1538 const enum dc_link_encoding_format link_encoding); 1539 1540 /* Link Interfaces */ 1541 /* 1542 * A link contains one or more sinks and their connected status. 1543 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1544 */ 1545 struct dc_link { 1546 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1547 unsigned int sink_count; 1548 struct dc_sink *local_sink; 1549 unsigned int link_index; 1550 enum dc_connection_type type; 1551 enum signal_type connector_signal; 1552 enum dc_irq_source irq_source_hpd; 1553 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1554 1555 bool is_hpd_filter_disabled; 1556 bool dp_ss_off; 1557 1558 /** 1559 * @link_state_valid: 1560 * 1561 * If there is no link and local sink, this variable should be set to 1562 * false. Otherwise, it should be set to true; usually, the function 1563 * core_link_enable_stream sets this field to true. 1564 */ 1565 bool link_state_valid; 1566 bool aux_access_disabled; 1567 bool sync_lt_in_progress; 1568 bool skip_stream_reenable; 1569 bool is_internal_display; 1570 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1571 bool is_dig_mapping_flexible; 1572 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1573 bool is_hpd_pending; /* Indicates a new received hpd */ 1574 1575 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1576 * for every link training. This is incompatible with DP LL compliance automation, 1577 * which expects the same link settings to be used every retry on a link loss. 1578 * This flag is used to skip the fallback when link loss occurs during automation. 1579 */ 1580 bool skip_fallback_on_link_loss; 1581 1582 bool edp_sink_present; 1583 1584 struct dp_trace dp_trace; 1585 1586 /* caps is the same as reported_link_cap. link_traing use 1587 * reported_link_cap. Will clean up. TODO 1588 */ 1589 struct dc_link_settings reported_link_cap; 1590 struct dc_link_settings verified_link_cap; 1591 struct dc_link_settings cur_link_settings; 1592 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1593 struct dc_link_settings preferred_link_setting; 1594 /* preferred_training_settings are override values that 1595 * come from DM. DM is responsible for the memory 1596 * management of the override pointers. 1597 */ 1598 struct dc_link_training_overrides preferred_training_settings; 1599 struct dp_audio_test_data audio_test_data; 1600 1601 uint8_t ddc_hw_inst; 1602 1603 uint8_t hpd_src; 1604 1605 uint8_t link_enc_hw_inst; 1606 /* DIG link encoder ID. Used as index in link encoder resource pool. 1607 * For links with fixed mapping to DIG, this is not changed after dc_link 1608 * object creation. 1609 */ 1610 enum engine_id eng_id; 1611 enum engine_id dpia_preferred_eng_id; 1612 1613 bool test_pattern_enabled; 1614 /* Pending/Current test pattern are only used to perform and track 1615 * FIXED_VS retimer test pattern/lane adjustment override state. 1616 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1617 * to perform specific lane adjust overrides before setting certain 1618 * PHY test patterns. In cases when lane adjust and set test pattern 1619 * calls are not performed atomically (i.e. performing link training), 1620 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1621 * and current_test_pattern will contain required context for any future 1622 * set pattern/set lane adjust to transition between override state(s). 1623 * */ 1624 enum dp_test_pattern current_test_pattern; 1625 enum dp_test_pattern pending_test_pattern; 1626 1627 union compliance_test_state compliance_test_state; 1628 1629 void *priv; 1630 1631 struct ddc_service *ddc; 1632 1633 enum dp_panel_mode panel_mode; 1634 bool aux_mode; 1635 1636 /* Private to DC core */ 1637 1638 const struct dc *dc; 1639 1640 struct dc_context *ctx; 1641 1642 struct panel_cntl *panel_cntl; 1643 struct link_encoder *link_enc; 1644 struct graphics_object_id link_id; 1645 /* Endpoint type distinguishes display endpoints which do not have entries 1646 * in the BIOS connector table from those that do. Helps when tracking link 1647 * encoder to display endpoint assignments. 1648 */ 1649 enum display_endpoint_type ep_type; 1650 union ddi_channel_mapping ddi_channel_mapping; 1651 struct connector_device_tag_info device_tag; 1652 struct dpcd_caps dpcd_caps; 1653 uint32_t dongle_max_pix_clk; 1654 unsigned short chip_caps; 1655 unsigned int dpcd_sink_count; 1656 struct hdcp_caps hdcp_caps; 1657 enum edp_revision edp_revision; 1658 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1659 1660 struct psr_settings psr_settings; 1661 1662 struct replay_settings replay_settings; 1663 1664 /* Drive settings read from integrated info table */ 1665 struct dc_lane_settings bios_forced_drive_settings; 1666 1667 /* Vendor specific LTTPR workaround variables */ 1668 uint8_t vendor_specific_lttpr_link_rate_wa; 1669 bool apply_vendor_specific_lttpr_link_rate_wa; 1670 1671 /* MST record stream using this link */ 1672 struct link_flags { 1673 bool dp_keep_receiver_powered; 1674 bool dp_skip_DID2; 1675 bool dp_skip_reset_segment; 1676 bool dp_skip_fs_144hz; 1677 bool dp_mot_reset_segment; 1678 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1679 bool dpia_mst_dsc_always_on; 1680 /* Forced DPIA into TBT3 compatibility mode. */ 1681 bool dpia_forced_tbt3_mode; 1682 bool dongle_mode_timing_override; 1683 bool blank_stream_on_ocs_change; 1684 bool read_dpcd204h_on_irq_hpd; 1685 } wa_flags; 1686 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1687 1688 struct dc_link_status link_status; 1689 struct dprx_states dprx_states; 1690 1691 struct gpio *hpd_gpio; 1692 enum dc_link_fec_state fec_state; 1693 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1694 1695 struct dc_panel_config panel_config; 1696 struct phy_state phy_state; 1697 // BW ALLOCATON USB4 ONLY 1698 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1699 bool skip_implict_edp_power_control; 1700 }; 1701 1702 /* Return an enumerated dc_link. 1703 * dc_link order is constant and determined at 1704 * boot time. They cannot be created or destroyed. 1705 * Use dc_get_caps() to get number of links. 1706 */ 1707 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1708 1709 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1710 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1711 const struct dc_link *link, 1712 unsigned int *inst_out); 1713 1714 /* Return an array of link pointers to edp links. */ 1715 void dc_get_edp_links(const struct dc *dc, 1716 struct dc_link **edp_links, 1717 int *edp_num); 1718 1719 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1720 bool powerOn); 1721 1722 /* The function initiates detection handshake over the given link. It first 1723 * determines if there are display connections over the link. If so it initiates 1724 * detection protocols supported by the connected receiver device. The function 1725 * contains protocol specific handshake sequences which are sometimes mandatory 1726 * to establish a proper connection between TX and RX. So it is always 1727 * recommended to call this function as the first link operation upon HPD event 1728 * or power up event. Upon completion, the function will update link structure 1729 * in place based on latest RX capabilities. The function may also cause dpms 1730 * to be reset to off for all currently enabled streams to the link. It is DM's 1731 * responsibility to serialize detection and DPMS updates. 1732 * 1733 * @reason - Indicate which event triggers this detection. dc may customize 1734 * detection flow depending on the triggering events. 1735 * return false - if detection is not fully completed. This could happen when 1736 * there is an unrecoverable error during detection or detection is partially 1737 * completed (detection has been delegated to dm mst manager ie. 1738 * link->connection_type == dc_connection_mst_branch when returning false). 1739 * return true - detection is completed, link has been fully updated with latest 1740 * detection result. 1741 */ 1742 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1743 1744 struct dc_sink_init_data; 1745 1746 /* When link connection type is dc_connection_mst_branch, remote sink can be 1747 * added to the link. The interface creates a remote sink and associates it with 1748 * current link. The sink will be retained by link until remove remote sink is 1749 * called. 1750 * 1751 * @dc_link - link the remote sink will be added to. 1752 * @edid - byte array of EDID raw data. 1753 * @len - size of the edid in byte 1754 * @init_data - 1755 */ 1756 struct dc_sink *dc_link_add_remote_sink( 1757 struct dc_link *dc_link, 1758 const uint8_t *edid, 1759 int len, 1760 struct dc_sink_init_data *init_data); 1761 1762 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1763 * @link - link the sink should be removed from 1764 * @sink - sink to be removed. 1765 */ 1766 void dc_link_remove_remote_sink( 1767 struct dc_link *link, 1768 struct dc_sink *sink); 1769 1770 /* Enable HPD interrupt handler for a given link */ 1771 void dc_link_enable_hpd(const struct dc_link *link); 1772 1773 /* Disable HPD interrupt handler for a given link */ 1774 void dc_link_disable_hpd(const struct dc_link *link); 1775 1776 /* determine if there is a sink connected to the link 1777 * 1778 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1779 * return - false if an unexpected error occurs, true otherwise. 1780 * 1781 * NOTE: This function doesn't detect downstream sink connections i.e 1782 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1783 * return dc_connection_single if the branch device is connected despite of 1784 * downstream sink's connection status. 1785 */ 1786 bool dc_link_detect_connection_type(struct dc_link *link, 1787 enum dc_connection_type *type); 1788 1789 /* query current hpd pin value 1790 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1791 * 1792 */ 1793 bool dc_link_get_hpd_state(struct dc_link *link); 1794 1795 /* Getter for cached link status from given link */ 1796 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1797 1798 /* enable/disable hardware HPD filter. 1799 * 1800 * @link - The link the HPD pin is associated with. 1801 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1802 * handler once after no HPD change has been detected within dc default HPD 1803 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1804 * pulses within default HPD interval, no HPD event will be received until HPD 1805 * toggles have stopped. Then HPD event will be queued to irq handler once after 1806 * dc default HPD filtering interval since last HPD event. 1807 * 1808 * @enable = false - disable hardware HPD filter. HPD event will be queued 1809 * immediately to irq handler after no HPD change has been detected within 1810 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1811 */ 1812 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1813 1814 /* submit i2c read/write payloads through ddc channel 1815 * @link_index - index to a link with ddc in i2c mode 1816 * @cmd - i2c command structure 1817 * return - true if success, false otherwise. 1818 */ 1819 bool dc_submit_i2c( 1820 struct dc *dc, 1821 uint32_t link_index, 1822 struct i2c_command *cmd); 1823 1824 /* submit i2c read/write payloads through oem channel 1825 * @link_index - index to a link with ddc in i2c mode 1826 * @cmd - i2c command structure 1827 * return - true if success, false otherwise. 1828 */ 1829 bool dc_submit_i2c_oem( 1830 struct dc *dc, 1831 struct i2c_command *cmd); 1832 1833 enum aux_return_code_type; 1834 /* Attempt to transfer the given aux payload. This function does not perform 1835 * retries or handle error states. The reply is returned in the payload->reply 1836 * and the result through operation_result. Returns the number of bytes 1837 * transferred,or -1 on a failure. 1838 */ 1839 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1840 struct aux_payload *payload, 1841 enum aux_return_code_type *operation_result); 1842 1843 bool dc_is_oem_i2c_device_present( 1844 struct dc *dc, 1845 size_t slave_address 1846 ); 1847 1848 /* return true if the connected receiver supports the hdcp version */ 1849 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1850 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1851 1852 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1853 * 1854 * TODO - When defer_handling is true the function will have a different purpose. 1855 * It no longer does complete hpd rx irq handling. We should create a separate 1856 * interface specifically for this case. 1857 * 1858 * Return: 1859 * true - Downstream port status changed. DM should call DC to do the 1860 * detection. 1861 * false - no change in Downstream port status. No further action required 1862 * from DM. 1863 */ 1864 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1865 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1866 bool defer_handling, bool *has_left_work); 1867 /* handle DP specs define test automation sequence*/ 1868 void dc_link_dp_handle_automated_test(struct dc_link *link); 1869 1870 /* handle DP Link loss sequence and try to recover RX link loss with best 1871 * effort 1872 */ 1873 void dc_link_dp_handle_link_loss(struct dc_link *link); 1874 1875 /* Determine if hpd rx irq should be handled or ignored 1876 * return true - hpd rx irq should be handled. 1877 * return false - it is safe to ignore hpd rx irq event 1878 */ 1879 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1880 1881 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1882 * @link - link the hpd irq data associated with 1883 * @hpd_irq_dpcd_data - input hpd irq data 1884 * return - true if hpd irq data indicates a link lost 1885 */ 1886 bool dc_link_check_link_loss_status(struct dc_link *link, 1887 union hpd_irq_data *hpd_irq_dpcd_data); 1888 1889 /* Read hpd rx irq data from a given link 1890 * @link - link where the hpd irq data should be read from 1891 * @irq_data - output hpd irq data 1892 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1893 * read has failed. 1894 */ 1895 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1896 struct dc_link *link, 1897 union hpd_irq_data *irq_data); 1898 1899 /* The function clears recorded DP RX states in the link. DM should call this 1900 * function when it is resuming from S3 power state to previously connected links. 1901 * 1902 * TODO - in the future we should consider to expand link resume interface to 1903 * support clearing previous rx states. So we don't have to rely on dm to call 1904 * this interface explicitly. 1905 */ 1906 void dc_link_clear_dprx_states(struct dc_link *link); 1907 1908 /* Destruct the mst topology of the link and reset the allocated payload table 1909 * 1910 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1911 * still wants to reset MST topology on an unplug event */ 1912 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1913 1914 /* The function calculates effective DP link bandwidth when a given link is 1915 * using the given link settings. 1916 * 1917 * return - total effective link bandwidth in kbps. 1918 */ 1919 uint32_t dc_link_bandwidth_kbps( 1920 const struct dc_link *link, 1921 const struct dc_link_settings *link_setting); 1922 1923 /* The function takes a snapshot of current link resource allocation state 1924 * @dc: pointer to dc of the dm calling this 1925 * @map: a dc link resource snapshot defined internally to dc. 1926 * 1927 * DM needs to capture a snapshot of current link resource allocation mapping 1928 * and store it in its persistent storage. 1929 * 1930 * Some of the link resource is using first come first serve policy. 1931 * The allocation mapping depends on original hotplug order. This information 1932 * is lost after driver is loaded next time. The snapshot is used in order to 1933 * restore link resource to its previous state so user will get consistent 1934 * link capability allocation across reboot. 1935 * 1936 */ 1937 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1938 1939 /* This function restores link resource allocation state from a snapshot 1940 * @dc: pointer to dc of the dm calling this 1941 * @map: a dc link resource snapshot defined internally to dc. 1942 * 1943 * DM needs to call this function after initial link detection on boot and 1944 * before first commit streams to restore link resource allocation state 1945 * from previous boot session. 1946 * 1947 * Some of the link resource is using first come first serve policy. 1948 * The allocation mapping depends on original hotplug order. This information 1949 * is lost after driver is loaded next time. The snapshot is used in order to 1950 * restore link resource to its previous state so user will get consistent 1951 * link capability allocation across reboot. 1952 * 1953 */ 1954 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1955 1956 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1957 * interface i.e stream_update->dsc_config 1958 */ 1959 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1960 1961 /* translate a raw link rate data to bandwidth in kbps */ 1962 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1963 1964 /* determine the optimal bandwidth given link and required bw. 1965 * @link - current detected link 1966 * @req_bw - requested bandwidth in kbps 1967 * @link_settings - returned most optimal link settings that can fit the 1968 * requested bandwidth 1969 * return - false if link can't support requested bandwidth, true if link 1970 * settings is found. 1971 */ 1972 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1973 struct dc_link_settings *link_settings, 1974 uint32_t req_bw); 1975 1976 /* return the max dp link settings can be driven by the link without considering 1977 * connected RX device and its capability 1978 */ 1979 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1980 struct dc_link_settings *max_link_enc_cap); 1981 1982 /* determine when the link is driving MST mode, what DP link channel coding 1983 * format will be used. The decision will remain unchanged until next HPD event. 1984 * 1985 * @link - a link with DP RX connection 1986 * return - if stream is committed to this link with MST signal type, type of 1987 * channel coding format dc will choose. 1988 */ 1989 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1990 const struct dc_link *link); 1991 1992 /* get max dp link settings the link can enable with all things considered. (i.e 1993 * TX/RX/Cable capabilities and dp override policies. 1994 * 1995 * @link - a link with DP RX connection 1996 * return - max dp link settings the link can enable. 1997 * 1998 */ 1999 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2000 2001 /* Get the highest encoding format that the link supports; highest meaning the 2002 * encoding format which supports the maximum bandwidth. 2003 * 2004 * @link - a link with DP RX connection 2005 * return - highest encoding format link supports. 2006 */ 2007 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2008 2009 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2010 * to a link with dp connector signal type. 2011 * @link - a link with dp connector signal type 2012 * return - true if connected, false otherwise 2013 */ 2014 bool dc_link_is_dp_sink_present(struct dc_link *link); 2015 2016 /* Force DP lane settings update to main-link video signal and notify the change 2017 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2018 * tuning purpose. The interface assumes link has already been enabled with DP 2019 * signal. 2020 * 2021 * @lt_settings - a container structure with desired hw_lane_settings 2022 */ 2023 void dc_link_set_drive_settings(struct dc *dc, 2024 struct link_training_settings *lt_settings, 2025 struct dc_link *link); 2026 2027 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2028 * test or debugging purpose. The test pattern will remain until next un-plug. 2029 * 2030 * @link - active link with DP signal output enabled. 2031 * @test_pattern - desired test pattern to output. 2032 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2033 * @test_pattern_color_space - for video test pattern choose a desired color 2034 * space. 2035 * @p_link_settings - For PHY pattern choose a desired link settings 2036 * @p_custom_pattern - some test pattern will require a custom input to 2037 * customize some pattern details. Otherwise keep it to NULL. 2038 * @cust_pattern_size - size of the custom pattern input. 2039 * 2040 */ 2041 bool dc_link_dp_set_test_pattern( 2042 struct dc_link *link, 2043 enum dp_test_pattern test_pattern, 2044 enum dp_test_pattern_color_space test_pattern_color_space, 2045 const struct link_training_settings *p_link_settings, 2046 const unsigned char *p_custom_pattern, 2047 unsigned int cust_pattern_size); 2048 2049 /* Force DP link settings to always use a specific value until reboot to a 2050 * specific link. If link has already been enabled, the interface will also 2051 * switch to desired link settings immediately. This is a debug interface to 2052 * generic dp issue trouble shooting. 2053 */ 2054 void dc_link_set_preferred_link_settings(struct dc *dc, 2055 struct dc_link_settings *link_setting, 2056 struct dc_link *link); 2057 2058 /* Force DP link to customize a specific link training behavior by overriding to 2059 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2060 * display specific link training issues or apply some display specific 2061 * workaround in link training. 2062 * 2063 * @link_settings - if not NULL, force preferred link settings to the link. 2064 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2065 * will apply this particular override in future link training. If NULL is 2066 * passed in, dc resets previous overrides. 2067 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2068 * training settings. 2069 */ 2070 void dc_link_set_preferred_training_settings(struct dc *dc, 2071 struct dc_link_settings *link_setting, 2072 struct dc_link_training_overrides *lt_overrides, 2073 struct dc_link *link, 2074 bool skip_immediate_retrain); 2075 2076 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2077 bool dc_link_is_fec_supported(const struct dc_link *link); 2078 2079 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2080 * link enablement. 2081 * return - true if FEC should be enabled, false otherwise. 2082 */ 2083 bool dc_link_should_enable_fec(const struct dc_link *link); 2084 2085 /* determine lttpr mode the current link should be enabled with a specific link 2086 * settings. 2087 */ 2088 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2089 struct dc_link_settings *link_setting); 2090 2091 /* Force DP RX to update its power state. 2092 * NOTE: this interface doesn't update dp main-link. Calling this function will 2093 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2094 * RX power state back upon finish DM specific execution requiring DP RX in a 2095 * specific power state. 2096 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2097 * state. 2098 */ 2099 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2100 2101 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2102 * current value read from extended receiver cap from 02200h - 0220Fh. 2103 * Some DP RX has problems of providing accurate DP receiver caps from extended 2104 * field, this interface is a workaround to revert link back to use base caps. 2105 */ 2106 void dc_link_overwrite_extended_receiver_cap( 2107 struct dc_link *link); 2108 2109 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2110 bool wait_for_hpd); 2111 2112 /* Set backlight level of an embedded panel (eDP, LVDS). 2113 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2114 * and 16 bit fractional, where 1.0 is max backlight value. 2115 */ 2116 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2117 uint32_t backlight_pwm_u16_16, 2118 uint32_t frame_ramp); 2119 2120 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2121 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2122 bool isHDR, 2123 uint32_t backlight_millinits, 2124 uint32_t transition_time_in_ms); 2125 2126 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2127 uint32_t *backlight_millinits, 2128 uint32_t *backlight_millinits_peak); 2129 2130 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2131 2132 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2133 2134 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2135 bool wait, bool force_static, const unsigned int *power_opts); 2136 2137 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2138 2139 bool dc_link_setup_psr(struct dc_link *dc_link, 2140 const struct dc_stream_state *stream, struct psr_config *psr_config, 2141 struct psr_context *psr_context); 2142 2143 /* 2144 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2145 * 2146 * @link: pointer to the dc_link struct instance 2147 * @enable: enable(active) or disable(inactive) replay 2148 * @wait: state transition need to wait the active set completed. 2149 * @force_static: force disable(inactive) the replay 2150 * @power_opts: set power optimazation parameters to DMUB. 2151 * 2152 * return: allow Replay active will return true, else will return false. 2153 */ 2154 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2155 bool wait, bool force_static, const unsigned int *power_opts); 2156 2157 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2158 2159 /* On eDP links this function call will stall until T12 has elapsed. 2160 * If the panel is not in power off state, this function will return 2161 * immediately. 2162 */ 2163 bool dc_link_wait_for_t12(struct dc_link *link); 2164 2165 /* Determine if dp trace has been initialized to reflect upto date result * 2166 * return - true if trace is initialized and has valid data. False dp trace 2167 * doesn't have valid result. 2168 */ 2169 bool dc_dp_trace_is_initialized(struct dc_link *link); 2170 2171 /* Query a dp trace flag to indicate if the current dp trace data has been 2172 * logged before 2173 */ 2174 bool dc_dp_trace_is_logged(struct dc_link *link, 2175 bool in_detection); 2176 2177 /* Set dp trace flag to indicate whether DM has already logged the current dp 2178 * trace data. DM can set is_logged to true upon logging and check 2179 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2180 */ 2181 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2182 bool in_detection, 2183 bool is_logged); 2184 2185 /* Obtain driver time stamp for last dp link training end. The time stamp is 2186 * formatted based on dm_get_timestamp DM function. 2187 * @in_detection - true to get link training end time stamp of last link 2188 * training in detection sequence. false to get link training end time stamp 2189 * of last link training in commit (dpms) sequence 2190 */ 2191 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2192 bool in_detection); 2193 2194 /* Get how many link training attempts dc has done with latest sequence. 2195 * @in_detection - true to get link training count of last link 2196 * training in detection sequence. false to get link training count of last link 2197 * training in commit (dpms) sequence 2198 */ 2199 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2200 bool in_detection); 2201 2202 /* Get how many link loss has happened since last link training attempts */ 2203 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2204 2205 /* 2206 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2207 */ 2208 /* 2209 * Send a request from DP-Tx requesting to allocate BW remotely after 2210 * allocating it locally. This will get processed by CM and a CB function 2211 * will be called. 2212 * 2213 * @link: pointer to the dc_link struct instance 2214 * @req_bw: The requested bw in Kbyte to allocated 2215 * 2216 * return: none 2217 */ 2218 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2219 2220 /* 2221 * Handle function for when the status of the Request above is complete. 2222 * We will find out the result of allocating on CM and update structs. 2223 * 2224 * @link: pointer to the dc_link struct instance 2225 * @bw: Allocated or Estimated BW depending on the result 2226 * @result: Response type 2227 * 2228 * return: none 2229 */ 2230 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2231 uint8_t bw, uint8_t result); 2232 2233 /* 2234 * Handle the USB4 BW Allocation related functionality here: 2235 * Plug => Try to allocate max bw from timing parameters supported by the sink 2236 * Unplug => de-allocate bw 2237 * 2238 * @link: pointer to the dc_link struct instance 2239 * @peak_bw: Peak bw used by the link/sink 2240 * 2241 * return: allocated bw else return 0 2242 */ 2243 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2244 struct dc_link *link, int peak_bw); 2245 2246 /* 2247 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2248 * available BW for each host router 2249 * 2250 * @dc: pointer to dc struct 2251 * @stream: pointer to all possible streams 2252 * @count: number of valid DPIA streams 2253 * 2254 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2255 */ 2256 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2257 const unsigned int count); 2258 2259 /* Sink Interfaces - A sink corresponds to a display output device */ 2260 2261 struct dc_container_id { 2262 // 128bit GUID in binary form 2263 unsigned char guid[16]; 2264 // 8 byte port ID -> ELD.PortID 2265 unsigned int portId[2]; 2266 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2267 unsigned short manufacturerName; 2268 // 2 byte product code -> ELD.ProductCode 2269 unsigned short productCode; 2270 }; 2271 2272 2273 struct dc_sink_dsc_caps { 2274 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2275 // 'false' if they are sink's DSC caps 2276 bool is_virtual_dpcd_dsc; 2277 // 'true' if MST topology supports DSC passthrough for sink 2278 // 'false' if MST topology does not support DSC passthrough 2279 bool is_dsc_passthrough_supported; 2280 struct dsc_dec_dpcd_caps dsc_dec_caps; 2281 }; 2282 2283 struct dc_sink_fec_caps { 2284 bool is_rx_fec_supported; 2285 bool is_topology_fec_supported; 2286 }; 2287 2288 struct scdc_caps { 2289 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2290 union hdmi_scdc_device_id_data device_id; 2291 }; 2292 2293 /* 2294 * The sink structure contains EDID and other display device properties 2295 */ 2296 struct dc_sink { 2297 enum signal_type sink_signal; 2298 struct dc_edid dc_edid; /* raw edid */ 2299 struct dc_edid_caps edid_caps; /* parse display caps */ 2300 struct dc_container_id *dc_container_id; 2301 uint32_t dongle_max_pix_clk; 2302 void *priv; 2303 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2304 bool converter_disable_audio; 2305 2306 struct scdc_caps scdc_caps; 2307 struct dc_sink_dsc_caps dsc_caps; 2308 struct dc_sink_fec_caps fec_caps; 2309 2310 bool is_vsc_sdp_colorimetry_supported; 2311 2312 /* private to DC core */ 2313 struct dc_link *link; 2314 struct dc_context *ctx; 2315 2316 uint32_t sink_id; 2317 2318 /* private to dc_sink.c */ 2319 // refcount must be the last member in dc_sink, since we want the 2320 // sink structure to be logically cloneable up to (but not including) 2321 // refcount 2322 struct kref refcount; 2323 }; 2324 2325 void dc_sink_retain(struct dc_sink *sink); 2326 void dc_sink_release(struct dc_sink *sink); 2327 2328 struct dc_sink_init_data { 2329 enum signal_type sink_signal; 2330 struct dc_link *link; 2331 uint32_t dongle_max_pix_clk; 2332 bool converter_disable_audio; 2333 }; 2334 2335 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2336 2337 /* Newer interfaces */ 2338 struct dc_cursor { 2339 struct dc_plane_address address; 2340 struct dc_cursor_attributes attributes; 2341 }; 2342 2343 2344 /* Interrupt interfaces */ 2345 enum dc_irq_source dc_interrupt_to_irq_source( 2346 struct dc *dc, 2347 uint32_t src_id, 2348 uint32_t ext_id); 2349 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2350 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2351 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2352 struct dc *dc, uint32_t link_index); 2353 2354 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2355 2356 /* Power Interfaces */ 2357 2358 void dc_set_power_state( 2359 struct dc *dc, 2360 enum dc_acpi_cm_power_state power_state); 2361 void dc_resume(struct dc *dc); 2362 2363 void dc_power_down_on_boot(struct dc *dc); 2364 2365 /* 2366 * HDCP Interfaces 2367 */ 2368 enum hdcp_message_status dc_process_hdcp_msg( 2369 enum signal_type signal, 2370 struct dc_link *link, 2371 struct hdcp_protection_message *message_info); 2372 bool dc_is_dmcu_initialized(struct dc *dc); 2373 2374 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2375 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2376 2377 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2378 unsigned int pitch, 2379 unsigned int height, 2380 enum surface_pixel_format format, 2381 struct dc_cursor_attributes *cursor_attr); 2382 2383 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2384 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2385 2386 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2387 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2388 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2389 2390 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2391 void dc_unlock_memory_clock_frequency(struct dc *dc); 2392 2393 /* set min memory clock to the min required for current mode, max to maxDPM */ 2394 void dc_lock_memory_clock_frequency(struct dc *dc); 2395 2396 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2397 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2398 2399 /* cleanup on driver unload */ 2400 void dc_hardware_release(struct dc *dc); 2401 2402 /* disables fw based mclk switch */ 2403 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2404 2405 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2406 2407 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2408 2409 void dc_z10_restore(const struct dc *dc); 2410 void dc_z10_save_init(struct dc *dc); 2411 2412 bool dc_is_dmub_outbox_supported(struct dc *dc); 2413 bool dc_enable_dmub_notifications(struct dc *dc); 2414 2415 bool dc_abm_save_restore( 2416 struct dc *dc, 2417 struct dc_stream_state *stream, 2418 struct abm_save_restore *pData); 2419 2420 void dc_enable_dmub_outbox(struct dc *dc); 2421 2422 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2423 uint32_t link_index, 2424 struct aux_payload *payload); 2425 2426 /* Get dc link index from dpia port index */ 2427 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2428 uint8_t dpia_port_index); 2429 2430 bool dc_process_dmub_set_config_async(struct dc *dc, 2431 uint32_t link_index, 2432 struct set_config_cmd_payload *payload, 2433 struct dmub_notification *notify); 2434 2435 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2436 uint32_t link_index, 2437 uint8_t mst_alloc_slots, 2438 uint8_t *mst_slots_in_use); 2439 2440 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2441 uint32_t hpd_int_enable); 2442 2443 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2444 2445 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2446 2447 struct dc_power_profile { 2448 int power_level; /* Lower is better */ 2449 }; 2450 2451 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2452 2453 /* DSC Interfaces */ 2454 #include "dc_dsc.h" 2455 2456 /* Disable acc mode Interfaces */ 2457 void dc_disable_accelerated_mode(struct dc *dc); 2458 2459 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2460 struct dc_stream_state *new_stream); 2461 2462 #endif /* DC_INTERFACE_H_ */ 2463