| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/mips/cpu/ |
| H A D | cache.S | 101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ argument
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ argument
|
| /dports/devel/blitz/blitz-1.0.2/blitz/ |
| H A D | memblock.cc | 41 const int cacheLineSize = BZ_L1_CACHE_LINE_SIZE; in deallocate() local
96 const int cacheLineSize = BZ_L1_CACHE_LINE_SIZE; in allocate() local
|
| /dports/net/grpcui/grpcui-1.1.0/vendor/golang.org/x/sys/cpu/ |
| H A D | cpu_mipsx.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_mips64x.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_riscv64.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_wasm.go | 13 const cacheLineSize = 0 const
|
| /dports/net/go-bapu/carlostrub-bapu-23ca6b019fbc/vendor/golang.org/x/sys/cpu/ |
| H A D | cpu_mips64x.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_wasm.go | 13 const cacheLineSize = 0 const
|
| H A D | cpu_mipsx.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_riscv64.go | 9 const cacheLineSize = 32 const
|
| /dports/net/goreplay/goreplay-1.2.0/vendor/golang.org/x/sys/sys-85ca7c5b95cd/cpu/ |
| H A D | cpu_mips64x.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_mipsx.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_riscv64.go | 9 const cacheLineSize = 32 const
|
| /dports/security/vault/vault-1.8.2/vendor/github.com/containerd/containerd/vendor/golang.org/x/sys/cpu/ |
| H A D | cpu_mipsx.go | 9 const cacheLineSize = 32 const
|
| /dports/net/evans/evans-0.9.1/vendor/golang.org/x/sys/cpu/ |
| H A D | cpu_mips64x.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_riscv64.go | 9 const cacheLineSize = 32 const
|
| H A D | cpu_wasm.go | 13 const cacheLineSize = 0 const
|
| H A D | cpu_mipsx.go | 9 const cacheLineSize = 32 const
|
| /dports/databases/pg_tileserv/pg_tileserv-1.0.8/vendor/golang.org/x/sys/cpu/ |
| H A D | cpu_riscv64.go | 9 const cacheLineSize = 32 const
|