1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/rman.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <machine/bus.h>
35
36 #include <dev/fdt/simplebus.h>
37
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
48
49 #if defined(__aarch64__)
50 #include "opt_soc.h"
51 #endif
52
53 #include <dev/clk/allwinner/aw_ccung.h>
54
55 #include <dt-bindings/clock/sun8i-h3-ccu.h>
56 #include <dt-bindings/reset/sun8i-h3-ccu.h>
57
58 /* Non-exported resets */
59 #define RST_BUS_SCR 53
60
61 /* Non-exported clocks */
62 #define CLK_PLL_CPUX 0
63 #define CLK_PLL_AUDIO_BASE 1
64 #define CLK_PLL_AUDIO 2
65 #define CLK_PLL_AUDIO_2X 3
66 #define CLK_PLL_AUDIO_4X 4
67 #define CLK_PLL_AUDIO_8X 5
68 #define CLK_PLL_VIDEO 6
69 #define CLK_PLL_VE 7
70 #define CLK_PLL_DDR 8
71 #define CLK_PLL_PERIPH0_2X 10
72 #define CLK_PLL_GPU 11
73 #define CLK_PLL_PERIPH1 12
74 #define CLK_PLL_DE 13
75
76 #define CLK_AXI 15
77 #define CLK_AHB1 16
78 #define CLK_APB1 17
79 #define CLK_APB2 18
80 #define CLK_AHB2 19
81
82 #define CLK_BUS_SCR 66
83
84 #define CLK_USBPHY0 88
85 #define CLK_USBPHY1 89
86 #define CLK_USBPHY2 90
87 #define CLK_USBPHY3 91
88 #define CLK_USBOHCI0 92
89 #define CLK_USBOHCI1 93
90 #define CLK_USBOHCI2 94
91 #define CLK_USBOHCI3 95
92 #define CLK_DRAM 96
93
94 #define CLK_MBUS 113
95
96 static struct aw_ccung_reset h3_ccu_resets[] = {
97 CCU_RESET(RST_USB_PHY0, 0xcc, 0)
98 CCU_RESET(RST_USB_PHY1, 0xcc, 1)
99 CCU_RESET(RST_USB_PHY2, 0xcc, 2)
100 CCU_RESET(RST_USB_PHY3, 0xcc, 3)
101
102 CCU_RESET(RST_MBUS, 0xfc, 31)
103
104 CCU_RESET(RST_BUS_CE, 0x2c0, 5)
105 CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
106 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
107 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
108 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
109 CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
110 CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
111 CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
112 CCU_RESET(RST_BUS_TS, 0x2c0, 18)
113 CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
114 CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
115 CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
116 CCU_RESET(RST_BUS_OTG, 0x2c0, 23)
117 CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24)
118 CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25)
119 CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26)
120 CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27)
121 CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28)
122 CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29)
123 CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30)
124 CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31)
125
126 CCU_RESET(RST_BUS_VE, 0x2c4, 0)
127 CCU_RESET(RST_BUS_TCON0, 0x2c4, 3)
128 CCU_RESET(RST_BUS_TCON1, 0x2c4, 4)
129 CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5)
130 CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
131 CCU_RESET(RST_BUS_TVE, 0x2c4, 9)
132 CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
133 CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
134 CCU_RESET(RST_BUS_DE, 0x2c4, 12)
135 CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
136 CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
137 CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
138 CCU_RESET(RST_BUS_DBG, 0x2c4, 31)
139
140 CCU_RESET(RST_BUS_EPHY, 0x2c8, 2)
141
142 CCU_RESET(RST_BUS_CODEC, 0x2d0, 0)
143 CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
144 CCU_RESET(RST_BUS_THS, 0x2d0, 8)
145 CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
146 CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
147 CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
148
149 CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
150 CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
151 CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
152 CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
153 CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
154 CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
155 CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
156 CCU_RESET(RST_BUS_SCR, 0x2d8, 20)
157 };
158
159 static struct aw_ccung_gate h3_ccu_gates[] = {
160 CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
161 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
162 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
163 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
164 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
165 CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
166 CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
167 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17)
168 CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
169 CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
170 CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
171 CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
172 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
173 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
174 CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
175 CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26)
176 CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27)
177 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
178 CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
179 CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30)
180 CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31)
181
182 CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
183 CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
184 CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
185 CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
186 CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
187 CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9)
188 CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
189 CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
190 CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
191 CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
192 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
193
194 CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
195 CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
196 CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
197 CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
198 CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
199 CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
200 CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
201
202 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
203 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
204 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
205 CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
206 CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
207 CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
208 CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
209 CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20)
210
211 CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0)
212 CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
213
214 CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8)
215 CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9)
216 CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10)
217 CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11)
218 CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16)
219 CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17)
220 CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18)
221 CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19)
222
223 CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31)
224 CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31)
225 CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
226 CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
227
228 CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
229 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
230 CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
231 CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
232
233 CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
234
235 CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
236
237 CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
238
239 CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
240 };
241
242 static const char *pll_cpux_parents[] = {"osc24M"};
243 NKMP_CLK(pll_cpux_clk,
244 CLK_PLL_CPUX, /* id */
245 "pll_cpux", pll_cpux_parents, /* name, parents */
246 0x00, /* offset */
247 8, 5, 0, 0, /* n factor */
248 4, 2, 0, 0, /* k factor */
249 0, 2, 0, 0, /* m factor */
250 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */
251 31, /* gate */
252 28, 1000, /* lock */
253 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */
254
255 static const char *pll_audio_parents[] = {"osc24M"};
256 NKMP_CLK(pll_audio_clk,
257 CLK_PLL_AUDIO, /* id */
258 "pll_audio", pll_audio_parents, /* name, parents */
259 0x08, /* offset */
260 8, 7, 0, 0, /* n factor */
261 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
262 0, 5, 0, 0, /* m factor */
263 16, 4, 0, 0, /* p factor */
264 31, /* gate */
265 28, 1000, /* lock */
266 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
267
268 static const char *pll_audio_mult_parents[] = {"pll_audio"};
269 FIXED_CLK(pll_audio_2x_clk,
270 CLK_PLL_AUDIO_2X, /* id */
271 "pll_audio-2x", /* name */
272 pll_audio_mult_parents, /* parent */
273 0, /* freq */
274 2, /* mult */
275 1, /* div */
276 0); /* flags */
277 FIXED_CLK(pll_audio_4x_clk,
278 CLK_PLL_AUDIO_4X, /* id */
279 "pll_audio-4x", /* name */
280 pll_audio_mult_parents, /* parent */
281 0, /* freq */
282 4, /* mult */
283 1, /* div */
284 0); /* flags */
285 FIXED_CLK(pll_audio_8x_clk,
286 CLK_PLL_AUDIO_8X, /* id */
287 "pll_audio-8x", /* name */
288 pll_audio_mult_parents, /* parent */
289 0, /* freq */
290 8, /* mult */
291 1, /* div */
292 0); /* flags */
293
294 static const char *pll_video_parents[] = {"osc24M"};
295 FRAC_CLK(pll_video_clk,
296 CLK_PLL_VIDEO, /* id */
297 "pll_video", pll_video_parents, /* name, parents */
298 0x10, /* offset */
299 8, 7, 0, 0, /* n factor */
300 0, 4, 0, 0, /* m factor */
301 31, 28, 1000, /* gate, lock, lock retries */
302 AW_CLK_HAS_LOCK, /* flags */
303 270000000, 297000000, /* freq0, freq1 */
304 24, 25, /* mode sel, freq sel */
305 192000000, 600000000); /* min freq, max freq */
306
307 static const char *pll_ve_parents[] = {"osc24M"};
308 FRAC_CLK(pll_ve_clk,
309 CLK_PLL_VE, /* id */
310 "pll_ve", pll_ve_parents, /* name, parents */
311 0x18, /* offset */
312 8, 7, 0, 0, /* n factor */
313 0, 4, 0, 0, /* m factor */
314 31, 28, 1000, /* gate, lock, lock retries */
315 AW_CLK_HAS_LOCK, /* flags */
316 270000000, 297000000, /* freq0, freq1 */
317 24, 25, /* mode sel, freq sel */
318 192000000, 600000000); /* min freq, max freq */
319
320 static const char *pll_ddr_parents[] = {"osc24M"};
321 NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
322 CLK_PLL_DDR, /* id */
323 "pll_ddr", pll_ddr_parents, /* name, parents */
324 0x20, /* offset */
325 8, 5, 0, 0, /* n factor */
326 4, 2, 0, 0, /* k factor */
327 0, 2, 0, 0, /* m factor */
328 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
329 31, /* gate */
330 28, 1000, /* lock */
331 20, /* update */
332 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
333
334 static const char *pll_periph0_parents[] = {"osc24M"};
335 static const char *pll_periph0_2x_parents[] = {"pll_periph0"};
336 NKMP_CLK(pll_periph0_clk,
337 CLK_PLL_PERIPH0, /* id */
338 "pll_periph0", pll_periph0_parents, /* name, parents */
339 0x28, /* offset */
340 8, 5, 0, 0, /* n factor */
341 4, 2, 0, 0, /* k factor */
342 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
343 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
344 31, /* gate */
345 28, 1000, /* lock */
346 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
347 FIXED_CLK(pll_periph0_2x_clk,
348 CLK_PLL_PERIPH0_2X, /* id */
349 "pll_periph0-2x", /* name */
350 pll_periph0_2x_parents, /* parent */
351 0, /* freq */
352 2, /* mult */
353 1, /* div */
354 0); /* flags */
355
356 static const char *pll_gpu_parents[] = {"osc24M"};
357 FRAC_CLK(pll_gpu_clk,
358 CLK_PLL_GPU, /* id */
359 "pll_gpu", pll_gpu_parents, /* name, parents */
360 0x38, /* offset */
361 8, 7, 0, 0, /* n factor */
362 0, 4, 0, 0, /* m factor */
363 31, 28, 1000, /* gate, lock, lock retries */
364 AW_CLK_HAS_LOCK, /* flags */
365 270000000, 297000000, /* freq0, freq1 */
366 24, 25, /* mode sel, freq sel */
367 192000000, 600000000); /* min freq, max freq */
368
369 static const char *pll_periph1_parents[] = {"osc24M"};
370 NKMP_CLK(pll_periph1_clk,
371 CLK_PLL_PERIPH1, /* id */
372 "pll_periph1", pll_periph1_parents, /* name, parents */
373 0x44, /* offset */
374 8, 5, 0, 0, /* n factor */
375 4, 2, 0, 0, /* k factor */
376 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
377 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
378 31, /* gate */
379 28, 1000, /* lock */
380 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
381
382 static const char *pll_de_parents[] = {"osc24M"};
383 FRAC_CLK(pll_de_clk,
384 CLK_PLL_DE, /* id */
385 "pll_de", pll_de_parents, /* name, parents */
386 0x48, /* offset */
387 8, 7, 0, 0, /* n factor */
388 0, 4, 0, 0, /* m factor */
389 31, 28, 1000, /* gate, lock, lock retries */
390 AW_CLK_HAS_LOCK, /* flags */
391 270000000, 297000000, /* freq0, freq1 */
392 24, 25, /* mode sel, freq sel */
393 192000000, 600000000); /* min freq, max freq */
394
395 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"};
396 MUX_CLK(cpux_clk,
397 CLK_CPUX, /* id */
398 "cpux", cpux_parents, /* name, parents */
399 0x50, 16, 2); /* offset, shift, width */
400
401 static const char *axi_parents[] = {"cpux"};
402 DIV_CLK(axi_clk,
403 CLK_AXI, /* id */
404 "axi", axi_parents, /* name, parents */
405 0x50, /* offset */
406 0, 2, /* shift, width */
407 0, NULL); /* flags, div table */
408
409 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
410 PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */
411 "ahb1", ahb1_parents, /* name, parents */
412 0x54, /* offset */
413 12, 2, /* mux */
414 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
415 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
416 12, 2, 3); /* prediv condition */
417
418 static const char *apb1_parents[] = {"ahb1"};
419 static struct clk_div_table apb1_div_table[] = {
420 { .value = 0, .divider = 2, },
421 { .value = 1, .divider = 2, },
422 { .value = 2, .divider = 4, },
423 { .value = 3, .divider = 8, },
424 { },
425 };
426 DIV_CLK(apb1_clk,
427 CLK_APB1, /* id */
428 "apb1", apb1_parents, /* name, parents */
429 0x54, /* offset */
430 8, 2, /* shift, width */
431 CLK_DIV_WITH_TABLE, /* flags */
432 apb1_div_table); /* div table */
433
434 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"};
435 NM_CLK(apb2_clk,
436 CLK_APB2, /* id */
437 "apb2", apb2_parents, /* name, parents */
438 0x58, /* offset */
439 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
440 0, 5, 0, 0, /* m factor */
441 24, 2, /* mux */
442 0, /* gate */
443 AW_CLK_HAS_MUX);
444
445 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
446 PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */
447 "ahb2", ahb2_parents, /* name, parents */
448 0x5c, /* offset */
449 0, 2, /* mux */
450 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */
451 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */
452 0, 2, 1); /* prediv condition */
453
454 static const char *ths_parents[] = {"osc24M"};
455 static struct clk_div_table ths_div_table[] = {
456 { .value = 0, .divider = 1, },
457 { .value = 1, .divider = 2, },
458 { .value = 2, .divider = 4, },
459 { .value = 3, .divider = 6, },
460 { },
461 };
462 DIV_CLK(thsdiv_clk,
463 0, /* id */
464 "thsdiv", ths_parents, /* name, parents */
465 0x74, /* offset */
466 0, 2, /* shift, width */
467 CLK_DIV_WITH_TABLE, /* flags */
468 ths_div_table); /* div table */
469
470 static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"};
471 NM_CLK(nand_clk,
472 CLK_NAND, "nand", mod_parents, /* id, name, parents */
473 0x80, /* offset */
474 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
475 0, 4, 0, 0, /* m factor */
476 24, 2, /* mux */
477 31, /* gate */
478 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
479
480 NM_CLK(mmc0_clk,
481 CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
482 0x88, /* offset */
483 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
484 0, 4, 0, 0, /* m factor */
485 24, 2, /* mux */
486 31, /* gate */
487 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
488 AW_CLK_REPARENT); /* flags */
489
490 NM_CLK(mmc1_clk,
491 CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
492 0x8c, /* offset */
493 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
494 0, 4, 0, 0, /* m factor */
495 24, 2, /* mux */
496 31, /* gate */
497 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
498 AW_CLK_REPARENT); /* flags */
499
500 NM_CLK(mmc2_clk,
501 CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
502 0x90, /* offset */
503 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
504 0, 4, 0, 0, /* m factor */
505 24, 2, /* mux */
506 31, /* gate */
507 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
508 AW_CLK_REPARENT); /* flags */
509
510 static const char *ts_parents[] = {"osc24M", "pll_periph0"};
511 NM_CLK(ts_clk,
512 CLK_TS, "ts", ts_parents, /* id, name, parents */
513 0x98, /* offset */
514 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
515 0, 4, 0, 0, /* m factor */
516 24, 2, /* mux */
517 31, /* gate */
518 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
519
520 NM_CLK(ce_clk,
521 CLK_CE, "ce", mod_parents, /* id, name, parents */
522 0x9C, /* offset */
523 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
524 0, 4, 0, 0, /* m factor */
525 24, 2, /* mux */
526 31, /* gate */
527 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
528
529 NM_CLK(spi0_clk,
530 CLK_SPI0, "spi0", mod_parents, /* id, name, parents */
531 0xA0, /* offset */
532 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
533 0, 4, 0, 0, /* m factor */
534 24, 2, /* mux */
535 31, /* gate */
536 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
537 AW_CLK_REPARENT); /* flags */
538
539 NM_CLK(spi1_clk,
540 CLK_SPI1, "spi1", mod_parents, /* id, name, parents */
541 0xA4, /* offset */
542 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
543 0, 4, 0, 0, /* m factor */
544 24, 2, /* mux */
545 31, /* gate */
546 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
547 AW_CLK_REPARENT); /* flags */
548
549 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"};
550 MUX_CLK(i2s0mux_clk,
551 0, "i2s0mux", i2s_parents, /* id, name, parents */
552 0xb0, 16, 2); /* offset, mux shift, mux width */
553 MUX_CLK(i2s1mux_clk,
554 0, "i2s1mux", i2s_parents, /* id, name, parents */
555 0xb4, 16, 2); /* offset, mux shift, mux width */
556 MUX_CLK(i2s2mux_clk,
557 0, "i2s2mux", i2s_parents, /* id, name, parents */
558 0xb8, 16, 2); /* offset, mux shift, mux width */
559
560 static const char *spdif_parents[] = {"pll_audio"};
561 NM_CLK(spdif_clk,
562 CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */
563 0xC0, /* offset */
564 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */
565 0, 4, 0, 0, /* m factor */
566 0, 0, /* mux */
567 31, /* gate */
568 AW_CLK_HAS_GATE); /* flags */
569
570 static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"};
571 NM_CLK(dram_clk,
572 CLK_DRAM, "dram", dram_parents, /* id, name, parents */
573 0xF4, /* offset */
574 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
575 0, 4, 0, 0, /* m factor */
576 20, 2, /* mux */
577 0, /* gate */
578 AW_CLK_HAS_MUX); /* flags */
579
580 static const char *de_parents[] = {"pll_periph0-2x", "pll_de"};
581 NM_CLK(de_clk,
582 CLK_DE, "de", de_parents, /* id, name, parents */
583 0x104, /* offset */
584 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
585 0, 4, 0, 0, /* m factor */
586 24, 2, /* mux */
587 31, /* gate */
588 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
589
590 static const char *tcon0_parents[] = {"pll_video"};
591 NM_CLK(tcon0_clk,
592 CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */
593 0x118, /* offset */
594 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
595 0, 4, 0, 0, /* m factor */
596 24, 2, /* mux */
597 31, /* gate */
598 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
599
600 static const char *tve_parents[] = {"pll_de", "pll_periph1"};
601 NM_CLK(tve_clk,
602 CLK_TVE, "tve", tve_parents, /* id, name, parents */
603 0x120, /* offset */
604 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
605 0, 4, 0, 0, /* m factor */
606 24, 2, /* mux */
607 31, /* gate */
608 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
609
610 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
611 NM_CLK(deinterlace_clk,
612 CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */
613 0x124, /* offset */
614 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
615 0, 4, 0, 0, /* m factor */
616 24, 2, /* mux */
617 31, /* gate */
618 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
619
620 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
621 NM_CLK(csi_sclk_clk,
622 CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
623 0x134, /* offset */
624 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
625 16, 4, 0, 0, /* m factor */
626 24, 2, /* mux */
627 31, /* gate */
628 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
629
630 static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"};
631 NM_CLK(csi_mclk_clk,
632 CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
633 0x134, /* offset */
634 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
635 0, 4, 0, 0, /* m factor */
636 8, 2, /* mux */
637 15, /* gate */
638 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
639
640 static const char *ve_parents[] = {"pll_ve"};
641 NM_CLK(ve_clk,
642 CLK_VE, "ve", ve_parents, /* id, name, parents */
643 0x13C, /* offset */
644 16, 3, 0, 0, /* n factor */
645 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
646 0, 0, /* mux */
647 31, /* gate */
648 AW_CLK_HAS_GATE); /* flags */
649
650 static const char *hdmi_parents[] = {"pll_video"};
651 NM_CLK(hdmi_clk,
652 CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
653 0x150, /* offset */
654 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
655 0, 4, 0, 0, /* m factor */
656 24, 2, /* mux */
657 31, /* gate */
658 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
659
660 static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"};
661 NM_CLK(mbus_clk,
662 CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
663 0x15C, /* offset */
664 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
665 0, 3, 0, 0, /* m factor */
666 24, 2, /* mux */
667 31, /* gate */
668 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
669
670 static const char *gpu_parents[] = {"pll_gpu"};
671 NM_CLK(gpu_clk,
672 CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
673 0x1A0, /* offset */
674 0, 2, 0, 0, /* n factor */
675 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
676 0, 0, /* mux */
677 31, /* gate */
678 AW_CLK_HAS_GATE); /* flags */
679
680 static struct aw_ccung_clk h3_ccu_clks[] = {
681 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk},
682 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
683 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_clk},
684 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_clk},
685 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
686 { .type = AW_CLK_FRAC, .clk.frac = &pll_video_clk},
687 { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
688 { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
689 { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk},
690 { .type = AW_CLK_NM, .clk.nm = &apb2_clk},
691 { .type = AW_CLK_NM, .clk.nm = &nand_clk},
692 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
693 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
694 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
695 { .type = AW_CLK_NM, .clk.nm = &ts_clk},
696 { .type = AW_CLK_NM, .clk.nm = &ce_clk},
697 { .type = AW_CLK_NM, .clk.nm = &spi0_clk},
698 { .type = AW_CLK_NM, .clk.nm = &spi1_clk},
699 { .type = AW_CLK_NM, .clk.nm = &spdif_clk},
700 { .type = AW_CLK_NM, .clk.nm = &dram_clk},
701 { .type = AW_CLK_NM, .clk.nm = &de_clk},
702 { .type = AW_CLK_NM, .clk.nm = &tcon0_clk},
703 { .type = AW_CLK_NM, .clk.nm = &tve_clk},
704 { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk},
705 { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk},
706 { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk},
707 { .type = AW_CLK_NM, .clk.nm = &ve_clk},
708 { .type = AW_CLK_NM, .clk.nm = &hdmi_clk},
709 { .type = AW_CLK_NM, .clk.nm = &mbus_clk},
710 { .type = AW_CLK_NM, .clk.nm = &gpu_clk},
711 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk},
712 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk},
713 { .type = AW_CLK_MUX, .clk.mux = &cpux_clk},
714 { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk},
715 { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk},
716 { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk},
717 { .type = AW_CLK_DIV, .clk.div = &axi_clk},
718 { .type = AW_CLK_DIV, .clk.div = &apb1_clk},
719 { .type = AW_CLK_DIV, .clk.div = &thsdiv_clk},
720 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_2x_clk},
721 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk},
722 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk},
723 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk},
724 };
725
726 static struct aw_clk_init h3_init_clks[] = {
727 {"ahb1", "pll_periph0", 0, false},
728 {"ahb2", "pll_periph0", 0, false},
729 {"dram", "pll_ddr", 0, false},
730 };
731
732 static struct ofw_compat_data compat_data[] = {
733 #if defined(SOC_ALLWINNER_H3)
734 { "allwinner,sun8i-h3-ccu", 1 },
735 #endif
736 #if defined(SOC_ALLWINNER_H5)
737 { "allwinner,sun50i-h5-ccu", 1 },
738 #endif
739 { NULL, 0},
740 };
741
742 static int
ccu_h3_probe(device_t dev)743 ccu_h3_probe(device_t dev)
744 {
745
746 if (!ofw_bus_status_okay(dev))
747 return (ENXIO);
748
749 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
750 return (ENXIO);
751
752 device_set_desc(dev, "Allwinner H3/H5 Clock Control Unit NG");
753 return (BUS_PROBE_DEFAULT);
754 }
755
756 static int
ccu_h3_attach(device_t dev)757 ccu_h3_attach(device_t dev)
758 {
759 struct aw_ccung_softc *sc;
760
761 sc = device_get_softc(dev);
762
763 sc->resets = h3_ccu_resets;
764 sc->nresets = nitems(h3_ccu_resets);
765 sc->gates = h3_ccu_gates;
766 sc->ngates = nitems(h3_ccu_gates);
767 sc->clks = h3_ccu_clks;
768 sc->nclks = nitems(h3_ccu_clks);
769 sc->clk_init = h3_init_clks;
770 sc->n_clk_init = nitems(h3_init_clks);
771
772 return (aw_ccung_attach(dev));
773 }
774
775 static device_method_t ccu_h3ng_methods[] = {
776 /* Device interface */
777 DEVMETHOD(device_probe, ccu_h3_probe),
778 DEVMETHOD(device_attach, ccu_h3_attach),
779
780 DEVMETHOD_END
781 };
782
783 DEFINE_CLASS_1(ccu_h3ng, ccu_h3ng_driver, ccu_h3ng_methods,
784 sizeof(struct aw_ccung_softc), aw_ccung_driver);
785
786 EARLY_DRIVER_MODULE(ccu_h3ng, simplebus, ccu_h3ng_driver, 0, 0,
787 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
788