1 // OpenSTA, Static Timing Analyzer 2 // Copyright (c) 2020, Parallax Software, Inc. 3 // 4 // This program is free software: you can redistribute it and/or modify 5 // it under the terms of the GNU General Public License as published by 6 // the Free Software Foundation, either version 3 of the License, or 7 // (at your option) any later version. 8 // 9 // This program is distributed in the hope that it will be useful, 10 // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 // GNU General Public License for more details. 13 // 14 // You should have received a copy of the GNU General Public License 15 // along with this program. If not, see <https://www.gnu.org/licenses/>. 16 17 #pragma once 18 19 #include <mutex> 20 21 #include "DisallowCopyAssign.hh" 22 #include "StringUtil.hh" 23 #include "StringSet.hh" 24 #include "Map.hh" 25 #include "HashSet.hh" 26 #include "UnorderedMap.hh" 27 #include "MinMax.hh" 28 #include "StaState.hh" 29 #include "NetworkClass.hh" 30 #include "LibertyClass.hh" 31 #include "GraphClass.hh" 32 #include "SdcClass.hh" 33 #include "RiseFallValues.hh" 34 #include "Clock.hh" 35 #include "DataCheck.hh" 36 #include "CycleAccting.hh" 37 38 namespace sta { 39 40 class OperatingConditions; 41 class PortExtCap; 42 class ClockGatingCheck; 43 class InputDriveCell; 44 class DisabledPorts; 45 class GraphLoop; 46 class DeratingFactors; 47 class DeratingFactorsGlobal; 48 class DeratingFactorsNet; 49 class DeratingFactorsCell; 50 class PatternMatch; 51 class FindNetCaps; 52 class ClkHpinDisable; 53 class FindClkHpinDisables; 54 class Corner; 55 class ClockGroupIterator; 56 class GroupPathIterator; 57 class ClockPinIterator; 58 class ClockIterator; 59 60 typedef std::pair<const Pin*, const Clock*> PinClockPair; 61 62 class ClockInsertionPinClkLess 63 { 64 public: 65 bool operator()(const ClockInsertion *insert1, 66 const ClockInsertion *insert2) const; 67 }; 68 69 class ClockLatencyPinClkLess 70 { 71 public: 72 bool operator()(const ClockLatency *latency1, 73 const ClockLatency *latency2) const; 74 }; 75 76 // This is symmetric with respect to the clocks 77 // in the pair so Pair(clk1, clk2) is the same 78 // as Pair(clk2, clk1). 79 class ClockPairLess 80 { 81 public: 82 bool operator()(const ClockPair &pair1, 83 const ClockPair &pair2) const; 84 }; 85 86 class PinClockPairLess 87 { 88 public: 89 PinClockPairLess(const Network *network); 90 bool operator()(const PinClockPair &pin_clk1, 91 const PinClockPair &pin_clk2) const; 92 93 protected: 94 const Network *network_; 95 }; 96 97 class ClkHpinDisableLess 98 { 99 public: 100 bool operator()(const ClkHpinDisable *disable1, 101 const ClkHpinDisable *disable2) const; 102 }; 103 104 typedef Map<const char*,Clock*, CharPtrLess> ClockNameMap; 105 typedef UnorderedMap<const Pin*, ClockSet*> ClockPinMap; 106 typedef Set<InputDelay*> InputDelaySet; 107 typedef Map<const Pin*,InputDelaySet*> InputDelaysPinMap; 108 typedef Set<OutputDelay*> OutputDelaySet; 109 typedef Map<const Pin*,OutputDelaySet*> OutputDelaysPinMap; 110 // Use HashSet so no read lock is required. 111 typedef HashSet<CycleAccting*, CycleAcctingHash, CycleAcctingEqual> CycleAcctingSet; 112 typedef Set<Instance*> InstanceSet; 113 typedef UnorderedMap<const Pin*,ExceptionPathSet*> PinExceptionsMap; 114 typedef Map<const Clock*,ExceptionPathSet*> ClockExceptionsMap; 115 typedef Map<const Instance*,ExceptionPathSet*> InstanceExceptionsMap; 116 typedef Map<const Net*,ExceptionPathSet*> NetExceptionsMap; 117 typedef UnorderedMap<const EdgePins*,ExceptionPathSet*, 118 PinPairHash, PinPairEqual> EdgeExceptionsMap; 119 typedef Vector<ExceptionThru*> ExceptionThruSeq; 120 typedef Map<const Port*,InputDrive*> InputDriveMap; 121 typedef Map<int, ExceptionPathSet*, std::less<int> > ExceptionPathPtHash; 122 typedef Set<ClockLatency*, ClockLatencyPinClkLess> ClockLatencies; 123 typedef Map<const Pin*, ClockUncertainties*> PinClockUncertaintyMap; 124 typedef Set<InterClockUncertainty*, 125 InterClockUncertaintyLess> InterClockUncertaintySet; 126 typedef Map<const Clock*, ClockGatingCheck*> ClockGatingCheckMap; 127 typedef Map<const Instance*, ClockGatingCheck*> InstanceClockGatingCheckMap; 128 typedef Map<const Pin*, ClockGatingCheck*> PinClockGatingCheckMap; 129 typedef Set<ClockInsertion*, ClockInsertionPinClkLess> ClockInsertions; 130 typedef Map<const Pin*, float> PinLatchBorrowLimitMap; 131 typedef Map<const Instance*, float> InstLatchBorrowLimitMap; 132 typedef Map<const Clock*, float> ClockLatchBorrowLimitMap; 133 typedef Set<DataCheck*, DataCheckLess> DataCheckSet; 134 typedef Map<const Pin*, DataCheckSet*> DataChecksMap; 135 typedef Map<Port*, PortExtCap*> PortExtCapMap; 136 typedef Map<Net*, MinMaxFloatValues> NetResistanceMap; 137 typedef Map<Port*, MinMaxFloatValues> PortSlewLimitMap; 138 typedef Map<const Pin*, MinMaxFloatValues> PinSlewLimitMap; 139 typedef Map<Cell*, MinMaxFloatValues> CellSlewLimitMap; 140 typedef Map<Cell*, MinMaxFloatValues> CellCapLimitMap; 141 typedef Map<Port*, MinMaxFloatValues> PortCapLimitMap; 142 typedef Map<Pin*, MinMaxFloatValues> PinCapLimitMap; 143 typedef Map<Port*, MinMaxFloatValues> PortFanoutLimitMap; 144 typedef Map<Cell*, MinMaxFloatValues> CellFanoutLimitMap; 145 typedef Map<Net*, MinMaxFloatValues> NetWireCapMap; 146 typedef Map<Pin*, MinMaxFloatValues*> PinWireCapMap; 147 typedef Map<Instance*, Pvt*> InstancePvtMap; 148 typedef Map<Edge*, ClockLatency*> EdgeClockLatencyMap; 149 typedef Map<const Pin*, RiseFallValues*> PinMinPulseWidthMap; 150 typedef Map<const Clock*, RiseFallValues*> ClockMinPulseWidthMap; 151 typedef Map<const Instance*, RiseFallValues*> InstMinPulseWidthMap; 152 typedef Map<const Net*, DeratingFactorsNet*> NetDeratingFactorsMap; 153 typedef Map<const Instance*, DeratingFactorsCell*> InstDeratingFactorsMap; 154 typedef Map<const LibertyCell*, DeratingFactorsCell*> CellDeratingFactorsMap; 155 typedef Set<ClockGroups*> ClockGroupsSet; 156 typedef Map<const Clock*, ClockGroupsSet*> ClockGroupsClkMap; 157 typedef Map<const char*, ClockGroups*, CharPtrLess> ClockGroupsNameMap; 158 typedef Map<PinClockPair, ClockSense, PinClockPairLess> ClockSenseMap; 159 typedef Set<ClkHpinDisable*, ClkHpinDisableLess> ClkHpinDisables; 160 typedef Set<GroupPath*> GroupPathSet; 161 typedef Map<const char*, GroupPathSet*, CharPtrLess> GroupPathMap; 162 typedef Set<ClockPair, ClockPairLess> ClockPairSet; 163 164 void 165 findLeafLoadPins(Pin *pin, 166 const Network *network, 167 PinSet *leaf_pins); 168 void 169 findLeafDriverPins(Pin *pin, 170 const Network *network, 171 PinSet *leaf_pins); 172 173 class Sdc : public StaState 174 { 175 public: 176 explicit Sdc(StaState *sta); 177 ~Sdc(); 178 // Note that Search may reference a Filter exception removed by clear(). 179 void clear(); 180 // Return true if pin is referenced by any constraint. 181 bool isConstrained(const Pin *pin) const; 182 // Return true if inst is referenced by any constraint. 183 // Does NOT include references by pins connected to the instance. 184 bool isConstrained(const Instance *inst) const; 185 // Return true if net is referenced by any constraint. 186 // Does NOT include references by pins connected to the net. 187 bool isConstrained(const Net *net) const; 188 // Build data structures for search. 189 void searchPreamble(); 190 void deleteNetBefore(Net *net); 191 192 // SWIG sdc interface. analysisType()193 AnalysisType analysisType() { return analysis_type_; } 194 void setAnalysisType(AnalysisType analysis_type); 195 void setOperatingConditions(OperatingConditions *op_cond, 196 const MinMaxAll *min_max); 197 void setOperatingConditions(OperatingConditions *op_cond, 198 const MinMax *min_max); 199 void setTimingDerate(TimingDerateType type, 200 PathClkOrData clk_data, 201 const RiseFallBoth *rf, 202 const EarlyLate *early_late, 203 float derate); 204 // Delay type is always net for net derating. 205 void setTimingDerate(const Net *net, 206 PathClkOrData clk_data, 207 const RiseFallBoth *rf, 208 const EarlyLate *early_late, 209 float derate); 210 void setTimingDerate(const Instance *inst, 211 TimingDerateType type, 212 PathClkOrData clk_data, 213 const RiseFallBoth *rf, 214 const EarlyLate *early_late, 215 float derate); 216 void setTimingDerate(const LibertyCell *cell, 217 TimingDerateType type, 218 PathClkOrData clk_data, 219 const RiseFallBoth *rf, 220 const EarlyLate *early_late, 221 float derate); 222 float timingDerateInstance(const Pin *pin, 223 TimingDerateType type, 224 PathClkOrData clk_data, 225 const RiseFall *rf, 226 const EarlyLate *early_late) const; 227 float timingDerateNet(const Pin *pin, 228 PathClkOrData clk_data, 229 const RiseFall *rf, 230 const EarlyLate *early_late) const; 231 void unsetTimingDerate(); 232 void setInputSlew(Port *port, const RiseFallBoth *rf, 233 const MinMaxAll *min_max, float slew); 234 // Set the rise/fall drive resistance on design port. 235 void setDriveResistance(Port *port, 236 const RiseFallBoth *rf, 237 const MinMaxAll *min_max, 238 float res); 239 // Set the drive on design port using external cell timing arcs of 240 // cell driven by from_slews between from_port and to_port. 241 void setDriveCell(LibertyLibrary *library, 242 LibertyCell *cell, 243 Port *port, 244 LibertyPort *from_port, 245 float *from_slews, 246 LibertyPort *to_port, 247 const RiseFallBoth *rf, 248 const MinMaxAll *min_max); 249 void setLatchBorrowLimit(Pin *pin, 250 float limit); 251 void setLatchBorrowLimit(Instance *inst, 252 float limit); 253 void setLatchBorrowLimit(Clock *clk, 254 float limit); 255 // Return the latch borrow limit respecting precidence if multiple 256 // limits apply. 257 void latchBorrowLimit(Pin *data_pin, 258 Pin *enable_pin, 259 Clock *clk, 260 // Return values. 261 float &limit, 262 bool &exists); 263 void setMinPulseWidth(const RiseFallBoth *rf, 264 float min_width); 265 void setMinPulseWidth(const Pin *pin, 266 const RiseFallBoth *rf, 267 float min_width); 268 void setMinPulseWidth(const Instance *inst, 269 const RiseFallBoth *rf, 270 float min_width); 271 void setMinPulseWidth(const Clock *clk, 272 const RiseFallBoth *rf, 273 float min_width); 274 // Return min pulse with respecting precidence. 275 void minPulseWidth(const Pin *pin, 276 const Clock *clk, 277 const RiseFall *hi_low, 278 float &min_width, 279 bool &exists) const; 280 void setSlewLimit(Clock *clk, 281 const RiseFallBoth *rf, 282 const PathClkOrData clk_data, 283 const MinMax *min_max, 284 float slew); 285 bool haveClkSlewLimits() const; 286 void slewLimit(Clock *clk, 287 const RiseFall *rf, 288 const PathClkOrData clk_data, 289 const MinMax *min_max, 290 float &slew, 291 bool &exists); 292 void slewLimit(Port *port, 293 const MinMax *min_max, 294 float &slew, 295 bool &exists); 296 void setSlewLimit(Port *port, 297 const MinMax *min_max, 298 float slew); 299 void slewLimit(Cell *cell, 300 const MinMax *min_max, 301 float &slew, 302 bool &exists); 303 void setSlewLimit(Cell *cell, 304 const MinMax *min_max, 305 float slew); 306 void capacitanceLimit(Port *port, 307 const MinMax *min_max, 308 float &cap, 309 bool &exists); 310 void capacitanceLimit(Pin *pin, 311 const MinMax *min_max, 312 float &cap, 313 bool &exists); 314 void capacitanceLimit(Cell *cell, 315 const MinMax *min_max, 316 float &cap, 317 bool &exists); 318 void setCapacitanceLimit(Port *port, 319 const MinMax *min_max, 320 float cap); 321 void setCapacitanceLimit(Pin *pin, 322 const MinMax *min_max, 323 float cap); 324 void setCapacitanceLimit(Cell *cell, 325 const MinMax *min_max, 326 float cap); 327 void fanoutLimit(Port *port, 328 const MinMax *min_max, 329 float &fanout, 330 bool &exists); 331 void setFanoutLimit(Port *port, 332 const MinMax *min_max, 333 float fanout); 334 void fanoutLimit(Cell *cell, 335 const MinMax *min_max, 336 float &fanout, 337 bool &exists); 338 void setFanoutLimit(Cell *cell, 339 const MinMax *min_max, 340 float fanout); 341 void setMaxArea(float area); 342 float maxArea() const; 343 virtual Clock *makeClock(const char *name, 344 PinSet *pins, 345 bool add_to_pins, 346 float period, 347 FloatSeq *waveform, 348 const char *comment); 349 // edges size must be 3. 350 virtual Clock *makeGeneratedClock(const char *name, 351 PinSet *pins, 352 bool add_to_pins, 353 Pin *src_pin, 354 Clock *master_clk, 355 Pin *pll_out, 356 Pin *pll_fdbk, 357 int divide_by, 358 int multiply_by, 359 float duty_cycle, 360 bool invert, 361 bool combinational, 362 IntSeq *edges, 363 FloatSeq *edge_shifts, 364 const char *comment); 365 // Invalidate all generated clock waveforms. 366 void invalidateGeneratedClks() const; 367 virtual void removeClock(Clock *clk); 368 virtual void clockDeletePin(Clock *clk, 369 Pin *pin); 370 // Clock used for inputs without defined arrivals. 371 ClockEdge *defaultArrivalClockEdge() const; defaultArrivalClock() const372 Clock *defaultArrivalClock() const { return default_arrival_clk_; } 373 // Propagated (non-ideal) clocks. 374 void setPropagatedClock(Clock *clk); 375 void removePropagatedClock(Clock *clk); 376 void setPropagatedClock(Pin *pin); 377 void removePropagatedClock(Pin *pin); 378 bool isPropagatedClock(const Pin *pin); 379 void setClockSlew(Clock *clk, 380 const RiseFallBoth *rf, 381 const MinMaxAll *min_max, 382 float slew); 383 void removeClockSlew(Clock *clk); 384 // Latency can be on a clk, pin, or clk/pin combination. 385 void setClockLatency(Clock *clk, 386 Pin *pin, 387 const RiseFallBoth *rf, 388 const MinMaxAll *min_max, 389 float delay); 390 void removeClockLatency(const Clock *clk, 391 const Pin *pin); 392 ClockLatency *clockLatency(Edge *edge) const; 393 bool hasClockLatency(const Pin *pin) const; 394 void clockLatency(Edge *edge, 395 const RiseFall *rf, 396 const MinMax *min_max, 397 // Return values. 398 float &latency, 399 bool &exists) const; clockLatencies()400 ClockLatencies *clockLatencies() { return &clk_latencies_; } clockLatencies() const401 const ClockLatencies *clockLatencies() const { return &clk_latencies_; } 402 // Clock latency on pin with respect to clk. 403 // This does NOT check for latency on clk (without pin). 404 void clockLatency(const Clock *clk, 405 const Pin *pin, 406 const RiseFall *rf, 407 const MinMax *min_max, 408 // Return values. 409 float &latency, 410 bool &exists) const; 411 void clockLatency(const Clock *clk, 412 const RiseFall *rf, 413 const MinMax *min_max, 414 // Return values. 415 float &latency, 416 bool &exists) const; 417 float clockLatency(const Clock *clk, 418 const RiseFall *rf, 419 const MinMax *min_max) const; 420 // Clock insertion delay (set_clk_latency -source). 421 // Insertion delay can be on a clk, pin, or clk/pin combination. 422 void setClockInsertion(const Clock *clk, 423 const Pin *pin, 424 const RiseFallBoth *rf, 425 const MinMaxAll *min_max, 426 const EarlyLateAll *early_late, 427 float delay); 428 void setClockInsertion(const Clock *clk, const Pin *pin, 429 const RiseFall *rf, 430 const MinMax *min_max, 431 const EarlyLate *early_late, 432 float delay); 433 void removeClockInsertion(const Clock *clk, 434 const Pin *pin); 435 bool hasClockInsertion(const Pin *pin) const; 436 float clockInsertion(const Clock *clk, 437 const RiseFall *rf, 438 const MinMax *min_max, 439 const EarlyLate *early_late) const; 440 // Respects precedence of pin/clk and set_input_delay on clk pin. 441 void clockInsertion(const Clock *clk, 442 const Pin *pin, 443 const RiseFall *rf, 444 const MinMax *min_max, 445 const EarlyLate *early_late, 446 // Return values. 447 float &insertion, 448 bool &exists) const; clockInsertions()449 ClockInsertions *clockInsertions() { return clk_insertions_; } 450 // Clock uncertainty. 451 virtual void setClockUncertainty(Pin *pin, 452 const SetupHoldAll *setup_hold, 453 float uncertainty); 454 virtual void removeClockUncertainty(Pin *pin, 455 const SetupHoldAll *setup_hold); 456 virtual void setClockUncertainty(Clock *from_clk, 457 const RiseFallBoth *from_rf, 458 Clock *to_clk, 459 const RiseFallBoth *to_rf, 460 const SetupHoldAll *setup_hold, 461 float uncertainty); 462 virtual void removeClockUncertainty(Clock *from_clk, 463 const RiseFallBoth *from_rf, 464 Clock *to_clk, 465 const RiseFallBoth *to_rf, 466 const SetupHoldAll *setup_hold); 467 ClockGroups *makeClockGroups(const char *name, 468 bool logically_exclusive, 469 bool physically_exclusive, 470 bool asynchronous, 471 bool allow_paths, 472 const char *comment); 473 void makeClockGroup(ClockGroups *clk_groups, 474 ClockSet *clks); 475 void removeClockGroups(const char *name); 476 // nullptr name removes all. 477 void removeClockGroupsLogicallyExclusive(const char *name); 478 void removeClockGroupsPhysicallyExclusive(const char *name); 479 void removeClockGroupsAsynchronous(const char *name); 480 bool sameClockGroup(const Clock *clk1, 481 const Clock *clk2); 482 // Clocks explicitly excluded by set_clock_group. 483 bool sameClockGroupExplicit(const Clock *clk1, 484 const Clock *clk2); 485 ClockGroupIterator *clockGroupIterator(); 486 void setClockSense(PinSet *pins, 487 ClockSet *clks, 488 ClockSense sense); 489 bool clkStopPropagation(const Pin *pin, 490 const Clock *clk) const; 491 bool clkStopPropagation(const Clock *clk, 492 const Pin *from_pin, 493 const RiseFall *from_rf, 494 const Pin *to_pin, 495 const RiseFall *to_rf) const; 496 void setClockGatingCheck(const RiseFallBoth *rf, 497 const SetupHold *setup_hold, 498 float margin); 499 void setClockGatingCheck(Instance *inst, 500 const RiseFallBoth *rf, 501 const SetupHold *setup_hold, 502 float margin, 503 LogicValue active_value); 504 void setClockGatingCheck(Clock *clk, 505 const RiseFallBoth *rf, 506 const SetupHold *setup_hold, 507 float margin); 508 void setClockGatingCheck(const Pin *pin, 509 const RiseFallBoth *rf, 510 const SetupHold *setup_hold, 511 float margin, 512 LogicValue active_value); 513 void setDataCheck(Pin *from, 514 const RiseFallBoth *from_rf, 515 Pin *to, 516 const RiseFallBoth *to_rf, 517 Clock *clk, 518 const SetupHoldAll *setup_hold, 519 float margin); 520 void removeDataCheck(Pin *from, 521 const RiseFallBoth *from_rf, 522 Pin *to, 523 const RiseFallBoth *to_rf, 524 Clock *clk, 525 const SetupHoldAll *setup_hold); 526 DataCheckSet *dataChecksFrom(const Pin *from) const; 527 DataCheckSet *dataChecksTo(const Pin *to) const; 528 void setInputDelay(Pin *pin, 529 const RiseFallBoth *rf, 530 Clock *clk, 531 const RiseFall *clk_rf, 532 Pin *ref_pin, 533 bool source_latency_included, 534 bool network_latency_included, 535 const MinMaxAll *min_max, 536 bool add, float delay); 537 void removeInputDelay(Pin *pin, 538 RiseFallBoth *rf, 539 Clock *clk, 540 RiseFall *clk_rf, 541 MinMaxAll *min_max); 542 void setOutputDelay(Pin *pin, 543 const RiseFallBoth *rf, 544 Clock *clk, 545 const RiseFall *clk_tr, 546 Pin *ref_pin, 547 bool source_latency_included, 548 bool network_latency_included, 549 const MinMaxAll *min_max, 550 bool add, float delay); 551 void removeOutputDelay(Pin *pin, 552 RiseFallBoth *rf, 553 Clock *clk, 554 RiseFall *clk_rf, 555 MinMaxAll *min_max); 556 // Set port external pin load (set_load -pin_load port). 557 void setPortExtPinCap(Port *port, 558 const RiseFall *rf, 559 const MinMax *min_max, 560 float cap); 561 // Set port external wire load (set_load -wire port). 562 void setPortExtWireCap(Port *port, 563 bool subtract_pin_cap, 564 const RiseFall *rf, 565 const Corner *corner, 566 const MinMax *min_max, 567 float cap); 568 // Remove all "set_load" and "set_fanout_load" annotations. 569 void removeLoadCaps(); 570 // Remove all "set_load net" annotations. 571 void removeNetLoadCaps(); 572 void setNetWireCap(Net *net, 573 bool subtract_pin_cap, 574 const Corner *corner, 575 const MinMax *min_max, 576 float cap); 577 bool hasNetWireCap(Net *net) const; 578 // True if driver pin net has wire capacitance. 579 bool drvrPinHasWireCap(const Pin *pin); 580 // Net wire capacitance (set_load -wire net). 581 void drvrPinWireCap(const Pin *drvr_pin, 582 const Corner *corner, 583 const MinMax *min_max, 584 // Return values. 585 float &cap, 586 bool &exists) const; 587 // Pin capacitance derated by operating conditions and instance pvt. 588 float pinCapacitance(const Pin *pin, 589 const RiseFall *rf, 590 const OperatingConditions *op_cond, 591 const Corner *corner, 592 const MinMax *min_max); 593 void setResistance(Net *net, 594 const MinMaxAll *min_max, 595 float res); 596 void resistance(Net *net, 597 const MinMax *min_max, 598 float &res, 599 bool &exists); netResistances()600 NetResistanceMap *netResistances() { return &net_res_map_; } 601 void setPortExtFanout(Port *port, 602 const MinMax *min_max, 603 int fanout); 604 // set_disable_timing cell [-from] [-to] 605 // Disable all edges thru cell if from/to are null. 606 // Bus and bundle ports are NOT supported. 607 void disable(LibertyCell *cell, 608 LibertyPort *from, 609 LibertyPort *to); 610 void removeDisable(LibertyCell *cell, 611 LibertyPort *from, 612 LibertyPort *to); 613 // set_disable_timing liberty port. 614 // Bus and bundle ports are NOT supported. 615 void disable(LibertyPort *port); 616 void removeDisable(LibertyPort *port); 617 // set_disable_timing port (top level instance port). 618 // Bus and bundle ports are NOT supported. 619 void disable(Port *port); 620 void removeDisable(Port *port); 621 // set_disable_timing instance [-from] [-to]. 622 // Disable all edges thru instance if from/to are null. 623 // Bus and bundle ports are NOT supported. 624 void disable(Instance *inst, 625 LibertyPort *from, 626 LibertyPort *to); 627 void removeDisable(Instance *inst, 628 LibertyPort *from, 629 LibertyPort *to); 630 // set_disable_timing pin 631 void disable(Pin *pin); 632 void removeDisable(Pin *pin); 633 // set_disable_timing [get_timing_arc -of_objects instance]] 634 void disable(Edge *edge); 635 void removeDisable(Edge *edge); 636 // set_disable_timing [get_timing_arc -of_objects lib_cell]] 637 void disable(TimingArcSet *arc_set); 638 void removeDisable(TimingArcSet *arc_set); 639 // Disable a wire edge. From/to pins musts be on the same net. 640 // There is no SDC equivalent to this. 641 void disable(Pin *from, Pin *to); 642 void removeDisable(Pin *from, Pin *to); 643 bool isDisabled(const Pin *pin) const; 644 // Edge disabled by hierarchical pin disable or instance/cell port pair. 645 // Disables do NOT apply to timing checks. 646 // inst can be either the from_pin or to_pin instance because it 647 // is only referenced when they are the same (non-wire edge). 648 bool isDisabled(const Instance *inst, 649 const Pin *from_pin, 650 const Pin *to_pin, 651 const TimingRole *role) const; 652 bool isDisabled(Edge *edge); 653 bool isDisabled(TimingArcSet *arc_set) const; 654 DisabledCellPortsMap *disabledCellPorts(); 655 DisabledInstancePortsMap *disabledInstancePorts(); disabledPins()656 PinSet *disabledPins() { return &disabled_pins_; } disabledPorts()657 PortSet *disabledPorts() { return &disabled_ports_; } disabledLibPorts()658 LibertyPortSet *disabledLibPorts() { return &disabled_lib_ports_; } disabledEdges()659 EdgeSet *disabledEdges() { return &disabled_edges_; } 660 void disableClockGatingCheck(Instance *inst); 661 void disableClockGatingCheck(Pin *pin); 662 void removeDisableClockGatingCheck(Instance *inst); 663 void removeDisableClockGatingCheck(Pin *pin); 664 bool isDisableClockGatingCheck(const Pin *pin); 665 bool isDisableClockGatingCheck(const Instance *inst); 666 // set_LogicValue::zero, set_LogicValue::one, set_logic_dc 667 void setLogicValue(Pin *pin, 668 LogicValue value); 669 // set_case_analysis 670 void setCaseAnalysis(Pin *pin, 671 LogicValue value); 672 void removeCaseAnalysis(Pin *pin); 673 void logicValue(const Pin *pin, 674 LogicValue &value, 675 bool &exists); 676 void caseLogicValue(const Pin *pin, LogicValue &value, bool &exists); 677 // Pin has set_case_analysis or set_logic constant value. 678 bool hasLogicValue(const Pin *pin); 679 // The from/thrus/to arguments passed into the following functions 680 // that make exceptions are owned by the constraints once they are 681 // passed in. The constraint internals may change or delete them do 682 // to exception merging. 683 void makeFalsePath(ExceptionFrom *from, 684 ExceptionThruSeq *thrus, 685 ExceptionTo *to, 686 const MinMaxAll *min_max, 687 const char *comment); 688 // Loop paths are false paths used to disable paths around 689 // combinational loops when dynamic loop breaking is enabled. 690 void makeLoopExceptions(); 691 void makeLoopExceptions(GraphLoop *loop); 692 void makeMulticyclePath(ExceptionFrom *from, 693 ExceptionThruSeq *thrus, 694 ExceptionTo *to, 695 const MinMaxAll *min_max, 696 bool use_end_clk, 697 int path_multiplier, 698 const char *comment); 699 void makePathDelay(ExceptionFrom *from, 700 ExceptionThruSeq *thrus, 701 ExceptionTo *to, 702 const MinMax *min_max, 703 bool ignore_clk_latency, 704 float delay, 705 const char *comment); pathDelaysWithoutTo() const706 bool pathDelaysWithoutTo() const { return path_delays_without_to_; } 707 // Delete matching false/multicycle/path_delay exceptions. 708 // Caller owns from, thrus, to exception points (and must delete them). 709 void resetPath(ExceptionFrom *from, 710 ExceptionThruSeq *thrus, 711 ExceptionTo *to, 712 const MinMaxAll *min_max); 713 void makeGroupPath(const char *name, 714 bool is_default, 715 ExceptionFrom *from, 716 ExceptionThruSeq *thrus, 717 ExceptionTo *to, 718 const char *comment); 719 GroupPathIterator *groupPathIterator(); 720 bool isGroupPathName(const char *group_name); 721 void addException(ExceptionPath *exception); 722 // The pin/clk/instance/net set arguments passed into the following 723 // functions that make exception from/thru/to's are owned by the 724 // constraints once they are passed in. 725 ExceptionFrom *makeExceptionFrom(PinSet *from_pins, 726 ClockSet *from_clks, 727 InstanceSet *from_insts, 728 const RiseFallBoth *from_rf); 729 // Make an exception -through specification. 730 ExceptionThru *makeExceptionThru(PinSet *pins, 731 NetSet *nets, 732 InstanceSet *insts, 733 const RiseFallBoth *rf); 734 bool exceptionToInvalid(const Pin *pin); 735 // Make an exception -to specification. 736 ExceptionTo *makeExceptionTo(PinSet *pins, 737 ClockSet *clks, 738 InstanceSet *insts, 739 const RiseFallBoth *rf, 740 const RiseFallBoth *end_rf); 741 FilterPath *makeFilterPath(ExceptionFrom *from, 742 ExceptionThruSeq *thrus, 743 ExceptionTo *to); 744 Clock *findClock(const char *name) const; 745 virtual void findClocksMatching(PatternMatch *pattern, 746 ClockSeq *clks) const; 747 // Wireload set by set_wire_load_model or default library default_wire_load. 748 Wireload *wireloadDefaulted(const MinMax *min_max); 749 Wireload *wireload(const MinMax *min_max); 750 void setWireload(Wireload *wireload, 751 const MinMaxAll *min_max); 752 WireloadMode wireloadMode(); 753 void setWireloadMode(WireloadMode mode); 754 const WireloadSelection *wireloadSelection(const MinMax *min_max); 755 void setWireloadSelection(WireloadSelection *selection, 756 const MinMaxAll *min_max); 757 // Common reconvergent clock pessimism. 758 // TCL variable sta_crpr_enabled. 759 bool crprEnabled() const; 760 void setCrprEnabled(bool enabled); 761 // TCL variable sta_crpr_mode. 762 CrprMode crprMode() const; 763 void setCrprMode(CrprMode mode); 764 // True when analysis type is on chip variation and crpr is enabled. 765 bool crprActive() const; 766 // TCL variable sta_propagate_gated_clock_enable. 767 // Propagate gated clock enable arrivals. 768 bool propagateGatedClockEnable() const; 769 void setPropagateGatedClockEnable(bool enable); 770 // TCL variable sta_preset_clear_arcs_enabled. 771 // Enable search through preset/clear arcs. 772 bool presetClrArcsEnabled() const; 773 void setPresetClrArcsEnabled(bool enable); 774 // TCL variable sta_cond_default_arcs_enabled. 775 // Enable/disable default arcs when conditional arcs exist. 776 bool condDefaultArcsEnabled() const; 777 void setCondDefaultArcsEnabled(bool enabled); 778 bool isDisabledCondDefault(Edge *edge) const; 779 // TCL variable sta_internal_bidirect_instance_paths_enabled. 780 // Enable/disable timing from bidirect pins back into the instance. 781 bool bidirectInstPathsEnabled() const; 782 void setBidirectInstPathsEnabled(bool enabled); 783 // TCL variable sta_bidirect_net_paths_enabled. 784 // Enable/disable timing from bidirect driver pins to their own loads. 785 bool bidirectNetPathsEnabled() const; 786 void setBidirectNetPathsEnabled(bool enabled); 787 // TCL variable sta_recovery_removal_checks_enabled. 788 bool recoveryRemovalChecksEnabled() const; 789 void setRecoveryRemovalChecksEnabled(bool enabled); 790 // TCL variable sta_gated_clock_checks_enabled. 791 bool gatedClkChecksEnabled() const; 792 void setGatedClkChecksEnabled(bool enabled); 793 // TCL variable sta_dynamic_loop_breaking. 794 bool dynamicLoopBreaking() const; 795 void setDynamicLoopBreaking(bool enable); 796 // TCL variable sta_propagate_all_clocks. 797 bool propagateAllClocks() const; 798 void setPropagateAllClocks(bool prop); 799 // TCL var sta_clock_through_tristate_enabled. 800 bool clkThruTristateEnabled() const; 801 void setClkThruTristateEnabled(bool enable); 802 // TCL variable sta_input_port_default_clock. 803 bool useDefaultArrivalClock(); 804 void setUseDefaultArrivalClock(bool enable); 805 806 // STA interface. 807 InputDelaySet *refPinInputDelays(const Pin *ref_pin) const; logicValues()808 LogicValueMap *logicValues() { return &logic_value_map_; } caseLogicValues()809 LogicValueMap *caseLogicValues() { return &case_value_map_; } 810 // Returns nullptr if set_operating_conditions has not been called. 811 OperatingConditions *operatingConditions(const MinMax *min_max); 812 // Instance specific process/voltage/temperature. 813 Pvt *pvt(Instance *inst, const MinMax *min_max) const; 814 // Pvt may be shared among multiple instances. 815 void setPvt(Instance *inst, 816 const MinMaxAll *min_max, 817 Pvt *pvt); 818 InputDrive *findInputDrive(Port *port); 819 // True if pin is defined as a clock source (pin may be hierarchical). 820 bool isClock(const Pin *pin) const; 821 // True if pin is a clock source vertex. 822 bool isLeafPinClock(const Pin *pin) const; 823 // True if pin is a non-generated clock source vertex. 824 bool isLeafPinNonGeneratedClock(const Pin *pin) const; 825 // Find the clocks defined for pin. 826 ClockSet *findClocks(const Pin *pin) const; 827 ClockSet *findLeafPinClocks(const Pin *pin) const; 828 void sortedClocks(ClockSeq &clks); clocks()829 ClockSeq *clocks() { return &clocks_; } clks()830 ClockSeq &clks() { return clocks_; } 831 bool clkDisabledByHpinThru(const Clock *clk, 832 const Pin *from_pin, 833 const Pin *to_pin); 834 void clkHpinDisablesInvalid(); 835 ClockUncertainties *clockUncertainties(const Pin *pin); 836 void clockUncertainty(const Pin *pin, 837 const SetupHold *setup_hold, 838 float &uncertainty, 839 bool &exists); 840 // Inter-clock uncertainty. 841 void clockUncertainty(const Clock *src_clk, 842 const RiseFall *src_rf, 843 const Clock *tgt_clk, 844 const RiseFall *tgt_rf, 845 const SetupHold *setup_hold, 846 float &uncertainty, bool &exists); 847 void clockGatingMarginEnablePin(const Pin *enable_pin, 848 const RiseFall *enable_rf, 849 const SetupHold *setup_hold, 850 bool &exists, float &margin); 851 void clockGatingMarginInstance(Instance *inst, 852 const RiseFall *enable_rf, 853 const SetupHold *setup_hold, 854 bool &exists, float &margin); 855 void clockGatingMarginClkPin(const Pin *clk_pin, 856 const RiseFall *enable_rf, 857 const SetupHold *setup_hold, 858 bool &exists, float &margin); 859 void clockGatingMarginClk(const Clock *clk, 860 const RiseFall *enable_rf, 861 const SetupHold *setup_hold, 862 bool &exists, float &margin); 863 void clockGatingMargin(const RiseFall *enable_rf, 864 const SetupHold *setup_hold, 865 bool &exists, float &margin); 866 // Gated clock active (non-controlling) logic value. 867 LogicValue clockGatingActiveValue(const Pin *clk_pin, 868 const Pin *enable_pin); 869 // Find the cycle accounting info for paths that start at src clock 870 // edge and end at target clock edge. 871 CycleAccting *cycleAccting(const ClockEdge *src, 872 const ClockEdge *tgt); 873 // Report clock to clock relationships that exceed max_cycle_count. 874 void reportClkToClkMaxCycleWarnings(); 875 inputDelays() const876 const InputDelaySet &inputDelays() const { return input_delays_; } 877 // Pin -> input delays. inputDelayPinMap() const878 const InputDelaysPinMap &inputDelayPinMap() const { return input_delay_pin_map_; } 879 // Input delays on leaf_pin. 880 InputDelaySet *inputDelaysLeafPin(const Pin *leaf_pin); 881 bool hasInputDelay(const Pin *leaf_pin) const; 882 // Pin is internal (not top level port) and has an input arrival. 883 bool isInputDelayInternal(const Pin *pin) const; 884 outputDelays() const885 const OutputDelaySet &outputDelays() const { return output_delays_; } 886 // Pin -> output delays. outputDelayPinMap() const887 const OutputDelaysPinMap &outputDelayPinMap() const { return output_delay_pin_map_; } 888 // Output delays on leaf_pin. 889 OutputDelaySet *outputDelaysLeafPin(const Pin *leaf_pin); 890 bool hasOutputDelay(const Pin *leaf_pin) const; 891 892 PortExtCap *portExtCap(Port *port) const; 893 bool hasPortExtCap(Port *port) const; 894 void portExtCap(Port *port, 895 const RiseFall *rf, 896 const MinMax *min_max, 897 // Return values. 898 float &pin_cap, 899 bool &has_pin_cap, 900 float &wire_cap, 901 bool &has_wire_cap, 902 int &fanout, 903 bool &has_fanout) const; 904 float portExtCap(Port *port, 905 const RiseFall *rf, 906 const MinMax *min_max) const; 907 // Connected total capacitance. 908 // pin_cap = pin capacitance + port external pin 909 // wire_cap = port external wire capacitance + net wire capacitance 910 void connectedCap(const Pin *pin, 911 const RiseFall *rf, 912 const OperatingConditions *op_cond, 913 const Corner *corner, 914 const MinMax *min_max, 915 float &pin_cap, 916 float &wire_cap, 917 float &fanout, 918 bool &has_set_load) const; 919 void portExtFanout(Port *port, 920 const MinMax *min_max, 921 // Return values. 922 int &fanout, 923 bool &exists); 924 int portExtFanout(Port *port, 925 const MinMax *min_max); 926 // Return true if search should proceed from pin/clk (no false paths 927 // start at pin/clk). When thru is true, consider -thru exceptions 928 // that start at pin/net/instance also). Transition tr applies to 929 // pin, not clk. 930 bool exceptionFromStates(const Pin *pin, 931 const RiseFall *rf, 932 const Clock *clk, 933 const RiseFall *clk_rf, 934 const MinMax *min_max, 935 ExceptionStateSet *&states) const; 936 bool exceptionFromStates(const Pin *pin, 937 const RiseFall *rf, 938 const Clock *clk, 939 const RiseFall *clk_rf, 940 const MinMax *min_max, 941 bool include_filter, 942 ExceptionStateSet *&states) const; 943 void exceptionFromClkStates(const Pin *pin, 944 const RiseFall *rf, 945 const Clock *clk, 946 const RiseFall *clk_rf, 947 const MinMax *min_max, 948 ExceptionStateSet *&states) const; 949 void filterRegQStates(const Pin *to_pin, 950 const RiseFall *to_rf, 951 const MinMax *min_max, 952 ExceptionStateSet *&states) const; 953 // Return hierarchical -thru exceptions that start between 954 // from_pin and to_pin. 955 void exceptionThruStates(const Pin *from_pin, 956 const Pin *to_pin, 957 const RiseFall *to_rf, 958 const MinMax *min_max, 959 ExceptionStateSet *&states) const; 960 // Find the highest priority exception with first exception pt at 961 // pin/clk end. 962 void exceptionTo(ExceptionPathType type, 963 const Pin *pin, 964 const RiseFall *rf, 965 const ClockEdge *clk_edge, 966 const MinMax *min_max, 967 bool match_min_max_exactly, 968 // Return values. 969 ExceptionPath *&hi_priority_exception, 970 int &hi_priority) const; 971 virtual bool exceptionMatchesTo(ExceptionPath *exception, 972 const Pin *pin, 973 const RiseFall *rf, 974 const ClockEdge *clk_edge, 975 const MinMax *min_max, 976 bool match_min_max_exactly, 977 bool require_to_pin) const; 978 bool isCompleteTo(ExceptionState *state, 979 const Pin *pin, 980 const RiseFall *rf, 981 const ClockEdge *clk_edge, 982 const MinMax *min_max, 983 bool match_min_max_exactly, 984 bool require_to_pin) const; 985 bool isPathDelayInternalStartpoint(const Pin *pin) const; 986 PinSet *pathDelayInternalStartpoints() const; 987 bool isPathDelayInternalEndpoint(const Pin *pin) const; exceptions()988 ExceptionPathSet *exceptions() { return &exceptions_; } 989 void deleteExceptions(); 990 void deleteException(ExceptionPath *exception); 991 void recordException(ExceptionPath *exception); 992 void unrecordException(ExceptionPath *exception); 993 void annotateGraph(); 994 void removeGraphAnnotations(); 995 996 // Network edit before/after methods. 997 void disconnectPinBefore(Pin *pin); 998 void connectPinAfter(Pin *pin); 999 void clkHpinDisablesChanged(Pin *pin); 1000 void makeClkHpinDisable(Clock *clk, 1001 Pin *drvr, 1002 Pin *load); 1003 void ensureClkHpinDisables(); 1004 bool bidirectDrvrSlewFromLoad(const Pin *pin) const; 1005 1006 protected: 1007 void initVariables(); 1008 void clearCycleAcctings(); 1009 void removeLibertyAnnotations(); 1010 void deleteExceptionMap(PinExceptionsMap *&exception_map); 1011 void deleteExceptionMap(InstanceExceptionsMap *&exception_map); 1012 void deleteExceptionMap(NetExceptionsMap *&exception_map); 1013 void deleteExceptionMap(ClockExceptionsMap *&exception_map); 1014 void deleteExceptionMap(EdgeExceptionsMap *&exception_map); 1015 void deleteExceptionsReferencing(Clock *clk); 1016 void deleteClkPinMappings(Clock *clk); 1017 void deleteExceptionPtHashMapSets(ExceptionPathPtHash &map); 1018 void makeClkPinMappings(Clock *clk); 1019 virtual void deletePinClocks(Clock *defining_clk, 1020 PinSet *pins); 1021 void makeDefaultArrivalClock(); 1022 InputDrive *ensureInputDrive(Port *port); 1023 PortExtCap *ensurePortExtPinCap(Port *port); 1024 ExceptionPath *findMergeMatch(ExceptionPath *exception); 1025 void addException1(ExceptionPath *exception); 1026 void addException2(ExceptionPath *exception); 1027 void recordPathDelayInternalStartpoints(ExceptionPath *exception); 1028 void unrecordPathDelayInternalStartpoints(ExceptionFrom *from); 1029 bool pathDelayFrom(const Pin *pin); 1030 virtual void recordPathDelayInternalEndpoints(ExceptionPath *exception); 1031 virtual void unrecordPathDelayInternalEndpoints(ExceptionPath *exception); 1032 bool pathDelayTo(const Pin *pin); 1033 bool hasLibertyChecks(const Pin *pin); 1034 void deleteMatchingExceptions(ExceptionPath *exception); 1035 void findMatchingExceptions(ExceptionPath *exception, 1036 ExceptionPathSet &matches); 1037 void checkForThruHpins(ExceptionPath *exception); 1038 void findMatchingExceptionsFirstFrom(ExceptionPath *exception, 1039 ExceptionPathSet &matches); 1040 void findMatchingExceptionsFirstThru(ExceptionPath *exception, 1041 ExceptionPathSet &matches); 1042 void findMatchingExceptionsFirstTo(ExceptionPath *exception, 1043 ExceptionPathSet &matches); 1044 void findMatchingExceptionsClks(ExceptionPath *exception, 1045 ClockSet *clks, 1046 ClockExceptionsMap *exception_map, 1047 ExceptionPathSet &matches); 1048 void findMatchingExceptionsPins(ExceptionPath *exception, 1049 PinSet *pins, 1050 PinExceptionsMap *exception_map, 1051 ExceptionPathSet &matches); 1052 void findMatchingExceptionsInsts(ExceptionPath *exception, 1053 InstanceSet *insts, 1054 InstanceExceptionsMap *exception_map, 1055 ExceptionPathSet &matches); 1056 void findMatchingExceptions(ExceptionPath *exception, 1057 ExceptionPathSet *potential_matches, 1058 ExceptionPathSet &matches); 1059 void expandExceptionExcluding(ExceptionPath *exception, 1060 ExceptionPath *excluding, 1061 ExceptionPathSet &expanded_matches); 1062 void recordException1(ExceptionPath *exception); 1063 void recordExceptionFirstPts(ExceptionPath *exception); 1064 void recordExceptionFirstFrom(ExceptionPath *exception); 1065 void recordExceptionFirstThru(ExceptionPath *exception); 1066 void recordExceptionFirstTo(ExceptionPath *exception); 1067 void recordExceptionClks(ExceptionPath *exception, 1068 ClockSet *clks, 1069 ClockExceptionsMap *&exception_map); 1070 void recordExceptionInsts(ExceptionPath *exception, 1071 InstanceSet *insts, 1072 InstanceExceptionsMap *&exception_map); 1073 void recordExceptionPins(ExceptionPath *exception, 1074 PinSet *pins, 1075 PinExceptionsMap *&exception_map); 1076 void recordExceptionNets(ExceptionPath *exception, 1077 NetSet *nets, 1078 NetExceptionsMap *&exception_map); 1079 void recordExceptionHpin(ExceptionPath *exception, 1080 Pin *pin, 1081 PinExceptionsMap *&exception_map); 1082 void recordExceptionEdges(ExceptionPath *exception, 1083 EdgePinsSet *edges, 1084 EdgeExceptionsMap *&exception_map); 1085 void recordMergeHash(ExceptionPath *exception, ExceptionPt *missing_pt); 1086 void recordMergeHashes(ExceptionPath *exception); 1087 void unrecordExceptionFirstPts(ExceptionPath *exception); 1088 void unrecordExceptionClks(ExceptionPath *exception, 1089 ClockSet *clks, 1090 ClockExceptionsMap *exception_map); 1091 void unrecordExceptionPins(ExceptionPath *exception, 1092 PinSet *pins, 1093 PinExceptionsMap *exception_map); 1094 void unrecordExceptionInsts(ExceptionPath *exception, 1095 InstanceSet *insts, 1096 InstanceExceptionsMap *exception_map); 1097 void unrecordExceptionEdges(ExceptionPath *exception, 1098 EdgePinsSet *edges, 1099 EdgeExceptionsMap *exception_map); 1100 void unrecordExceptionNets(ExceptionPath *exception, 1101 NetSet *nets, 1102 NetExceptionsMap *exception_map); 1103 void unrecordExceptionHpin(ExceptionPath *exception, 1104 Pin *pin, 1105 PinExceptionsMap *&exception_map); 1106 void unrecordMergeHashes(ExceptionPath *exception); 1107 void unrecordMergeHash(ExceptionPath *exception, 1108 ExceptionPt *missing_pt); 1109 void mergeException(ExceptionPath *exception); 1110 void expandException(ExceptionPath *exception, 1111 ExceptionPathSet &expansions); 1112 bool exceptionFromStates(const ExceptionPathSet *exceptions, 1113 const Pin *pin, 1114 const RiseFall *rf, 1115 const MinMax *min_max, 1116 bool include_filter, 1117 ExceptionStateSet *&states) const; 1118 void exceptionThruStates(const ExceptionPathSet *exceptions, 1119 const RiseFall *to_rf, 1120 const MinMax *min_max, 1121 // Return value. 1122 ExceptionStateSet *&states) const; 1123 void exceptionTo(const ExceptionPathSet *to_exceptions, 1124 ExceptionPathType type, 1125 const Pin *pin, 1126 const RiseFall *rf, 1127 const ClockEdge *clk_edge, 1128 const MinMax *min_max, 1129 bool match_min_max_exactly, 1130 // Return values. 1131 ExceptionPath *&hi_priority_exception, 1132 int &hi_priority) const; 1133 void exceptionTo(ExceptionPath *exception, 1134 ExceptionPathType type, 1135 const Pin *pin, 1136 const RiseFall *rf, 1137 const ClockEdge *clk_edge, 1138 const MinMax *min_max, 1139 bool match_min_max_exactly, 1140 // Return values. 1141 ExceptionPath *&hi_priority_exception, 1142 int &hi_priority) const; 1143 void makeLoopPath(ExceptionThruSeq *thrus); 1144 void makeLoopException(Pin *loop_input_pin, 1145 Pin *loop_pin, 1146 Pin *loop_prev_pin); 1147 void makeLoopExceptionThru(Pin *pin, 1148 ExceptionThruSeq *thrus); 1149 void deleteLoopExceptions(); 1150 void deleteConstraints(); 1151 InputDelay *findInputDelay(const Pin *pin, 1152 ClockEdge *clk_edge, 1153 Pin *ref_pin); 1154 InputDelay *makeInputDelay(Pin *pin, 1155 ClockEdge *clk_edge, 1156 Pin *ref_pin); 1157 void deleteInputDelays(Pin *pin, 1158 InputDelay *except); 1159 void deleteInputDelaysReferencing(Clock *clk); 1160 void deleteInputDelay(InputDelay *input_delay); 1161 OutputDelay *findOutputDelay(const Pin *pin, 1162 ClockEdge *clk_edge, 1163 Pin *ref_pin); 1164 OutputDelay *makeOutputDelay(Pin *pin, 1165 ClockEdge *clk_edge, 1166 Pin *ref_pin); 1167 void deleteOutputDelays(Pin *pin, OutputDelay *except); 1168 void deleteOutputDelaysReferencing(Clock *clk); 1169 void deleteOutputDelay(OutputDelay *output_delay); 1170 void deleteInstancePvts(); 1171 void deleteClockInsertion(ClockInsertion *insertion); 1172 void deleteClockInsertionsReferencing(Clock *clk); 1173 void deleteInterClockUncertainty(InterClockUncertainty *uncertainties); 1174 void deleteInterClockUncertaintiesReferencing(Clock *clk); 1175 void deleteLatchBorrowLimitsReferencing(Clock *clk); 1176 void deleteMinPulseWidthReferencing(Clock *clk); 1177 void deleteMasterClkRefs(Clock *clk); 1178 // Liberty library to look for defaults. 1179 LibertyLibrary *defaultLibertyLibrary(); 1180 void annotateGraphConstrainOutputs(); 1181 void annotateDisables(); 1182 void annotateGraphDisabled(const Pin *pin); 1183 void setEdgeDisabledInstPorts(DisabledInstancePorts *disabled_inst); 1184 void setEdgeDisabledInstFrom(Pin *from_pin, 1185 bool disable_checks); 1186 void setEdgeDisabledInstPorts(DisabledPorts *disabled_port, 1187 Instance *inst); 1188 void deleteClockLatenciesReferencing(Clock *clk); 1189 void deleteClockLatency(ClockLatency *latency); 1190 void deleteDeratingFactors(); 1191 void annotateGraphOutputDelays(); 1192 void annotateGraphDataChecks(); 1193 void annotateGraphConstrained(const PinSet *pins); 1194 void annotateGraphConstrained(const InstanceSet *insts); 1195 void annotateGraphConstrained(const Instance *inst); 1196 void annotateGraphConstrained(const Pin *pin); 1197 void annotateHierClkLatency(); 1198 void annotateHierClkLatency(const Pin *hpin, 1199 ClockLatency *latency); 1200 void initInstancePvtMaps(); 1201 void pinCaps(const Pin *pin, 1202 const RiseFall *rf, 1203 const OperatingConditions *op_cond, 1204 const Corner *corner, 1205 const MinMax *min_max, 1206 float &pin_cap, 1207 float &wire_cap, 1208 float &fanout, 1209 bool &has_ext_cap) const; 1210 void netCaps(const Pin *drvr_pin, 1211 const RiseFall *rf, 1212 const OperatingConditions *op_cond, 1213 const Corner *corner, 1214 const MinMax *min_max, 1215 // Return values. 1216 float &pin_cap, 1217 float &wire_cap, 1218 float &fanout, 1219 bool &has_set_load) const; 1220 // connectedCap pin_cap. 1221 float connectedPinCap(const Pin *pin, 1222 const RiseFall *rf, 1223 const OperatingConditions *op_cond, 1224 const Corner *corner, 1225 const MinMax *min_max); 1226 float portCapacitance(Instance *inst, LibertyPort *port, 1227 const RiseFall *rf, 1228 const OperatingConditions *op_cond, 1229 const Corner *corner, 1230 const MinMax *min_max) const; 1231 void removeClockGroups(ClockGroups *groups); 1232 void ensureClkGroupExclusions(); 1233 void makeClkGroupExclusions(ClockGroups *clk_groups); 1234 void makeClkGroupExclusions1(ClockGroupSet *groups); 1235 void makeClkGroupExclusions(ClockGroupSet *groups); 1236 void makeClkGroupSame(ClockGroup *group); 1237 void clearClkGroupExclusions(); 1238 char *makeClockGroupsName(); 1239 void setClockSense(const Pin *pin, 1240 const Clock *clk, 1241 ClockSense sense); 1242 bool clkStopSense(const Pin *to_pin, 1243 const Clock *clk, 1244 const RiseFall *from_rf, 1245 const RiseFall *to_rf) const; 1246 void disconnectPinBefore(Pin *pin, 1247 ExceptionPathSet *exceptions); 1248 void clockGroupsDeleteClkRefs(Clock *clk); 1249 void clearGroupPathMap(); 1250 1251 AnalysisType analysis_type_; 1252 OperatingConditions *operating_conditions_[MinMax::index_count]; 1253 InstancePvtMap *instance_pvt_maps_[MinMax::index_count]; 1254 DeratingFactorsGlobal *derating_factors_; 1255 NetDeratingFactorsMap *net_derating_factors_; 1256 InstDeratingFactorsMap *inst_derating_factors_; 1257 CellDeratingFactorsMap *cell_derating_factors_; 1258 // Clock sequence retains clock definition order. 1259 // This is important for getting consistent regression results, 1260 // which iterating over the name map can't provide. 1261 ClockSeq clocks_; 1262 // Clocks are assigned an index. 1263 int clk_index_; 1264 // Default clock used for unclocked input arrivals. 1265 Clock *default_arrival_clk_; 1266 bool use_default_arrival_clock_; 1267 ClockNameMap clock_name_map_; 1268 ClockPinMap clock_pin_map_; 1269 // Clocks on hierarchical pins are indexed by the load pins. 1270 ClockPinMap clock_leaf_pin_map_; 1271 ClkHpinDisables clk_hpin_disables_; 1272 bool clk_hpin_disables_valid_; 1273 PinSet propagated_clk_pins_; 1274 ClockLatencies clk_latencies_; 1275 ClockInsertions *clk_insertions_; 1276 PinClockUncertaintyMap pin_clk_uncertainty_map_; 1277 InterClockUncertaintySet inter_clk_uncertainties_; 1278 // clk_groups name -> clk_groups 1279 ClockGroupsNameMap clk_groups_name_map_; 1280 // clk to clk paths excluded by clock groups. 1281 ClockPairSet *clk_group_exclusions_; 1282 // clks in the same set_clock_group set. 1283 ClockPairSet *clk_group_same_; 1284 ClockSenseMap clk_sense_map_; 1285 ClockGatingCheck *clk_gating_check_; 1286 ClockGatingCheckMap clk_gating_check_map_; 1287 InstanceClockGatingCheckMap inst_clk_gating_check_map_; 1288 PinClockGatingCheckMap pin_clk_gating_check_map_; 1289 CycleAcctingSet cycle_acctings_; 1290 std::mutex cycle_acctings_lock_; 1291 DataChecksMap data_checks_from_map_; 1292 DataChecksMap data_checks_to_map_; 1293 1294 InputDelaySet input_delays_; 1295 InputDelaysPinMap input_delay_pin_map_; 1296 int input_delay_index_; 1297 InputDelaysPinMap input_delay_ref_pin_map_; 1298 // Input delays on hierarchical pins are indexed by the load pins. 1299 InputDelaysPinMap input_delay_leaf_pin_map_; 1300 InputDelaysPinMap input_delay_internal_pin_map_; 1301 1302 OutputDelaySet output_delays_; 1303 OutputDelaysPinMap output_delay_pin_map_; 1304 OutputDelaysPinMap output_delay_ref_pin_map_; 1305 // Output delays on hierarchical pins are indexed by the load pins. 1306 OutputDelaysPinMap output_delay_leaf_pin_map_; 1307 1308 PortSlewLimitMap port_slew_limit_map_; 1309 CellSlewLimitMap cell_slew_limit_map_; 1310 bool have_clk_slew_limits_; 1311 CellCapLimitMap cell_cap_limit_map_; 1312 PortCapLimitMap port_cap_limit_map_; 1313 PinCapLimitMap pin_cap_limit_map_; 1314 PortFanoutLimitMap port_fanout_limit_map_; 1315 CellFanoutLimitMap cell_fanout_limit_map_; 1316 // External parasitics on top level ports. 1317 // set_load port 1318 // set_fanout_load port 1319 // Indexed by corner_index. 1320 PortExtCapMap *port_cap_map_; 1321 // set_load net 1322 // Indexed by corner_index. 1323 NetWireCapMap *net_wire_cap_map_; 1324 // Indexed by corner_index. 1325 PinWireCapMap *drvr_pin_wire_cap_map_; 1326 NetResistanceMap net_res_map_; 1327 PinSet disabled_pins_; 1328 PortSet disabled_ports_; 1329 LibertyPortSet disabled_lib_ports_; 1330 PinPairSet disabled_wire_edges_; 1331 EdgeSet disabled_edges_; 1332 DisabledCellPortsMap disabled_cell_ports_; 1333 DisabledInstancePortsMap disabled_inst_ports_; 1334 InstanceSet disabled_clk_gating_checks_inst_; 1335 PinSet disabled_clk_gating_checks_pin_; 1336 ExceptionPathSet exceptions_; 1337 1338 bool have_thru_hpin_exceptions_; 1339 // First pin/clock/instance/net/edge exception point to exception set map. 1340 PinExceptionsMap *first_from_pin_exceptions_; 1341 ClockExceptionsMap *first_from_clk_exceptions_; 1342 InstanceExceptionsMap *first_from_inst_exceptions_; 1343 PinExceptionsMap *first_thru_pin_exceptions_; 1344 InstanceExceptionsMap *first_thru_inst_exceptions_; 1345 // Nets that have exception -thru nets. 1346 NetExceptionsMap *first_thru_net_exceptions_; 1347 PinExceptionsMap *first_to_pin_exceptions_; 1348 ClockExceptionsMap *first_to_clk_exceptions_; 1349 InstanceExceptionsMap *first_to_inst_exceptions_; 1350 // Edges that traverse hierarchical exception pins. 1351 EdgeExceptionsMap *first_thru_edge_exceptions_; 1352 1353 // Exception hash with one missing from/thru/to point, used for merging. 1354 ExceptionPathPtHash exception_merge_hash_; 1355 // Path delay -from pin internal startpoints. 1356 PinSet *path_delay_internal_startpoints_; 1357 // Path delay -to pin internal endpoints. 1358 PinSet *path_delay_internal_endpoints_; 1359 // There is a path delay exception without a -to. 1360 bool path_delays_without_to_; 1361 // Group path exception names. 1362 GroupPathMap group_path_map_; 1363 InputDriveMap input_drive_map_; 1364 // set_LogicValue::one/zero/dc 1365 LogicValueMap logic_value_map_; 1366 // set_case_analysis 1367 LogicValueMap case_value_map_; 1368 PinLatchBorrowLimitMap pin_latch_borrow_limit_map_; 1369 InstLatchBorrowLimitMap inst_latch_borrow_limit_map_; 1370 ClockLatchBorrowLimitMap clk_latch_borrow_limit_map_; 1371 RiseFallValues min_pulse_width_; 1372 PinMinPulseWidthMap pin_min_pulse_width_map_; 1373 InstMinPulseWidthMap inst_min_pulse_width_map_; 1374 ClockMinPulseWidthMap clk_min_pulse_width_map_; 1375 float max_area_; 1376 Wireload *wireload_[MinMax::index_count]; 1377 WireloadMode wireload_mode_; 1378 WireloadSelection *wireload_selection_[MinMax::index_count]; 1379 bool crpr_enabled_; 1380 CrprMode crpr_mode_; 1381 bool pocv_enabled_; 1382 bool propagate_gated_clock_enable_; 1383 bool preset_clr_arcs_enabled_; 1384 bool cond_default_arcs_enabled_; 1385 bool bidirect_net_paths_enabled_; 1386 bool bidirect_inst_paths_enabled_; 1387 bool recovery_removal_checks_enabled_; 1388 bool gated_clk_checks_enabled_; 1389 bool clk_thru_tristate_enabled_; 1390 bool dynamic_loop_breaking_; 1391 bool propagate_all_clks_; 1392 1393 // Annotations on graph objects that are stored in constraints 1394 // rather on the graph itself. 1395 EdgeClockLatencyMap edge_clk_latency_; 1396 1397 private: 1398 DISALLOW_COPY_AND_ASSIGN(Sdc); 1399 1400 friend class WriteSdc; 1401 friend class FindNetCaps; 1402 friend class ClockGroupIterator; 1403 friend class GroupPathIterator; 1404 }; 1405 1406 class ClockIterator : public ClockSeq::Iterator 1407 { 1408 public: 1409 ClockIterator(Sdc *sdc); 1410 1411 private: 1412 ClockIterator(ClockSeq &clocks); 1413 friend class Sdc; 1414 DISALLOW_COPY_AND_ASSIGN(ClockIterator); 1415 }; 1416 1417 class ClockGroupIterator : public ClockGroupsNameMap::Iterator 1418 { 1419 public: 1420 ClockGroupIterator(Sdc *sdc); 1421 1422 private: 1423 ClockGroupIterator(ClockGroupsNameMap &clk_groups_name_map); 1424 1425 friend class Sdc; 1426 DISALLOW_COPY_AND_ASSIGN(ClockGroupIterator); 1427 }; 1428 1429 class GroupPathIterator : public GroupPathMap::Iterator 1430 { 1431 public: 1432 GroupPathIterator(Sdc *sdc); 1433 1434 private: 1435 GroupPathIterator(GroupPathMap &group_path_map); 1436 1437 friend class Sdc; 1438 DISALLOW_COPY_AND_ASSIGN(GroupPathIterator); 1439 }; 1440 1441 } // namespace 1442