1 /* $NetBSD: zs.c,v 1.48 2022/05/26 14:30:11 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 1998 Minoura Makoto
5 * Copyright (c) 1996 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Gordon W. Ross.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Zilog Z8530 Dual UART driver (machine-dependent part)
35 *
36 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port;
37 * while channel B is dedicated to the mouse.
38 * Extra Z8530's can be installed for serial ports. This driver
39 * supports up to 5 chips including the built-in one.
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.48 2022/05/26 14:30:11 tsutsui Exp $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/conf.h>
48 #include <sys/device.h>
49 #include <sys/file.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/proc.h>
53 #include <sys/tty.h>
54 #include <sys/time.h>
55 #include <sys/syslog.h>
56 #include <sys/cpu.h>
57 #include <sys/bus.h>
58 #include <sys/intr.h>
59
60 #include <arch/x68k/dev/intiovar.h>
61 #include <machine/z8530var.h>
62
63 #include <dev/ic/z8530reg.h>
64
65 #include "ioconf.h"
66 #include "zsc.h" /* NZSC */
67 #include "opt_zsc.h"
68 #ifndef ZSCN_SPEED
69 #define ZSCN_SPEED 9600
70 #endif
71 #include "zstty.h"
72
73
74 extern void Debugger(void);
75
76 /*
77 * Some warts needed by z8530tty.c -
78 * The default parity REALLY needs to be the same as the PROM uses,
79 * or you can not see messages done with printf during boot-up...
80 */
81 int zs_def_cflag = (CREAD | CS8 | HUPCL);
82 int zscn_def_cflag = (CREAD | CS8 | HUPCL);
83
84 /*
85 * X68k provides a 5.0 MHz clock to the ZS chips.
86 */
87 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */
88
89
90 /* Default physical addresses. */
91 #define ZS_MAXDEV 5
92 static const bus_addr_t zs_physaddr[ZS_MAXDEV] = {
93 0x00e98000,
94 0x00eafc00,
95 0x00eafc10,
96 0x00eafc20,
97 0x00eafc30
98 };
99
100 static uint8_t zs_init_reg[16] = {
101 0, /* 0: CMD (reset, etc.) */
102 0, /* 1: No interrupts yet. */
103 0x70, /* 2: XXX: IVECT */
104 ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
105 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
106 ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
107 0, /* 6: TXSYNC/SYNCLO */
108 0, /* 7: RXSYNC/SYNCHI */
109 0, /* 8: alias for data port */
110 ZSWR9_MASTER_IE,
111 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */
112 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
113 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
114 0, /*13: BAUDHI (default=9600) */
115 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
116 ZSWR15_BREAK_IE,
117 };
118
119 static volatile struct zschan *conschan = 0;
120
121
122 /****************************************************************
123 * Autoconfig
124 ****************************************************************/
125
126 /* Definition of the driver for autoconfig. */
127 static int zs_match(device_t, cfdata_t, void *);
128 static void zs_attach(device_t, device_t, void *);
129 static int zs_print(void *, const char *name);
130
131 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
132 zs_match, zs_attach, NULL, NULL);
133
134 static int zshard(void *);
135 static int zs_get_speed(struct zs_chanstate *);
136
137
138 /*
139 * Is the zs chip present?
140 */
141 static int
zs_match(device_t parent,cfdata_t cf,void * aux)142 zs_match(device_t parent, cfdata_t cf, void *aux)
143 {
144 struct intio_attach_args *ia = aux;
145 struct zsdevice *zsaddr = (void *)ia->ia_addr;
146 int i;
147
148 if (strcmp(ia->ia_name, "zsc") != 0)
149 return 0;
150
151 for (i = 0; i < ZS_MAXDEV; i++)
152 if (zsaddr == (void *)zs_physaddr[i]) /* XXX */
153 break;
154 if (i == ZS_MAXDEV) {
155 /* not a recognized address */
156 return 0;
157 }
158
159 ia->ia_size = 8;
160 if (intio_map_allocate_region(parent, ia, INTIO_MAP_TESTONLY))
161 return 0;
162
163 if (badaddr((void *)IIOV(zsaddr)))
164 return 0;
165
166 return (1);
167 }
168
169 /*
170 * Attach a found zs.
171 */
172 static void
zs_attach(device_t parent,device_t self,void * aux)173 zs_attach(device_t parent, device_t self, void *aux)
174 {
175 struct zsc_softc *zsc = device_private(self);
176 struct intio_attach_args *ia = aux;
177 struct zsc_attach_args zsc_args;
178 volatile struct zschan *zc;
179 struct zs_chanstate *cs;
180 int r __diagused;
181 int s, channel;
182
183 zsc->zsc_dev = self;
184 aprint_normal("\n");
185
186 zsc->zsc_addr = (void *)ia->ia_addr;
187
188 ia->ia_size = 8;
189 r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
190 #ifdef DIAGNOSTIC
191 if (r)
192 panic("zs: intio IO map corruption");
193 #endif
194
195 /*
196 * Initialize software state for each channel.
197 */
198 for (channel = 0; channel < 2; channel++) {
199 device_t child;
200
201 zsc_args.channel = channel;
202 zsc_args.hwflags = 0;
203 cs = &zsc->zsc_cs_store[channel];
204 zsc->zsc_cs[channel] = cs;
205
206 zs_lock_init(cs);
207 cs->cs_channel = channel;
208 cs->cs_private = NULL;
209 cs->cs_ops = &zsops_null;
210 cs->cs_brg_clk = PCLK / 16;
211
212 if (channel == 0)
213 zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_a);
214 else
215 zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_b);
216 cs->cs_reg_csr = &zc->zc_csr;
217 cs->cs_reg_data = &zc->zc_data;
218
219 zs_init_reg[2] = ia->ia_intr;
220 memcpy(cs->cs_creg, zs_init_reg, 16);
221 memcpy(cs->cs_preg, zs_init_reg, 16);
222
223 if (zc == conschan) {
224 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE;
225 cs->cs_defspeed = zs_get_speed(cs);
226 cs->cs_defcflag = zscn_def_cflag;
227 } else {
228 cs->cs_defspeed = 9600;
229 cs->cs_defcflag = zs_def_cflag;
230 }
231
232 /* Make these correspond to cs_defcflag (-crtscts) */
233 cs->cs_rr0_dcd = ZSRR0_DCD;
234 cs->cs_rr0_cts = 0;
235 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
236 cs->cs_wr5_rts = 0;
237
238 /*
239 * Clear the master interrupt enable.
240 * The INTENA is common to both channels,
241 * so just do it on the A channel.
242 */
243 if (channel == 0) {
244 s = splzs();
245 zs_write_reg(cs, 9, 0);
246 splx(s);
247 }
248
249 /*
250 * Look for a child driver for this channel.
251 * The child attach will setup the hardware.
252 */
253 child = config_found(self, (void *)&zsc_args, zs_print,
254 CFARGS_NONE);
255 #if ZSTTY > 0
256 if (zc == conschan &&
257 ((child && strcmp(device_xname(child), "zstty0")) ||
258 child == NULL)) /* XXX */
259 panic("%s: console device mismatch", __func__);
260 #endif
261 if (child == NULL) {
262 /* No sub-driver. Just reset it. */
263 uint8_t reset = (channel == 0) ?
264 ZSWR9_A_RESET : ZSWR9_B_RESET;
265 s = splzs();
266 zs_write_reg(cs, 9, reset);
267 splx(s);
268 }
269 }
270
271 /*
272 * Now safe to install interrupt handlers.
273 */
274 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc))
275 panic("%s: interrupt vector busy", __func__);
276 zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
277 (void (*)(void *))zsc_intr_soft, zsc);
278 /* XXX; evcnt_attach() ? */
279
280 /*
281 * Set the master interrupt enable and interrupt vector.
282 * (common to both channels, do it on A)
283 */
284 cs = zsc->zsc_cs[0];
285 s = splzs();
286 /* interrupt vector */
287 zs_write_reg(cs, 2, ia->ia_intr);
288 /* master interrupt control (enable) */
289 zs_write_reg(cs, 9, zs_init_reg[9]);
290 splx(s);
291 }
292
293 static int
zs_print(void * aux,const char * name)294 zs_print(void *aux, const char *name)
295 {
296 struct zsc_attach_args *args = aux;
297
298 if (name != NULL)
299 aprint_normal("%s: ", name);
300
301 if (args->channel != -1)
302 aprint_normal(" channel %d", args->channel);
303
304 return UNCONF;
305 }
306
307
308 /*
309 * For x68k-port, we don't use autovectored interrupt.
310 * We do not need to look at all of the zs chips.
311 */
312 static int
zshard(void * arg)313 zshard(void *arg)
314 {
315 struct zsc_softc *zsc = arg;
316 int rval;
317 int s;
318
319 /*
320 * Actually, zs hardware ipl is 5.
321 * Here we disable all interrupts to shorten the zshard
322 * handling time. Otherwise, too many characters are
323 * dropped.
324 */
325 s = splhigh();
326 rval = zsc_intr_hard(zsc);
327
328 /* We are at splzs here, so no need to lock. */
329 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
330 softint_schedule(zsc->zsc_softintr_cookie);
331 splx(s);
332
333 return (rval);
334 }
335
336 /*
337 * Compute the current baud rate given a ZS channel.
338 */
339 static int
zs_get_speed(struct zs_chanstate * cs)340 zs_get_speed(struct zs_chanstate *cs)
341 {
342 int tconst;
343
344 tconst = zs_read_reg(cs, 12);
345 tconst |= zs_read_reg(cs, 13) << 8;
346 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
347 }
348
349 /*
350 * MD functions for setting the baud rate and control modes.
351 */
352 int
zs_set_speed(struct zs_chanstate * cs,int bps)353 zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */)
354 {
355 int tconst, real_bps;
356
357 if (bps == 0)
358 return (0);
359
360 #ifdef DIAGNOSTIC
361 if (cs->cs_brg_clk == 0)
362 panic("zs_set_speed");
363 #endif
364
365 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
366 if (tconst < 0)
367 return (EINVAL);
368
369 /* Convert back to make sure we can do it. */
370 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
371
372 #if 0 /* XXX */
373 /* XXX - Allow some tolerance here? */
374 if (real_bps != bps)
375 return (EINVAL);
376 #else
377 /*
378 * Since our PCLK has somewhat strange value,
379 * we have to allow tolerance here.
380 */
381 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst)
382 return (EINVAL);
383 #endif
384
385 cs->cs_preg[12] = tconst;
386 cs->cs_preg[13] = tconst >> 8;
387
388 /* Caller will stuff the pending registers. */
389 return (0);
390 }
391
392 int
zs_set_modes(struct zs_chanstate * cs,int cflag)393 zs_set_modes(struct zs_chanstate *cs, int cflag /* bits per second */)
394 {
395 int s;
396
397 /*
398 * Output hardware flow control on the chip is horrendous:
399 * if carrier detect drops, the receiver is disabled, and if
400 * CTS drops, the transmitter is stopped IN MID CHARACTER!
401 * Therefore, NEVER set the HFC bit, and instead use the
402 * status interrupt to detect CTS changes.
403 */
404 s = splzs();
405 cs->cs_rr0_pps = 0;
406 if ((cflag & (CLOCAL | MDMBUF)) != 0) {
407 cs->cs_rr0_dcd = 0;
408 if ((cflag & MDMBUF) == 0)
409 cs->cs_rr0_pps = ZSRR0_DCD;
410 } else
411 cs->cs_rr0_dcd = ZSRR0_DCD;
412 if ((cflag & CRTSCTS) != 0) {
413 cs->cs_wr5_dtr = ZSWR5_DTR;
414 cs->cs_wr5_rts = ZSWR5_RTS;
415 cs->cs_rr0_cts = ZSRR0_CTS;
416 } else if ((cflag & MDMBUF) != 0) {
417 cs->cs_wr5_dtr = 0;
418 cs->cs_wr5_rts = ZSWR5_DTR;
419 cs->cs_rr0_cts = ZSRR0_DCD;
420 } else {
421 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
422 cs->cs_wr5_rts = 0;
423 cs->cs_rr0_cts = 0;
424 }
425 splx(s);
426
427 /* Caller will stuff the pending registers. */
428 return (0);
429 }
430
431
432 /*
433 * Read or write the chip with suitable delays.
434 */
435
436 uint8_t
zs_read_reg(struct zs_chanstate * cs,uint8_t reg)437 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
438 {
439 uint8_t val;
440
441 *cs->cs_reg_csr = reg;
442 ZS_DELAY();
443 val = *cs->cs_reg_csr;
444 ZS_DELAY();
445 return val;
446 }
447
448 void
zs_write_reg(struct zs_chanstate * cs,uint8_t reg,uint8_t val)449 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
450 {
451 *cs->cs_reg_csr = reg;
452 ZS_DELAY();
453 *cs->cs_reg_csr = val;
454 ZS_DELAY();
455 }
456
457 uint8_t
zs_read_csr(struct zs_chanstate * cs)458 zs_read_csr(struct zs_chanstate *cs)
459 {
460 uint8_t val;
461
462 val = *cs->cs_reg_csr;
463 ZS_DELAY();
464 return val;
465 }
466
467 void
zs_write_csr(struct zs_chanstate * cs,uint8_t val)468 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
469 {
470 *cs->cs_reg_csr = val;
471 ZS_DELAY();
472 }
473
474 uint8_t
zs_read_data(struct zs_chanstate * cs)475 zs_read_data(struct zs_chanstate *cs)
476 {
477 uint8_t val;
478
479 val = *cs->cs_reg_data;
480 ZS_DELAY();
481 return val;
482 }
483
484 void
zs_write_data(struct zs_chanstate * cs,uint8_t val)485 zs_write_data(struct zs_chanstate *cs, uint8_t val)
486 {
487 *cs->cs_reg_data = val;
488 ZS_DELAY();
489 }
490
491
492 /****************************************************************
493 * Console support functions (x68k specific!)
494 * Note: this code is allowed to know about the layout of
495 * the chip registers, and uses that to keep things simple.
496 * XXX - I think I like the mvme167 code better. -gwr
497 ****************************************************************/
498
499 /*
500 * Handle user request to enter kernel debugger.
501 */
502 void
zs_abort(struct zs_chanstate * cs)503 zs_abort(struct zs_chanstate *cs)
504 {
505 int rr0;
506
507 /* Wait for end of break to avoid PROM abort. */
508 /* XXX - Limit the wait? */
509 do {
510 rr0 = *cs->cs_reg_csr;
511 ZS_DELAY();
512 } while (rr0 & ZSRR0_BREAK);
513
514 #ifdef DDB
515 Debugger();
516 #else
517 printf("BREAK!!\n");
518 #endif
519 }
520
521
522 #if NZSTTY > 0
523
524 #include <dev/cons.h>
525 cons_decl(zs);
526
527 static int zs_getc(void);
528 static void zs_putc(int);
529
530 static struct zs_chanstate zscn_cs;
531
532 /*
533 * Polled input char.
534 */
535 static int
zs_getc(void)536 zs_getc(void)
537 {
538 int s, c, rr0;
539
540 s = splzs();
541 /* Wait for a character to arrive. */
542 do {
543 rr0 = zs_read_csr(&zscn_cs);
544 } while ((rr0 & ZSRR0_RX_READY) == 0);
545
546 c = zs_read_data(&zscn_cs);
547 splx(s);
548
549 /*
550 * This is used by the kd driver to read scan codes,
551 * so don't translate '\r' ==> '\n' here...
552 */
553 return (c);
554 }
555
556 /*
557 * Polled output char.
558 */
559 static void
zs_putc(int c)560 zs_putc(int c)
561 {
562 int s, rr0;
563
564 s = splzs();
565 /* Wait for transmitter to become ready. */
566 do {
567 rr0 = zs_read_csr(&zscn_cs);
568 } while ((rr0 & ZSRR0_TX_READY) == 0);
569
570 zs_write_data(&zscn_cs, c);
571 splx(s);
572 }
573
574 void
zscninit(struct consdev * cn)575 zscninit(struct consdev *cn)
576 {
577 volatile struct zschan *cnchan = (volatile void *)IIOV(ZSCN_PHYSADDR);
578 int s;
579
580 memset(&zscn_cs, 0, sizeof(struct zs_chanstate));
581 zscn_cs.cs_reg_csr = &cnchan->zc_csr;
582 zscn_cs.cs_reg_data = &cnchan->zc_data;
583 zscn_cs.cs_channel = 0;
584 zscn_cs.cs_brg_clk = PCLK / 16;
585 memcpy(zscn_cs.cs_preg, zs_init_reg, 16);
586 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */
587 zscn_cs.cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
588 zs_set_speed(&zscn_cs, ZSCN_SPEED);
589 s = splzs();
590 zs_write_reg(&zscn_cs, 9, 0);
591 zs_write_reg(&zscn_cs, 9, ZSWR9_HARD_RESET);
592 zs_loadchannelregs(&zscn_cs);
593 splx(s);
594 conschan = cnchan;
595 }
596
597 /*
598 * Polled console input putchar.
599 */
600 int
zscngetc(dev_t dev)601 zscngetc(dev_t dev)
602 {
603 return (zs_getc());
604 }
605
606 /*
607 * Polled console output putchar.
608 */
609 void
zscnputc(dev_t dev,int c)610 zscnputc(dev_t dev, int c)
611 {
612 zs_putc(c);
613 }
614
615 void
zscnprobe(struct consdev * cd)616 zscnprobe(struct consdev *cd)
617 {
618 int maj;
619 extern const struct cdevsw zstty_cdevsw;
620
621 /* locate the major number */
622 maj = cdevsw_lookup_major(&zstty_cdevsw);
623 /* XXX: minor number is 0 */
624
625 if (maj == -1)
626 cd->cn_pri = CN_DEAD;
627 else {
628 #ifdef ZSCONSOLE
629 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */
630 #else
631 cd->cn_pri = CN_NORMAL;
632 #endif
633 cd->cn_dev = makedev(maj, 0);
634 }
635 }
636
637 void
zscnpollc(dev_t dev,int on)638 zscnpollc(dev_t dev, int on)
639 {
640 }
641
642 #endif
643