1 /* GENERAL3.C (c) Copyright Roger Bowler, 2009 */
2 /* Additional General Instructions */
3
4 /*-------------------------------------------------------------------*/
5 /* This module implements additional general instructions introduced */
6 /* as later extensions to z/Architecture and described in the manual */
7 /* SA22-7832-06 z/Architecture Principles of Operation */
8 /*-------------------------------------------------------------------*/
9
10 #include "hstdinc.h"
11
12 #if !defined(_HENGINE_DLL_)
13 #define _HENGINE_DLL_
14 #endif
15
16 #if !defined(_GENERAL3_C_)
17 #define _GENERAL3_C_
18 #endif
19
20 #include "hercules.h"
21 #include "opcode.h"
22 #include "inline.h"
23
24
25 #if defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY)
26
27 #if defined(FEATURE_INTERLOCKED_ACCESS_FACILITY) /*810*/
28 /*-------------------------------------------------------------------*/
29 /* Perform Interlocked Storage Immediate Operation */
30 /* Subroutine called by ASI and ALSI instructions */
31 /*-------------------------------------------------------------------*/
DEF_INST(perform_interlocked_storage_immediate)32 DEF_INST(perform_interlocked_storage_immediate) /*810*/
33 {
34 BYTE opcode; /* 2nd byte of opcode */
35 BYTE i2; /* Immediate byte */
36 int b1; /* Base of effective addr */
37 VADR addr1; /* Effective address */
38 BYTE *m1; /* Mainstor address */
39 U32 n; /* 32-bit operand value */
40 U32 result; /* Result value */
41 U32 old, new; /* Values for cmpxchg4 */
42 int cc; /* Condition code */
43 int rc; /* Return code */
44
45 SIY(inst, regs, i2, b1, addr1);
46
47 /* Extract second byte of instruction opcode */
48 opcode = inst[5];
49
50 /* Get mainstor address of storage operand */
51 m1 = MADDRL (addr1, 4, b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
52
53 do {
54 /* Load 32-bit operand from operand address */
55 n = ARCH_DEP(vfetch4) (addr1, b1, regs);
56
57 switch (opcode) {
58 case 0x6A: /* Add Storage Immediate */
59 /* Add signed operands and set condition code */
60 cc = add_signed (&result, n, (S32)(S8)i2);
61 break;
62 case 0x6E: /* Add Logical Storage with Signed Immediate */
63 /* Add operands and set condition code */
64 cc = (S8)i2 < 0 ?
65 sub_logical (&result, n, (S32)(-(S8)i2)) :
66 add_logical (&result, n, (S32)(S8)i2);
67 break;
68 default: /* To prevent compiler warnings */
69 result = 0;
70 cc = 0;
71 } /* end switch(opcode) */
72
73 /* Regular store if operand is not on a fullword boundary */
74 if ((addr1 & 0x03) != 0) {
75 ARCH_DEP(vstore4) (result, addr1, b1, regs);
76 break;
77 }
78
79 /* Interlocked exchange if operand is on a fullword boundary */
80 old = CSWAP32(n);
81 new = CSWAP32(result);
82 rc = cmpxchg4(&old, new, m1);
83
84 } while (rc != 0);
85
86 /* Set condition code in PSW */
87 regs->psw.cc = cc;
88
89 } /* end DEF_INST(perform_interlocked_storage_immediate) */
90
91 /*-------------------------------------------------------------------*/
92 /* Perform Interlocked Long Storage Immediate Operation */
93 /* Subroutine called by AGSI and ALGSI instructions */
94 /*-------------------------------------------------------------------*/
DEF_INST(perform_interlocked_long_storage_immediate)95 DEF_INST(perform_interlocked_long_storage_immediate) /*810*/
96 {
97 BYTE opcode; /* 2nd byte of opcode */
98 BYTE i2; /* Immediate byte */
99 int b1; /* Base of effective addr */
100 VADR addr1; /* Effective address */
101 BYTE *m1; /* Mainstor address */
102 U64 n; /* 64-bit operand value */
103 U64 result; /* Result value */
104 U64 old, new; /* Values for cmpxchg4 */
105 int cc; /* Condition code */
106 int rc; /* Return code */
107
108 SIY(inst, regs, i2, b1, addr1);
109
110 /* Extract second byte of instruction opcode */
111 opcode = inst[5];
112
113 /* Get mainstor address of storage operand */
114 m1 = MADDRL (addr1, 8, b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
115
116 do {
117 /* Load 64-bit operand from operand address */
118 n = ARCH_DEP(vfetch8) (addr1, b1, regs);
119
120 switch (opcode) {
121 case 0x7A: /* Add Long Storage Immediate */
122 /* Add signed operands and set condition code */
123 cc = add_signed_long (&result, n, (S64)(S8)i2);
124 break;
125 case 0x7E: /* Add Logical Long Storage with Signed Immediate */
126 /* Add operands and set condition code */
127 cc = (S8)i2 < 0 ?
128 sub_logical_long (&result, n, (S64)(-(S8)i2)) :
129 add_logical_long (&result, n, (S64)(S8)i2);
130 break;
131 default: /* To prevent compiler warnings */
132 result = 0;
133 cc = 0;
134 } /* end switch(opcode) */
135
136 /* Regular store if operand is not on a doubleword boundary */
137 if ((addr1 & 0x07) != 0) {
138 ARCH_DEP(vstore8) (result, addr1, b1, regs);
139 break;
140 }
141
142 /* Interlocked exchange if operand is on doubleword boundary */
143 old = CSWAP64(n);
144 new = CSWAP64(result);
145 rc = cmpxchg8(&old, new, m1);
146
147 } while (rc != 0);
148
149 /* Set condition code in PSW */
150 regs->psw.cc = cc;
151
152 } /* end DEF_INST(perform_interlocked_long_storage_immediate) */
153 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
154
155 /*-------------------------------------------------------------------*/
156 /* EB6A ASI - Add Immediate Storage [SIY] */
157 /*-------------------------------------------------------------------*/
DEF_INST(add_immediate_storage)158 DEF_INST(add_immediate_storage)
159 {
160 #if !defined(FEATURE_INTERLOCKED_ACCESS_FACILITY) /*810*/
161 BYTE i2; /* Immediate byte */
162 int b1; /* Base of effective addr */
163 VADR effective_addr1; /* Effective address */
164 U32 n; /* 32-bit operand value */
165 int cc; /* Condition Code */
166
167 SIY(inst, regs, i2, b1, effective_addr1);
168
169 /* Load 32-bit operand from operand address */
170 n = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
171
172 /* Add signed operands and set condition code */
173 cc = add_signed (&n, n, (S32)(S8)i2);
174
175 /* Store 32-bit operand at operand address */
176 ARCH_DEP(vstore4) ( n, effective_addr1, b1, regs );
177
178 /* Update Condition Code */
179 regs->psw.cc = cc;
180
181 #else /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
182 ARCH_DEP(perform_interlocked_storage_immediate) (inst, regs);
183 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
184
185 /* Program check if fixed-point overflow */
186 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
187 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
188
189 } /* end DEF_INST(add_immediate_storage) */
190
191
192 /*-------------------------------------------------------------------*/
193 /* EB7A AGSI - Add Immediate Long Storage [SIY] */
194 /*-------------------------------------------------------------------*/
DEF_INST(add_immediate_long_storage)195 DEF_INST(add_immediate_long_storage)
196 {
197 #if !defined(FEATURE_INTERLOCKED_ACCESS_FACILITY) /*810*/
198 BYTE i2; /* Immediate byte */
199 int b1; /* Base of effective addr */
200 VADR effective_addr1; /* Effective address */
201 U64 n; /* 64-bit operand value */
202 int cc; /* Condition Code */
203
204 SIY(inst, regs, i2, b1, effective_addr1);
205
206 /* Load 64-bit operand from operand address */
207 n = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
208
209 /* Add signed operands and set condition code */
210 cc = add_signed_long (&n, n, (S64)(S8)i2);
211
212 /* Store 64-bit value at operand address */
213 ARCH_DEP(vstore8) ( n, effective_addr1, b1, regs );
214
215 /* Update Condition Code */
216 regs->psw.cc = cc;
217
218 #else /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
219 ARCH_DEP(perform_interlocked_long_storage_immediate) (inst, regs);
220 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
221
222 /* Program check if fixed-point overflow */
223 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
224 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
225
226 } /* end DEF_INST(add_immediate_long_storage) */
227
228
229 /*-------------------------------------------------------------------*/
230 /* EB6E ALSI - Add Logical with Signed Immediate [SIY] */
231 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_with_signed_immediate)232 DEF_INST(add_logical_with_signed_immediate)
233 {
234 #if !defined(FEATURE_INTERLOCKED_ACCESS_FACILITY) /*810*/
235 BYTE i2; /* Immediate byte */
236 int b1; /* Base of effective addr */
237 VADR effective_addr1; /* Effective address */
238 U32 n; /* 32-bit operand value */
239 int cc; /* Condition Code */
240
241 SIY(inst, regs, i2, b1, effective_addr1);
242
243 /* Load 32-bit operand from operand address */
244 n = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
245
246 /* Add operands and set condition code */
247 cc = (S8)i2 < 0 ?
248 sub_logical (&n, n, (S32)(-(S8)i2)) :
249 add_logical (&n, n, (S32)(S8)i2);
250
251 /* Store 32-bit operand at operand address */
252 ARCH_DEP(vstore4) ( n, effective_addr1, b1, regs );
253
254 /* Update Condition Code */
255 regs->psw.cc = cc;
256
257 #else /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
258 ARCH_DEP(perform_interlocked_storage_immediate) (inst, regs);
259 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
260
261 } /* end DEF_INST(add_logical_with_signed_immediate) */
262
263
264 /*-------------------------------------------------------------------*/
265 /* EB7E ALGSI - Add Logical with Signed Immediate Long [SIY] */
266 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_with_signed_immediate_long)267 DEF_INST(add_logical_with_signed_immediate_long)
268 {
269 #if !defined(FEATURE_INTERLOCKED_ACCESS_FACILITY) /*810*/
270 BYTE i2; /* Immediate byte */
271 int b1; /* Base of effective addr */
272 VADR effective_addr1; /* Effective address */
273 U64 n; /* 64-bit operand value */
274 int cc; /* Condition Code */
275
276 SIY(inst, regs, i2, b1, effective_addr1);
277
278 /* Load 64-bit operand from operand address */
279 n = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
280
281 /* Add operands and set condition code */
282 cc = (S8)i2 < 0 ?
283 sub_logical_long (&n, n, (S64)(-(S8)i2)) :
284 add_logical_long (&n, n, (S64)(S8)i2);
285
286 /* Store 64-bit value at operand address */
287 ARCH_DEP(vstore8) ( n, effective_addr1, b1, regs );
288
289 /* Update Condition Code */
290 regs->psw.cc = cc;
291
292 #else /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
293 ARCH_DEP(perform_interlocked_long_storage_immediate) (inst, regs);
294 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
295
296 } /* end DEF_INST(add_logical_with_signed_immediate_long) */
297
298
299 /*-------------------------------------------------------------------*/
300 /* ECF6 CRB - Compare and Branch Register [RRS] */
301 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_branch_register)302 DEF_INST(compare_and_branch_register)
303 {
304 int r1, r2; /* Register numbers */
305 int m3; /* Mask bits */
306 int b4; /* Base of effective addr */
307 VADR effective_addr4; /* Effective address */
308 int cc; /* Comparison result */
309
310 RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
311
312 /* Compare signed operands and set comparison result */
313 cc = (S32)regs->GR_L(r1) < (S32)regs->GR_L(r2) ? 1 :
314 (S32)regs->GR_L(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
315
316 /* Branch to operand address if m3 mask bit is set */
317 if ((0x8 >> cc) & m3)
318 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
319 else
320 INST_UPDATE_PSW(regs, 6, 0);
321
322 } /* end DEF_INST(compare_and_branch_register) */
323
324
325 #if defined(FEATURE_ESAME)
326 /*-------------------------------------------------------------------*/
327 /* ECE4 CGRB - Compare and Branch Long Register [RRS] */
328 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_branch_long_register)329 DEF_INST(compare_and_branch_long_register)
330 {
331 int r1, r2; /* Register numbers */
332 int m3; /* Mask bits */
333 int b4; /* Base of effective addr */
334 VADR effective_addr4; /* Effective address */
335 int cc; /* Comparison result */
336
337 RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
338
339 /* Compare signed operands and set comparison result */
340 cc = (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
341 (S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
342
343 /* Branch to operand address if m3 mask bit is set */
344 if ((0x8 >> cc) & m3)
345 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
346 else
347 INST_UPDATE_PSW(regs, 6, 0);
348
349 } /* end DEF_INST(compare_and_branch_long_register) */
350 #endif /*defined(FEATURE_ESAME)*/
351
352
353 /*-------------------------------------------------------------------*/
354 /* EC76 CRJ - Compare and Branch Relative Register [RIE] */
355 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_branch_relative_register)356 DEF_INST(compare_and_branch_relative_register)
357 {
358 int r1, r2; /* Register numbers */
359 int m3; /* Mask bits */
360 S16 i4; /* 16-bit immediate offset */
361 int cc; /* Comparison result */
362
363 RIE_RRIM_B(inst, regs, r1, r2, i4, m3);
364
365 /* Compare signed operands and set comparison result */
366 cc = (S32)regs->GR_L(r1) < (S32)regs->GR_L(r2) ? 1 :
367 (S32)regs->GR_L(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
368
369 /* Branch to immediate offset if m3 mask bit is set */
370 if ((0x8 >> cc) & m3)
371 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
372 else
373 INST_UPDATE_PSW(regs, 6, 0);
374
375 } /* end DEF_INST(compare_and_branch_relative_register) */
376
377
378 #if defined(FEATURE_ESAME)
379 /*-------------------------------------------------------------------*/
380 /* EC64 CGRJ - Compare and Branch Relative Long Register [RIE] */
381 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_branch_relative_long_register)382 DEF_INST(compare_and_branch_relative_long_register)
383 {
384 int r1, r2; /* Register numbers */
385 int m3; /* Mask bits */
386 S16 i4; /* 16-bit immediate offset */
387 int cc; /* Comparison result */
388
389 RIE_RRIM_B(inst, regs, r1, r2, i4, m3);
390
391 /* Compare signed operands and set comparison result */
392 cc = (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
393 (S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
394
395 /* Branch to immediate offset if m3 mask bit is set */
396 if ((0x8 >> cc) & m3)
397 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
398 else
399 INST_UPDATE_PSW(regs, 6, 0);
400
401 } /* end DEF_INST(compare_and_branch_relative_long_register) */
402 #endif /*defined(FEATURE_ESAME)*/
403
404
405 /*-------------------------------------------------------------------*/
406 /* B972 CRT - Compare and Trap Register [RRF] */
407 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_trap_register)408 DEF_INST(compare_and_trap_register)
409 {
410 int r1, r2; /* Register numbers */
411 int m3; /* Mask bits */
412 int cc; /* Comparison result */
413
414 RRF_M(inst, regs, r1, r2, m3);
415
416 /* Compare signed operands and set comparison result */
417 cc = (S32)regs->GR_L(r1) < (S32)regs->GR_L(r2) ? 1 :
418 (S32)regs->GR_L(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
419
420 /* Raise data exception if m3 mask bit is set */
421 if ((0x8 >> cc) & m3)
422 {
423 regs->dxc = DXC_COMPARE_AND_TRAP;
424 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
425 }
426
427 } /* end DEF_INST(compare_and_trap_register) */
428
429
430 #if defined(FEATURE_ESAME)
431 /*-------------------------------------------------------------------*/
432 /* B960 CGRT - Compare and Trap Long Register [RRF] */
433 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_trap_long_register)434 DEF_INST(compare_and_trap_long_register)
435 {
436 int r1, r2; /* Register numbers */
437 int m3; /* Mask bits */
438 int cc; /* Comparison result */
439
440 RRF_M(inst, regs, r1, r2, m3);
441
442 /* Compare signed operands and set comparison result */
443 cc = (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
444 (S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
445
446 /* Raise data exception if m3 mask bit is set */
447 if ((0x8 >> cc) & m3)
448 {
449 regs->dxc = DXC_COMPARE_AND_TRAP;
450 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
451 }
452
453 } /* end DEF_INST(compare_and_trap_long_register) */
454 #endif /*defined(FEATURE_ESAME)*/
455
456
457 /*-------------------------------------------------------------------*/
458 /* E554 CHHSI - Compare Halfword Immediate Halfword Storage [SIL] */
459 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_immediate_halfword_storage)460 DEF_INST(compare_halfword_immediate_halfword_storage)
461 {
462 int b1; /* Base of effective addr */
463 VADR effective_addr1; /* Effective address */
464 S16 i2; /* 16-bit immediate value */
465 S16 n; /* 16-bit storage value */
466
467 SIL(inst, regs, i2, b1, effective_addr1);
468
469 /* Load 16-bit value from first operand address */
470 n = (S16)ARCH_DEP(vfetch2) ( effective_addr1, b1, regs );
471
472 /* Compare signed operands and set condition code */
473 regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
474
475 } /* end DEF_INST(compare_halfword_immediate_halfword_storage) */
476
477
478 /*-------------------------------------------------------------------*/
479 /* E558 CGHSI - Compare Halfword Immediate Long Storage [SIL] */
480 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_immediate_long_storage)481 DEF_INST(compare_halfword_immediate_long_storage)
482 {
483 int b1; /* Base of effective addr */
484 VADR effective_addr1; /* Effective address */
485 S16 i2; /* 16-bit immediate value */
486 S64 n; /* 64-bit storage value */
487
488 SIL(inst, regs, i2, b1, effective_addr1);
489
490 /* Load 64-bit value from first operand address */
491 n = (S64)ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
492
493 /* Compare signed operands and set condition code */
494 regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
495
496 } /* end DEF_INST(compare_halfword_immediate_long_storage) */
497
498
499 /*-------------------------------------------------------------------*/
500 /* E55C CHSI - Compare Halfword Immediate Storage [SIL] */
501 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_immediate_storage)502 DEF_INST(compare_halfword_immediate_storage)
503 {
504 int b1; /* Base of effective addr */
505 VADR effective_addr1; /* Effective address */
506 S16 i2; /* 16-bit immediate value */
507 S32 n; /* 32-bit storage value */
508
509 SIL(inst, regs, i2, b1, effective_addr1);
510
511 /* Load 32-bit value from first operand address */
512 n = (S32)ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
513
514 /* Compare signed operands and set condition code */
515 regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
516
517 } /* end DEF_INST(compare_halfword_immediate_storage) */
518
519
520 #if defined(FEATURE_ESAME)
521 /*-------------------------------------------------------------------*/
522 /* E334 CGH - Compare Halfword Long [RXY] */
523 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_long)524 DEF_INST(compare_halfword_long)
525 {
526 int r1; /* Values of R fields */
527 int b2; /* Base of effective addr */
528 VADR effective_addr2; /* Effective address */
529 S64 n; /* 64-bit operand value */
530
531 RXY(inst, regs, r1, b2, effective_addr2);
532
533 /* Load rightmost 2 bytes of comparand from operand address */
534 n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
535
536 /* Compare signed operands and set condition code */
537 regs->psw.cc =
538 (S64)regs->GR_G(r1) < n ? 1 :
539 (S64)regs->GR_G(r1) > n ? 2 : 0;
540
541 } /* end DEF_INST(compare_halfword_long) */
542 #endif /*defined(FEATURE_ESAME)*/
543
544
545 /*-------------------------------------------------------------------*/
546 /* C6x5 CHRL - Compare Halfword Relative Long [RIL] */
547 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_relative_long)548 DEF_INST(compare_halfword_relative_long)
549 {
550 int r1; /* Register number */
551 VADR addr2; /* Relative operand address */
552 U16 n; /* Relative operand value */
553
554 RIL_A(inst, regs, r1, addr2);
555
556 /* Load relative operand from instruction address space */
557 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
558
559 /* Compare signed operands and set condition code */
560 regs->psw.cc =
561 (S32)regs->GR_L(r1) < (S16)n ? 1 :
562 (S32)regs->GR_L(r1) > (S16)n ? 2 : 0;
563
564 } /* end DEF_INST(compare_halfword_relative_long) */
565
566
567 #if defined(FEATURE_ESAME)
568 /*-------------------------------------------------------------------*/
569 /* C6x4 CGHRL - Compare Halfword Relative Long Long [RIL] */
570 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_relative_long_long)571 DEF_INST(compare_halfword_relative_long_long)
572 {
573 int r1; /* Register number */
574 VADR addr2; /* Relative operand address */
575 U16 n; /* Relative operand value */
576
577 RIL_A(inst, regs, r1, addr2);
578
579 /* Load relative operand from instruction address space */
580 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
581
582 /* Compare signed operands and set condition code */
583 regs->psw.cc =
584 (S64)regs->GR_G(r1) < (S16)n ? 1 :
585 (S64)regs->GR_G(r1) > (S16)n ? 2 : 0;
586
587 } /* end DEF_INST(compare_halfword_relative_long_long) */
588 #endif /*defined(FEATURE_ESAME)*/
589
590
591 /*-------------------------------------------------------------------*/
592 /* ECFE CIB - Compare Immediate and Branch [RIS] */
593 /*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_branch)594 DEF_INST(compare_immediate_and_branch)
595 {
596 int r1; /* Register number */
597 int m3; /* Mask bits */
598 int b4; /* Base of effective addr */
599 VADR effective_addr4; /* Effective address */
600 int cc; /* Comparison result */
601 BYTE i2; /* Immediate value */
602
603 RIS_B(inst, regs, r1, i2, m3, b4, effective_addr4);
604
605 /* Compare signed operands and set comparison result */
606 cc = (S32)regs->GR_L(r1) < (S32)(S8)i2 ? 1 :
607 (S32)regs->GR_L(r1) > (S32)(S8)i2 ? 2 : 0;
608
609 /* Branch to operand address if m3 mask bit is set */
610 if ((0x8 >> cc) & m3)
611 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
612 else
613 INST_UPDATE_PSW(regs, 6, 0);
614
615 } /* end DEF_INST(compare_immediate_and_branch) */
616
617
618 #if defined(FEATURE_ESAME)
619 /*-------------------------------------------------------------------*/
620 /* ECFC CGIB - Compare Immediate and Branch Long [RIS] */
621 /*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_branch_long)622 DEF_INST(compare_immediate_and_branch_long)
623 {
624 int r1; /* Register number */
625 int m3; /* Mask bits */
626 int b4; /* Base of effective addr */
627 VADR effective_addr4; /* Effective address */
628 int cc; /* Comparison result */
629 BYTE i2; /* Immediate value */
630
631 RIS_B(inst, regs, r1, i2, m3, b4, effective_addr4);
632
633 /* Compare signed operands and set comparison result */
634 cc = (S64)regs->GR_G(r1) < (S64)(S8)i2 ? 1 :
635 (S64)regs->GR_G(r1) > (S64)(S8)i2 ? 2 : 0;
636
637 /* Branch to operand address if m3 mask bit is set */
638 if ((0x8 >> cc) & m3)
639 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
640 else
641 INST_UPDATE_PSW(regs, 6, 0);
642
643 } /* end DEF_INST(compare_immediate_and_branch_long) */
644 #endif /*defined(FEATURE_ESAME)*/
645
646
647 /*-------------------------------------------------------------------*/
648 /* EC7E CIJ - Compare Immediate and Branch Relative [RIE] */
649 /*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_branch_relative)650 DEF_INST(compare_immediate_and_branch_relative)
651 {
652 int r1; /* Register numbers */
653 int m3; /* Mask bits */
654 BYTE i2; /* Immediate operand value */
655 S16 i4; /* 16-bit immediate offset */
656 int cc; /* Comparison result */
657
658 RIE_RMII_B(inst, regs, r1, i2, m3, i4);
659
660 /* Compare signed operands and set comparison result */
661 cc = (S32)regs->GR_L(r1) < (S32)(S8)i2 ? 1 :
662 (S32)regs->GR_L(r1) > (S32)(S8)i2 ? 2 : 0;
663
664 /* Branch to immediate offset if m3 mask bit is set */
665 if ((0x8 >> cc) & m3)
666 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
667 else
668 INST_UPDATE_PSW(regs, 6, 0);
669
670 } /* end DEF_INST(compare_immediate_and_branch_relative) */
671
672
673 #if defined(FEATURE_ESAME)
674 /*-------------------------------------------------------------------*/
675 /* EC7C CGIJ - Compare Immediate and Branch Relative Long [RIE] */
676 /*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_branch_relative_long)677 DEF_INST(compare_immediate_and_branch_relative_long)
678 {
679 int r1; /* Register numbers */
680 int m3; /* Mask bits */
681 BYTE i2; /* Immediate operand value */
682 S16 i4; /* 16-bit immediate offset */
683 int cc; /* Comparison result */
684
685 RIE_RMII_B(inst, regs, r1, i2, m3, i4);
686
687 /* Compare signed operands and set comparison result */
688 cc = (S64)regs->GR_G(r1) < (S64)(S8)i2 ? 1 :
689 (S64)regs->GR_G(r1) > (S64)(S8)i2 ? 2 : 0;
690
691 /* Branch to immediate offset if m3 mask bit is set */
692 if ((0x8 >> cc) & m3)
693 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
694 else
695 INST_UPDATE_PSW(regs, 6, 0);
696
697 } /* end DEF_INST(compare_immediate_and_branch_relative_long) */
698 #endif /*defined(FEATURE_ESAME)*/
699
700
701 /*-------------------------------------------------------------------*/
702 /* EC72 CIT - Compare Immediate and Trap [RIE] */
703 /*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_trap)704 DEF_INST(compare_immediate_and_trap)
705 {
706 int r1; /* Register number */
707 int m3; /* Mask bits */
708 int cc; /* Comparison result */
709 U16 i2; /* 16-bit immediate value */
710
711 RIE_RIM(inst, regs, r1, i2, m3);
712
713 /* Compare signed operands and set comparison result */
714 cc = (S32)regs->GR_L(r1) < (S32)(S16)i2 ? 1 :
715 (S32)regs->GR_L(r1) > (S32)(S16)i2 ? 2 : 0;
716
717 /* Raise data exception if m3 mask bit is set */
718 if ((0x8 >> cc) & m3)
719 {
720 regs->dxc = DXC_COMPARE_AND_TRAP;
721 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
722 }
723
724 } /* end DEF_INST(compare_immediate_and_trap) */
725
726
727 #if defined(FEATURE_ESAME)
728 /*-------------------------------------------------------------------*/
729 /* EC70 CGIT - Compare Immediate and Trap Long [RIE] */
730 /*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_trap_long)731 DEF_INST(compare_immediate_and_trap_long)
732 {
733 int r1; /* Register number */
734 int m3; /* Mask bits */
735 int cc; /* Comparison result */
736 U16 i2; /* 16-bit immediate value */
737
738 RIE_RIM(inst, regs, r1, i2, m3);
739
740 /* Compare signed operands and set comparison result */
741 cc = (S64)regs->GR_G(r1) < (S64)(S16)i2 ? 1 :
742 (S64)regs->GR_G(r1) > (S64)(S16)i2 ? 2 : 0;
743
744 /* Raise data exception if m3 mask bit is set */
745 if ((0x8 >> cc) & m3)
746 {
747 regs->dxc = DXC_COMPARE_AND_TRAP;
748 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
749 }
750
751 } /* end DEF_INST(compare_immediate_and_trap_long) */
752 #endif /*defined(FEATURE_ESAME)*/
753
754
755 /*-------------------------------------------------------------------*/
756 /* ECF7 CLRB - Compare Logical and Branch Register [RRS] */
757 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_register)758 DEF_INST(compare_logical_and_branch_register)
759 {
760 int r1, r2; /* Register numbers */
761 int m3; /* Mask bits */
762 int b4; /* Base of effective addr */
763 VADR effective_addr4; /* Effective address */
764 int cc; /* Comparison result */
765
766 RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
767
768 /* Compare unsigned operands and set comparison result */
769 cc = regs->GR_L(r1) < regs->GR_L(r2) ? 1 :
770 regs->GR_L(r1) > regs->GR_L(r2) ? 2 : 0;
771
772 /* Branch to operand address if m3 mask bit is set */
773 if ((0x8 >> cc) & m3)
774 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
775 else
776 INST_UPDATE_PSW(regs, 6, 0);
777
778 } /* end DEF_INST(compare_logical_and_branch_register) */
779
780
781 #if defined(FEATURE_ESAME)
782 /*-------------------------------------------------------------------*/
783 /* ECE5 CLGRB - Compare Logical and Branch Long Register [RRS] */
784 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_long_register)785 DEF_INST(compare_logical_and_branch_long_register)
786 {
787 int r1, r2; /* Register numbers */
788 int m3; /* Mask bits */
789 int b4; /* Base of effective addr */
790 VADR effective_addr4; /* Effective address */
791 int cc; /* Comparison result */
792
793 RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
794
795 /* Compare unsigned operands and set comparison result */
796 cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
797 regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
798
799 /* Branch to operand address if m3 mask bit is set */
800 if ((0x8 >> cc) & m3)
801 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
802 else
803 INST_UPDATE_PSW(regs, 6, 0);
804
805 } /* end DEF_INST(compare_logical_and_branch_long_register) */
806 #endif /*defined(FEATURE_ESAME)*/
807
808
809 /*-------------------------------------------------------------------*/
810 /* EC77 CLRJ - Compare Logical and Branch Relative Register [RIE] */
811 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_relative_register)812 DEF_INST(compare_logical_and_branch_relative_register)
813 {
814 int r1, r2; /* Register numbers */
815 int m3; /* Mask bits */
816 S16 i4; /* 16-bit immediate offset */
817 int cc; /* Comparison result */
818
819 RIE_RRIM_B(inst, regs, r1, r2, i4, m3);
820
821 /* Compare unsigned operands and set comparison result */
822 cc = regs->GR_L(r1) < regs->GR_L(r2) ? 1 :
823 regs->GR_L(r1) > regs->GR_L(r2) ? 2 : 0;
824
825 /* Branch to immediate offset if m3 mask bit is set */
826 if ((0x8 >> cc) & m3)
827 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
828 else
829 INST_UPDATE_PSW(regs, 6, 0);
830
831 } /* end DEF_INST(compare_logical_and_branch_relative_register) */
832
833
834 #if defined(FEATURE_ESAME)
835 /*-------------------------------------------------------------------*/
836 /* EC65 CLGRJ - Compare Logical and Branch Relative Long Reg [RIE] */
837 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_relative_long_register)838 DEF_INST(compare_logical_and_branch_relative_long_register)
839 {
840 int r1, r2; /* Register numbers */
841 int m3; /* Mask bits */
842 S16 i4; /* 16-bit immediate offset */
843 int cc; /* Comparison result */
844
845 RIE_RRIM_B(inst, regs, r1, r2, i4, m3);
846
847 /* Compare unsigned operands and set comparison result */
848 cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
849 regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
850
851 /* Branch to immediate offset if m3 mask bit is set */
852 if ((0x8 >> cc) & m3)
853 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
854 else
855 INST_UPDATE_PSW(regs, 6, 0);
856
857 } /* end DEF_INST(compare_logical_and_branch_relative_long_register) */
858 #endif /*defined(FEATURE_ESAME)*/
859
860
861 /*-------------------------------------------------------------------*/
862 /* B973 CLRT - Compare Logical and Trap Register [RRF] */
863 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_trap_register)864 DEF_INST(compare_logical_and_trap_register)
865 {
866 int r1, r2; /* Register numbers */
867 int m3; /* Mask bits */
868 int cc; /* Comparison result */
869
870 RRF_M(inst, regs, r1, r2, m3);
871
872 /* Compare unsigned operands and set comparison result */
873 cc = regs->GR_L(r1) < regs->GR_L(r2) ? 1 :
874 regs->GR_L(r1) > regs->GR_L(r2) ? 2 : 0;
875
876 /* Raise data exception if m3 mask bit is set */
877 if ((0x8 >> cc) & m3)
878 {
879 regs->dxc = DXC_COMPARE_AND_TRAP;
880 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
881 }
882
883 } /* end DEF_INST(compare_logical_and_trap_register) */
884
885
886 #if defined(FEATURE_ESAME)
887 /*-------------------------------------------------------------------*/
888 /* B961 CLGRT - Compare Logical and Trap Long Register [RRF] */
889 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_trap_long_register)890 DEF_INST(compare_logical_and_trap_long_register)
891 {
892 int r1, r2; /* Register numbers */
893 int m3; /* Mask bits */
894 int cc; /* Comparison result */
895
896 RRF_M(inst, regs, r1, r2, m3);
897
898 /* Compare unsigned operands and set comparison result */
899 cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
900 regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
901
902 /* Raise data exception if m3 mask bit is set */
903 if ((0x8 >> cc) & m3)
904 {
905 regs->dxc = DXC_COMPARE_AND_TRAP;
906 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
907 }
908
909 } /* end DEF_INST(compare_logical_and_trap_long_register) */
910 #endif /*defined(FEATURE_ESAME)*/
911
912
913 /*-------------------------------------------------------------------*/
914 /* ECFF CLIB - Compare Logical Immediate and Branch [RIS] */
915 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_and_branch)916 DEF_INST(compare_logical_immediate_and_branch)
917 {
918 int r1; /* Register number */
919 int m3; /* Mask bits */
920 int b4; /* Base of effective addr */
921 VADR effective_addr4; /* Effective address */
922 int cc; /* Comparison result */
923 BYTE i2; /* Immediate value */
924
925 RIS_B(inst, regs, r1, i2, m3, b4, effective_addr4);
926
927 /* Compare unsigned operands and set comparison result */
928 cc = regs->GR_L(r1) < i2 ? 1 :
929 regs->GR_L(r1) > i2 ? 2 : 0;
930
931 /* Branch to operand address if m3 mask bit is set */
932 if ((0x8 >> cc) & m3)
933 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
934 else
935 INST_UPDATE_PSW(regs, 6, 0);
936
937 } /* end DEF_INST(compare_logical_immediate_and_branch) */
938
939
940 #if defined(FEATURE_ESAME)
941 /*-------------------------------------------------------------------*/
942 /* ECFD CLGIB - Compare Logical Immediate and Branch Long [RIS] */
943 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_and_branch_long)944 DEF_INST(compare_logical_immediate_and_branch_long)
945 {
946 int r1; /* Register number */
947 int m3; /* Mask bits */
948 int b4; /* Base of effective addr */
949 VADR effective_addr4; /* Effective address */
950 int cc; /* Comparison result */
951 BYTE i2; /* Immediate value */
952
953 RIS_B(inst, regs, r1, i2, m3, b4, effective_addr4);
954
955 /* Compare unsigned operands and set comparison result */
956 cc = regs->GR_G(r1) < i2 ? 1 :
957 regs->GR_G(r1) > i2 ? 2 : 0;
958
959 /* Branch to operand address if m3 mask bit is set */
960 if ((0x8 >> cc) & m3)
961 SUCCESSFUL_BRANCH(regs, effective_addr4, 6);
962 else
963 INST_UPDATE_PSW(regs, 6, 0);
964
965 } /* end DEF_INST(compare_logical_immediate_and_branch_long) */
966 #endif /*defined(FEATURE_ESAME)*/
967
968
969 /*-------------------------------------------------------------------*/
970 /* EC7F CLIJ - Compare Logical Immediate and Branch Relative [RIE] */
971 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_and_branch_relative)972 DEF_INST(compare_logical_immediate_and_branch_relative)
973 {
974 int r1; /* Register number */
975 int m3; /* Mask bits */
976 BYTE i2; /* Immediate operand value */
977 S16 i4; /* 16-bit immediate offset */
978 int cc; /* Comparison result */
979
980 RIE_RMII_B(inst, regs, r1, i2, m3, i4);
981
982 /* Compare unsigned operands and set comparison result */
983 cc = regs->GR_L(r1) < i2 ? 1 :
984 regs->GR_L(r1) > i2 ? 2 : 0;
985
986 /* Branch to immediate offset if m3 mask bit is set */
987 if ((0x8 >> cc) & m3)
988 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
989 else
990 INST_UPDATE_PSW(regs, 6, 0);
991
992 } /* end DEF_INST(compare_logical_immediate_and_branch_relative) */
993
994
995 #if defined(FEATURE_ESAME)
996 /*-------------------------------------------------------------------*/
997 /* EC7D CLGIJ - Compare Logical Immed and Branch Relative Long [RIE] */
998 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_and_branch_relative_long)999 DEF_INST(compare_logical_immediate_and_branch_relative_long)
1000 {
1001 int r1; /* Register number */
1002 int m3; /* Mask bits */
1003 BYTE i2; /* Immediate operand value */
1004 S16 i4; /* 16-bit immediate offset */
1005 int cc; /* Comparison result */
1006
1007 RIE_RMII_B(inst, regs, r1, i2, m3, i4);
1008
1009 /* Compare unsigned operands and set comparison result */
1010 cc = regs->GR_G(r1) < i2 ? 1 :
1011 regs->GR_G(r1) > i2 ? 2 : 0;
1012
1013 /* Branch to immediate offset if m3 mask bit is set */
1014 if ((0x8 >> cc) & m3)
1015 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i4, 6);
1016 else
1017 INST_UPDATE_PSW(regs, 6, 0);
1018
1019 } /* end DEF_INST(compare_logical_immediate_and_branch_relative_long) */
1020 #endif /*defined(FEATURE_ESAME)*/
1021
1022
1023 /*-------------------------------------------------------------------*/
1024 /* EC73 CLFIT - Compare Logical Immediate and Trap Fullword [RIE] */
1025 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_and_trap_fullword)1026 DEF_INST(compare_logical_immediate_and_trap_fullword)
1027 {
1028 int r1; /* Register number */
1029 int m3; /* Mask bits */
1030 int cc; /* Comparison result */
1031 U16 i2; /* 16-bit immediate value */
1032
1033 RIE_RIM(inst, regs, r1, i2, m3);
1034
1035 /* Compare unsigned operands and set comparison result */
1036 cc = regs->GR_L(r1) < i2 ? 1 :
1037 regs->GR_L(r1) > i2 ? 2 : 0;
1038
1039 /* Raise data exception if m3 mask bit is set */
1040 if ((0x8 >> cc) & m3)
1041 {
1042 regs->dxc = DXC_COMPARE_AND_TRAP;
1043 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
1044 }
1045
1046 } /* end DEF_INST(compare_logical_immediate_and_trap_fullword) */
1047
1048
1049 #if defined(FEATURE_ESAME)
1050 /*-------------------------------------------------------------------*/
1051 /* EC71 CLGIT - Compare Logical Immediate and Trap Long [RIE] */
1052 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_and_trap_long)1053 DEF_INST(compare_logical_immediate_and_trap_long)
1054 {
1055 int r1; /* Register number */
1056 int m3; /* Mask bits */
1057 int cc; /* Comparison result */
1058 U16 i2; /* 16-bit immediate value */
1059
1060 RIE_RIM(inst, regs, r1, i2, m3);
1061
1062 /* Compare unsigned operands and set comparison result */
1063 cc = regs->GR_G(r1) < i2 ? 1 :
1064 regs->GR_G(r1) > i2 ? 2 : 0;
1065
1066 /* Raise data exception if m3 mask bit is set */
1067 if ((0x8 >> cc) & m3)
1068 {
1069 regs->dxc = DXC_COMPARE_AND_TRAP;
1070 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
1071 }
1072
1073 } /* end DEF_INST(compare_logical_immediate_and_trap_long) */
1074 #endif /*defined(FEATURE_ESAME)*/
1075
1076
1077 /*-------------------------------------------------------------------*/
1078 /* E55D CLFHSI - Compare Logical Immediate Fullword Storage [SIL] */
1079 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_fullword_storage)1080 DEF_INST(compare_logical_immediate_fullword_storage)
1081 {
1082 int b1; /* Base of effective addr */
1083 VADR effective_addr1; /* Effective address */
1084 U16 i2; /* 16-bit immediate value */
1085 U32 n; /* 32-bit storage value */
1086
1087 SIL(inst, regs, i2, b1, effective_addr1);
1088
1089 /* Load 32-bit value from first operand address */
1090 n = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
1091
1092 /* Compare unsigned operands and set condition code */
1093 regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
1094
1095 } /* end DEF_INST(compare_logical_immediate_fullword_storage) */
1096
1097
1098 /*-------------------------------------------------------------------*/
1099 /* E555 CLHHSI - Compare Logical Immediate Halfword Storage [SIL] */
1100 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_halfword_storage)1101 DEF_INST(compare_logical_immediate_halfword_storage)
1102 {
1103 int b1; /* Base of effective addr */
1104 VADR effective_addr1; /* Effective address */
1105 U16 i2; /* 16-bit immediate value */
1106 U16 n; /* 16-bit storage value */
1107
1108 SIL(inst, regs, i2, b1, effective_addr1);
1109
1110 /* Load 16-bit value from first operand address */
1111 n = ARCH_DEP(vfetch2) ( effective_addr1, b1, regs );
1112
1113 /* Compare unsigned operands and set condition code */
1114 regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
1115
1116 } /* end DEF_INST(compare_logical_immediate_halfword_storage) */
1117
1118
1119 /*-------------------------------------------------------------------*/
1120 /* E559 CLGHSI - Compare Logical Immediate Long Storage [SIL] */
1121 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_long_storage)1122 DEF_INST(compare_logical_immediate_long_storage)
1123 {
1124 int b1; /* Base of effective addr */
1125 VADR effective_addr1; /* Effective address */
1126 U16 i2; /* 16-bit immediate value */
1127 U64 n; /* 64-bit storage value */
1128
1129 SIL(inst, regs, i2, b1, effective_addr1);
1130
1131 /* Load 64-bit value from first operand address */
1132 n = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
1133
1134 /* Compare unsigned operands and set condition code */
1135 regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
1136
1137 } /* end DEF_INST(compare_logical_immediate_long_storage) */
1138
1139
1140 /*-------------------------------------------------------------------*/
1141 /* C6xF CLRL - Compare Logical Relative Long [RIL] */
1142 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_relative_long)1143 DEF_INST(compare_logical_relative_long)
1144 {
1145 int r1; /* Register number */
1146 VADR addr2; /* Relative operand address */
1147 U32 n; /* Relative operand value */
1148
1149 RIL_A(inst, regs, r1, addr2);
1150
1151 /* Program check if operand not on fullword boundary */
1152 FW_CHECK(addr2, regs);
1153
1154 /* Load relative operand from instruction address space */
1155 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1156
1157 /* Compare signed operands and set condition code */
1158 regs->psw.cc =
1159 regs->GR_L(r1) < n ? 1 :
1160 regs->GR_L(r1) > n ? 2 : 0;
1161
1162 } /* end DEF_INST(compare_logical_relative_long) */
1163
1164
1165 #if defined(FEATURE_ESAME)
1166 /*-------------------------------------------------------------------*/
1167 /* C6xA CLGRL - Compare Logical Relative Long Long [RIL] */
1168 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_relative_long_long)1169 DEF_INST(compare_logical_relative_long_long)
1170 {
1171 int r1; /* Register number */
1172 VADR addr2; /* Relative operand address */
1173 U64 n; /* Relative operand value */
1174
1175 RIL_A(inst, regs, r1, addr2);
1176
1177 /* Program check if operand not on doubleword boundary */
1178 DW_CHECK(addr2, regs);
1179
1180 /* Load relative operand from instruction address space */
1181 n = ARCH_DEP(vfetch8) ( addr2, USE_INST_SPACE, regs );
1182
1183 /* Compare signed operands and set condition code */
1184 regs->psw.cc =
1185 regs->GR_G(r1) < n ? 1 :
1186 regs->GR_G(r1) > n ? 2 : 0;
1187
1188 } /* end DEF_INST(compare_logical_relative_long_long) */
1189 #endif /*defined(FEATURE_ESAME)*/
1190
1191
1192 #if defined(FEATURE_ESAME)
1193 /*-------------------------------------------------------------------*/
1194 /* C6xE CLGFRL - Compare Logical Relative Long Long Fullword [RIL] */
1195 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_relative_long_long_fullword)1196 DEF_INST(compare_logical_relative_long_long_fullword)
1197 {
1198 int r1; /* Register number */
1199 VADR addr2; /* Relative operand address */
1200 U32 n; /* Relative operand value */
1201
1202 RIL_A(inst, regs, r1, addr2);
1203
1204 /* Program check if operand not on fullword boundary */
1205 FW_CHECK(addr2, regs);
1206
1207 /* Load relative operand from instruction address space */
1208 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1209
1210 /* Compare signed operands and set condition code */
1211 regs->psw.cc =
1212 regs->GR_G(r1) < n ? 1 :
1213 regs->GR_G(r1) > n ? 2 : 0;
1214
1215 } /* end DEF_INST(compare_logical_relative_long_long_fullword) */
1216 #endif /*defined(FEATURE_ESAME)*/
1217
1218
1219 /*-------------------------------------------------------------------*/
1220 /* C6x7 CLHRL - Compare Logical Halfword Relative Long [RIL] */
1221 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_relative_long_halfword)1222 DEF_INST(compare_logical_relative_long_halfword)
1223 {
1224 int r1; /* Register number */
1225 VADR addr2; /* Relative operand address */
1226 U16 n; /* Relative operand value */
1227
1228 RIL_A(inst, regs, r1, addr2);
1229
1230 /* Load relative operand from instruction address space */
1231 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
1232
1233 /* Compare signed operands and set condition code */
1234 regs->psw.cc =
1235 regs->GR_L(r1) < n ? 1 :
1236 regs->GR_L(r1) > n ? 2 : 0;
1237
1238 } /* end DEF_INST(compare_logical_relative_long_halfword) */
1239
1240
1241 #if defined(FEATURE_ESAME)
1242 /*-------------------------------------------------------------------*/
1243 /* C6x6 CLGHRL - Compare Logical Halfword Relative Long Long [RIL] */
1244 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_relative_long_long_halfword)1245 DEF_INST(compare_logical_relative_long_long_halfword)
1246 {
1247 int r1; /* Register number */
1248 VADR addr2; /* Relative operand address */
1249 U16 n; /* Relative operand value */
1250
1251 RIL_A(inst, regs, r1, addr2);
1252
1253 /* Load relative operand from instruction address space */
1254 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
1255
1256 /* Compare signed operands and set condition code */
1257 regs->psw.cc =
1258 regs->GR_G(r1) < n ? 1 :
1259 regs->GR_G(r1) > n ? 2 : 0;
1260
1261 } /* end DEF_INST(compare_logical_relative_long_long_halfword) */
1262 #endif /*defined(FEATURE_ESAME)*/
1263
1264
1265 /*-------------------------------------------------------------------*/
1266 /* C6xD CRL - Compare Relative Long [RIL] */
1267 /*-------------------------------------------------------------------*/
DEF_INST(compare_relative_long)1268 DEF_INST(compare_relative_long)
1269 {
1270 int r1; /* Register number */
1271 VADR addr2; /* Relative operand address */
1272 U32 n; /* Relative operand value */
1273
1274 RIL_A(inst, regs, r1, addr2);
1275
1276 /* Program check if operand not on fullword boundary */
1277 FW_CHECK(addr2, regs);
1278
1279 /* Load relative operand from instruction address space */
1280 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1281
1282 /* Compare signed operands and set condition code */
1283 regs->psw.cc =
1284 (S32)regs->GR_L(r1) < (S32)n ? 1 :
1285 (S32)regs->GR_L(r1) > (S32)n ? 2 : 0;
1286
1287 } /* end DEF_INST(compare_relative_long) */
1288
1289
1290 #if defined(FEATURE_ESAME)
1291 /*-------------------------------------------------------------------*/
1292 /* C6x8 CGRL - Compare Relative Long Long [RIL] */
1293 /*-------------------------------------------------------------------*/
DEF_INST(compare_relative_long_long)1294 DEF_INST(compare_relative_long_long)
1295 {
1296 int r1; /* Register number */
1297 VADR addr2; /* Relative operand address */
1298 U64 n; /* Relative operand value */
1299
1300 RIL_A(inst, regs, r1, addr2);
1301
1302 /* Program check if operand not on doubleword boundary */
1303 DW_CHECK(addr2, regs);
1304
1305 /* Load relative operand from instruction address space */
1306 n = ARCH_DEP(vfetch8) ( addr2, USE_INST_SPACE, regs );
1307
1308 /* Compare signed operands and set condition code */
1309 regs->psw.cc =
1310 (S64)regs->GR_G(r1) < (S64)n ? 1 :
1311 (S64)regs->GR_G(r1) > (S64)n ? 2 : 0;
1312
1313 } /* end DEF_INST(compare_relative_long_long) */
1314 #endif /*defined(FEATURE_ESAME)*/
1315
1316
1317 #if defined(FEATURE_ESAME)
1318 /*-------------------------------------------------------------------*/
1319 /* C6xC CGFRL - Compare Relative Long Long Fullword [RIL] */
1320 /*-------------------------------------------------------------------*/
DEF_INST(compare_relative_long_long_fullword)1321 DEF_INST(compare_relative_long_long_fullword)
1322 {
1323 int r1; /* Register number */
1324 VADR addr2; /* Relative operand address */
1325 U32 n; /* Relative operand value */
1326
1327 RIL_A(inst, regs, r1, addr2);
1328
1329 /* Program check if operand not on fullword boundary */
1330 FW_CHECK(addr2, regs);
1331
1332 /* Load relative operand from instruction address space */
1333 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1334
1335 /* Compare signed operands and set condition code */
1336 regs->psw.cc =
1337 (S64)regs->GR_G(r1) < (S32)n ? 1 :
1338 (S64)regs->GR_G(r1) > (S32)n ? 2 : 0;
1339
1340 } /* end DEF_INST(compare_relative_long_long_fullword) */
1341 #endif /*defined(FEATURE_ESAME)*/
1342
1343
1344 #if defined(FEATURE_ESAME)
1345 /*-------------------------------------------------------------------*/
1346 /* EB4C ECAG - Extract Cache Attribute [RSY] */
1347 /*-------------------------------------------------------------------*/
DEF_INST(extract_cache_attribute)1348 DEF_INST(extract_cache_attribute)
1349 {
1350 int r1, r3; /* Register numbers */
1351 int b2; /* Base of effective addr */
1352 VADR effective_addr2; /* Effective address */
1353 int ai, li, ti; /* Operand address subfields */
1354
1355 RSY(inst, regs, r1, r3, b2, effective_addr2);
1356
1357 /* Address bit 63 contains the Type Indication (TI) */
1358 ti = effective_addr2 & 0x1;
1359
1360 /* Address bits 60-62 contain the Level Indication (LI) */
1361 li = (effective_addr2 >> 1) & 0x7;
1362
1363 /* Address bits 56-59 contain the Attribute Indication (AI) */
1364 ai = (effective_addr2 >> 4) & 0xF;
1365
1366 //logmsg ("ECAG ai=%d li=%d ti=%d\n", ai, li, ti);
1367
1368 /* If reserved bits 40-55 are not zero then set r1 to all ones */
1369 if ((effective_addr2 & 0xFFFF00) != 0)
1370 {
1371 regs->GR(r1) = 0xFFFFFFFFFFFFFFFFULL;
1372 return;
1373 }
1374
1375 /* If AI=0 (topology summary) is requested, set register r1 to
1376 indicate that cache level 0 is private to this CPU and that
1377 cache levels 1-7 are not implemented */
1378 if (ai == 0)
1379 {
1380 regs->GR_H(r1) = 0x04000000;
1381 regs->GR_L(r1) = 0x00000000;
1382 return;
1383 }
1384
1385 /* If cache level is not 0, set register r1 to all ones which
1386 indicates that the requested cache level is not implemented */
1387 if (li > 0)
1388 {
1389 regs->GR(r1) = 0xFFFFFFFFFFFFFFFFULL;
1390 return;
1391 }
1392
1393 /* If AI=1 (cache line size) is requested for cache level 0
1394 set register r1 to indicate a fictitious cache line size */
1395 if (ai == 1 && li == 0)
1396 {
1397 regs->GR(r1) = 256;
1398 return;
1399 }
1400
1401 /* If AI=2 (total cache size) is requested for cache level 0
1402 set register r1 to indicate a fictitious total cache size */
1403 if (ai == 2 && li == 0)
1404 {
1405 regs->GR(r1) = 256 * 2048;
1406 return;
1407 }
1408
1409 /* Set register r1 to all ones indicating that the requested
1410 attribute indication is reserved */
1411 regs->GR(r1) = 0xFFFFFFFFFFFFFFFFULL;
1412
1413 } /* end DEF_INST(extract_cache_attribute) */
1414 #endif /*defined(FEATURE_ESAME)*/
1415
1416
1417 #if defined(FEATURE_ACCESS_REGISTERS)
1418 /*-------------------------------------------------------------------*/
1419 /* E375 LAEY - Load Address Extended (Long Displacement) [RXY] */
1420 /*-------------------------------------------------------------------*/
DEF_INST(load_address_extended_y)1421 DEF_INST(load_address_extended_y)
1422 {
1423 int r1; /* Value of R field */
1424 int b2; /* Base of effective addr */
1425 VADR effective_addr2; /* Effective address */
1426
1427 RXY0(inst, regs, r1, b2, effective_addr2);
1428
1429 /* Load operand address into register */
1430 SET_GR_A(r1, regs,effective_addr2);
1431
1432 /* Load corresponding value into access register */
1433 if ( PRIMARY_SPACE_MODE(&(regs->psw)) )
1434 regs->AR(r1) = ALET_PRIMARY;
1435 else if ( SECONDARY_SPACE_MODE(&(regs->psw)) )
1436 regs->AR(r1) = ALET_SECONDARY;
1437 else if ( HOME_SPACE_MODE(&(regs->psw)) )
1438 regs->AR(r1) = ALET_HOME;
1439 else /* ACCESS_REGISTER_MODE(&(regs->psw)) */
1440 regs->AR(r1) = (b2 == 0) ? 0 : regs->AR(b2);
1441 SET_AEA_AR(regs, r1);
1442
1443 } /* end DEF_INST(load_address_extended_y) */
1444 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
1445
1446
1447 #if defined(FEATURE_ESAME)
1448 /*-------------------------------------------------------------------*/
1449 /* E332 LTGF - Load and Test Long Fullword [RXY] */
1450 /*-------------------------------------------------------------------*/
DEF_INST(load_and_test_long_fullword)1451 DEF_INST(load_and_test_long_fullword)
1452 {
1453 int r1; /* Value of R field */
1454 int b2; /* Base of effective addr */
1455 VADR effective_addr2; /* Effective address */
1456 U32 n; /* Second operand value */
1457
1458 RXY(inst, regs, r1, b2, effective_addr2);
1459
1460 /* Load R1 register from sign-extended second operand */
1461 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1462 regs->GR_G(r1) = (S64)(S32)n;
1463
1464 /* Set condition code according to value loaded */
1465 regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
1466 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
1467
1468 } /* end DEF_INST(load_and_test_long_fullword) */
1469 #endif /*defined(FEATURE_ESAME)*/
1470
1471
1472 /*-------------------------------------------------------------------*/
1473 /* C4x5 LHRL - Load Halfword Relative Long [RIL] */
1474 /*-------------------------------------------------------------------*/
DEF_INST(load_halfword_relative_long)1475 DEF_INST(load_halfword_relative_long)
1476 {
1477 int r1; /* Register number */
1478 VADR addr2; /* Relative operand address */
1479 U16 n; /* Relative operand value */
1480
1481 RIL_A(inst, regs, r1, addr2);
1482
1483 /* Load relative operand from instruction address space */
1484 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
1485
1486 /* Sign-extend operand value and load into R1 register */
1487 regs->GR_L(r1) = (S32)(S16)n;
1488
1489 } /* end DEF_INST(load_halfword_relative_long) */
1490
1491
1492 #if defined(FEATURE_ESAME)
1493 /*-------------------------------------------------------------------*/
1494 /* C4x4 LGHRL - Load Halfword Relative Long Long [RIL] */
1495 /*-------------------------------------------------------------------*/
DEF_INST(load_halfword_relative_long_long)1496 DEF_INST(load_halfword_relative_long_long)
1497 {
1498 int r1; /* Register number */
1499 VADR addr2; /* Relative operand address */
1500 U16 n; /* Relative operand value */
1501
1502 RIL_A(inst, regs, r1, addr2);
1503
1504 /* Load relative operand from instruction address space */
1505 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
1506
1507 /* Sign-extend operand value and load into R1 register */
1508 regs->GR_G(r1) = (S64)(S16)n;
1509
1510 } /* end DEF_INST(load_halfword_relative_long_long) */
1511 #endif /*defined(FEATURE_ESAME)*/
1512
1513
1514 /*-------------------------------------------------------------------*/
1515 /* C4x2 LLHRL - Load Logical Halfword Relative Long [RIL] */
1516 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_halfword_relative_long)1517 DEF_INST(load_logical_halfword_relative_long)
1518 {
1519 int r1; /* Register number */
1520 VADR addr2; /* Relative operand address */
1521 U16 n; /* Relative operand value */
1522
1523 RIL_A(inst, regs, r1, addr2);
1524
1525 /* Load relative operand from instruction address space */
1526 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
1527
1528 /* Zero-extend operand value and load into R1 register */
1529 regs->GR_L(r1) = n;
1530
1531 } /* end DEF_INST(load_logical_halfword_relative_long) */
1532
1533
1534 #if defined(FEATURE_ESAME)
1535 /*-------------------------------------------------------------------*/
1536 /* C4x6 LLGHRL - Load Logical Halfword Relative Long Long [RIL] */
1537 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_halfword_relative_long_long)1538 DEF_INST(load_logical_halfword_relative_long_long)
1539 {
1540 int r1; /* Register number */
1541 VADR addr2; /* Relative operand address */
1542 U16 n; /* Relative operand value */
1543
1544 RIL_A(inst, regs, r1, addr2);
1545
1546 /* Load relative operand from instruction address space */
1547 n = ARCH_DEP(vfetch2) ( addr2, USE_INST_SPACE, regs );
1548
1549 /* Zero-extend operand value and load into R1 register */
1550 regs->GR_G(r1) = n;
1551
1552 } /* end DEF_INST(load_logical_halfword_relative_long_long) */
1553 #endif /*defined(FEATURE_ESAME)*/
1554
1555
1556 #if defined(FEATURE_ESAME)
1557 /*-------------------------------------------------------------------*/
1558 /* C4xE LLGFRL - Load Logical Relative Long Long Fullword [RIL] */
1559 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_relative_long_long_fullword)1560 DEF_INST(load_logical_relative_long_long_fullword)
1561 {
1562 int r1; /* Register number */
1563 VADR addr2; /* Relative operand address */
1564 U32 n; /* Relative operand value */
1565
1566 RIL_A(inst, regs, r1, addr2);
1567
1568 /* Program check if operand not on fullword boundary */
1569 FW_CHECK(addr2, regs);
1570
1571 /* Load relative operand from instruction address space */
1572 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1573
1574 /* Zero-extend operand value and load into R1 register */
1575 regs->GR_G(r1) = n;
1576
1577 } /* end DEF_INST(load_logical_relative_long_long_fullword) */
1578 #endif /*defined(FEATURE_ESAME)*/
1579
1580
1581 /*-------------------------------------------------------------------*/
1582 /* C4xD LRL - Load Relative Long [RIL] */
1583 /*-------------------------------------------------------------------*/
DEF_INST(load_relative_long)1584 DEF_INST(load_relative_long)
1585 {
1586 int r1; /* Register number */
1587 VADR addr2; /* Relative operand address */
1588 U32 n; /* Relative operand value */
1589
1590 RIL_A(inst, regs, r1, addr2);
1591
1592 /* Program check if operand not on fullword boundary */
1593 FW_CHECK(addr2, regs);
1594
1595 /* Load relative operand from instruction address space */
1596 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1597
1598 /* Load operand value into R1 register */
1599 regs->GR_L(r1) = n;
1600
1601 } /* end DEF_INST(load_relative_long) */
1602
1603
1604 #if defined(FEATURE_ESAME)
1605 /*-------------------------------------------------------------------*/
1606 /* C4x8 LGRL - Load Relative Long Long [RIL] */
1607 /*-------------------------------------------------------------------*/
DEF_INST(load_relative_long_long)1608 DEF_INST(load_relative_long_long)
1609 {
1610 int r1; /* Register number */
1611 VADR addr2; /* Relative operand address */
1612 U64 n; /* Relative operand value */
1613
1614 RIL_A(inst, regs, r1, addr2);
1615
1616 /* Program check if operand not on doubleword boundary */
1617 DW_CHECK(addr2, regs);
1618
1619 /* Load relative operand from instruction address space */
1620 n = ARCH_DEP(vfetch8) ( addr2, USE_INST_SPACE, regs );
1621
1622 /* Load operand value into R1 register */
1623 regs->GR_G(r1) = n;
1624
1625 } /* end DEF_INST(load_relative_long_long) */
1626 #endif /*defined(FEATURE_ESAME)*/
1627
1628
1629 #if defined(FEATURE_ESAME)
1630 /*-------------------------------------------------------------------*/
1631 /* C4xC LGFRL - Load Relative Long Long Fullword [RIL] */
1632 /*-------------------------------------------------------------------*/
DEF_INST(load_relative_long_long_fullword)1633 DEF_INST(load_relative_long_long_fullword)
1634 {
1635 int r1; /* Register number */
1636 VADR addr2; /* Relative operand address */
1637 U32 n; /* Relative operand value */
1638
1639 RIL_A(inst, regs, r1, addr2);
1640
1641 /* Program check if operand not on fullword boundary */
1642 FW_CHECK(addr2, regs);
1643
1644 /* Load relative operand from instruction address space */
1645 n = ARCH_DEP(vfetch4) ( addr2, USE_INST_SPACE, regs );
1646
1647 /* Sign-extend operand value and load into R1 register */
1648 regs->GR_G(r1) = (S64)(S32)n;
1649
1650 } /* end DEF_INST(load_relative_long_long_fullword) */
1651 #endif /*defined(FEATURE_ESAME)*/
1652
1653
1654 /*-------------------------------------------------------------------*/
1655 /* E54C MVHI - Move Fullword from Halfword Immediate [SIL] */
1656 /*-------------------------------------------------------------------*/
DEF_INST(move_fullword_from_halfword_immediate)1657 DEF_INST(move_fullword_from_halfword_immediate)
1658 {
1659 int b1; /* Base of effective addr */
1660 VADR effective_addr1; /* Effective address */
1661 S16 i2; /* 16-bit immediate value */
1662 S32 n; /* Sign-extended value of i2 */
1663
1664 SIL(inst, regs, i2, b1, effective_addr1);
1665
1666 /* Sign-extend 16-bit immediate value to 32 bits */
1667 n = i2;
1668
1669 /* Store 4-byte value at operand address */
1670 ARCH_DEP(vstore4) ( n, effective_addr1, b1, regs );
1671
1672 } /* end DEF_INST(move_fullword_from_halfword_immediate) */
1673
1674
1675 /*-------------------------------------------------------------------*/
1676 /* E544 MVHHI - Move Halfword from Halfword Immediate [SIL] */
1677 /*-------------------------------------------------------------------*/
DEF_INST(move_halfword_from_halfword_immediate)1678 DEF_INST(move_halfword_from_halfword_immediate)
1679 {
1680 int b1; /* Base of effective addr */
1681 VADR effective_addr1; /* Effective address */
1682 S16 i2; /* 16-bit immediate value */
1683
1684 SIL(inst, regs, i2, b1, effective_addr1);
1685
1686 /* Store 16-bit immediate value at operand address */
1687 ARCH_DEP(vstore2) ( i2, effective_addr1, b1, regs );
1688
1689 } /* end DEF_INST(move_halfword_from_halfword_immediate) */
1690
1691
1692 /*-------------------------------------------------------------------*/
1693 /* E548 MVGHI - Move Long from Halfword Immediate [SIL] */
1694 /*-------------------------------------------------------------------*/
DEF_INST(move_long_from_halfword_immediate)1695 DEF_INST(move_long_from_halfword_immediate)
1696 {
1697 int b1; /* Base of effective addr */
1698 VADR effective_addr1; /* Effective address */
1699 S16 i2; /* 16-bit immediate value */
1700 S64 n; /* Sign-extended value of i2 */
1701
1702 SIL(inst, regs, i2, b1, effective_addr1);
1703
1704 /* Sign-extend 16-bit immediate value to 64 bits */
1705 n = i2;
1706
1707 /* Store 8-byte value at operand address */
1708 ARCH_DEP(vstore8) ( n, effective_addr1, b1, regs );
1709
1710 } /* end DEF_INST(move_long_from_halfword_immediate) */
1711
1712
1713 /*-------------------------------------------------------------------*/
1714 /* E37C MHY - Multiply Halfword (Long Displacement) [RXY] */
1715 /*-------------------------------------------------------------------*/
DEF_INST(multiply_halfword_y)1716 DEF_INST(multiply_halfword_y)
1717 {
1718 int r1; /* Value of R field */
1719 int b2; /* Base of effective addr */
1720 VADR effective_addr2; /* Effective address */
1721 S32 n; /* 32-bit operand values */
1722
1723 RXY(inst, regs, r1, b2, effective_addr2);
1724
1725 /* Load 2 bytes from operand address */
1726 n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
1727
1728 /* Multiply R1 register by n, ignore leftmost 32 bits of
1729 result, and place rightmost 32 bits in R1 register */
1730 mul_signed ((U32 *)&n, &(regs->GR_L(r1)), regs->GR_L(r1), n);
1731
1732 } /* end DEF_INST(multiply_halfword_y) */
1733
1734
1735 /*-------------------------------------------------------------------*/
1736 /* C2x1 MSFI - Multiply Single Immediate Fullword [RIL] */
1737 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_immediate_fullword)1738 DEF_INST(multiply_single_immediate_fullword)
1739 {
1740 int r1; /* Register number */
1741 int opcd; /* Opcode */
1742 U32 i2; /* 32-bit operand value */
1743
1744 RIL(inst, regs, r1, opcd, i2);
1745
1746 /* Multiply signed operands ignoring overflow */
1747 regs->GR_L(r1) = (S32)regs->GR_L(r1) * (S32)i2;
1748
1749 } /* end DEF_INST(multiply_single_immediate_fullword) */
1750
1751
1752 #if defined(FEATURE_ESAME)
1753 /*-------------------------------------------------------------------*/
1754 /* C2x0 MSGFI - Multiply Single Immediate Long Fullword [RIL] */
1755 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_immediate_long_fullword)1756 DEF_INST(multiply_single_immediate_long_fullword)
1757 {
1758 int r1; /* Register number */
1759 int opcd; /* Opcode */
1760 U32 i2; /* 32-bit operand value */
1761
1762 RIL(inst, regs, r1, opcd, i2);
1763
1764 /* Multiply signed operands ignoring overflow */
1765 regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S32)i2;
1766
1767 } /* end DEF_INST(multiply_single_immediate_long_fullword) */
1768 #endif /*defined(FEATURE_ESAME)*/
1769
1770
1771 /*-------------------------------------------------------------------*/
1772 /* E35C MFY - Multiply (Long Displacement) [RXY] */
1773 /*-------------------------------------------------------------------*/
DEF_INST(multiply_y)1774 DEF_INST(multiply_y)
1775 {
1776 int r1; /* Value of R field */
1777 int b2; /* Base of effective addr */
1778 VADR effective_addr2; /* Effective address */
1779 U32 n; /* 32-bit operand values */
1780
1781 RXY(inst, regs, r1, b2, effective_addr2);
1782
1783 ODD_CHECK(r1, regs);
1784
1785 /* Load second operand from operand address */
1786 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1787
1788 /* Multiply r1+1 by n and place result in r1 and r1+1 */
1789 mul_signed (&(regs->GR_L(r1)), &(regs->GR_L(r1+1)),
1790 regs->GR_L(r1+1),
1791 n);
1792
1793 } /* end DEF_INST(multiply_y) */
1794
1795
1796 /*-------------------------------------------------------------------*/
1797 /* E336 PFD - Prefetch Data [RXY] */
1798 /*-------------------------------------------------------------------*/
DEF_INST(prefetch_data)1799 DEF_INST(prefetch_data)
1800 {
1801 int m1; /* Mask value */
1802 int b2; /* Base of effective addr */
1803 VADR effective_addr2; /* Effective address */
1804
1805 RXY(inst, regs, m1, b2, effective_addr2);
1806
1807 /* The Prefetch Data instruction acts as a no-op */
1808
1809 } /* end DEF_INST(prefetch_data) */
1810
1811
1812 /*-------------------------------------------------------------------*/
1813 /* C6x2 PFDRL - Prefetch Data Relative Long [RIL] */
1814 /*-------------------------------------------------------------------*/
DEF_INST(prefetch_data_relative_long)1815 DEF_INST(prefetch_data_relative_long)
1816 {
1817 int m1; /* Mask value */
1818 VADR addr2; /* Relative operand address */
1819
1820 RIL_A(inst, regs, m1, addr2);
1821
1822 /* The Prefetch Data instruction acts as a no-op */
1823
1824 } /* end DEF_INST(prefetch_data_relative_long) */
1825
1826 #endif /*defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY)*/
1827
1828 #if defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY) \
1829 || defined(FEATURE_MISC_INSTRUCTION_EXTENSIONS_FACILITY) /*912*/ \
1830 || defined(FEATURE_HIGH_WORD_FACILITY) /*810*/
1831 /*-------------------------------------------------------------------*/
1832 /* Rotate Then Perform Operation On Selected Bits Long Register */
1833 /* Subroutine is called by RNSBG,RISBG,ROSBG,RXSBG instructions */
1834 /* and also by the RISBHG,RISBLG instructions */ /*810*/
1835 /* and by the RISBGN instruction */ /*912*/
1836 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_xxx_selected_bits_long_reg)1837 DEF_INST(rotate_then_xxx_selected_bits_long_reg)
1838 {
1839 int r1, r2; /* Register numbers */
1840 int start, end; /* Start and end bit number */
1841 U64 mask, rota, resu; /* 64-bit work areas */
1842 int n; /* Number of bits to shift */
1843 int t_bit = 0; /* Test-results indicator */
1844 int z_bit = 0; /* Zero-remaining indicator */
1845 int i; /* Loop counter */
1846 BYTE i3, i4, i5; /* Immediate values */
1847 BYTE opcode; /* 2nd byte of opcode */
1848
1849 RIE_RRIII(inst, regs, r1, r2, i3, i4, i5);
1850
1851 /* Extract second byte of instruction opcode */
1852 opcode = inst[5];
1853
1854 /* Extract parameters from immediate fields */
1855 start = i3 & 0x3F;
1856 end = i4 & 0x3F;
1857 n = i5 & 0x3F;
1858 if ((opcode & 0xFC) == 0x50 /*Low*/ ) { /*810*/
1859 start |= 0x20; /*810*/
1860 end |= 0x20; /*810*/
1861 } /*810*/
1862 if ((opcode & 0xFC) == 0x5C /*High*/ ) { /*810*/
1863 start &= 0x1F; /*810*/
1864 end &= 0x1F; /*810*/
1865 } /*810*/
1866 if ((opcode & 0x03) == 0x01 /*Insert*/ ) /*810*/
1867 z_bit = i4 >> 7;
1868 else
1869 t_bit = i3 >> 7;
1870
1871 /* Copy value from R2 register and rotate left n bits */
1872 rota = (regs->GR_G(r2) << n)
1873 | ((n == 0) ? 0 : (regs->GR_G(r2) >> (64 - n)));
1874
1875 /* Construct mask for selected bits */
1876 for (i=0, mask=0; i < 64; i++)
1877 {
1878 mask <<= 1;
1879 if (start <= end) {
1880 if (i >= start && i <= end) mask |= 1;
1881 } else {
1882 if (i <= end || i >= start) mask |= 1;
1883 }
1884 } /* end for(i) */
1885
1886 /* Isolate selected bits of rotated second operand */
1887 rota &= mask;
1888
1889 /* Isolate selected bits of first operand */
1890 resu = regs->GR_G(r1) & mask;
1891
1892 /* Perform operation on selected bits */
1893 switch (opcode) {
1894 case 0x54: /* And */
1895 resu &= rota;
1896 break;
1897 case 0x51: /* Insert Low */ /*810*/
1898 case 0x55: /* Insert */
1899 case 0x5D: /* Insert High */ /*810*/
1900 resu = rota;
1901 break;
1902 case 0x56: /* Or */
1903 resu |= rota;
1904 break;
1905 case 0x57: /* Exclusive Or */
1906 resu ^= rota;
1907 break;
1908 } /* end switch(opcode) */
1909
1910 /* And/Or/Xor set condition code according to result bits*/ /*810*/
1911 if ((opcode & 0x03) != 0x01 /*Insert*/ ) /*810*/
1912 regs->psw.cc = (resu == 0) ? 0 : 1;
1913
1914 /* Insert result bits into R1 register */
1915 if (t_bit == 0)
1916 {
1917 if (z_bit == 0)
1918 regs->GR_G(r1) = (regs->GR_G(r1) & ~mask) | resu;
1919 else if ((opcode & 0xFC) == 0x50 /*Low*/ ) /*810*/
1920 regs->GR_L(r1) = (U32)resu; /*810*/
1921 else if ((opcode & 0xFC) == 0x5C /*High*/ ) /*810*/
1922 regs->GR_H(r1) = (U32)(resu >> 32); /*810*/
1923 else
1924 regs->GR_G(r1) = resu;
1925 } /* end if(t_bit==0) */
1926
1927 /* For RISBG set condition code according to signed result */
1928 if (opcode == 0x55)
1929 regs->psw.cc =
1930 (S64)regs->GR_G(r1) < 0 ? 1 :
1931 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
1932
1933 /* For RISBHG,RISBLG the condition code remains unchanged*/ /*810*/
1934 /* For RISBGN the condition code remains unchanged */ /*912*/
1935
1936 } /* end DEF_INST(rotate_then_xxx_selected_bits_long_reg) */
1937 #endif /*defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY)*/
1938 /*|| defined(FEATURE_MISC_INSTRUCTION_EXTENSIONS_FACILITY)*/ /*912*/
1939 /*|| defined(FEATURE_HIGH_WORD_FACILITY)*/ /*810*/
1940
1941 #if defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY)
1942
1943 #if defined(FEATURE_ESAME)
1944 /*-------------------------------------------------------------------*/
1945 /* EC54 RNSBG - Rotate Then And Selected Bits [RIE] */
1946 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_and_selected_bits_long_reg)1947 DEF_INST(rotate_then_and_selected_bits_long_reg)
1948 {
1949 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
1950 } /* end DEF_INST(rotate_then_and_selected_bits_long_reg) */
1951
1952
1953 /*-------------------------------------------------------------------*/
1954 /* EC55 RISBG - Rotate Then Insert Selected Bits [RIE] */
1955 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_insert_selected_bits_long_reg)1956 DEF_INST(rotate_then_insert_selected_bits_long_reg)
1957 {
1958 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
1959 } /* end DEF_INST(rotate_then_insert_selected_bits_long_reg) */
1960
1961
1962 /*-------------------------------------------------------------------*/
1963 /* EC56 ROSBG - Rotate Then Or Selected Bits [RIE] */
1964 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_or_selected_bits_long_reg)1965 DEF_INST(rotate_then_or_selected_bits_long_reg)
1966 {
1967 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
1968 } /* end DEF_INST(rotate_then_or_selected_bits_long_reg) */
1969
1970
1971 /*-------------------------------------------------------------------*/
1972 /* EC57 RXSBG - Rotate Then Exclusive Or Selected Bits [RIE] */
1973 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_exclusive_or_selected_bits_long_reg)1974 DEF_INST(rotate_then_exclusive_or_selected_bits_long_reg)
1975 {
1976 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
1977 } /* end DEF_INST(rotate_then_exclusive_or_selected_bits_long_reg) */
1978 #endif /*defined(FEATURE_ESAME)*/
1979
1980
1981 /*-------------------------------------------------------------------*/
1982 /* C4x7 STHRL - Store Halfword Relative Long [RIL] */
1983 /*-------------------------------------------------------------------*/
DEF_INST(store_halfword_relative_long)1984 DEF_INST(store_halfword_relative_long)
1985 {
1986 int r1; /* Register number */
1987 VADR addr2; /* Relative operand address */
1988
1989 RIL_A(inst, regs, r1, addr2);
1990
1991 /* Store low 2 bytes of R1 register in instruction address space */
1992 ARCH_DEP(vstore2) ( regs->GR_LHL(r1), addr2, USE_INST_SPACE, regs );
1993
1994 } /* end DEF_INST(store_halfword_relative_long) */
1995
1996
1997 /*-------------------------------------------------------------------*/
1998 /* C4xF STRL - Store Relative Long [RIL] */
1999 /*-------------------------------------------------------------------*/
DEF_INST(store_relative_long)2000 DEF_INST(store_relative_long)
2001 {
2002 int r1; /* Register number */
2003 VADR addr2; /* Relative operand address */
2004
2005 RIL_A(inst, regs, r1, addr2);
2006
2007 /* Program check if operand not on fullword boundary */
2008 FW_CHECK(addr2, regs);
2009
2010 /* Store low 4 bytes of R1 register in instruction address space */
2011 ARCH_DEP(vstore4) ( regs->GR_L(r1), addr2, USE_INST_SPACE, regs );
2012
2013 } /* end DEF_INST(store_relative_long) */
2014
2015
2016 /*-------------------------------------------------------------------*/
2017 /* C4xB STGRL - Store Relative Long Long [RIL] */
2018 /*-------------------------------------------------------------------*/
DEF_INST(store_relative_long_long)2019 DEF_INST(store_relative_long_long)
2020 {
2021 int r1; /* Register number */
2022 VADR addr2; /* Relative operand address */
2023
2024 RIL_A(inst, regs, r1, addr2);
2025
2026 /* Program check if operand not on doubleword boundary */
2027 DW_CHECK(addr2, regs);
2028
2029 /* Store R1 register in instruction address space */
2030 ARCH_DEP(vstore8) ( regs->GR_G(r1), addr2, USE_INST_SPACE, regs );
2031
2032 } /* end DEF_INST(store_relative_long_long) */
2033
2034 #endif /*defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY)*/
2035
2036
2037 #if defined(FEATURE_HIGH_WORD_FACILITY) /*810*/
2038
2039 /*-------------------------------------------------------------------*/
2040 /* B9C8 AHHHR - Add High High High Register [RRR] */
2041 /*-------------------------------------------------------------------*/
DEF_INST(add_high_high_high_register)2042 DEF_INST(add_high_high_high_register) /*810*/
2043 {
2044 int r1, r2, r3; /* Values of R fields */
2045
2046 RRR(inst, regs, r1, r2, r3);
2047
2048 /* Add signed operands and set condition code */
2049 regs->psw.cc =
2050 add_signed (&(regs->GR_H(r1)),
2051 regs->GR_H(r2),
2052 regs->GR_H(r3));
2053
2054 /* Program check if fixed-point overflow */
2055 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2056 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2057
2058 } /* end DEF_INST(add_high_high_high_register) */
2059
2060
2061 /*-------------------------------------------------------------------*/
2062 /* B9D8 AHHLR - Add High High Low Register [RRR] */
2063 /*-------------------------------------------------------------------*/
DEF_INST(add_high_high_low_register)2064 DEF_INST(add_high_high_low_register) /*810*/
2065 {
2066 int r1, r2, r3; /* Values of R fields */
2067
2068 RRR(inst, regs, r1, r2, r3);
2069
2070 /* Add signed operands and set condition code */
2071 regs->psw.cc =
2072 add_signed (&(regs->GR_H(r1)),
2073 regs->GR_H(r2),
2074 regs->GR_L(r3));
2075
2076 /* Program check if fixed-point overflow */
2077 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2078 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2079
2080 } /* end DEF_INST(add_high_high_low_register) */
2081
2082 /*-------------------------------------------------------------------*/
2083 /* CCx8 AIH - Add High Immediate [RIL] */
2084 /*-------------------------------------------------------------------*/
DEF_INST(add_high_immediate)2085 DEF_INST(add_high_immediate) /*810*/
2086 {
2087 int r1; /* Register number */
2088 int opcd; /* Opcode */
2089 U32 i2; /* 32-bit operand value */
2090
2091 RIL(inst, regs, r1, opcd, i2);
2092
2093 /* Add signed operands and set condition code */
2094 regs->psw.cc = add_signed (&(regs->GR_H(r1)),
2095 regs->GR_H(r1),
2096 (S32)i2);
2097
2098 /* Program check if fixed-point overflow */
2099 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2100 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2101
2102 } /* end DEF_INST(add_high_immediate) */
2103
2104
2105 /*-------------------------------------------------------------------*/
2106 /* B9CA ALHHHR - Add Logical High High High Register [RRR] */
2107 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_high_high_high_register)2108 DEF_INST(add_logical_high_high_high_register) /*810*/
2109 {
2110 int r1, r2, r3; /* Values of R fields */
2111
2112 RRR0(inst, regs, r1, r2, r3);
2113
2114 /* Add signed operands and set condition code */
2115 regs->psw.cc = add_logical (&(regs->GR_H(r1)),
2116 regs->GR_H(r2),
2117 regs->GR_H(r3));
2118
2119 } /* end DEF_INST(add_logical_high_high_high_register) */
2120
2121
2122 /*-------------------------------------------------------------------*/
2123 /* B9DA ALHHLR - Add Logical High High Low Register [RRR] */
2124 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_high_high_low_register)2125 DEF_INST(add_logical_high_high_low_register) /*810*/
2126 {
2127 int r1, r2, r3; /* Values of R fields */
2128
2129 RRR0(inst, regs, r1, r2, r3);
2130
2131 /* Add signed operands and set condition code */
2132 regs->psw.cc = add_logical (&(regs->GR_H(r1)),
2133 regs->GR_H(r2),
2134 regs->GR_L(r3));
2135
2136 } /* end DEF_INST(add_logical_high_high_low_register) */
2137
2138
2139 /*-------------------------------------------------------------------*/
2140 /* CCxA ALSIH - Add Logical with Signed Immediate High [RIL] */
2141 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_with_signed_immediate_high)2142 DEF_INST(add_logical_with_signed_immediate_high) /*810*/
2143 {
2144 int r1; /* Register number */
2145 int opcd; /* Opcode */
2146 U32 i2; /* 32-bit operand value */
2147
2148 RIL0(inst, regs, r1, opcd, i2);
2149
2150 /* Add operands and set condition code */
2151 regs->psw.cc = (S32)i2 < 0 ?
2152 sub_logical (&(regs->GR_H(r1)), regs->GR_H(r1), -(S32)i2) :
2153 add_logical (&(regs->GR_H(r1)), regs->GR_H(r1), i2);
2154
2155 } /* end DEF_INST(add_logical_with_signed_immediate_high) */
2156
2157
2158 /*-------------------------------------------------------------------*/
2159 /* CCxB ALSIHN - Add Logical with Signed Immediate High No CC [RIL] */
2160 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_with_signed_immediate_high_n)2161 DEF_INST(add_logical_with_signed_immediate_high_n) /*810*/
2162 {
2163 int r1; /* Register number */
2164 int opcd; /* Opcode */
2165 U32 i2; /* 32-bit operand value */
2166
2167 RIL0(inst, regs, r1, opcd, i2);
2168
2169 /* Add operands without setting condition code */
2170 if ((S32)i2 < 0) {
2171 sub_logical (&(regs->GR_H(r1)), regs->GR_H(r1), -(S32)i2);
2172 } else {
2173 add_logical (&(regs->GR_H(r1)), regs->GR_H(r1), i2);
2174 }
2175
2176 } /* end DEF_INST(add_logical_with_signed_immediate_high_n) */
2177
2178
2179 /*-------------------------------------------------------------------*/
2180 /* CCx6 BRCTH - Branch Relative on Count High [RIL] */
2181 /*-------------------------------------------------------------------*/
DEF_INST(branch_relative_on_count_high)2182 DEF_INST(branch_relative_on_count_high) /*810*/
2183 {
2184 int r1; /* Register number */
2185 int opcd; /* Opcode */
2186 S32 i2; /* 32-bit operand value */
2187
2188 RIL_B(inst, regs, r1, opcd, i2);
2189
2190 /* Subtract 1 from the R1 operand and branch if non-zero */
2191 if ( --(regs->GR_H(r1)) )
2192 SUCCESSFUL_RELATIVE_BRANCH_LONG(regs, 2LL*i2);
2193 else
2194 INST_UPDATE_PSW(regs, 6, 0);
2195
2196 } /* end DEF_INST(branch_relative_on_count_high) */
2197
2198
2199 /*-------------------------------------------------------------------*/
2200 /* B9CD CHHR - Compare High High Register [RRE] */
2201 /*-------------------------------------------------------------------*/
DEF_INST(compare_high_high_register)2202 DEF_INST(compare_high_high_register) /*810*/
2203 {
2204 int r1, r2; /* Values of R fields */
2205
2206 RRE0(inst, regs, r1, r2);
2207
2208 /* Compare signed operands and set condition code */
2209 regs->psw.cc =
2210 (S32)regs->GR_H(r1) < (S32)regs->GR_H(r2) ? 1 :
2211 (S32)regs->GR_H(r1) > (S32)regs->GR_H(r2) ? 2 : 0;
2212
2213 } /* DEF_INST(compare_high_high_register) */
2214
2215
2216 /*-------------------------------------------------------------------*/
2217 /* B9DD CHLR - Compare High Low Register [RRE] */
2218 /*-------------------------------------------------------------------*/
DEF_INST(compare_high_low_register)2219 DEF_INST(compare_high_low_register) /*810*/
2220 {
2221 int r1, r2; /* Values of R fields */
2222
2223 RRE0(inst, regs, r1, r2);
2224
2225 /* Compare signed operands and set condition code */
2226 regs->psw.cc =
2227 (S32)regs->GR_H(r1) < (S32)regs->GR_L(r2) ? 1 :
2228 (S32)regs->GR_H(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
2229
2230 } /* DEF_INST(compare_high_low_register) */
2231
2232
2233 /*-------------------------------------------------------------------*/
2234 /* E3CD CHF - Compare High Fullword [RXY] */
2235 /*-------------------------------------------------------------------*/
DEF_INST(compare_high_fullword)2236 DEF_INST(compare_high_fullword) /*810*/
2237 {
2238 int r1; /* Values of R fields */
2239 int b2; /* Base of effective addr */
2240 VADR effective_addr2; /* Effective address */
2241 U32 n; /* 32-bit operand values */
2242
2243 RXY(inst, regs, r1, b2, effective_addr2);
2244
2245 /* Load second operand from operand address */
2246 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2247
2248 /* Compare signed operands and set condition code */
2249 regs->psw.cc =
2250 (S32)regs->GR_H(r1) < (S32)n ? 1 :
2251 (S32)regs->GR_H(r1) > (S32)n ? 2 : 0;
2252
2253 } /* DEF_INST(compare_high_fullword) */
2254
2255
2256 /*-------------------------------------------------------------------*/
2257 /* CCxD CIH - Compare High Immediate [RIL] */
2258 /*-------------------------------------------------------------------*/
DEF_INST(compare_high_immediate)2259 DEF_INST(compare_high_immediate) /*810*/
2260 {
2261 int r1; /* Register number */
2262 int opcd; /* Opcode */
2263 U32 i2; /* 32-bit operand value */
2264
2265 RIL0(inst, regs, r1, opcd, i2);
2266
2267 /* Compare signed operands and set condition code */
2268 regs->psw.cc = (S32)regs->GR_H(r1) < (S32)i2 ? 1 :
2269 (S32)regs->GR_H(r1) > (S32)i2 ? 2 : 0;
2270
2271 } /* end DEF_INST(compare_high_immediate) */
2272
2273
2274 /*-------------------------------------------------------------------*/
2275 /* B9CF CLHHR - Compare Logical High High Register [RRE] */
2276 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_high_high_register)2277 DEF_INST(compare_logical_high_high_register) /*810*/
2278 {
2279 int r1, r2; /* Values of R fields */
2280
2281 RRE0(inst, regs, r1, r2);
2282
2283 /* Compare unsigned operands and set condition code */
2284 regs->psw.cc = regs->GR_H(r1) < regs->GR_H(r2) ? 1 :
2285 regs->GR_H(r1) > regs->GR_H(r2) ? 2 : 0;
2286
2287 } /* end DEF_INST(compare_logical_high_high_register) */
2288
2289
2290 /*-------------------------------------------------------------------*/
2291 /* B9DF CLHLR - Compare Logical High Low Register [RRE] */
2292 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_high_low_register)2293 DEF_INST(compare_logical_high_low_register) /*810*/
2294 {
2295 int r1, r2; /* Values of R fields */
2296
2297 RRE0(inst, regs, r1, r2);
2298
2299 /* Compare unsigned operands and set condition code */
2300 regs->psw.cc = regs->GR_H(r1) < regs->GR_L(r2) ? 1 :
2301 regs->GR_H(r1) > regs->GR_L(r2) ? 2 : 0;
2302
2303 } /* end DEF_INST(compare_logical_high_low_register) */
2304
2305
2306 /*-------------------------------------------------------------------*/
2307 /* E3CF CLHF - Compare Logical High Fullword [RXY] */
2308 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_high_fullword)2309 DEF_INST(compare_logical_high_fullword) /*810*/
2310 {
2311 int r1; /* Values of R fields */
2312 int b2; /* Base of effective addr */
2313 VADR effective_addr2; /* Effective address */
2314 U32 n; /* 32-bit operand values */
2315
2316 RXY(inst, regs, r1, b2, effective_addr2);
2317
2318 /* Load second operand from operand address */
2319 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2320
2321 /* Compare unsigned operands and set condition code */
2322 regs->psw.cc = regs->GR_H(r1) < n ? 1 :
2323 regs->GR_H(r1) > n ? 2 : 0;
2324
2325 } /* end DEF_INST(compare_logical_high_fullword) */
2326
2327
2328 /*-------------------------------------------------------------------*/
2329 /* CCxF CLIH - Compare Logical High Immediate [RIL] */
2330 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_high_immediate)2331 DEF_INST(compare_logical_high_immediate) /*810*/
2332 {
2333 int r1; /* Register number */
2334 int opcd; /* Opcode */
2335 U32 i2; /* 32-bit operand value */
2336
2337 RIL0(inst, regs, r1, opcd, i2);
2338
2339 /* Compare unsigned operands and set condition code */
2340 regs->psw.cc = regs->GR_H(r1) < i2 ? 1 :
2341 regs->GR_H(r1) > i2 ? 2 : 0;
2342
2343 } /* end DEF_INST(compare_logical_high_immediate) */
2344
2345
2346 /*-------------------------------------------------------------------*/
2347 /* E3C0 LBH - Load Byte High [RXY] */
2348 /*-------------------------------------------------------------------*/
DEF_INST(load_byte_high)2349 DEF_INST(load_byte_high) /*810*/
2350 {
2351 int r1; /* Value of R field */
2352 int b2; /* Base of effective addr */
2353 VADR effective_addr2; /* Effective address */
2354
2355 RXY(inst, regs, r1, b2, effective_addr2);
2356
2357 /* Load sign-extended byte from operand address */
2358 regs->GR_H(r1) = (S8)ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
2359
2360 } /* end DEF_INST(load_byte_high) */
2361
2362
2363 /*-------------------------------------------------------------------*/
2364 /* E3CA LFH - Load Fullword High [RXY] */
2365 /*-------------------------------------------------------------------*/
DEF_INST(load_fullword_high)2366 DEF_INST(load_fullword_high) /*810*/
2367 {
2368 int r1; /* Value of R field */
2369 int b2; /* Base of effective addr */
2370 VADR effective_addr2; /* Effective address */
2371
2372 RXY(inst, regs, r1, b2, effective_addr2);
2373
2374 /* Load R1 register bits 0-31 from second operand */
2375 regs->GR_H(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2376
2377 } /* end DEF_INST(load_fullword_high) */
2378
2379
2380 /*-------------------------------------------------------------------*/
2381 /* E3C4 LHH - Load Halfword High [RXY] */
2382 /*-------------------------------------------------------------------*/
DEF_INST(load_halfword_high)2383 DEF_INST(load_halfword_high) /*810*/
2384 {
2385 int r1; /* Value of R field */
2386 int b2; /* Base of effective addr */
2387 VADR effective_addr2; /* Effective address */
2388
2389 RXY(inst, regs, r1, b2, effective_addr2);
2390
2391 /* Load sign-extended halfword from operand address */
2392 regs->GR_H(r1) = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
2393
2394 } /* end DEF_INST(load_halfword_high) */
2395
2396
2397 /*-------------------------------------------------------------------*/
2398 /* E3C2 LLCH - Load Logical Character High [RXY] */
2399 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_character_high)2400 DEF_INST(load_logical_character_high) /*810*/
2401 {
2402 int r1; /* Value of R field */
2403 int b2; /* Base of effective addr */
2404 VADR effective_addr2; /* Effective address */
2405
2406 RXY(inst, regs, r1, b2, effective_addr2);
2407
2408 /* Load byte into R1 register bits 24-31 and clear bits 0-23 */
2409 regs->GR_H(r1) = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
2410
2411 } /* end DEF_INST(load_logical_character_high) */
2412
2413
2414 /*-------------------------------------------------------------------*/
2415 /* E3C6 LLHH - Load Logical Halfword High [RXY] */
2416 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_halfword_high)2417 DEF_INST(load_logical_halfword_high) /*810*/
2418 {
2419 int r1; /* Value of R field */
2420 int b2; /* Base of effective addr */
2421 VADR effective_addr2; /* Effective address */
2422
2423 RXY(inst, regs, r1, b2, effective_addr2);
2424
2425 /* Load halfword into R1 register bits 16-31 and clear bits 0-15 */
2426 regs->GR_H(r1) = ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
2427
2428 } /* end DEF_INST(load_logical_halfword_high) */
2429
2430
2431 /*-------------------------------------------------------------------*/
2432 /* EC5D RISBHG - Rotate Then Insert Selected Bits High [RIE] */
2433 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_insert_selected_bits_high_long_reg)2434 DEF_INST(rotate_then_insert_selected_bits_high_long_reg) /*810*/
2435 {
2436 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
2437 } /* end DEF_INST(rotate_then_insert_selected_bits_high_long_reg) */
2438
2439
2440 /*-------------------------------------------------------------------*/
2441 /* EC51 RISBLG - Rotate Then Insert Selected Bits Low [RIE] */
2442 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_insert_selected_bits_low_long_reg)2443 DEF_INST(rotate_then_insert_selected_bits_low_long_reg) /*810*/
2444 {
2445 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
2446 } /* end DEF_INST(rotate_then_insert_selected_bits_low_long_reg) */
2447
2448
2449 /*-------------------------------------------------------------------*/
2450 /* E3C3 STCH - Store Character High [RXY] */
2451 /*-------------------------------------------------------------------*/
DEF_INST(store_character_high)2452 DEF_INST(store_character_high) /*810*/
2453 {
2454 int r1; /* Value of R field */
2455 int b2; /* Base of effective addr */
2456 VADR effective_addr2; /* Effective address */
2457
2458 RXY(inst, regs, r1, b2, effective_addr2);
2459
2460 /* Store bits 24-31 of R1 register at operand address */
2461 ARCH_DEP(vstoreb) ( regs->GR_HHLCL(r1), effective_addr2, b2, regs );
2462
2463 } /* end DEF_INST(store_character_high) */
2464
2465
2466 /*-------------------------------------------------------------------*/
2467 /* E3CB STFH - Store Fullword High [RXY] */
2468 /*-------------------------------------------------------------------*/
DEF_INST(store_fullword_high)2469 DEF_INST(store_fullword_high) /*810*/
2470 {
2471 int r1; /* Values of R fields */
2472 int b2; /* Base of effective addr */
2473 VADR effective_addr2; /* Effective address */
2474
2475 RXY(inst, regs, r1, b2, effective_addr2);
2476
2477 /* Store bits 0-31 of R1 register at operand address */
2478 ARCH_DEP(vstore4) ( regs->GR_H(r1), effective_addr2, b2, regs );
2479
2480 } /* end DEF_INST(store_fullword_high) */
2481
2482
2483 /*-------------------------------------------------------------------*/
2484 /* E3C7 STHH - Store Halfword High [RXY] */
2485 /*-------------------------------------------------------------------*/
DEF_INST(store_halfword_high)2486 DEF_INST(store_halfword_high) /*810*/
2487 {
2488 int r1; /* Value of R field */
2489 int b2; /* Base of effective addr */
2490 VADR effective_addr2; /* Effective address */
2491
2492 RXY(inst, regs, r1, b2, effective_addr2);
2493
2494 /* Store bits 16-31 of R1 register at operand address */
2495 ARCH_DEP(vstore2) ( regs->GR_HHL(r1), effective_addr2, b2, regs );
2496
2497 } /* end DEF_INST(store_halfword_high) */
2498
2499
2500 /*-------------------------------------------------------------------*/
2501 /* B9C9 SHHHR - Subtract High High High Register [RRR] */
2502 /*-------------------------------------------------------------------*/
DEF_INST(subtract_high_high_high_register)2503 DEF_INST(subtract_high_high_high_register) /*810*/
2504 {
2505 int r1, r2, r3; /* Values of R fields */
2506
2507 RRR(inst, regs, r1, r2, r3);
2508
2509 /* Subtract signed operands and set condition code */
2510 regs->psw.cc = sub_signed (&(regs->GR_H(r1)),
2511 regs->GR_H(r2),
2512 regs->GR_H(r3));
2513
2514 /* Program check if fixed-point overflow */
2515 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2516 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2517
2518 } /* end DEF_INST(subtract_high_high_high_register) */
2519
2520
2521 /*-------------------------------------------------------------------*/
2522 /* B9D9 SHHLR - Subtract High High Low Register [RRR] */
2523 /*-------------------------------------------------------------------*/
DEF_INST(subtract_high_high_low_register)2524 DEF_INST(subtract_high_high_low_register) /*810*/
2525 {
2526 int r1, r2, r3; /* Values of R fields */
2527
2528 RRR(inst, regs, r1, r2, r3);
2529
2530 /* Subtract signed operands and set condition code */
2531 regs->psw.cc = sub_signed (&(regs->GR_H(r1)),
2532 regs->GR_H(r2),
2533 regs->GR_L(r3));
2534
2535 /* Program check if fixed-point overflow */
2536 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2537 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2538
2539 } /* end DEF_INST(subtract_high_high_low_register) */
2540
2541
2542 /*-------------------------------------------------------------------*/
2543 /* B9CB SLHHHR - Subtract Logical High High High Register [RRR] */
2544 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_high_high_high_register)2545 DEF_INST(subtract_logical_high_high_high_register) /*810*/
2546 {
2547 int r1, r2, r3; /* Values of R fields */
2548
2549 RRR0(inst, regs, r1, r2, r3);
2550
2551 /* Subtract unsigned operands and set condition code */
2552 regs->psw.cc = sub_logical (&(regs->GR_H(r1)),
2553 regs->GR_H(r2),
2554 regs->GR_H(r3));
2555
2556 } /* end DEF_INST(subtract_logical_high_high_high_register) */
2557
2558
2559 /*-------------------------------------------------------------------*/
2560 /* B9DB SLHHLR - Subtract Logical High High Low Register [RRR] */
2561 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_high_high_low_register)2562 DEF_INST(subtract_logical_high_high_low_register) /*810*/
2563 {
2564 int r1, r2, r3; /* Values of R fields */
2565
2566 RRR0(inst, regs, r1, r2, r3);
2567
2568 /* Subtract unsigned operands and set condition code */
2569 regs->psw.cc = sub_logical (&(regs->GR_H(r1)),
2570 regs->GR_H(r2),
2571 regs->GR_L(r3));
2572
2573 } /* end DEF_INST(subtract_logical_high_high_low_register) */
2574
2575 #endif /*defined(FEATURE_HIGH_WORD_FACILITY)*/ /*810*/
2576
2577
2578 #if defined(FEATURE_INTERLOCKED_ACCESS_FACILITY) /*810*/
2579
2580 /*-------------------------------------------------------------------*/
2581 /* Load and Perform Interlocked Access Operation */
2582 /* Subroutine called by LAA,LAAL,LAN,LAX,LAO instructions */
2583 /*-------------------------------------------------------------------*/
DEF_INST(load_and_perform_interlocked_access)2584 DEF_INST(load_and_perform_interlocked_access) /*810*/
2585 {
2586 int r1, r3; /* Register numbers */
2587 int b2; /* Base of effective addr */
2588 VADR addr2; /* Effective address */
2589 BYTE *m2; /* Mainstor address */
2590 U32 v2, v3; /* Operand values */
2591 U32 result; /* Result value */
2592 U32 old, new; /* Values for cmpxchg4 */
2593 int cc; /* Condition code */
2594 int rc; /* Return code */
2595 BYTE opcode; /* 2nd byte of opcode */
2596
2597 RSY(inst, regs, r1, r3, b2, addr2);
2598
2599 /* Extract second byte of instruction opcode */
2600 opcode = inst[5];
2601
2602 /* Obtain third operand value from R3 register */
2603 v3 = regs->GR_L(r3);
2604
2605 /* Get mainstor address of storage operand */
2606 m2 = MADDRL (addr2, 4, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
2607
2608 do {
2609 /* Load storage operand value from operand address */
2610 v2 = ARCH_DEP(vfetch4) ( addr2, b2, regs );
2611
2612 switch (opcode) {
2613 case 0xF4: /* Load and And */
2614 /* AND operand values and set condition code */
2615 result = v2 & v3;
2616 cc = result ? 1 : 0;
2617 break;
2618 case 0xF6: /* Load and Or */
2619 /* OR operand values and set condition code */
2620 result = v2 | v3;
2621 cc = result ? 1 : 0;
2622 break;
2623 case 0xF7: /* Load and Exclusive Or */
2624 /* XOR operand values and set condition code */
2625 result = v2 ^ v3;
2626 cc = result ? 1 : 0;
2627 break;
2628 case 0xF8: /* Load and Add */
2629 /* Add signed operands and set condition code */
2630 cc = add_signed (&result, v2, v3);
2631 break;
2632 case 0xFA: /* Load and Add Logical */
2633 /* Add unsigned operands and set condition code */
2634 cc = add_logical (&result, v2, v3);
2635 break;
2636 default: /* To prevent compiler warnings */
2637 result = 0;
2638 cc = 0;
2639 } /* end switch(opcode) */
2640
2641 /* Interlocked exchange to storage location */
2642 old = CSWAP32(v2);
2643 new = CSWAP32(result);
2644 rc = cmpxchg4 (&old, new, m2);
2645
2646 } while (rc != 0);
2647
2648 /* Load original storage operand value into R1 register */
2649 regs->GR_L(r1) = v2;
2650
2651 /* Set condition code in PSW */
2652 regs->psw.cc = cc;
2653
2654 } /* end DEF_INST(load_and_perform_interlocked_access) */
2655
2656 /*-------------------------------------------------------------------*/
2657 /* Load and Perform Interlocked Access Operation Long */
2658 /* Subroutine called by LAAG,LAALG,LANG,LAXG,LAOG instructions */
2659 /*-------------------------------------------------------------------*/
DEF_INST(load_and_perform_interlocked_access_long)2660 DEF_INST(load_and_perform_interlocked_access_long) /*810*/
2661 {
2662 int r1, r3; /* Register numbers */
2663 int b2; /* Base of effective addr */
2664 VADR addr2; /* Effective address */
2665 BYTE *m2; /* Mainstor address */
2666 U64 v2, v3; /* Operand values */
2667 U64 result; /* Result value */
2668 U64 old, new; /* Values for cmpxchg4 */
2669 int cc; /* Condition code */
2670 int rc; /* Return code */
2671 BYTE opcode; /* 2nd byte of opcode */
2672
2673 RSY(inst, regs, r1, r3, b2, addr2);
2674
2675 /* Extract second byte of instruction opcode */
2676 opcode = inst[5];
2677
2678 /* Obtain third operand value from R3 register */
2679 v3 = regs->GR_G(r3);
2680
2681 /* Get mainstor address of storage operand */
2682 m2 = MADDRL (addr2, 8, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
2683
2684 do {
2685 /* Load storage operand value from operand address */
2686 v2 = ARCH_DEP(vfetch8) ( addr2, b2, regs );
2687
2688 switch (opcode) {
2689 case 0xE4: /* Load and And Long */
2690 /* AND operand values and set condition code */
2691 result = v2 & v3;
2692 cc = result ? 1 : 0;
2693 break;
2694 case 0xE6: /* Load and Or Long */
2695 /* OR operand values and set condition code */
2696 result = v2 | v3;
2697 cc = result ? 1 : 0;
2698 break;
2699 case 0xE7: /* Load and Exclusive Or Long */
2700 /* XOR operand values and set condition code */
2701 result = v2 ^ v3;
2702 cc = result ? 1 : 0;
2703 break;
2704 case 0xE8: /* Load and Add Long */
2705 /* Add signed operands and set condition code */
2706 cc = add_signed_long (&result, v2, v3);
2707 break;
2708 case 0xEA: /* Load and Add Logical Long */
2709 /* Add unsigned operands and set condition code */
2710 cc = add_logical_long (&result, v2, v3);
2711 break;
2712 default: /* To prevent compiler warnings */
2713 result = 0;
2714 cc = 0;
2715 } /* end switch(opcode) */
2716
2717 /* Interlocked exchange to storage location */
2718 old = CSWAP64(v2);
2719 new = CSWAP64(result);
2720 rc = cmpxchg8 (&old, new, m2);
2721
2722 } while (rc != 0);
2723
2724 /* Load original storage operand value into R1 register */
2725 regs->GR_G(r1) = v2;
2726
2727 /* Set condition code in PSW */
2728 regs->psw.cc = cc;
2729
2730 } /* end DEF_INST(load_and_perform_interlocked_access_long) */
2731
2732
2733 /*-------------------------------------------------------------------*/
2734 /* EBF8 LAA - Load and Add [RSY] */
2735 /*-------------------------------------------------------------------*/
DEF_INST(load_and_add)2736 DEF_INST(load_and_add) /*810*/
2737 {
2738 ARCH_DEP(load_and_perform_interlocked_access) (inst, regs);
2739
2740 /* Program check if fixed-point overflow */
2741 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2742 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2743
2744 } /* end DEF_INST(load_and_add) */
2745
2746
2747 /*-------------------------------------------------------------------*/
2748 /* EBE8 LAAG - Load and Add Long [RSY] */
2749 /*-------------------------------------------------------------------*/
DEF_INST(load_and_add_long)2750 DEF_INST(load_and_add_long) /*810*/
2751 {
2752 ARCH_DEP(load_and_perform_interlocked_access_long) (inst, regs);
2753
2754 /* Program check if fixed-point overflow */
2755 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2756 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2757
2758 } /* end DEF_INST(load_and_add_long) */
2759
2760
2761 /*-------------------------------------------------------------------*/
2762 /* EBFA LAAL - Load and Add Logical [RSY] */
2763 /*-------------------------------------------------------------------*/
DEF_INST(load_and_add_logical)2764 DEF_INST(load_and_add_logical) /*810*/
2765 {
2766 ARCH_DEP(load_and_perform_interlocked_access) (inst, regs);
2767 } /* end DEF_INST(load_and_add_logical) */
2768
2769
2770 /*-------------------------------------------------------------------*/
2771 /* EBEA LAALG - Load and Add Logical Long [RSY] */
2772 /*-------------------------------------------------------------------*/
DEF_INST(load_and_add_logical_long)2773 DEF_INST(load_and_add_logical_long) /*810*/
2774 {
2775 ARCH_DEP(load_and_perform_interlocked_access_long) (inst, regs);
2776 } /* end DEF_INST(load_and_add_logical_long) */
2777
2778
2779 /*-------------------------------------------------------------------*/
2780 /* EBF4 LAN - Load and And [RSY] */
2781 /*-------------------------------------------------------------------*/
DEF_INST(load_and_and)2782 DEF_INST(load_and_and) /*810*/
2783 {
2784 ARCH_DEP(load_and_perform_interlocked_access) (inst, regs);
2785 } /* end DEF_INST(load_and_and) */
2786
2787
2788 /*-------------------------------------------------------------------*/
2789 /* EBE4 LANG - Load and And Long [RSY] */
2790 /*-------------------------------------------------------------------*/
DEF_INST(load_and_and_long)2791 DEF_INST(load_and_and_long) /*810*/
2792 {
2793 ARCH_DEP(load_and_perform_interlocked_access_long) (inst, regs);
2794 } /* end DEF_INST(load_and_and_long) */
2795
2796
2797 /*-------------------------------------------------------------------*/
2798 /* EBF7 LAX - Load and Exclusive Or [RSY] */
2799 /*-------------------------------------------------------------------*/
DEF_INST(load_and_exclusive_or)2800 DEF_INST(load_and_exclusive_or) /*810*/
2801 {
2802 ARCH_DEP(load_and_perform_interlocked_access) (inst, regs);
2803 } /* end DEF_INST(load_and_exclusive_or) */
2804
2805
2806 /*-------------------------------------------------------------------*/
2807 /* EBE7 LAXG - Load and Exclusive Or Long [RSY] */
2808 /*-------------------------------------------------------------------*/
DEF_INST(load_and_exclusive_or_long)2809 DEF_INST(load_and_exclusive_or_long) /*810*/
2810 {
2811 ARCH_DEP(load_and_perform_interlocked_access_long) (inst, regs);
2812 } /* end DEF_INST(load_and_exclusive_or_long) */
2813
2814
2815 /*-------------------------------------------------------------------*/
2816 /* EBF6 LAO - Load and Or [RSY] */
2817 /*-------------------------------------------------------------------*/
DEF_INST(load_and_or)2818 DEF_INST(load_and_or) /*810*/
2819 {
2820 ARCH_DEP(load_and_perform_interlocked_access) (inst, regs);
2821 } /* end DEF_INST(load_and_or) */
2822
2823
2824 /*-------------------------------------------------------------------*/
2825 /* EBE6 LAOG - Load and Or Long [RSY] */
2826 /*-------------------------------------------------------------------*/
DEF_INST(load_and_or_long)2827 DEF_INST(load_and_or_long) /*810*/
2828 {
2829 ARCH_DEP(load_and_perform_interlocked_access_long) (inst, regs);
2830 } /* end DEF_INST(load_and_or_long) */
2831
2832
2833 /*-------------------------------------------------------------------*/
2834 /* C8x4 LPD - Load Pair Disjoint [SSF] */
2835 /*-------------------------------------------------------------------*/
DEF_INST(load_pair_disjoint)2836 DEF_INST(load_pair_disjoint) /*810*/
2837 {
2838 int r3; /* Register number */
2839 int b1, b2; /* Base register numbers */
2840 VADR effective_addr1,
2841 effective_addr2; /* Effective addresses */
2842 U32 v1, v2; /* Operand values */
2843 U32 w1, w2; /* Refetched values */
2844
2845 SSF(inst, regs, b1, effective_addr1, b2, effective_addr2, r3);
2846
2847 ODD_CHECK(r3, regs);
2848
2849 /* Fetch the values of the storage operands */
2850 v1 = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
2851 v2 = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2852
2853 /* Fetch operands again to check for alteration by another CPU */
2854 w1 = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
2855 w2 = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2856
2857 /* Load R3 register from first storage operand */
2858 regs->GR_L(r3) = v1;
2859
2860 /* Load R3+1 register from second storage operand */
2861 regs->GR_L(r3+1) = v2;
2862
2863 /* Set condition code 0 if operands unaltered, or 3 if altered */
2864 regs->psw.cc = (v1 == w1 && v2 == w2) ? 0 : 3;
2865
2866 } /* end DEF_INST(load_pair_disjoint) */
2867
2868
2869 /*-------------------------------------------------------------------*/
2870 /* C8x5 LPDG - Load Pair Disjoint Long [SSF] */
2871 /*-------------------------------------------------------------------*/
DEF_INST(load_pair_disjoint_long)2872 DEF_INST(load_pair_disjoint_long) /*810*/
2873 {
2874 int r3; /* Register number */
2875 int b1, b2; /* Base register numbers */
2876 VADR effective_addr1,
2877 effective_addr2; /* Effective addresses */
2878 U64 v1, v2; /* Operand values */
2879 U64 w1, w2; /* Refetched values */
2880
2881 SSF(inst, regs, b1, effective_addr1, b2, effective_addr2, r3);
2882
2883 ODD_CHECK(r3, regs);
2884
2885 /* Fetch the values of the storage operands */
2886 v1 = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
2887 v2 = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2888
2889 /* Fetch operands again to check for alteration by another CPU */
2890 w1 = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
2891 w2 = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2892
2893 /* Load R3 register from first storage operand */
2894 regs->GR_G(r3) = v1;
2895
2896 /* Load R3+1 register from second storage operand */
2897 regs->GR_G(r3+1) = v2;
2898
2899 /* Set condition code 0 if operands unaltered, or 3 if altered */
2900 regs->psw.cc = (v1 == w1 && v2 == w2) ? 0 : 3;
2901
2902 } /* end DEF_INST(load_pair_disjoint_long) */
2903
2904 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY)*/ /*810*/
2905
2906
2907 #if defined(FEATURE_LOAD_STORE_ON_CONDITION_FACILITY) /*810*/
2908
2909 /*-------------------------------------------------------------------*/
2910 /* B9F2 LOCR - Load on Condition Register [RRF] */
2911 /*-------------------------------------------------------------------*/
DEF_INST(load_on_condition_register)2912 DEF_INST(load_on_condition_register) /*810*/
2913 {
2914 int r1, r2; /* Values of R fields */
2915 int m3; /* Value of M field */
2916
2917 RRF_M(inst, regs, r1, r2, m3);
2918
2919 /* Test M3 mask bit corresponding to condition code */
2920 if (m3 & (0x8 >> regs->psw.cc))
2921 {
2922 /* Copy R2 register bits 32-63 to R1 register */
2923 regs->GR_L(r1) = regs->GR_L(r2);
2924 }
2925
2926 } /* end DEF_INST(load_on_condition_register) */
2927
2928
2929 #if defined(FEATURE_ESAME)
2930 /*-------------------------------------------------------------------*/
2931 /* B9E2 LOCGR - Load on Condition Long Register [RRF] */
2932 /*-------------------------------------------------------------------*/
DEF_INST(load_on_condition_long_register)2933 DEF_INST(load_on_condition_long_register) /*810*/
2934 {
2935 int r1, r2; /* Values of R fields */
2936 int m3; /* Value of M field */
2937
2938 RRF_M(inst, regs, r1, r2, m3);
2939
2940 /* Test M3 mask bit corresponding to condition code */
2941 if (m3 & (0x8 >> regs->psw.cc))
2942 {
2943 /* Copy R2 register bits 0-63 to R1 register */
2944 regs->GR_G(r1) = regs->GR_G(r2);
2945 }
2946
2947 } /* end DEF_INST(load_on_condition_long_register) */
2948 #endif /*defined(FEATURE_ESAME)*/
2949
2950
2951 /*-------------------------------------------------------------------*/
2952 /* EBF2 LOC - Load on Condition [RSY] */
2953 /*-------------------------------------------------------------------*/
DEF_INST(load_on_condition)2954 DEF_INST(load_on_condition) /*810*/
2955 {
2956 int r1; /* Value of R field */
2957 int m3; /* Value of M field */
2958 int b2; /* Base of effective addr */
2959 VADR effective_addr2; /* Effective address */
2960
2961 RSY(inst, regs, r1, m3, b2, effective_addr2);
2962
2963 /* Test M3 mask bit corresponding to condition code */
2964 if (m3 & (0x8 >> regs->psw.cc))
2965 {
2966 /* Load R1 register bits 32-63 from second operand */
2967 regs->GR_L(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2968 }
2969
2970 } /* end DEF_INST(load_on_condition) */
2971
2972
2973 #if defined(FEATURE_ESAME)
2974 /*-------------------------------------------------------------------*/
2975 /* EBE2 LOCG - Load on Condition Long [RSY] */
2976 /*-------------------------------------------------------------------*/
DEF_INST(load_on_condition_long)2977 DEF_INST(load_on_condition_long) /*810*/
2978 {
2979 int r1; /* Value of R field */
2980 int m3; /* Value of M field */
2981 int b2; /* Base of effective addr */
2982 VADR effective_addr2; /* Effective address */
2983
2984 RSY(inst, regs, r1, m3, b2, effective_addr2);
2985
2986 /* Test M3 mask bit corresponding to condition code */
2987 if (m3 & (0x8 >> regs->psw.cc))
2988 {
2989 /* Load R1 register bits 0-63 from second operand */
2990 regs->GR_G(r1) = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2991 }
2992
2993 } /* end DEF_INST(load_on_condition_long) */
2994 #endif /*defined(FEATURE_ESAME)*/
2995
2996
2997 /*-------------------------------------------------------------------*/
2998 /* EBF3 STOC - Store on Condition [RSY] */
2999 /*-------------------------------------------------------------------*/
DEF_INST(store_on_condition)3000 DEF_INST(store_on_condition) /*810*/
3001 {
3002 int r1; /* Value of R field */
3003 int m3; /* Value of M field */
3004 int b2; /* Base of effective addr */
3005 VADR effective_addr2; /* Effective address */
3006
3007 RSY(inst, regs, r1, m3, b2, effective_addr2);
3008
3009 /* Test M3 mask bit corresponding to condition code */
3010 if (m3 & (0x8 >> regs->psw.cc))
3011 {
3012 /* Store R1 register bits 32-63 at operand address */
3013 ARCH_DEP(vstore4) ( regs->GR_L(r1), effective_addr2, b2, regs );
3014 }
3015
3016 } /* end DEF_INST(store_on_condition) */
3017
3018
3019 #if defined(FEATURE_ESAME)
3020 /*-------------------------------------------------------------------*/
3021 /* EBE3 STOCG - Store on Condition Long [RSY] */
3022 /*-------------------------------------------------------------------*/
DEF_INST(store_on_condition_long)3023 DEF_INST(store_on_condition_long) /*810*/
3024 {
3025 int r1; /* Value of R field */
3026 int m3; /* Value of M field */
3027 int b2; /* Base of effective addr */
3028 VADR effective_addr2; /* Effective address */
3029
3030 RSY(inst, regs, r1, m3, b2, effective_addr2);
3031
3032 /* Test M3 mask bit corresponding to condition code */
3033 if (m3 & (0x8 >> regs->psw.cc))
3034 {
3035 /* Store R1 register bits 0-63 at operand address */
3036 ARCH_DEP(vstore8) ( regs->GR_G(r1), effective_addr2, b2, regs );
3037 }
3038
3039 } /* end DEF_INST(store_on_condition_long) */
3040 #endif /*defined(FEATURE_ESAME)*/
3041
3042 #endif /*defined(FEATURE_LOAD_STORE_ON_CONDITION_FACILITY)*/ /*810*/
3043
3044
3045 #if defined(FEATURE_DISTINCT_OPERANDS_FACILITY) /*810*/
3046
3047 /*-------------------------------------------------------------------*/
3048 /* B9F8 ARK - Add Distinct Register [RRR] */
3049 /*-------------------------------------------------------------------*/
DEF_INST(add_distinct_register)3050 DEF_INST(add_distinct_register) /*810*/
3051 {
3052 int r1, r2, r3; /* Values of R fields */
3053
3054 RRR(inst, regs, r1, r2, r3);
3055
3056 /* Add signed operands and set condition code */
3057 regs->psw.cc =
3058 add_signed (&(regs->GR_L(r1)),
3059 regs->GR_L(r2),
3060 regs->GR_L(r3));
3061
3062 /* Program check if fixed-point overflow */
3063 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3064 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3065
3066 } /* end DEF_INST(add_distinct_register) */
3067
3068
3069 #if defined(FEATURE_ESAME)
3070 /*-------------------------------------------------------------------*/
3071 /* B9E8 AGRK - Add Distinct Long Register [RRR] */
3072 /*-------------------------------------------------------------------*/
DEF_INST(add_distinct_long_register)3073 DEF_INST(add_distinct_long_register) /*810*/
3074 {
3075 int r1, r2, r3; /* Values of R fields */
3076
3077 RRR(inst, regs, r1, r2, r3);
3078
3079 /* Add signed operands and set condition code */
3080 regs->psw.cc = add_signed_long(&(regs->GR_G(r1)),
3081 regs->GR_G(r2),
3082 regs->GR_G(r3));
3083
3084 /* Program check if fixed-point overflow */
3085 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3086 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3087
3088 } /* end DEF_INST(add_distinct_long_register) */
3089 #endif /*defined(FEATURE_ESAME)*/
3090
3091
3092 /*-------------------------------------------------------------------*/
3093 /* ECD8 AHIK - Add Distinct Halfword Immediate [RIE] */
3094 /*-------------------------------------------------------------------*/
DEF_INST(add_distinct_halfword_immediate)3095 DEF_INST(add_distinct_halfword_immediate) /*810*/
3096 {
3097 int r1, r3; /* Values of R fields */
3098 U16 i2; /* 16-bit immediate operand */
3099
3100 RIE(inst, regs, r1, r3, i2);
3101
3102 /* Add signed operands and set condition code */
3103 regs->psw.cc = add_signed (&(regs->GR_L(r1)),
3104 (S16)i2,
3105 regs->GR_L(r3));
3106
3107 /* Program check if fixed-point overflow */
3108 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3109 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3110
3111 } /* end DEF_INST(add_distinct_halfword_immediate) */
3112
3113
3114 #if defined(FEATURE_ESAME)
3115 /*-------------------------------------------------------------------*/
3116 /* ECD9 AGHIK - Add Distinct Long Halfword Immediate [RIE] */
3117 /*-------------------------------------------------------------------*/
DEF_INST(add_distinct_long_halfword_immediate)3118 DEF_INST(add_distinct_long_halfword_immediate) /*810*/
3119 {
3120 int r1, r3; /* Values of R fields */
3121 U16 i2; /* 16-bit immediate operand */
3122
3123 RIE(inst, regs, r1, r3, i2);
3124
3125 /* Add signed operands and set condition code */
3126 regs->psw.cc = add_signed_long(&(regs->GR_G(r1)),
3127 (S16)i2,
3128 regs->GR_G(r3));
3129
3130 /* Program check if fixed-point overflow */
3131 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3132 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3133
3134 } /* end DEF_INST(add_distinct_long_halfword_immediate) */
3135 #endif /*defined(FEATURE_ESAME)*/
3136
3137
3138 /*-------------------------------------------------------------------*/
3139 /* B9FA ALRK - Add Logical Distinct Register [RRR] */
3140 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_distinct_register)3141 DEF_INST(add_logical_distinct_register) /*810*/
3142 {
3143 int r1, r2, r3; /* Values of R fields */
3144
3145 RRR0(inst, regs, r1, r2, r3);
3146
3147 /* Add signed operands and set condition code */
3148 regs->psw.cc = add_logical (&(regs->GR_L(r1)),
3149 regs->GR_L(r2),
3150 regs->GR_L(r3));
3151
3152 } /* end DEF_INST(add_logical_distinct_register) */
3153
3154
3155 #if defined(FEATURE_ESAME)
3156 /*-------------------------------------------------------------------*/
3157 /* B9EA ALGRK - Add Logical Distinct Long Register [RRR] */
3158 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_distinct_long_register)3159 DEF_INST(add_logical_distinct_long_register) /*810*/
3160 {
3161 int r1, r2, r3; /* Values of R fields */
3162
3163 RRR0(inst, regs, r1, r2, r3);
3164
3165 /* Add unsigned operands and set condition code */
3166 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
3167 regs->GR_G(r2),
3168 regs->GR_G(r3));
3169
3170 } /* end DEF_INST(add_logical_distinct_long_register) */
3171 #endif /*defined(FEATURE_ESAME)*/
3172
3173
3174 /*-------------------------------------------------------------------*/
3175 /* ECDA ALHSIK - Add Logical Distinct with Signed Halfword Imm [RIE] */
3176 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_distinct_signed_halfword_immediate)3177 DEF_INST(add_logical_distinct_signed_halfword_immediate) /*810*/
3178 {
3179 int r1, r3; /* Values of R fields */
3180 U16 i2; /* 16-bit immediate operand */
3181
3182 RIE0(inst, regs, r1, r3, i2);
3183
3184 /* Add operands and set condition code */
3185 regs->psw.cc = (S16)i2 < 0 ?
3186 sub_logical (&(regs->GR_L(r1)), regs->GR_L(r3), (S32)(-(S16)i2)) :
3187 add_logical (&(regs->GR_L(r1)), regs->GR_L(r3), (S32)(S16)i2);
3188
3189 } /* end DEF_INST(add_logical_distinct_signed_halfword_immediate) */
3190
3191
3192 #if defined(FEATURE_ESAME)
3193 /*-------------------------------------------------------------------*/
3194 /* ECDB ALGHSIK - Add Logical Distinct Long with Signed Hw Imm [RIE] */
3195 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_distinct_long_signed_halfword_immediate)3196 DEF_INST(add_logical_distinct_long_signed_halfword_immediate) /*810*/
3197 {
3198 int r1, r3; /* Values of R fields */
3199 U16 i2; /* 16-bit immediate operand */
3200
3201 RIE0(inst, regs, r1, r3, i2);
3202
3203 /* Add operands and set condition code */
3204 regs->psw.cc = (S16)i2 < 0 ?
3205 sub_logical_long (&(regs->GR_G(r1)), regs->GR_G(r3), (S64)(-(S16)i2)) :
3206 add_logical_long (&(regs->GR_G(r1)), regs->GR_G(r3), (S64)(S16)i2);
3207
3208 } /* end DEF_INST(add_logical_distinct_long_signed_halfword_immediate) */
3209 #endif /*defined(FEATURE_ESAME)*/
3210
3211
3212 /*-------------------------------------------------------------------*/
3213 /* B9F4 NRK - And Distinct Register [RRR] */
3214 /*-------------------------------------------------------------------*/
DEF_INST(and_distinct_register)3215 DEF_INST(and_distinct_register) /*810*/
3216 {
3217 int r1, r2, r3; /* Values of R fields */
3218
3219 RRR0(inst, regs, r1, r2, r3);
3220
3221 /* AND second and third operands and put result in first operand */
3222 regs->GR_L(r1) = regs->GR_L(r2) & regs->GR_L(r3);
3223
3224 /* Set condition code 1 if result is non-zero, otherwise 0 */
3225 regs->psw.cc = (regs->GR_L(r1)) ? 1 : 0;
3226
3227 } /* end DEF_INST(and_distinct_register) */
3228
3229
3230 #if defined(FEATURE_ESAME)
3231 /*-------------------------------------------------------------------*/
3232 /* B9E4 NGRK - And Distinct Long Register [RRR] */
3233 /*-------------------------------------------------------------------*/
DEF_INST(and_distinct_long_register)3234 DEF_INST(and_distinct_long_register) /*810*/
3235 {
3236 int r1, r2, r3; /* Values of R fields */
3237
3238 RRR0(inst, regs, r1, r2, r3);
3239
3240 /* AND second and third operands and put result in first operand */
3241 regs->GR_G(r1) = regs->GR_G(r2) & regs->GR_G(r3);
3242
3243 /* Set condition code 1 if result is non-zero, otherwise 0 */
3244 regs->psw.cc = (regs->GR_G(r1)) ? 1 : 0;
3245
3246 } /* end DEF_INST(and_distinct_long_register) */
3247 #endif /*defined(FEATURE_ESAME)*/
3248
3249
3250 /*-------------------------------------------------------------------*/
3251 /* B9F7 XRK - Exclusive Or Distinct Register [RRR] */
3252 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_distinct_register)3253 DEF_INST(exclusive_or_distinct_register) /*810*/
3254 {
3255 int r1, r2, r3; /* Values of R fields */
3256
3257 RRR0(inst, regs, r1, r2, r3);
3258
3259 /* XOR second and third operands and put result in first operand */
3260 regs->GR_L(r1) = regs->GR_L(r2) ^ regs->GR_L(r3);
3261
3262 /* Set condition code 1 if result is non-zero, otherwise 0 */
3263 regs->psw.cc = (regs->GR_L(r1)) ? 1 : 0;
3264
3265 } /* end DEF_INST(exclusive_or_distinct_register) */
3266
3267
3268 #if defined(FEATURE_ESAME)
3269 /*-------------------------------------------------------------------*/
3270 /* B9E7 XGRK - Exclusive Or Distinct Long Register [RRR] */
3271 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_distinct_long_register)3272 DEF_INST(exclusive_or_distinct_long_register) /*810*/
3273 {
3274 int r1, r2, r3; /* Values of R fields */
3275
3276 RRR0(inst, regs, r1, r2, r3);
3277
3278 /* XOR second and third operands and put result in first operand */
3279 regs->GR_G(r1) = regs->GR_G(r2) ^ regs->GR_G(r3);
3280
3281 /* Set condition code 1 if result is non-zero, otherwise 0 */
3282 regs->psw.cc = (regs->GR_G(r1)) ? 1 : 0;
3283
3284 } /* end DEF_INST(exclusive_or_distinct_long_register) */
3285 #endif /*defined(FEATURE_ESAME)*/
3286
3287
3288 /*-------------------------------------------------------------------*/
3289 /* B9F6 ORK - Or Distinct Register [RRR] */
3290 /*-------------------------------------------------------------------*/
DEF_INST(or_distinct_register)3291 DEF_INST(or_distinct_register) /*810*/
3292 {
3293 int r1, r2, r3; /* Values of R fields */
3294
3295 RRR0(inst, regs, r1, r2, r3);
3296
3297 /* OR second and third operands and put result in first operand */
3298 regs->GR_L(r1) = regs->GR_L(r2) | regs->GR_L(r3);
3299
3300 /* Set condition code 1 if result is non-zero, otherwise 0 */
3301 regs->psw.cc = (regs->GR_L(r1)) ? 1 : 0;
3302
3303 } /* end DEF_INST(or_distinct_register) */
3304
3305
3306 #if defined(FEATURE_ESAME)
3307 /*-------------------------------------------------------------------*/
3308 /* B9E6 OGRK - Or Distinct Long Register [RRR] */
3309 /*-------------------------------------------------------------------*/
DEF_INST(or_distinct_long_register)3310 DEF_INST(or_distinct_long_register) /*810*/
3311 {
3312 int r1, r2, r3; /* Values of R fields */
3313
3314 RRR0(inst, regs, r1, r2, r3);
3315
3316 /* OR second and third operands and put result in first operand */
3317 regs->GR_G(r1) = regs->GR_G(r2) | regs->GR_G(r3);
3318
3319 /* Set condition code 1 if result is non-zero, otherwise 0 */
3320 regs->psw.cc = (regs->GR_G(r1)) ? 1 : 0;
3321
3322 } /* end DEF_INST(or_distinct_long_register) */
3323 #endif /*defined(FEATURE_ESAME)*/
3324
3325
3326 /*-------------------------------------------------------------------*/
3327 /* EBDC SRAK - Shift Right Single Distinct [RSY] */
3328 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_single_distinct)3329 DEF_INST(shift_right_single_distinct) /*810*/
3330 {
3331 int r1, r3; /* Register numbers */
3332 int b2; /* Base of effective addr */
3333 VADR effective_addr2; /* Effective address */
3334 U32 n; /* Integer work area */
3335
3336 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3337
3338 /* Use rightmost six bits of operand address as shift count */
3339 n = effective_addr2 & 0x3F;
3340
3341 /* Shift signed value of the R3 register, result in R1 register */
3342 regs->GR_L(r1) = n > 30 ?
3343 ((S32)regs->GR_L(r3) < 0 ? -1 : 0) :
3344 (S32)regs->GR_L(r3) >> n;
3345
3346 /* Set the condition code */
3347 regs->psw.cc = ((S32)regs->GR_L(r1) > 0) ? 2 :
3348 (((S32)regs->GR_L(r1) < 0) ? 1 : 0);
3349
3350 } /* end DEF_INST(shift_right_single_distinct) */
3351
3352
3353 /*-------------------------------------------------------------------*/
3354 /* EBDD SLAK - Shift Left Single Distinct [RSY] */
3355 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_single_distinct)3356 DEF_INST(shift_left_single_distinct) /*810*/
3357 {
3358 int r1, r3; /* Register numbers */
3359 int b2; /* Base of effective addr */
3360 VADR effective_addr2; /* Effective address */
3361 U32 n, n1, n2; /* 32-bit operand values */
3362 U32 i, j; /* Integer work areas */
3363
3364 RSY(inst, regs, r1, r3, b2, effective_addr2);
3365
3366 /* Use rightmost six bits of operand address as shift count */
3367 n = effective_addr2 & 0x3F;
3368
3369 /* Fast path if no possible overflow */
3370 if (regs->GR_L(r3) < 0x10000 && n < 16)
3371 {
3372 regs->GR_L(r1) = regs->GR_L(r3) << n;
3373 regs->psw.cc = regs->GR_L(r1) ? 2 : 0;
3374 return;
3375 }
3376
3377 /* Load the numeric and sign portions from the R3 register */
3378 n1 = regs->GR_L(r3) & 0x7FFFFFFF;
3379 n2 = regs->GR_L(r3) & 0x80000000;
3380
3381 /* Shift the numeric portion left n positions */
3382 for (i = 0, j = 0; i < n; i++)
3383 {
3384 /* Shift bits 1-31 left one bit position */
3385 n1 <<= 1;
3386
3387 /* Overflow if bit shifted out is unlike the sign bit */
3388 if ((n1 & 0x80000000) != n2)
3389 j = 1;
3390 }
3391
3392 /* Load the updated value into the R1 register */
3393 regs->GR_L(r1) = (n1 & 0x7FFFFFFF) | n2;
3394
3395 /* Condition code 3 and program check if overflow occurred */
3396 if (j)
3397 {
3398 regs->psw.cc = 3;
3399 if ( FOMASK(®s->psw) )
3400 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3401 return;
3402 }
3403
3404 /* Set the condition code */
3405 regs->psw.cc = (S32)regs->GR_L(r1) > 0 ? 2 :
3406 (S32)regs->GR_L(r1) < 0 ? 1 : 0;
3407
3408 } /* end DEF_INST(shift_left_single_distinct) */
3409
3410
3411 /*-------------------------------------------------------------------*/
3412 /* EBDE SRLK - Shift Right Single Logical Distinct [RSY] */
3413 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_single_logical_distinct)3414 DEF_INST(shift_right_single_logical_distinct) /*810*/
3415 {
3416 int r1, r3; /* Register numbers */
3417 int b2; /* Base of effective addr */
3418 VADR effective_addr2; /* Effective address */
3419 U32 n; /* Integer work area */
3420
3421 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3422
3423 /* Use rightmost six bits of operand address as shift count */
3424 n = effective_addr2 & 0x3F;
3425
3426 /* Shift the R3 register and place the result in the R1 register */
3427 regs->GR_L(r1) = n > 31 ? 0 : regs->GR_L(r3) >> n;
3428
3429 } /* end DEF_INST(shift_right_single_logical_distinct) */
3430
3431
3432 /*-------------------------------------------------------------------*/
3433 /* EBDF SLLK - Shift Left Single Logical Distinct [RSY] */
3434 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_single_logical_distinct)3435 DEF_INST(shift_left_single_logical_distinct) /*810*/
3436 {
3437 int r1, r3; /* Register numbers */
3438 int b2; /* Base of effective addr */
3439 VADR effective_addr2; /* Effective address */
3440 U32 n; /* Integer work area */
3441
3442 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3443
3444 /* Use rightmost six bits of operand address as shift count */
3445 n = effective_addr2 & 0x3F;
3446
3447 /* Shift the R3 register and place the result in the R1 register */
3448 regs->GR_L(r1) = n > 31 ? 0 : regs->GR_L(r3) << n;
3449
3450 } /* end DEF_INST(shift_left_single_logical_distinct) */
3451
3452
3453 /*-------------------------------------------------------------------*/
3454 /* B9F9 SRK - Subtract Distinct Register [RRR] */
3455 /*-------------------------------------------------------------------*/
DEF_INST(subtract_distinct_register)3456 DEF_INST(subtract_distinct_register) /*810*/
3457 {
3458 int r1, r2, r3; /* Values of R fields */
3459
3460 RRR(inst, regs, r1, r2, r3);
3461
3462 /* Subtract signed operands and set condition code */
3463 regs->psw.cc =
3464 sub_signed (&(regs->GR_L(r1)),
3465 regs->GR_L(r2),
3466 regs->GR_L(r3));
3467
3468 /* Program check if fixed-point overflow */
3469 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3470 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3471
3472 } /* end DEF_INST(subtract_distinct_register) */
3473
3474
3475 #if defined(FEATURE_ESAME)
3476 /*-------------------------------------------------------------------*/
3477 /* B9E9 SGRK - Subtract Distinct Long Register [RRR] */
3478 /*-------------------------------------------------------------------*/
DEF_INST(subtract_distinct_long_register)3479 DEF_INST(subtract_distinct_long_register) /*810*/
3480 {
3481 int r1, r2, r3; /* Values of R fields */
3482
3483 RRR(inst, regs, r1, r2, r3);
3484
3485 /* Subtract signed operands and set condition code */
3486 regs->psw.cc = sub_signed_long(&(regs->GR_G(r1)),
3487 regs->GR_G(r2),
3488 regs->GR_G(r3));
3489
3490 /* Program check if fixed-point overflow */
3491 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3492 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3493
3494 } /* end DEF_INST(subtract_distinct_long_register) */
3495 #endif /*defined(FEATURE_ESAME)*/
3496
3497
3498 /*-------------------------------------------------------------------*/
3499 /* B9FB SLRK - Subtract Logical Distinct Register [RRR] */
3500 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_distinct_register)3501 DEF_INST(subtract_logical_distinct_register) /*810*/
3502 {
3503 int r1, r2, r3; /* Values of R fields */
3504
3505 RRR0(inst, regs, r1, r2, r3);
3506
3507 /* Subtract unsigned operands and set condition code */
3508 regs->psw.cc = sub_logical (&(regs->GR_L(r1)),
3509 regs->GR_L(r2),
3510 regs->GR_L(r3));
3511
3512 } /* end DEF_INST(subtract_logical_distinct_register) */
3513
3514
3515 #if defined(FEATURE_ESAME)
3516 /*-------------------------------------------------------------------*/
3517 /* B9EB SLGRK - Subtract Logical Distinct Long Register [RRR] */
3518 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_distinct_long_register)3519 DEF_INST(subtract_logical_distinct_long_register) /*810*/
3520 {
3521 int r1, r2, r3; /* Values of R fields */
3522
3523 RRR0(inst, regs, r1, r2, r3);
3524
3525 /* Subtract unsigned operands and set condition code */
3526 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
3527 regs->GR_G(r2),
3528 regs->GR_G(r3));
3529
3530 } /* end DEF_INST(subtract_logical_distinct_long_register) */
3531 #endif /*defined(FEATURE_ESAME)*/
3532
3533 #endif /*defined(FEATURE_DISTINCT_OPERANDS_FACILITY)*/ /*810*/
3534
3535
3536 #if defined(FEATURE_POPULATION_COUNT_FACILITY) /*810*/
3537 /*-------------------------------------------------------------------*/
3538 /* B9E1 POPCNT - Population Count [RRE] */
3539 /*-------------------------------------------------------------------*/
DEF_INST(population_count)3540 DEF_INST(population_count) /*810*/
3541 {
3542 int r1, r2; /* Values of R fields */
3543 int i; /* Loop counter */
3544 U64 n; /* Contents of R2 register */
3545 U64 result; /* Result counter */
3546 U64 mask = 0x0101010101010101ULL; /* Bit mask */
3547
3548 RRE0(inst, regs, r1, r2);
3549
3550 /* Load the value to be counted from the R2 register */
3551 n = regs->GR_G(r2);
3552
3553 /* Count the number of 1 bits in each byte */
3554 for (i = 0, result = 0; i < 8; i++) {
3555 result += n & mask;
3556 n >>= 1;
3557 }
3558
3559 /* Load the result into the R1 register */
3560 regs->GR_G(r1) = result;
3561
3562 /* Set condition code 0 if result is zero, or 1 if non-zero */
3563 regs->psw.cc = (result == 0) ? 0 : 1;
3564
3565 } /* end DEF_INST(population_count) */
3566 #endif /*defined(FEATURE_POPULATION_COUNT_FACILITY)*/ /*810*/
3567
3568
3569 #if defined(FEATURE_LOAD_AND_TRAP_FACILITY) /*912*/
3570
3571 /*-------------------------------------------------------------------*/
3572 /* E39F LAT - Load and Trap [RXY] */
3573 /*-------------------------------------------------------------------*/
DEF_INST(load_and_trap)3574 DEF_INST(load_and_trap)
3575 {
3576 int r1; /* Value of R field */
3577 int b2; /* Base of effective addr */
3578 VADR effective_addr2; /* Effective address */
3579
3580 RXY(inst, regs, r1, b2, effective_addr2);
3581
3582 /* Load R1 register from second operand */
3583 regs->GR_L(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
3584
3585 /* Raise data exception if result is zero */
3586 if (regs->GR_L(r1) == 0)
3587 {
3588 regs->dxc = DXC_COMPARE_AND_TRAP;
3589 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3590 }
3591
3592 } /* end DEF_INST(load_and_trap) */
3593
3594
3595 #if defined(FEATURE_ESAME)
3596 /*-------------------------------------------------------------------*/
3597 /* E385 LGAT - Load Long and Trap [RXY] */
3598 /*-------------------------------------------------------------------*/
DEF_INST(load_long_and_trap)3599 DEF_INST(load_long_and_trap) /*912*/
3600 {
3601 int r1; /* Value of R field */
3602 int b2; /* Base of effective addr */
3603 VADR effective_addr2; /* Effective address */
3604
3605 RXY(inst, regs, r1, b2, effective_addr2);
3606
3607 /* Load R1 register from second operand */
3608 regs->GR_G(r1) = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3609
3610 /* Raise data exception if result is zero */
3611 if (regs->GR_G(r1) == 0)
3612 {
3613 regs->dxc = DXC_COMPARE_AND_TRAP;
3614 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3615 }
3616
3617 } /* end DEF_INST(load_long_and_trap) */
3618 #endif /*defined(FEATURE_ESAME)*/
3619
3620
3621 #if defined(FEATURE_ESAME)
3622 /*-------------------------------------------------------------------*/
3623 /* E3C8 LFHAT - Load Fullword High and Trap [RXY] */
3624 /*-------------------------------------------------------------------*/
DEF_INST(load_fullword_high_and_trap)3625 DEF_INST(load_fullword_high_and_trap) /*912*/
3626 {
3627 int r1; /* Value of R field */
3628 int b2; /* Base of effective addr */
3629 VADR effective_addr2; /* Effective address */
3630
3631 RXY(inst, regs, r1, b2, effective_addr2);
3632
3633 /* Load R1 register bits 0-31 from second operand */
3634 regs->GR_H(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
3635
3636 /* Raise data exception if result is zero */
3637 if (regs->GR_H(r1) == 0)
3638 {
3639 regs->dxc = DXC_COMPARE_AND_TRAP;
3640 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3641 }
3642
3643 } /* end DEF_INST(load_fullword_high_and_trap) */
3644 #endif /*defined(FEATURE_ESAME)*/
3645
3646
3647 #if defined(FEATURE_ESAME)
3648 /*-------------------------------------------------------------------*/
3649 /* E39D LLGFAT - Load Logical Long Fullword and Trap [RXY] */
3650 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_fullword_and_trap)3651 DEF_INST(load_logical_long_fullword_and_trap) /*912*/
3652 {
3653 int r1; /* Value of R field */
3654 int b2; /* Base of effective addr */
3655 VADR effective_addr2; /* Effective address */
3656
3657 RXY(inst, regs, r1, b2, effective_addr2);
3658
3659 /* Load R1 register from second operand */
3660 regs->GR_G(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
3661
3662 /* Raise data exception if result is zero */
3663 if (regs->GR_G(r1) == 0)
3664 {
3665 regs->dxc = DXC_COMPARE_AND_TRAP;
3666 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3667 }
3668
3669 } /* end DEF_INST(load_logical_long_fullword_and_trap) */
3670 #endif /*defined(FEATURE_ESAME)*/
3671
3672
3673 #if defined(FEATURE_ESAME)
3674 /*-------------------------------------------------------------------*/
3675 /* E39C LLGTAT - Load Logical Long Thirtyone and Trap [RXY] */
3676 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_thirtyone_and_trap)3677 DEF_INST(load_logical_long_thirtyone_and_trap) /*912*/
3678 {
3679 int r1; /* Value of R field */
3680 int b2; /* Base of effective addr */
3681 VADR effective_addr2; /* Effective address */
3682
3683 RXY(inst, regs, r1, b2, effective_addr2);
3684
3685 /* Load R1 register from second operand */
3686 regs->GR_G(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs )
3687 & 0x7FFFFFFF;
3688
3689 /* Raise data exception if result is zero */
3690 if (regs->GR_G(r1) == 0)
3691 {
3692 regs->dxc = DXC_COMPARE_AND_TRAP;
3693 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3694 }
3695
3696 } /* end DEF_INST(load_logical_long_thirtyone_and_trap) */
3697 #endif /*defined(FEATURE_ESAME)*/
3698
3699 #endif /*defined(FEATURE_LOAD_AND_TRAP_FACILITY)*/ /*912*/
3700
3701
3702 #if defined(FEATURE_MISC_INSTRUCTION_EXTENSIONS_FACILITY) /*912*/
3703
3704 /*-------------------------------------------------------------------*/
3705 /* EB23 CLT - Compare Logical and Trap [RSY] */
3706 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_trap)3707 DEF_INST(compare_logical_and_trap) /*912*/
3708 {
3709 int r1; /* Register number */
3710 int b2; /* Base of effective addr */
3711 VADR effective_addr2; /* Effective address */
3712 U32 n; /* 32-bit operand value */
3713 int m3; /* Mask bits */
3714 int cc; /* Comparison result */
3715
3716 RSY(inst, regs, r1, m3, b2, effective_addr2);
3717
3718 /* Load second operand from operand address */
3719 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
3720
3721 /* Compare unsigned operands and set comparison result */
3722 cc = regs->GR_L(r1) < n ? 1 :
3723 regs->GR_L(r1) > n ? 2 : 0;
3724
3725 /* Raise data exception if m3 mask bit is set */
3726 if ((0x8 >> cc) & m3)
3727 {
3728 regs->dxc = DXC_COMPARE_AND_TRAP;
3729 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3730 }
3731
3732 } /* end DEF_INST(compare_logical_and_trap) */
3733
3734
3735 #if defined(FEATURE_ESAME)
3736 /*-------------------------------------------------------------------*/
3737 /* EB2B CLGT - Compare Logical and Trap Long [RSY] */
3738 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_trap_long)3739 DEF_INST(compare_logical_and_trap_long) /*912*/
3740 {
3741 int r1; /* Register number */
3742 int b2; /* Base of effective addr */
3743 VADR effective_addr2; /* Effective address */
3744 U64 n; /* 64-bit operand value */
3745 int m3; /* Mask bits */
3746 int cc; /* Comparison result */
3747
3748 RSY(inst, regs, r1, m3, b2, effective_addr2);
3749
3750 /* Load second operand from operand address */
3751 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3752
3753 /* Compare unsigned operands and set comparison result */
3754 cc = regs->GR_G(r1) < n ? 1 :
3755 regs->GR_G(r1) > n ? 2 : 0;
3756
3757 /* Raise data exception if m3 mask bit is set */
3758 if ((0x8 >> cc) & m3)
3759 {
3760 regs->dxc = DXC_COMPARE_AND_TRAP;
3761 ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
3762 }
3763
3764 } /* end DEF_INST(compare_logical_and_trap_long) */
3765 #endif /*defined(FEATURE_ESAME)*/
3766
3767
3768 #if defined(FEATURE_ESAME)
3769 /*-------------------------------------------------------------------*/
3770 /* EC59 RISBGN - Rotate Then Insert Selected Bits No CC [RIE] */
3771 /*-------------------------------------------------------------------*/
DEF_INST(rotate_then_insert_selected_bits_long_reg_n)3772 DEF_INST(rotate_then_insert_selected_bits_long_reg_n)
3773 {
3774 ARCH_DEP(rotate_then_xxx_selected_bits_long_reg) (inst, regs);
3775 } /* end DEF_INST(rotate_then_insert_selected_bits_long_reg_n) */
3776 #endif /*defined(FEATURE_ESAME)*/
3777
3778
3779 #endif /*defined(FEATURE_MISC_INSTRUCTION_EXTENSIONS_FACILITY)*/
3780
3781 #if defined(FEATURE_EXECUTION_HINT_FACILITY) /*912*/
3782
3783 /*-------------------------------------------------------------------*/
3784 /* C7 BPP - Branch Prediction Preload [SMI] */
3785 /*-------------------------------------------------------------------*/
DEF_INST(branch_prediction_preload)3786 DEF_INST(branch_prediction_preload) /*912*/
3787 {
3788 VADR addr2, addr3; /* Effective addresses */
3789 int b3; /* Base of effective address */
3790 int m1; /* Mask value */
3791
3792 SMI_A0(inst, regs, m1, addr2, b3, addr3);
3793
3794 /* Depending on the model, the CPU may not implement
3795 all of the branch-attribute codes. For codes that
3796 are not recognized by the CPU, and for reserved
3797 codes, the BPP instruction acts as a no-operation */
3798
3799 } /* end DEF_INST(branch_prediction_preload) */
3800
3801
3802 /*-------------------------------------------------------------------*/
3803 /* C5 BPRP - Branch Prediction Relative Preload [MII] */
3804 /*-------------------------------------------------------------------*/
DEF_INST(branch_prediction_relative_preload)3805 DEF_INST(branch_prediction_relative_preload) /*912*/
3806 {
3807 VADR addr2, addr3; /* Effective addresses */
3808 int m1; /* Mask value */
3809
3810 MII_A0(inst, regs, m1, addr2, addr3);
3811
3812 /* Depending on the model, the CPU may not implement
3813 all of the branch-attribute codes. For codes that
3814 are not recognized by the CPU, and for reserved
3815 codes, the BPRP instruction acts as a no-operation */
3816
3817 } /* end DEF_INST(branch_prediction_relative_preload) */
3818
3819
3820 /*-------------------------------------------------------------------*/
3821 /* B2FA NIAI - Next Instruction Access Intent [IE] */
3822 /*-------------------------------------------------------------------*/
DEF_INST(next_instruction_access_intent)3823 DEF_INST(next_instruction_access_intent) /*912*/
3824 {
3825 BYTE i1, i2; /* Immediate fields */
3826
3827 IE0(inst, regs, i1, i2);
3828
3829 /* Depending on the model, the CPU may not recognize all of the
3830 access intents. For access intents that are not recognized by
3831 the CPU, the NIAI instruction acts as a no-operation */
3832
3833 } /* end DEF_INST(next_instruction_access_intent) */
3834
3835 #endif /*defined(FEATURE_EXECUTION_HINT_FACILITY)*/ /*912*/
3836
3837
3838 #if !defined(_GEN_ARCH)
3839
3840 #if defined(_ARCHMODE2)
3841 #define _GEN_ARCH _ARCHMODE2
3842 #include "general3.c"
3843 #endif
3844
3845 #if defined(_ARCHMODE3)
3846 #undef _GEN_ARCH
3847 #define _GEN_ARCH _ARCHMODE3
3848 #include "general3.c"
3849 #endif
3850
3851 #endif /*!defined(_GEN_ARCH)*/
3852