1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "obstack.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "real.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "reload.h"
39 #include "function.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "toplev.h"
43 #include "recog.h"
44 #include "ggc.h"
45 #include "except.h"
46 #include "c-pragma.h"
47 #include "integrate.h"
48 #include "tm_p.h"
49 #include "target.h"
50 #include "target-def.h"
51
52 /* Forward definitions of types. */
53 typedef struct minipool_node Mnode;
54 typedef struct minipool_fixup Mfix;
55
56 /* In order to improve the layout of the prototypes below
57 some short type abbreviations are defined here. */
58 #define Hint HOST_WIDE_INT
59 #define Mmode enum machine_mode
60 #define Ulong unsigned long
61 #define Ccstar const char *
62
63 const struct attribute_spec arm_attribute_table[];
64
65 /* Forward function declarations. */
66 static void arm_add_gc_roots PARAMS ((void));
67 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
68 static unsigned bit_count PARAMS ((Ulong));
69 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
70 static rtx emit_multi_reg_push PARAMS ((int));
71 static rtx emit_sfm PARAMS ((int, int));
72 #ifndef AOF_ASSEMBLER
73 static bool arm_assemble_integer PARAMS ((rtx, unsigned int, int));
74 #endif
75 static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
76 static arm_cc get_arm_condition_code PARAMS ((rtx));
77 static void init_fpa_table PARAMS ((void));
78 static Hint int_log2 PARAMS ((Hint));
79 static rtx is_jump_table PARAMS ((rtx));
80 static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint));
81 static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int));
82 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
83 static Ccstar shift_op PARAMS ((rtx, Hint *));
84 static struct machine_function * arm_init_machine_status PARAMS ((void));
85 static int number_of_first_bit_set PARAMS ((int));
86 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
87 static void thumb_exit PARAMS ((FILE *, int, rtx));
88 static void thumb_pushpop PARAMS ((FILE *, int, int));
89 static Ccstar thumb_condition_code PARAMS ((rtx, int));
90 static rtx is_jump_table PARAMS ((rtx));
91 static Hint get_jump_table_size PARAMS ((rtx));
92 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
93 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
94 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
95 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
96 static void assign_minipool_offsets PARAMS ((Mfix *));
97 static void arm_print_value PARAMS ((FILE *, rtx));
98 static void dump_minipool PARAMS ((rtx));
99 static int arm_barrier_cost PARAMS ((rtx));
100 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
101 static void push_minipool_barrier PARAMS ((rtx, Hint));
102 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
103 static void note_invalid_constants PARAMS ((rtx, Hint));
104 static int current_file_function_operand PARAMS ((rtx));
105 static Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void));
106 static Ulong arm_compute_save_reg_mask PARAMS ((void));
107 static Ulong arm_isr_value PARAMS ((tree));
108 static Ulong arm_compute_func_type PARAMS ((void));
109 static tree arm_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
110 static tree arm_handle_isr_attribute PARAMS ((tree *, tree, tree, int, bool *));
111 static void arm_output_function_epilogue PARAMS ((FILE *, Hint));
112 static void arm_output_function_prologue PARAMS ((FILE *, Hint));
113 static void thumb_output_function_prologue PARAMS ((FILE *, Hint));
114 static int arm_comp_type_attributes PARAMS ((tree, tree));
115 static void arm_set_default_type_attributes PARAMS ((tree));
116 static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int));
117 static int count_insns_for_constant PARAMS ((HOST_WIDE_INT, int));
118 static int arm_get_strip_length PARAMS ((int));
119 #ifdef OBJECT_FORMAT_ELF
120 static void arm_elf_asm_named_section PARAMS ((const char *, unsigned int));
121 #endif
122 #ifndef ARM_PE
123 static void arm_encode_section_info PARAMS ((tree, int));
124 #endif
125 #ifdef AOF_ASSEMBLER
126 static void aof_globalize_label PARAMS ((FILE *, const char *));
127 #endif
128 static void arm_output_mi_thunk PARAMS ((FILE *, tree,
129 HOST_WIDE_INT,
130 HOST_WIDE_INT, tree));
131
132 #undef Hint
133 #undef Mmode
134 #undef Ulong
135 #undef Ccstar
136
137 /* Initialize the GCC target structure. */
138 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
139 #undef TARGET_MERGE_DECL_ATTRIBUTES
140 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
141 #endif
142
143 #undef TARGET_ATTRIBUTE_TABLE
144 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
145
146 #ifdef AOF_ASSEMBLER
147 #undef TARGET_ASM_BYTE_OP
148 #define TARGET_ASM_BYTE_OP "\tDCB\t"
149 #undef TARGET_ASM_ALIGNED_HI_OP
150 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
151 #undef TARGET_ASM_ALIGNED_SI_OP
152 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
153 #undef TARGET_ASM_GLOBALIZE_LABEL
154 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
155 #else
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP NULL
158 #undef TARGET_ASM_INTEGER
159 #define TARGET_ASM_INTEGER arm_assemble_integer
160 #endif
161
162 #undef TARGET_ASM_FUNCTION_PROLOGUE
163 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
164
165 #undef TARGET_ASM_FUNCTION_EPILOGUE
166 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
167
168 #undef TARGET_COMP_TYPE_ATTRIBUTES
169 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
170
171 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
172 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
173
174 #undef TARGET_INIT_BUILTINS
175 #define TARGET_INIT_BUILTINS arm_init_builtins
176
177 #undef TARGET_EXPAND_BUILTIN
178 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
179
180 #undef TARGET_SCHED_ADJUST_COST
181 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
182
183 #undef TARGET_ENCODE_SECTION_INFO
184 #ifdef ARM_PE
185 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
186 #else
187 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
188 #endif
189
190 #undef TARGET_STRIP_NAME_ENCODING
191 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
192
193 #undef TARGET_ASM_OUTPUT_MI_THUNK
194 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
195 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
196 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
197
198 struct gcc_target targetm = TARGET_INITIALIZER;
199
200 /* Obstack for minipool constant handling. */
201 static struct obstack minipool_obstack;
202 static char * minipool_startobj;
203
204 /* The maximum number of insns skipped which
205 will be conditionalised if possible. */
206 static int max_insns_skipped = 5;
207
208 extern FILE * asm_out_file;
209
210 /* True if we are currently building a constant table. */
211 int making_const_table;
212
213 /* Define the information needed to generate branch insns. This is
214 stored from the compare operation. */
215 rtx arm_compare_op0, arm_compare_op1;
216
217 /* What type of floating point are we tuning for? */
218 enum floating_point_type arm_fpu;
219
220 /* What type of floating point instructions are available? */
221 enum floating_point_type arm_fpu_arch;
222
223 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
224 enum prog_mode_type arm_prgmode;
225
226 /* Set by the -mfp=... option. */
227 const char * target_fp_name = NULL;
228
229 /* Used to parse -mstructure_size_boundary command line option. */
230 const char * structure_size_string = NULL;
231 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
232
233 /* Bit values used to identify processor capabilities. */
234 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
235 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
236 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
237 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
238 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
239 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
240 #define FL_THUMB (1 << 6) /* Thumb aware */
241 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
242 #define FL_STRONG (1 << 8) /* StrongARM */
243 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
244 #define FL_XSCALE (1 << 10) /* XScale */
245
246 /* The bits in this mask specify which
247 instructions we are allowed to generate. */
248 static unsigned long insn_flags = 0;
249
250 /* The bits in this mask specify which instruction scheduling options should
251 be used. Note - there is an overlap with the FL_FAST_MULT. For some
252 hardware we want to be able to generate the multiply instructions, but to
253 tune as if they were not present in the architecture. */
254 static unsigned long tune_flags = 0;
255
256 /* The following are used in the arm.md file as equivalents to bits
257 in the above two flag variables. */
258
259 /* Nonzero if this is an "M" variant of the processor. */
260 int arm_fast_multiply = 0;
261
262 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
263 int arm_arch4 = 0;
264
265 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
266 int arm_arch5 = 0;
267
268 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
269 int arm_arch5e = 0;
270
271 /* Nonzero if this chip can benefit from load scheduling. */
272 int arm_ld_sched = 0;
273
274 /* Nonzero if this chip is a StrongARM. */
275 int arm_is_strong = 0;
276
277 /* Nonzero if this chip is an XScale. */
278 int arm_arch_xscale = 0;
279
280 /* Nonzero if tuning for XScale */
281 int arm_tune_xscale = 0;
282
283 /* Nonzero if this chip is an ARM6 or an ARM7. */
284 int arm_is_6_or_7 = 0;
285
286 /* Nonzero if generating Thumb instructions. */
287 int thumb_code = 0;
288
289 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
290 must report the mode of the memory reference from PRINT_OPERAND to
291 PRINT_OPERAND_ADDRESS. */
292 enum machine_mode output_memory_reference_mode;
293
294 /* The register number to be used for the PIC offset register. */
295 const char * arm_pic_register_string = NULL;
296 int arm_pic_register = INVALID_REGNUM;
297
298 /* Set to 1 when a return insn is output, this means that the epilogue
299 is not needed. */
300 int return_used_this_function;
301
302 /* Set to 1 after arm_reorg has started. Reset to start at the start of
303 the next function. */
304 static int after_arm_reorg = 0;
305
306 /* The maximum number of insns to be used when loading a constant. */
307 static int arm_constant_limit = 3;
308
309 /* For an explanation of these variables, see final_prescan_insn below. */
310 int arm_ccfsm_state;
311 enum arm_cond_code arm_current_cc;
312 rtx arm_target_insn;
313 int arm_target_label;
314
315 /* The condition codes of the ARM, and the inverse function. */
316 static const char * const arm_condition_codes[] =
317 {
318 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
319 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
320 };
321
322 #define streq(string1, string2) (strcmp (string1, string2) == 0)
323
324 /* Initialization code. */
325
326 struct processors
327 {
328 const char *const name;
329 const unsigned long flags;
330 };
331
332 /* Not all of these give usefully different compilation alternatives,
333 but there is no simple way of generalizing them. */
334 static const struct processors all_cores[] =
335 {
336 /* ARM Cores */
337
338 {"arm2", FL_CO_PROC | FL_MODE26 },
339 {"arm250", FL_CO_PROC | FL_MODE26 },
340 {"arm3", FL_CO_PROC | FL_MODE26 },
341 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
342 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
343 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
344 {"arm610", FL_MODE26 | FL_MODE32 },
345 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
346 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
347 /* arm7m doesn't exist on its own, but only with D, (and I), but
348 those don't alter the code, so arm7m is sometimes used. */
349 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
350 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
351 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
352 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
353 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
354 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
355 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
356 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
357 {"arm710", FL_MODE26 | FL_MODE32 },
358 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB },
359 {"arm720", FL_MODE26 | FL_MODE32 },
360 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB },
361 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB },
362 {"arm710c", FL_MODE26 | FL_MODE32 },
363 {"arm7100", FL_MODE26 | FL_MODE32 },
364 {"arm7500", FL_MODE26 | FL_MODE32 },
365 /* Doesn't have an external co-proc, but does have embedded fpu. */
366 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
367 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
368 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
369 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
370 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
371 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
372 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
373 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
374 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
375 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
376 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
377 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
378 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
379 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
380 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
381 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
382 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
383
384 {NULL, 0}
385 };
386
387 static const struct processors all_architectures[] =
388 {
389 /* ARM Architectures */
390
391 { "armv2", FL_CO_PROC | FL_MODE26 },
392 { "armv2a", FL_CO_PROC | FL_MODE26 },
393 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
394 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
395 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
396 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
397 implementations that support it, so we will leave it out for now. */
398 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
399 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
400 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
401 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
402 { NULL, 0 }
403 };
404
405 /* This is a magic stucture. The 'string' field is magically filled in
406 with a pointer to the value specified by the user on the command line
407 assuming that the user has specified such a value. */
408
409 struct arm_cpu_select arm_select[] =
410 {
411 /* string name processors */
412 { NULL, "-mcpu=", all_cores },
413 { NULL, "-march=", all_architectures },
414 { NULL, "-mtune=", all_cores }
415 };
416
417 /* Return the number of bits set in VALUE. */
418 static unsigned
bit_count(value)419 bit_count (value)
420 unsigned long value;
421 {
422 unsigned long count = 0;
423
424 while (value)
425 {
426 count++;
427 value &= value - 1; /* Clear the least-significant set bit. */
428 }
429
430 return count;
431 }
432
433 /* Fix up any incompatible options that the user has specified.
434 This has now turned into a maze. */
435 void
arm_override_options()436 arm_override_options ()
437 {
438 unsigned i;
439
440 /* Set up the flags based on the cpu/architecture selected by the user. */
441 for (i = ARRAY_SIZE (arm_select); i--;)
442 {
443 struct arm_cpu_select * ptr = arm_select + i;
444
445 if (ptr->string != NULL && ptr->string[0] != '\0')
446 {
447 const struct processors * sel;
448
449 for (sel = ptr->processors; sel->name != NULL; sel++)
450 if (streq (ptr->string, sel->name))
451 {
452 if (i == 2)
453 tune_flags = sel->flags;
454 else
455 {
456 /* If we have been given an architecture and a processor
457 make sure that they are compatible. We only generate
458 a warning though, and we prefer the CPU over the
459 architecture. */
460 if (insn_flags != 0 && (insn_flags ^ sel->flags))
461 warning ("switch -mcpu=%s conflicts with -march= switch",
462 ptr->string);
463
464 insn_flags = sel->flags;
465 }
466
467 break;
468 }
469
470 if (sel->name == NULL)
471 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
472 }
473 }
474
475 /* If the user did not specify a processor, choose one for them. */
476 if (insn_flags == 0)
477 {
478 const struct processors * sel;
479 unsigned int sought;
480 static const struct cpu_default
481 {
482 const int cpu;
483 const char *const name;
484 }
485 cpu_defaults[] =
486 {
487 { TARGET_CPU_arm2, "arm2" },
488 { TARGET_CPU_arm6, "arm6" },
489 { TARGET_CPU_arm610, "arm610" },
490 { TARGET_CPU_arm710, "arm710" },
491 { TARGET_CPU_arm7m, "arm7m" },
492 { TARGET_CPU_arm7500fe, "arm7500fe" },
493 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
494 { TARGET_CPU_arm8, "arm8" },
495 { TARGET_CPU_arm810, "arm810" },
496 { TARGET_CPU_arm9, "arm9" },
497 { TARGET_CPU_strongarm, "strongarm" },
498 { TARGET_CPU_xscale, "xscale" },
499 { TARGET_CPU_generic, "arm" },
500 { 0, 0 }
501 };
502 const struct cpu_default * def;
503
504 /* Find the default. */
505 for (def = cpu_defaults; def->name; def++)
506 if (def->cpu == TARGET_CPU_DEFAULT)
507 break;
508
509 /* Make sure we found the default CPU. */
510 if (def->name == NULL)
511 abort ();
512
513 /* Find the default CPU's flags. */
514 for (sel = all_cores; sel->name != NULL; sel++)
515 if (streq (def->name, sel->name))
516 break;
517
518 if (sel->name == NULL)
519 abort ();
520
521 insn_flags = sel->flags;
522
523 /* Now check to see if the user has specified some command line
524 switch that require certain abilities from the cpu. */
525 sought = 0;
526
527 if (TARGET_INTERWORK || TARGET_THUMB)
528 {
529 sought |= (FL_THUMB | FL_MODE32);
530
531 /* Force apcs-32 to be used for interworking. */
532 target_flags |= ARM_FLAG_APCS_32;
533
534 /* There are no ARM processors that support both APCS-26 and
535 interworking. Therefore we force FL_MODE26 to be removed
536 from insn_flags here (if it was set), so that the search
537 below will always be able to find a compatible processor. */
538 insn_flags &= ~FL_MODE26;
539 }
540 else if (!TARGET_APCS_32)
541 sought |= FL_MODE26;
542
543 if (sought != 0 && ((sought & insn_flags) != sought))
544 {
545 /* Try to locate a CPU type that supports all of the abilities
546 of the default CPU, plus the extra abilities requested by
547 the user. */
548 for (sel = all_cores; sel->name != NULL; sel++)
549 if ((sel->flags & sought) == (sought | insn_flags))
550 break;
551
552 if (sel->name == NULL)
553 {
554 unsigned current_bit_count = 0;
555 const struct processors * best_fit = NULL;
556
557 /* Ideally we would like to issue an error message here
558 saying that it was not possible to find a CPU compatible
559 with the default CPU, but which also supports the command
560 line options specified by the programmer, and so they
561 ought to use the -mcpu=<name> command line option to
562 override the default CPU type.
563
564 Unfortunately this does not work with multilibing. We
565 need to be able to support multilibs for -mapcs-26 and for
566 -mthumb-interwork and there is no CPU that can support both
567 options. Instead if we cannot find a cpu that has both the
568 characteristics of the default cpu and the given command line
569 options we scan the array again looking for a best match. */
570 for (sel = all_cores; sel->name != NULL; sel++)
571 if ((sel->flags & sought) == sought)
572 {
573 unsigned count;
574
575 count = bit_count (sel->flags & insn_flags);
576
577 if (count >= current_bit_count)
578 {
579 best_fit = sel;
580 current_bit_count = count;
581 }
582 }
583
584 if (best_fit == NULL)
585 abort ();
586 else
587 sel = best_fit;
588 }
589
590 insn_flags = sel->flags;
591 }
592 }
593
594 /* If tuning has not been specified, tune for whichever processor or
595 architecture has been selected. */
596 if (tune_flags == 0)
597 tune_flags = insn_flags;
598
599 /* Make sure that the processor choice does not conflict with any of the
600 other command line choices. */
601 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
602 {
603 /* If APCS-32 was not the default then it must have been set by the
604 user, so issue a warning message. If the user has specified
605 "-mapcs-32 -mcpu=arm2" then we loose here. */
606 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
607 warning ("target CPU does not support APCS-32" );
608 target_flags &= ~ARM_FLAG_APCS_32;
609 }
610 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
611 {
612 warning ("target CPU does not support APCS-26" );
613 target_flags |= ARM_FLAG_APCS_32;
614 }
615
616 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
617 {
618 warning ("target CPU does not support interworking" );
619 target_flags &= ~ARM_FLAG_INTERWORK;
620 }
621
622 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
623 {
624 warning ("target CPU does not support THUMB instructions");
625 target_flags &= ~ARM_FLAG_THUMB;
626 }
627
628 if (TARGET_APCS_FRAME && TARGET_THUMB)
629 {
630 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
631 target_flags &= ~ARM_FLAG_APCS_FRAME;
632 }
633
634 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
635 from here where no function is being compiled currently. */
636 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
637 && TARGET_ARM)
638 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
639
640 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
641 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
642
643 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
644 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
645
646 /* If interworking is enabled then APCS-32 must be selected as well. */
647 if (TARGET_INTERWORK)
648 {
649 if (!TARGET_APCS_32)
650 warning ("interworking forces APCS-32 to be used" );
651 target_flags |= ARM_FLAG_APCS_32;
652 }
653
654 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
655 {
656 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
657 target_flags |= ARM_FLAG_APCS_FRAME;
658 }
659
660 if (TARGET_POKE_FUNCTION_NAME)
661 target_flags |= ARM_FLAG_APCS_FRAME;
662
663 if (TARGET_APCS_REENT && flag_pic)
664 error ("-fpic and -mapcs-reent are incompatible");
665
666 if (TARGET_APCS_REENT)
667 warning ("APCS reentrant code not supported. Ignored");
668
669 /* If this target is normally configured to use APCS frames, warn if they
670 are turned off and debugging is turned on. */
671 if (TARGET_ARM
672 && write_symbols != NO_DEBUG
673 && !TARGET_APCS_FRAME
674 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
675 warning ("-g with -mno-apcs-frame may not give sensible debugging");
676
677 /* If stack checking is disabled, we can use r10 as the PIC register,
678 which keeps r9 available. */
679 if (flag_pic)
680 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
681
682 if (TARGET_APCS_FLOAT)
683 warning ("passing floating point arguments in fp regs not yet supported");
684
685 /* Initialize boolean versions of the flags, for use in the arm.md file. */
686 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
687 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
688 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
689 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
690 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
691
692 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
693 arm_is_strong = (tune_flags & FL_STRONG) != 0;
694 thumb_code = (TARGET_ARM == 0);
695 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
696 && !(tune_flags & FL_ARCH4))) != 0;
697 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
698
699 /* Default value for floating point code... if no co-processor
700 bus, then schedule for emulated floating point. Otherwise,
701 assume the user has an FPA.
702 Note: this does not prevent use of floating point instructions,
703 -msoft-float does that. */
704 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
705
706 if (target_fp_name)
707 {
708 if (streq (target_fp_name, "2"))
709 arm_fpu_arch = FP_SOFT2;
710 else if (streq (target_fp_name, "3"))
711 arm_fpu_arch = FP_SOFT3;
712 else
713 error ("invalid floating point emulation option: -mfpe-%s",
714 target_fp_name);
715 }
716 else
717 arm_fpu_arch = FP_DEFAULT;
718
719 if (TARGET_FPE && arm_fpu != FP_HARD)
720 arm_fpu = FP_SOFT2;
721
722 /* For arm2/3 there is no need to do any scheduling if there is only
723 a floating point emulator, or we are doing software floating-point. */
724 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
725 && (tune_flags & FL_MODE32) == 0)
726 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
727
728 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
729
730 if (structure_size_string != NULL)
731 {
732 int size = strtol (structure_size_string, NULL, 0);
733
734 if (size == 8 || size == 32)
735 arm_structure_size_boundary = size;
736 else
737 warning ("structure size boundary can only be set to 8 or 32");
738 }
739
740 if (arm_pic_register_string != NULL)
741 {
742 int pic_register = decode_reg_name (arm_pic_register_string);
743
744 if (!flag_pic)
745 warning ("-mpic-register= is useless without -fpic");
746
747 /* Prevent the user from choosing an obviously stupid PIC register. */
748 else if (pic_register < 0 || call_used_regs[pic_register]
749 || pic_register == HARD_FRAME_POINTER_REGNUM
750 || pic_register == STACK_POINTER_REGNUM
751 || pic_register >= PC_REGNUM)
752 error ("unable to use '%s' for PIC register", arm_pic_register_string);
753 else
754 arm_pic_register = pic_register;
755 }
756
757 if (TARGET_THUMB && flag_schedule_insns)
758 {
759 /* Don't warn since it's on by default in -O2. */
760 flag_schedule_insns = 0;
761 }
762
763 /* If optimizing for space, don't synthesize constants.
764 For processors with load scheduling, it never costs more than 2 cycles
765 to load a constant, and the load scheduler may well reduce that to 1. */
766 if (optimize_size || (tune_flags & FL_LDSCHED))
767 arm_constant_limit = 1;
768
769 if (arm_arch_xscale)
770 arm_constant_limit = 2;
771
772 /* If optimizing for size, bump the number of instructions that we
773 are prepared to conditionally execute (even on a StrongARM).
774 Otherwise for the StrongARM, which has early execution of branches,
775 a sequence that is worth skipping is shorter. */
776 if (optimize_size)
777 max_insns_skipped = 6;
778 else if (arm_is_strong)
779 max_insns_skipped = 3;
780
781 /* Register global variables with the garbage collector. */
782 arm_add_gc_roots ();
783 }
784
785 static void
arm_add_gc_roots()786 arm_add_gc_roots ()
787 {
788 gcc_obstack_init(&minipool_obstack);
789 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
790 }
791
792 /* A table of known ARM exception types.
793 For use with the interrupt function attribute. */
794
795 typedef struct
796 {
797 const char *const arg;
798 const unsigned long return_value;
799 }
800 isr_attribute_arg;
801
802 static const isr_attribute_arg isr_attribute_args [] =
803 {
804 { "IRQ", ARM_FT_ISR },
805 { "irq", ARM_FT_ISR },
806 { "FIQ", ARM_FT_FIQ },
807 { "fiq", ARM_FT_FIQ },
808 { "ABORT", ARM_FT_ISR },
809 { "abort", ARM_FT_ISR },
810 { "ABORT", ARM_FT_ISR },
811 { "abort", ARM_FT_ISR },
812 { "UNDEF", ARM_FT_EXCEPTION },
813 { "undef", ARM_FT_EXCEPTION },
814 { "SWI", ARM_FT_EXCEPTION },
815 { "swi", ARM_FT_EXCEPTION },
816 { NULL, ARM_FT_NORMAL }
817 };
818
819 /* Returns the (interrupt) function type of the current
820 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
821
822 static unsigned long
arm_isr_value(argument)823 arm_isr_value (argument)
824 tree argument;
825 {
826 const isr_attribute_arg * ptr;
827 const char * arg;
828
829 /* No argument - default to IRQ. */
830 if (argument == NULL_TREE)
831 return ARM_FT_ISR;
832
833 /* Get the value of the argument. */
834 if (TREE_VALUE (argument) == NULL_TREE
835 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
836 return ARM_FT_UNKNOWN;
837
838 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
839
840 /* Check it against the list of known arguments. */
841 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++)
842 if (streq (arg, ptr->arg))
843 return ptr->return_value;
844
845 /* An unrecognized interrupt type. */
846 return ARM_FT_UNKNOWN;
847 }
848
849 /* Computes the type of the current function. */
850
851 static unsigned long
arm_compute_func_type()852 arm_compute_func_type ()
853 {
854 unsigned long type = ARM_FT_UNKNOWN;
855 tree a;
856 tree attr;
857
858 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
859 abort ();
860
861 /* Decide if the current function is volatile. Such functions
862 never return, and many memory cycles can be saved by not storing
863 register values that will never be needed again. This optimization
864 was added to speed up context switching in a kernel application. */
865 if (optimize > 0
866 && current_function_nothrow
867 && TREE_THIS_VOLATILE (current_function_decl))
868 type |= ARM_FT_VOLATILE;
869
870 if (current_function_needs_context)
871 type |= ARM_FT_NESTED;
872
873 attr = DECL_ATTRIBUTES (current_function_decl);
874
875 a = lookup_attribute ("naked", attr);
876 if (a != NULL_TREE)
877 type |= ARM_FT_NAKED;
878
879 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
880 type |= ARM_FT_EXCEPTION_HANDLER;
881 else
882 {
883 a = lookup_attribute ("isr", attr);
884 if (a == NULL_TREE)
885 a = lookup_attribute ("interrupt", attr);
886
887 if (a == NULL_TREE)
888 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
889 else
890 type |= arm_isr_value (TREE_VALUE (a));
891 }
892
893 return type;
894 }
895
896 /* Returns the type of the current function. */
897
898 unsigned long
arm_current_func_type()899 arm_current_func_type ()
900 {
901 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
902 cfun->machine->func_type = arm_compute_func_type ();
903
904 return cfun->machine->func_type;
905 }
906
907 /* Return 1 if it is possible to return using a single instruction. */
908
909 int
use_return_insn(iscond)910 use_return_insn (iscond)
911 int iscond;
912 {
913 int regno;
914 unsigned int func_type;
915 unsigned long saved_int_regs;
916
917 /* Never use a return instruction before reload has run. */
918 if (!reload_completed)
919 return 0;
920
921 func_type = arm_current_func_type ();
922
923 /* Naked functions and volatile functions need special
924 consideration. */
925 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
926 return 0;
927
928 /* So do interrupt functions that use the frame pointer. */
929 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
930 return 0;
931
932 /* As do variadic functions. */
933 if (current_function_pretend_args_size
934 || cfun->machine->uses_anonymous_args
935 /* Of if the function calls __builtin_eh_return () */
936 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
937 /* Or if there is no frame pointer and there is a stack adjustment. */
938 || ((arm_get_frame_size () + current_function_outgoing_args_size != 0)
939 && !frame_pointer_needed))
940 return 0;
941
942 saved_int_regs = arm_compute_save_reg_mask ();
943
944 /* Can't be done if interworking with Thumb, and any registers have been
945 stacked. */
946 if (TARGET_INTERWORK && saved_int_regs != 0)
947 return 0;
948
949 /* On StrongARM, conditional returns are expensive if they aren't
950 taken and multiple registers have been stacked. */
951 if (iscond && arm_is_strong)
952 {
953 /* Conditional return when just the LR is stored is a simple
954 conditional-load instruction, that's not expensive. */
955 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
956 return 0;
957
958 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
959 return 0;
960 }
961
962 /* If there are saved registers but the LR isn't saved, then we need
963 two instructions for the return. */
964 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
965 return 0;
966
967 /* Can't be done if any of the FPU regs are pushed,
968 since this also requires an insn. */
969 if (TARGET_HARD_FLOAT)
970 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
971 if (regs_ever_live[regno] && !call_used_regs[regno])
972 return 0;
973
974 return 1;
975 }
976
977 /* Return TRUE if int I is a valid immediate ARM constant. */
978
979 int
const_ok_for_arm(i)980 const_ok_for_arm (i)
981 HOST_WIDE_INT i;
982 {
983 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
984
985 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
986 be all zero, or all one. */
987 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
988 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
989 != ((~(unsigned HOST_WIDE_INT) 0)
990 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
991 return FALSE;
992
993 /* Fast return for 0 and powers of 2 */
994 if ((i & (i - 1)) == 0)
995 return TRUE;
996
997 do
998 {
999 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1000 return TRUE;
1001 mask =
1002 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1003 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1004 }
1005 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1006
1007 return FALSE;
1008 }
1009
1010 /* Return true if I is a valid constant for the operation CODE. */
1011 static int
const_ok_for_op(i,code)1012 const_ok_for_op (i, code)
1013 HOST_WIDE_INT i;
1014 enum rtx_code code;
1015 {
1016 if (const_ok_for_arm (i))
1017 return 1;
1018
1019 switch (code)
1020 {
1021 case PLUS:
1022 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1023
1024 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1025 case XOR:
1026 case IOR:
1027 return 0;
1028
1029 case AND:
1030 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1031
1032 default:
1033 abort ();
1034 }
1035 }
1036
1037 /* Emit a sequence of insns to handle a large constant.
1038 CODE is the code of the operation required, it can be any of SET, PLUS,
1039 IOR, AND, XOR, MINUS;
1040 MODE is the mode in which the operation is being performed;
1041 VAL is the integer to operate on;
1042 SOURCE is the other operand (a register, or a null-pointer for SET);
1043 SUBTARGETS means it is safe to create scratch registers if that will
1044 either produce a simpler sequence, or we will want to cse the values.
1045 Return value is the number of insns emitted. */
1046
1047 int
arm_split_constant(code,mode,val,target,source,subtargets)1048 arm_split_constant (code, mode, val, target, source, subtargets)
1049 enum rtx_code code;
1050 enum machine_mode mode;
1051 HOST_WIDE_INT val;
1052 rtx target;
1053 rtx source;
1054 int subtargets;
1055 {
1056 if (subtargets || code == SET
1057 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1058 && REGNO (target) != REGNO (source)))
1059 {
1060 /* After arm_reorg has been called, we can't fix up expensive
1061 constants by pushing them into memory so we must synthesize
1062 them in-line, regardless of the cost. This is only likely to
1063 be more costly on chips that have load delay slots and we are
1064 compiling without running the scheduler (so no splitting
1065 occurred before the final instruction emission).
1066
1067 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1068 */
1069 if (!after_arm_reorg
1070 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1071 > arm_constant_limit + (code != SET)))
1072 {
1073 if (code == SET)
1074 {
1075 /* Currently SET is the only monadic value for CODE, all
1076 the rest are diadic. */
1077 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1078 return 1;
1079 }
1080 else
1081 {
1082 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1083
1084 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1085 /* For MINUS, the value is subtracted from, since we never
1086 have subtraction of a constant. */
1087 if (code == MINUS)
1088 emit_insn (gen_rtx_SET (VOIDmode, target,
1089 gen_rtx_MINUS (mode, temp, source)));
1090 else
1091 emit_insn (gen_rtx_SET (VOIDmode, target,
1092 gen_rtx (code, mode, source, temp)));
1093 return 2;
1094 }
1095 }
1096 }
1097
1098 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1099 }
1100
1101 static int
count_insns_for_constant(remainder,i)1102 count_insns_for_constant (remainder, i)
1103 HOST_WIDE_INT remainder;
1104 int i;
1105 {
1106 HOST_WIDE_INT temp1;
1107 int num_insns = 0;
1108 do
1109 {
1110 int end;
1111
1112 if (i <= 0)
1113 i += 32;
1114 if (remainder & (3 << (i - 2)))
1115 {
1116 end = i - 8;
1117 if (end < 0)
1118 end += 32;
1119 temp1 = remainder & ((0x0ff << end)
1120 | ((i < end) ? (0xff >> (32 - end)) : 0));
1121 remainder &= ~temp1;
1122 num_insns++;
1123 i -= 6;
1124 }
1125 i -= 2;
1126 } while (remainder);
1127 return num_insns;
1128 }
1129
1130 /* As above, but extra parameter GENERATE which, if clear, suppresses
1131 RTL generation. */
1132
1133 static int
arm_gen_constant(code,mode,val,target,source,subtargets,generate)1134 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
1135 enum rtx_code code;
1136 enum machine_mode mode;
1137 HOST_WIDE_INT val;
1138 rtx target;
1139 rtx source;
1140 int subtargets;
1141 int generate;
1142 {
1143 int can_invert = 0;
1144 int can_negate = 0;
1145 int can_negate_initial = 0;
1146 int can_shift = 0;
1147 int i;
1148 int num_bits_set = 0;
1149 int set_sign_bit_copies = 0;
1150 int clear_sign_bit_copies = 0;
1151 int clear_zero_bit_copies = 0;
1152 int set_zero_bit_copies = 0;
1153 int insns = 0;
1154 unsigned HOST_WIDE_INT temp1, temp2;
1155 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1156
1157 /* Find out which operations are safe for a given CODE. Also do a quick
1158 check for degenerate cases; these can occur when DImode operations
1159 are split. */
1160 switch (code)
1161 {
1162 case SET:
1163 can_invert = 1;
1164 can_shift = 1;
1165 can_negate = 1;
1166 break;
1167
1168 case PLUS:
1169 can_negate = 1;
1170 can_negate_initial = 1;
1171 break;
1172
1173 case IOR:
1174 if (remainder == 0xffffffff)
1175 {
1176 if (generate)
1177 emit_insn (gen_rtx_SET (VOIDmode, target,
1178 GEN_INT (ARM_SIGN_EXTEND (val))));
1179 return 1;
1180 }
1181 if (remainder == 0)
1182 {
1183 if (reload_completed && rtx_equal_p (target, source))
1184 return 0;
1185 if (generate)
1186 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1187 return 1;
1188 }
1189 break;
1190
1191 case AND:
1192 if (remainder == 0)
1193 {
1194 if (generate)
1195 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1196 return 1;
1197 }
1198 if (remainder == 0xffffffff)
1199 {
1200 if (reload_completed && rtx_equal_p (target, source))
1201 return 0;
1202 if (generate)
1203 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1204 return 1;
1205 }
1206 can_invert = 1;
1207 break;
1208
1209 case XOR:
1210 if (remainder == 0)
1211 {
1212 if (reload_completed && rtx_equal_p (target, source))
1213 return 0;
1214 if (generate)
1215 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1216 return 1;
1217 }
1218 if (remainder == 0xffffffff)
1219 {
1220 if (generate)
1221 emit_insn (gen_rtx_SET (VOIDmode, target,
1222 gen_rtx_NOT (mode, source)));
1223 return 1;
1224 }
1225
1226 /* We don't know how to handle this yet below. */
1227 abort ();
1228
1229 case MINUS:
1230 /* We treat MINUS as (val - source), since (source - val) is always
1231 passed as (source + (-val)). */
1232 if (remainder == 0)
1233 {
1234 if (generate)
1235 emit_insn (gen_rtx_SET (VOIDmode, target,
1236 gen_rtx_NEG (mode, source)));
1237 return 1;
1238 }
1239 if (const_ok_for_arm (val))
1240 {
1241 if (generate)
1242 emit_insn (gen_rtx_SET (VOIDmode, target,
1243 gen_rtx_MINUS (mode, GEN_INT (val),
1244 source)));
1245 return 1;
1246 }
1247 can_negate = 1;
1248
1249 break;
1250
1251 default:
1252 abort ();
1253 }
1254
1255 /* If we can do it in one insn get out quickly. */
1256 if (const_ok_for_arm (val)
1257 || (can_negate_initial && const_ok_for_arm (-val))
1258 || (can_invert && const_ok_for_arm (~val)))
1259 {
1260 if (generate)
1261 emit_insn (gen_rtx_SET (VOIDmode, target,
1262 (source ? gen_rtx (code, mode, source,
1263 GEN_INT (val))
1264 : GEN_INT (val))));
1265 return 1;
1266 }
1267
1268 /* Calculate a few attributes that may be useful for specific
1269 optimizations. */
1270 for (i = 31; i >= 0; i--)
1271 {
1272 if ((remainder & (1 << i)) == 0)
1273 clear_sign_bit_copies++;
1274 else
1275 break;
1276 }
1277
1278 for (i = 31; i >= 0; i--)
1279 {
1280 if ((remainder & (1 << i)) != 0)
1281 set_sign_bit_copies++;
1282 else
1283 break;
1284 }
1285
1286 for (i = 0; i <= 31; i++)
1287 {
1288 if ((remainder & (1 << i)) == 0)
1289 clear_zero_bit_copies++;
1290 else
1291 break;
1292 }
1293
1294 for (i = 0; i <= 31; i++)
1295 {
1296 if ((remainder & (1 << i)) != 0)
1297 set_zero_bit_copies++;
1298 else
1299 break;
1300 }
1301
1302 switch (code)
1303 {
1304 case SET:
1305 /* See if we can do this by sign_extending a constant that is known
1306 to be negative. This is a good, way of doing it, since the shift
1307 may well merge into a subsequent insn. */
1308 if (set_sign_bit_copies > 1)
1309 {
1310 if (const_ok_for_arm
1311 (temp1 = ARM_SIGN_EXTEND (remainder
1312 << (set_sign_bit_copies - 1))))
1313 {
1314 if (generate)
1315 {
1316 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1317 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1318 GEN_INT (temp1)));
1319 emit_insn (gen_ashrsi3 (target, new_src,
1320 GEN_INT (set_sign_bit_copies - 1)));
1321 }
1322 return 2;
1323 }
1324 /* For an inverted constant, we will need to set the low bits,
1325 these will be shifted out of harm's way. */
1326 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1327 if (const_ok_for_arm (~temp1))
1328 {
1329 if (generate)
1330 {
1331 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1332 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1333 GEN_INT (temp1)));
1334 emit_insn (gen_ashrsi3 (target, new_src,
1335 GEN_INT (set_sign_bit_copies - 1)));
1336 }
1337 return 2;
1338 }
1339 }
1340
1341 /* See if we can generate this by setting the bottom (or the top)
1342 16 bits, and then shifting these into the other half of the
1343 word. We only look for the simplest cases, to do more would cost
1344 too much. Be careful, however, not to generate this when the
1345 alternative would take fewer insns. */
1346 if (val & 0xffff0000)
1347 {
1348 temp1 = remainder & 0xffff0000;
1349 temp2 = remainder & 0x0000ffff;
1350
1351 /* Overlaps outside this range are best done using other methods. */
1352 for (i = 9; i < 24; i++)
1353 {
1354 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1355 && !const_ok_for_arm (temp2))
1356 {
1357 rtx new_src = (subtargets
1358 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1359 : target);
1360 insns = arm_gen_constant (code, mode, temp2, new_src,
1361 source, subtargets, generate);
1362 source = new_src;
1363 if (generate)
1364 emit_insn (gen_rtx_SET
1365 (VOIDmode, target,
1366 gen_rtx_IOR (mode,
1367 gen_rtx_ASHIFT (mode, source,
1368 GEN_INT (i)),
1369 source)));
1370 return insns + 1;
1371 }
1372 }
1373
1374 /* Don't duplicate cases already considered. */
1375 for (i = 17; i < 24; i++)
1376 {
1377 if (((temp1 | (temp1 >> i)) == remainder)
1378 && !const_ok_for_arm (temp1))
1379 {
1380 rtx new_src = (subtargets
1381 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1382 : target);
1383 insns = arm_gen_constant (code, mode, temp1, new_src,
1384 source, subtargets, generate);
1385 source = new_src;
1386 if (generate)
1387 emit_insn
1388 (gen_rtx_SET (VOIDmode, target,
1389 gen_rtx_IOR
1390 (mode,
1391 gen_rtx_LSHIFTRT (mode, source,
1392 GEN_INT (i)),
1393 source)));
1394 return insns + 1;
1395 }
1396 }
1397 }
1398 break;
1399
1400 case IOR:
1401 case XOR:
1402 /* If we have IOR or XOR, and the constant can be loaded in a
1403 single instruction, and we can find a temporary to put it in,
1404 then this can be done in two instructions instead of 3-4. */
1405 if (subtargets
1406 /* TARGET can't be NULL if SUBTARGETS is 0 */
1407 || (reload_completed && !reg_mentioned_p (target, source)))
1408 {
1409 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1410 {
1411 if (generate)
1412 {
1413 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1414
1415 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1416 emit_insn (gen_rtx_SET (VOIDmode, target,
1417 gen_rtx (code, mode, source, sub)));
1418 }
1419 return 2;
1420 }
1421 }
1422
1423 if (code == XOR)
1424 break;
1425
1426 if (set_sign_bit_copies > 8
1427 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1428 {
1429 if (generate)
1430 {
1431 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1432 rtx shift = GEN_INT (set_sign_bit_copies);
1433
1434 emit_insn (gen_rtx_SET (VOIDmode, sub,
1435 gen_rtx_NOT (mode,
1436 gen_rtx_ASHIFT (mode,
1437 source,
1438 shift))));
1439 emit_insn (gen_rtx_SET (VOIDmode, target,
1440 gen_rtx_NOT (mode,
1441 gen_rtx_LSHIFTRT (mode, sub,
1442 shift))));
1443 }
1444 return 2;
1445 }
1446
1447 if (set_zero_bit_copies > 8
1448 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1449 {
1450 if (generate)
1451 {
1452 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1453 rtx shift = GEN_INT (set_zero_bit_copies);
1454
1455 emit_insn (gen_rtx_SET (VOIDmode, sub,
1456 gen_rtx_NOT (mode,
1457 gen_rtx_LSHIFTRT (mode,
1458 source,
1459 shift))));
1460 emit_insn (gen_rtx_SET (VOIDmode, target,
1461 gen_rtx_NOT (mode,
1462 gen_rtx_ASHIFT (mode, sub,
1463 shift))));
1464 }
1465 return 2;
1466 }
1467
1468 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1469 {
1470 if (generate)
1471 {
1472 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1473 emit_insn (gen_rtx_SET (VOIDmode, sub,
1474 gen_rtx_NOT (mode, source)));
1475 source = sub;
1476 if (subtargets)
1477 sub = gen_reg_rtx (mode);
1478 emit_insn (gen_rtx_SET (VOIDmode, sub,
1479 gen_rtx_AND (mode, source,
1480 GEN_INT (temp1))));
1481 emit_insn (gen_rtx_SET (VOIDmode, target,
1482 gen_rtx_NOT (mode, sub)));
1483 }
1484 return 3;
1485 }
1486 break;
1487
1488 case AND:
1489 /* See if two shifts will do 2 or more insn's worth of work. */
1490 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1491 {
1492 HOST_WIDE_INT shift_mask = ((0xffffffff
1493 << (32 - clear_sign_bit_copies))
1494 & 0xffffffff);
1495
1496 if ((remainder | shift_mask) != 0xffffffff)
1497 {
1498 if (generate)
1499 {
1500 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1501 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1502 new_src, source, subtargets, 1);
1503 source = new_src;
1504 }
1505 else
1506 {
1507 rtx targ = subtargets ? NULL_RTX : target;
1508 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1509 targ, source, subtargets, 0);
1510 }
1511 }
1512
1513 if (generate)
1514 {
1515 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1516 rtx shift = GEN_INT (clear_sign_bit_copies);
1517
1518 emit_insn (gen_ashlsi3 (new_src, source, shift));
1519 emit_insn (gen_lshrsi3 (target, new_src, shift));
1520 }
1521
1522 return insns + 2;
1523 }
1524
1525 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1526 {
1527 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1528
1529 if ((remainder | shift_mask) != 0xffffffff)
1530 {
1531 if (generate)
1532 {
1533 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1534
1535 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1536 new_src, source, subtargets, 1);
1537 source = new_src;
1538 }
1539 else
1540 {
1541 rtx targ = subtargets ? NULL_RTX : target;
1542
1543 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1544 targ, source, subtargets, 0);
1545 }
1546 }
1547
1548 if (generate)
1549 {
1550 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1551 rtx shift = GEN_INT (clear_zero_bit_copies);
1552
1553 emit_insn (gen_lshrsi3 (new_src, source, shift));
1554 emit_insn (gen_ashlsi3 (target, new_src, shift));
1555 }
1556
1557 return insns + 2;
1558 }
1559
1560 break;
1561
1562 default:
1563 break;
1564 }
1565
1566 for (i = 0; i < 32; i++)
1567 if (remainder & (1 << i))
1568 num_bits_set++;
1569
1570 if (code == AND || (can_invert && num_bits_set > 16))
1571 remainder = (~remainder) & 0xffffffff;
1572 else if (code == PLUS && num_bits_set > 16)
1573 remainder = (-remainder) & 0xffffffff;
1574 else
1575 {
1576 can_invert = 0;
1577 can_negate = 0;
1578 }
1579
1580 /* Now try and find a way of doing the job in either two or three
1581 instructions.
1582 We start by looking for the largest block of zeros that are aligned on
1583 a 2-bit boundary, we then fill up the temps, wrapping around to the
1584 top of the word when we drop off the bottom.
1585 In the worst case this code should produce no more than four insns. */
1586 {
1587 int best_start = 0;
1588 int best_consecutive_zeros = 0;
1589
1590 for (i = 0; i < 32; i += 2)
1591 {
1592 int consecutive_zeros = 0;
1593
1594 if (!(remainder & (3 << i)))
1595 {
1596 while ((i < 32) && !(remainder & (3 << i)))
1597 {
1598 consecutive_zeros += 2;
1599 i += 2;
1600 }
1601 if (consecutive_zeros > best_consecutive_zeros)
1602 {
1603 best_consecutive_zeros = consecutive_zeros;
1604 best_start = i - consecutive_zeros;
1605 }
1606 i -= 2;
1607 }
1608 }
1609
1610 /* So long as it won't require any more insns to do so, it's
1611 desirable to emit a small constant (in bits 0...9) in the last
1612 insn. This way there is more chance that it can be combined with
1613 a later addressing insn to form a pre-indexed load or store
1614 operation. Consider:
1615
1616 *((volatile int *)0xe0000100) = 1;
1617 *((volatile int *)0xe0000110) = 2;
1618
1619 We want this to wind up as:
1620
1621 mov rA, #0xe0000000
1622 mov rB, #1
1623 str rB, [rA, #0x100]
1624 mov rB, #2
1625 str rB, [rA, #0x110]
1626
1627 rather than having to synthesize both large constants from scratch.
1628
1629 Therefore, we calculate how many insns would be required to emit
1630 the constant starting from `best_start', and also starting from
1631 zero (ie with bit 31 first to be output). If `best_start' doesn't
1632 yield a shorter sequence, we may as well use zero. */
1633 if (best_start != 0
1634 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1635 && (count_insns_for_constant (remainder, 0) <=
1636 count_insns_for_constant (remainder, best_start)))
1637 best_start = 0;
1638
1639 /* Now start emitting the insns. */
1640 i = best_start;
1641 do
1642 {
1643 int end;
1644
1645 if (i <= 0)
1646 i += 32;
1647 if (remainder & (3 << (i - 2)))
1648 {
1649 end = i - 8;
1650 if (end < 0)
1651 end += 32;
1652 temp1 = remainder & ((0x0ff << end)
1653 | ((i < end) ? (0xff >> (32 - end)) : 0));
1654 remainder &= ~temp1;
1655
1656 if (generate)
1657 {
1658 rtx new_src, temp1_rtx;
1659
1660 if (code == SET || code == MINUS)
1661 {
1662 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1663 if (can_invert && code != MINUS)
1664 temp1 = ~temp1;
1665 }
1666 else
1667 {
1668 if (remainder && subtargets)
1669 new_src = gen_reg_rtx (mode);
1670 else
1671 new_src = target;
1672 if (can_invert)
1673 temp1 = ~temp1;
1674 else if (can_negate)
1675 temp1 = -temp1;
1676 }
1677
1678 temp1 = trunc_int_for_mode (temp1, mode);
1679 temp1_rtx = GEN_INT (temp1);
1680
1681 if (code == SET)
1682 ;
1683 else if (code == MINUS)
1684 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1685 else
1686 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1687
1688 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1689 source = new_src;
1690 }
1691
1692 if (code == SET)
1693 {
1694 can_invert = 0;
1695 code = PLUS;
1696 }
1697 else if (code == MINUS)
1698 code = PLUS;
1699
1700 insns++;
1701 i -= 6;
1702 }
1703 i -= 2;
1704 }
1705 while (remainder);
1706 }
1707
1708 return insns;
1709 }
1710
1711 /* Canonicalize a comparison so that we are more likely to recognize it.
1712 This can be done for a few constant compares, where we can make the
1713 immediate value easier to load. */
1714
1715 enum rtx_code
arm_canonicalize_comparison(code,op1)1716 arm_canonicalize_comparison (code, op1)
1717 enum rtx_code code;
1718 rtx * op1;
1719 {
1720 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1721
1722 switch (code)
1723 {
1724 case EQ:
1725 case NE:
1726 return code;
1727
1728 case GT:
1729 case LE:
1730 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1731 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1732 {
1733 *op1 = GEN_INT (i + 1);
1734 return code == GT ? GE : LT;
1735 }
1736 break;
1737
1738 case GE:
1739 case LT:
1740 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1741 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1742 {
1743 *op1 = GEN_INT (i - 1);
1744 return code == GE ? GT : LE;
1745 }
1746 break;
1747
1748 case GTU:
1749 case LEU:
1750 if (i != ~((unsigned HOST_WIDE_INT) 0)
1751 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1752 {
1753 *op1 = GEN_INT (i + 1);
1754 return code == GTU ? GEU : LTU;
1755 }
1756 break;
1757
1758 case GEU:
1759 case LTU:
1760 if (i != 0
1761 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1762 {
1763 *op1 = GEN_INT (i - 1);
1764 return code == GEU ? GTU : LEU;
1765 }
1766 break;
1767
1768 default:
1769 abort ();
1770 }
1771
1772 return code;
1773 }
1774
1775 /* Decide whether a type should be returned in memory (true)
1776 or in a register (false). This is called by the macro
1777 RETURN_IN_MEMORY. */
1778
1779 int
arm_return_in_memory(type)1780 arm_return_in_memory (type)
1781 tree type;
1782 {
1783 HOST_WIDE_INT size;
1784
1785 if (!AGGREGATE_TYPE_P (type))
1786 /* All simple types are returned in registers. */
1787 return 0;
1788
1789 size = int_size_in_bytes (type);
1790
1791 if (TARGET_ATPCS)
1792 {
1793 /* ATPCS returns aggregate types in memory only if they are
1794 larger than a word (or are variable size). */
1795 return (size < 0 || size > UNITS_PER_WORD);
1796 }
1797
1798 /* For the arm-wince targets we choose to be compitable with Microsoft's
1799 ARM and Thumb compilers, which always return aggregates in memory. */
1800 #ifndef ARM_WINCE
1801 /* All structures/unions bigger than one word are returned in memory.
1802 Also catch the case where int_size_in_bytes returns -1. In this case
1803 the aggregate is either huge or of varaible size, and in either case
1804 we will want to return it via memory and not in a register. */
1805 if (size < 0 || size > UNITS_PER_WORD)
1806 return 1;
1807
1808 if (TREE_CODE (type) == RECORD_TYPE)
1809 {
1810 tree field;
1811
1812 /* For a struct the APCS says that we only return in a register
1813 if the type is 'integer like' and every addressable element
1814 has an offset of zero. For practical purposes this means
1815 that the structure can have at most one non bit-field element
1816 and that this element must be the first one in the structure. */
1817
1818 /* Find the first field, ignoring non FIELD_DECL things which will
1819 have been created by C++. */
1820 for (field = TYPE_FIELDS (type);
1821 field && TREE_CODE (field) != FIELD_DECL;
1822 field = TREE_CHAIN (field))
1823 continue;
1824
1825 if (field == NULL)
1826 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1827
1828 /* Check that the first field is valid for returning in a register. */
1829
1830 /* ... Floats are not allowed */
1831 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1832 return 1;
1833
1834 /* ... Aggregates that are not themselves valid for returning in
1835 a register are not allowed. */
1836 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1837 return 1;
1838
1839 /* Now check the remaining fields, if any. Only bitfields are allowed,
1840 since they are not addressable. */
1841 for (field = TREE_CHAIN (field);
1842 field;
1843 field = TREE_CHAIN (field))
1844 {
1845 if (TREE_CODE (field) != FIELD_DECL)
1846 continue;
1847
1848 if (!DECL_BIT_FIELD_TYPE (field))
1849 return 1;
1850 }
1851
1852 return 0;
1853 }
1854
1855 if (TREE_CODE (type) == UNION_TYPE)
1856 {
1857 tree field;
1858
1859 /* Unions can be returned in registers if every element is
1860 integral, or can be returned in an integer register. */
1861 for (field = TYPE_FIELDS (type);
1862 field;
1863 field = TREE_CHAIN (field))
1864 {
1865 if (TREE_CODE (field) != FIELD_DECL)
1866 continue;
1867
1868 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1869 return 1;
1870
1871 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1872 return 1;
1873 }
1874
1875 return 0;
1876 }
1877 #endif /* not ARM_WINCE */
1878
1879 /* Return all other types in memory. */
1880 return 1;
1881 }
1882
1883 /* Indicate whether or not words of a double are in big-endian order. */
1884
1885 int
arm_float_words_big_endian()1886 arm_float_words_big_endian ()
1887 {
1888
1889 /* For FPA, float words are always big-endian. For VFP, floats words
1890 follow the memory system mode. */
1891
1892 if (TARGET_HARD_FLOAT)
1893 {
1894 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1895 return 1;
1896 }
1897
1898 if (TARGET_VFP)
1899 return (TARGET_BIG_END ? 1 : 0);
1900
1901 return 1;
1902 }
1903
1904 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1905 for a call to a function whose data type is FNTYPE.
1906 For a library call, FNTYPE is NULL. */
1907 void
arm_init_cumulative_args(pcum,fntype,libname,indirect)1908 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1909 CUMULATIVE_ARGS * pcum;
1910 tree fntype;
1911 rtx libname ATTRIBUTE_UNUSED;
1912 int indirect ATTRIBUTE_UNUSED;
1913 {
1914 /* On the ARM, the offset starts at 0. */
1915 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1916
1917 pcum->call_cookie = CALL_NORMAL;
1918
1919 if (TARGET_LONG_CALLS)
1920 pcum->call_cookie = CALL_LONG;
1921
1922 /* Check for long call/short call attributes. The attributes
1923 override any command line option. */
1924 if (fntype)
1925 {
1926 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1927 pcum->call_cookie = CALL_SHORT;
1928 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1929 pcum->call_cookie = CALL_LONG;
1930 }
1931 }
1932
1933 /* Determine where to put an argument to a function.
1934 Value is zero to push the argument on the stack,
1935 or a hard register in which to store the argument.
1936
1937 MODE is the argument's machine mode.
1938 TYPE is the data type of the argument (as a tree).
1939 This is null for libcalls where that information may
1940 not be available.
1941 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1942 the preceding args and about the function being called.
1943 NAMED is nonzero if this argument is a named parameter
1944 (otherwise it is an extra parameter matching an ellipsis). */
1945
1946 rtx
arm_function_arg(pcum,mode,type,named)1947 arm_function_arg (pcum, mode, type, named)
1948 CUMULATIVE_ARGS * pcum;
1949 enum machine_mode mode;
1950 tree type ATTRIBUTE_UNUSED;
1951 int named;
1952 {
1953 if (mode == VOIDmode)
1954 /* Compute operand 2 of the call insn. */
1955 return GEN_INT (pcum->call_cookie);
1956
1957 if (!named || pcum->nregs >= NUM_ARG_REGS)
1958 return NULL_RTX;
1959
1960 return gen_rtx_REG (mode, pcum->nregs);
1961 }
1962
1963 /* Variable sized types are passed by reference. This is a GCC
1964 extension to the ARM ABI. */
1965
1966 int
arm_function_arg_pass_by_reference(cum,mode,type,named)1967 arm_function_arg_pass_by_reference (cum, mode, type, named)
1968 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
1969 enum machine_mode mode ATTRIBUTE_UNUSED;
1970 tree type;
1971 int named ATTRIBUTE_UNUSED;
1972 {
1973 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
1974 }
1975
1976 /* Implement va_arg. */
1977
1978 rtx
arm_va_arg(valist,type)1979 arm_va_arg (valist, type)
1980 tree valist, type;
1981 {
1982 /* Variable sized types are passed by reference. */
1983 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
1984 {
1985 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
1986 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
1987 }
1988
1989 return std_expand_builtin_va_arg (valist, type);
1990 }
1991
1992 /* Encode the current state of the #pragma [no_]long_calls. */
1993 typedef enum
1994 {
1995 OFF, /* No #pramgma [no_]long_calls is in effect. */
1996 LONG, /* #pragma long_calls is in effect. */
1997 SHORT /* #pragma no_long_calls is in effect. */
1998 } arm_pragma_enum;
1999
2000 static arm_pragma_enum arm_pragma_long_calls = OFF;
2001
2002 void
arm_pr_long_calls(pfile)2003 arm_pr_long_calls (pfile)
2004 cpp_reader * pfile ATTRIBUTE_UNUSED;
2005 {
2006 arm_pragma_long_calls = LONG;
2007 }
2008
2009 void
arm_pr_no_long_calls(pfile)2010 arm_pr_no_long_calls (pfile)
2011 cpp_reader * pfile ATTRIBUTE_UNUSED;
2012 {
2013 arm_pragma_long_calls = SHORT;
2014 }
2015
2016 void
arm_pr_long_calls_off(pfile)2017 arm_pr_long_calls_off (pfile)
2018 cpp_reader * pfile ATTRIBUTE_UNUSED;
2019 {
2020 arm_pragma_long_calls = OFF;
2021 }
2022
2023 /* Table of machine attributes. */
2024 const struct attribute_spec arm_attribute_table[] =
2025 {
2026 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2027 /* Function calls made to this symbol must be done indirectly, because
2028 it may lie outside of the 26 bit addressing range of a normal function
2029 call. */
2030 { "long_call", 0, 0, false, true, true, NULL },
2031 /* Whereas these functions are always known to reside within the 26 bit
2032 addressing range. */
2033 { "short_call", 0, 0, false, true, true, NULL },
2034 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2035 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2036 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2037 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2038 #ifdef ARM_PE
2039 /* ARM/PE has three new attributes:
2040 interfacearm - ?
2041 dllexport - for exporting a function/variable that will live in a dll
2042 dllimport - for importing a function/variable from a dll
2043
2044 Microsoft allows multiple declspecs in one __declspec, separating
2045 them with spaces. We do NOT support this. Instead, use __declspec
2046 multiple times.
2047 */
2048 { "dllimport", 0, 0, true, false, false, NULL },
2049 { "dllexport", 0, 0, true, false, false, NULL },
2050 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2051 #endif
2052 { NULL, 0, 0, false, false, false, NULL }
2053 };
2054
2055 /* Handle an attribute requiring a FUNCTION_DECL;
2056 arguments as in struct attribute_spec.handler. */
2057
2058 static tree
arm_handle_fndecl_attribute(node,name,args,flags,no_add_attrs)2059 arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
2060 tree * node;
2061 tree name;
2062 tree args ATTRIBUTE_UNUSED;
2063 int flags ATTRIBUTE_UNUSED;
2064 bool * no_add_attrs;
2065 {
2066 if (TREE_CODE (*node) != FUNCTION_DECL)
2067 {
2068 warning ("`%s' attribute only applies to functions",
2069 IDENTIFIER_POINTER (name));
2070 *no_add_attrs = true;
2071 }
2072
2073 return NULL_TREE;
2074 }
2075
2076 /* Handle an "interrupt" or "isr" attribute;
2077 arguments as in struct attribute_spec.handler. */
2078
2079 static tree
arm_handle_isr_attribute(node,name,args,flags,no_add_attrs)2080 arm_handle_isr_attribute (node, name, args, flags, no_add_attrs)
2081 tree * node;
2082 tree name;
2083 tree args;
2084 int flags;
2085 bool * no_add_attrs;
2086 {
2087 if (DECL_P (*node))
2088 {
2089 if (TREE_CODE (*node) != FUNCTION_DECL)
2090 {
2091 warning ("`%s' attribute only applies to functions",
2092 IDENTIFIER_POINTER (name));
2093 *no_add_attrs = true;
2094 }
2095 /* FIXME: the argument if any is checked for type attributes;
2096 should it be checked for decl ones? */
2097 }
2098 else
2099 {
2100 if (TREE_CODE (*node) == FUNCTION_TYPE
2101 || TREE_CODE (*node) == METHOD_TYPE)
2102 {
2103 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2104 {
2105 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2106 *no_add_attrs = true;
2107 }
2108 }
2109 else if (TREE_CODE (*node) == POINTER_TYPE
2110 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2111 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2112 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2113 {
2114 *node = build_type_copy (*node);
2115 TREE_TYPE (*node) = build_type_attribute_variant
2116 (TREE_TYPE (*node),
2117 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2118 *no_add_attrs = true;
2119 }
2120 else
2121 {
2122 /* Possibly pass this attribute on from the type to a decl. */
2123 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2124 | (int) ATTR_FLAG_FUNCTION_NEXT
2125 | (int) ATTR_FLAG_ARRAY_NEXT))
2126 {
2127 *no_add_attrs = true;
2128 return tree_cons (name, args, NULL_TREE);
2129 }
2130 else
2131 {
2132 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2133 }
2134 }
2135 }
2136
2137 return NULL_TREE;
2138 }
2139
2140 /* Return 0 if the attributes for two types are incompatible, 1 if they
2141 are compatible, and 2 if they are nearly compatible (which causes a
2142 warning to be generated). */
2143
2144 static int
arm_comp_type_attributes(type1,type2)2145 arm_comp_type_attributes (type1, type2)
2146 tree type1;
2147 tree type2;
2148 {
2149 int l1, l2, s1, s2;
2150
2151 /* Check for mismatch of non-default calling convention. */
2152 if (TREE_CODE (type1) != FUNCTION_TYPE)
2153 return 1;
2154
2155 /* Check for mismatched call attributes. */
2156 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2157 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2158 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2159 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2160
2161 /* Only bother to check if an attribute is defined. */
2162 if (l1 | l2 | s1 | s2)
2163 {
2164 /* If one type has an attribute, the other must have the same attribute. */
2165 if ((l1 != l2) || (s1 != s2))
2166 return 0;
2167
2168 /* Disallow mixed attributes. */
2169 if ((l1 & s2) || (l2 & s1))
2170 return 0;
2171 }
2172
2173 /* Check for mismatched ISR attribute. */
2174 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2175 if (! l1)
2176 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2177 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2178 if (! l2)
2179 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2180 if (l1 != l2)
2181 return 0;
2182
2183 return 1;
2184 }
2185
2186 /* Encode long_call or short_call attribute by prefixing
2187 symbol name in DECL with a special character FLAG. */
2188
2189 void
arm_encode_call_attribute(decl,flag)2190 arm_encode_call_attribute (decl, flag)
2191 tree decl;
2192 int flag;
2193 {
2194 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2195 int len = strlen (str);
2196 char * newstr;
2197
2198 /* Do not allow weak functions to be treated as short call. */
2199 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2200 return;
2201
2202 newstr = alloca (len + 2);
2203 newstr[0] = flag;
2204 strcpy (newstr + 1, str);
2205
2206 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2207 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2208 }
2209
2210 /* Assigns default attributes to newly defined type. This is used to
2211 set short_call/long_call attributes for function types of
2212 functions defined inside corresponding #pragma scopes. */
2213
2214 static void
arm_set_default_type_attributes(type)2215 arm_set_default_type_attributes (type)
2216 tree type;
2217 {
2218 /* Add __attribute__ ((long_call)) to all functions, when
2219 inside #pragma long_calls or __attribute__ ((short_call)),
2220 when inside #pragma no_long_calls. */
2221 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2222 {
2223 tree type_attr_list, attr_name;
2224 type_attr_list = TYPE_ATTRIBUTES (type);
2225
2226 if (arm_pragma_long_calls == LONG)
2227 attr_name = get_identifier ("long_call");
2228 else if (arm_pragma_long_calls == SHORT)
2229 attr_name = get_identifier ("short_call");
2230 else
2231 return;
2232
2233 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2234 TYPE_ATTRIBUTES (type) = type_attr_list;
2235 }
2236 }
2237
2238 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2239 defined within the current compilation unit. If this caanot be
2240 determined, then 0 is returned. */
2241
2242 static int
current_file_function_operand(sym_ref)2243 current_file_function_operand (sym_ref)
2244 rtx sym_ref;
2245 {
2246 /* This is a bit of a fib. A function will have a short call flag
2247 applied to its name if it has the short call attribute, or it has
2248 already been defined within the current compilation unit. */
2249 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2250 return 1;
2251
2252 /* The current function is always defined within the current compilation
2253 unit. if it s a weak definition however, then this may not be the real
2254 definition of the function, and so we have to say no. */
2255 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2256 && !DECL_WEAK (current_function_decl))
2257 return 1;
2258
2259 /* We cannot make the determination - default to returning 0. */
2260 return 0;
2261 }
2262
2263 /* Return nonzero if a 32 bit "long_call" should be generated for
2264 this call. We generate a long_call if the function:
2265
2266 a. has an __attribute__((long call))
2267 or b. is within the scope of a #pragma long_calls
2268 or c. the -mlong-calls command line switch has been specified
2269
2270 However we do not generate a long call if the function:
2271
2272 d. has an __attribute__ ((short_call))
2273 or e. is inside the scope of a #pragma no_long_calls
2274 or f. has an __attribute__ ((section))
2275 or g. is defined within the current compilation unit.
2276
2277 This function will be called by C fragments contained in the machine
2278 description file. CALL_REF and CALL_COOKIE correspond to the matched
2279 rtl operands. CALL_SYMBOL is used to distinguish between
2280 two different callers of the function. It is set to 1 in the
2281 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2282 and "call_value" patterns. This is because of the difference in the
2283 SYM_REFs passed by these patterns. */
2284
2285 int
arm_is_longcall_p(sym_ref,call_cookie,call_symbol)2286 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
2287 rtx sym_ref;
2288 int call_cookie;
2289 int call_symbol;
2290 {
2291 if (!call_symbol)
2292 {
2293 if (GET_CODE (sym_ref) != MEM)
2294 return 0;
2295
2296 sym_ref = XEXP (sym_ref, 0);
2297 }
2298
2299 if (GET_CODE (sym_ref) != SYMBOL_REF)
2300 return 0;
2301
2302 if (call_cookie & CALL_SHORT)
2303 return 0;
2304
2305 if (TARGET_LONG_CALLS && flag_function_sections)
2306 return 1;
2307
2308 if (current_file_function_operand (sym_ref))
2309 return 0;
2310
2311 return (call_cookie & CALL_LONG)
2312 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2313 || TARGET_LONG_CALLS;
2314 }
2315
2316 /* Return nonzero if it is ok to make a tail-call to DECL. */
2317
2318 int
arm_function_ok_for_sibcall(decl)2319 arm_function_ok_for_sibcall (decl)
2320 tree decl;
2321 {
2322 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2323
2324 /* Never tailcall something for which we have no decl, or if we
2325 are in Thumb mode. */
2326 if (decl == NULL || TARGET_THUMB)
2327 return 0;
2328
2329 /* Get the calling method. */
2330 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2331 call_type = CALL_SHORT;
2332 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2333 call_type = CALL_LONG;
2334
2335 /* Cannot tail-call to long calls, since these are out of range of
2336 a branch instruction. However, if not compiling PIC, we know
2337 we can reach the symbol if it is in this compilation unit. */
2338 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2339 return 0;
2340
2341 /* If we are interworking and the function is not declared static
2342 then we can't tail-call it unless we know that it exists in this
2343 compilation unit (since it might be a Thumb routine). */
2344 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2345 return 0;
2346
2347 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2348 if (IS_INTERRUPT (arm_current_func_type ()))
2349 return 0;
2350
2351 /* Everything else is ok. */
2352 return 1;
2353 }
2354
2355
2356 int
legitimate_pic_operand_p(x)2357 legitimate_pic_operand_p (x)
2358 rtx x;
2359 {
2360 if (CONSTANT_P (x)
2361 && flag_pic
2362 && (GET_CODE (x) == SYMBOL_REF
2363 || (GET_CODE (x) == CONST
2364 && GET_CODE (XEXP (x, 0)) == PLUS
2365 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2366 return 0;
2367
2368 return 1;
2369 }
2370
2371 rtx
legitimize_pic_address(orig,mode,reg)2372 legitimize_pic_address (orig, mode, reg)
2373 rtx orig;
2374 enum machine_mode mode;
2375 rtx reg;
2376 {
2377 if (GET_CODE (orig) == SYMBOL_REF
2378 || GET_CODE (orig) == LABEL_REF)
2379 {
2380 #ifndef AOF_ASSEMBLER
2381 rtx pic_ref, address;
2382 #endif
2383 rtx insn;
2384 int subregs = 0;
2385
2386 if (reg == 0)
2387 {
2388 if (no_new_pseudos)
2389 abort ();
2390 else
2391 reg = gen_reg_rtx (Pmode);
2392
2393 subregs = 1;
2394 }
2395
2396 #ifdef AOF_ASSEMBLER
2397 /* The AOF assembler can generate relocations for these directly, and
2398 understands that the PIC register has to be added into the offset. */
2399 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2400 #else
2401 if (subregs)
2402 address = gen_reg_rtx (Pmode);
2403 else
2404 address = reg;
2405
2406 if (TARGET_ARM)
2407 emit_insn (gen_pic_load_addr_arm (address, orig));
2408 else
2409 emit_insn (gen_pic_load_addr_thumb (address, orig));
2410
2411 if ((GET_CODE (orig) == LABEL_REF
2412 || (GET_CODE (orig) == SYMBOL_REF &&
2413 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig, 0))))
2414 && NEED_GOT_RELOC)
2415 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2416 else
2417 {
2418 pic_ref = gen_rtx_MEM (Pmode,
2419 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2420 address));
2421 RTX_UNCHANGING_P (pic_ref) = 1;
2422 }
2423
2424 insn = emit_move_insn (reg, pic_ref);
2425 #endif
2426 current_function_uses_pic_offset_table = 1;
2427 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2428 by loop. */
2429 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2430 REG_NOTES (insn));
2431 return reg;
2432 }
2433 else if (GET_CODE (orig) == CONST)
2434 {
2435 rtx base, offset;
2436
2437 if (GET_CODE (XEXP (orig, 0)) == PLUS
2438 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2439 return orig;
2440
2441 if (reg == 0)
2442 {
2443 if (no_new_pseudos)
2444 abort ();
2445 else
2446 reg = gen_reg_rtx (Pmode);
2447 }
2448
2449 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2450 {
2451 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2452 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2453 base == reg ? 0 : reg);
2454 }
2455 else
2456 abort ();
2457
2458 if (GET_CODE (offset) == CONST_INT)
2459 {
2460 /* The base register doesn't really matter, we only want to
2461 test the index for the appropriate mode. */
2462 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
2463
2464 if (!no_new_pseudos)
2465 offset = force_reg (Pmode, offset);
2466 else
2467 abort ();
2468
2469 win:
2470 if (GET_CODE (offset) == CONST_INT)
2471 return plus_constant (base, INTVAL (offset));
2472 }
2473
2474 if (GET_MODE_SIZE (mode) > 4
2475 && (GET_MODE_CLASS (mode) == MODE_INT
2476 || TARGET_SOFT_FLOAT))
2477 {
2478 emit_insn (gen_addsi3 (reg, base, offset));
2479 return reg;
2480 }
2481
2482 return gen_rtx_PLUS (Pmode, base, offset);
2483 }
2484
2485 return orig;
2486 }
2487
2488 /* Generate code to load the PIC register. PROLOGUE is true if
2489 called from arm_expand_prologue (in which case we want the
2490 generated insns at the start of the function); false if called
2491 by an exception receiver that needs the PIC register reloaded
2492 (in which case the insns are just dumped at the current location). */
2493
2494 void
arm_finalize_pic(prologue)2495 arm_finalize_pic (prologue)
2496 int prologue ATTRIBUTE_UNUSED;
2497 {
2498 #ifndef AOF_ASSEMBLER
2499 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2500 rtx global_offset_table;
2501
2502 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2503 return;
2504
2505 if (!flag_pic)
2506 abort ();
2507
2508 start_sequence ();
2509 l1 = gen_label_rtx ();
2510
2511 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2512 /* On the ARM the PC register contains 'dot + 8' at the time of the
2513 addition, on the Thumb it is 'dot + 4'. */
2514 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2515 if (GOT_PCREL)
2516 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2517 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2518 else
2519 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2520
2521 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2522
2523 if (TARGET_ARM)
2524 {
2525 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2526 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2527 }
2528 else
2529 {
2530 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2531 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2532 }
2533
2534 seq = get_insns ();
2535 end_sequence ();
2536 if (prologue)
2537 emit_insn_after (seq, get_insns ());
2538 else
2539 emit_insn (seq);
2540
2541 /* Need to emit this whether or not we obey regdecls,
2542 since setjmp/longjmp can cause life info to screw up. */
2543 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2544 #endif /* AOF_ASSEMBLER */
2545 }
2546
2547 #define REG_OR_SUBREG_REG(X) \
2548 (GET_CODE (X) == REG \
2549 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2550
2551 #define REG_OR_SUBREG_RTX(X) \
2552 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2553
2554 #ifndef COSTS_N_INSNS
2555 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2556 #endif
2557
2558 int
arm_rtx_costs(x,code,outer)2559 arm_rtx_costs (x, code, outer)
2560 rtx x;
2561 enum rtx_code code;
2562 enum rtx_code outer;
2563 {
2564 enum machine_mode mode = GET_MODE (x);
2565 enum rtx_code subcode;
2566 int extra_cost;
2567
2568 if (TARGET_THUMB)
2569 {
2570 switch (code)
2571 {
2572 case ASHIFT:
2573 case ASHIFTRT:
2574 case LSHIFTRT:
2575 case ROTATERT:
2576 case PLUS:
2577 case MINUS:
2578 case COMPARE:
2579 case NEG:
2580 case NOT:
2581 return COSTS_N_INSNS (1);
2582
2583 case MULT:
2584 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2585 {
2586 int cycles = 0;
2587 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
2588
2589 while (i)
2590 {
2591 i >>= 2;
2592 cycles++;
2593 }
2594 return COSTS_N_INSNS (2) + cycles;
2595 }
2596 return COSTS_N_INSNS (1) + 16;
2597
2598 case SET:
2599 return (COSTS_N_INSNS (1)
2600 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
2601 + GET_CODE (SET_DEST (x)) == MEM));
2602
2603 case CONST_INT:
2604 if (outer == SET)
2605 {
2606 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2607 return 0;
2608 if (thumb_shiftable_const (INTVAL (x)))
2609 return COSTS_N_INSNS (2);
2610 return COSTS_N_INSNS (3);
2611 }
2612 else if (outer == PLUS
2613 && INTVAL (x) < 256 && INTVAL (x) > -256)
2614 return 0;
2615 else if (outer == COMPARE
2616 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2617 return 0;
2618 else if (outer == ASHIFT || outer == ASHIFTRT
2619 || outer == LSHIFTRT)
2620 return 0;
2621 return COSTS_N_INSNS (2);
2622
2623 case CONST:
2624 case CONST_DOUBLE:
2625 case LABEL_REF:
2626 case SYMBOL_REF:
2627 return COSTS_N_INSNS (3);
2628
2629 case UDIV:
2630 case UMOD:
2631 case DIV:
2632 case MOD:
2633 return 100;
2634
2635 case TRUNCATE:
2636 return 99;
2637
2638 case AND:
2639 case XOR:
2640 case IOR:
2641 /* XXX guess. */
2642 return 8;
2643
2644 case ADDRESSOF:
2645 case MEM:
2646 /* XXX another guess. */
2647 /* Memory costs quite a lot for the first word, but subsequent words
2648 load at the equivalent of a single insn each. */
2649 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2650 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
2651 ? 4 : 0));
2652
2653 case IF_THEN_ELSE:
2654 /* XXX a guess. */
2655 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2656 return 14;
2657 return 2;
2658
2659 case ZERO_EXTEND:
2660 /* XXX still guessing. */
2661 switch (GET_MODE (XEXP (x, 0)))
2662 {
2663 case QImode:
2664 return (1 + (mode == DImode ? 4 : 0)
2665 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2666
2667 case HImode:
2668 return (4 + (mode == DImode ? 4 : 0)
2669 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2670
2671 case SImode:
2672 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2673
2674 default:
2675 return 99;
2676 }
2677
2678 default:
2679 return 99;
2680 #if 0
2681 case FFS:
2682 case FLOAT:
2683 case FIX:
2684 case UNSIGNED_FIX:
2685 /* XXX guess */
2686 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
2687 rtx_name[code]);
2688 abort ();
2689 #endif
2690 }
2691 }
2692
2693 switch (code)
2694 {
2695 case MEM:
2696 /* Memory costs quite a lot for the first word, but subsequent words
2697 load at the equivalent of a single insn each. */
2698 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2699 + (GET_CODE (x) == SYMBOL_REF
2700 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2701
2702 case DIV:
2703 case MOD:
2704 return 100;
2705
2706 case ROTATE:
2707 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2708 return 4;
2709 /* Fall through */
2710 case ROTATERT:
2711 if (mode != SImode)
2712 return 8;
2713 /* Fall through */
2714 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2715 if (mode == DImode)
2716 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2717 + ((GET_CODE (XEXP (x, 0)) == REG
2718 || (GET_CODE (XEXP (x, 0)) == SUBREG
2719 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2720 ? 0 : 8));
2721 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2722 || (GET_CODE (XEXP (x, 0)) == SUBREG
2723 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2724 ? 0 : 4)
2725 + ((GET_CODE (XEXP (x, 1)) == REG
2726 || (GET_CODE (XEXP (x, 1)) == SUBREG
2727 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2728 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2729 ? 0 : 4));
2730
2731 case MINUS:
2732 if (mode == DImode)
2733 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2734 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2735 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2736 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2737 ? 0 : 8));
2738
2739 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2740 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2741 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2742 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2743 ? 0 : 8)
2744 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2745 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2746 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2747 ? 0 : 8));
2748
2749 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2750 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2751 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2752 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2753 || subcode == ASHIFTRT || subcode == LSHIFTRT
2754 || subcode == ROTATE || subcode == ROTATERT
2755 || (subcode == MULT
2756 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2757 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2758 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2759 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2760 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2761 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2762 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2763 return 1;
2764 /* Fall through */
2765
2766 case PLUS:
2767 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2768 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2769 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2770 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2771 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2772 ? 0 : 8));
2773
2774 /* Fall through */
2775 case AND: case XOR: case IOR:
2776 extra_cost = 0;
2777
2778 /* Normally the frame registers will be spilt into reg+const during
2779 reload, so it is a bad idea to combine them with other instructions,
2780 since then they might not be moved outside of loops. As a compromise
2781 we allow integration with ops that have a constant as their second
2782 operand. */
2783 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2784 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2785 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2786 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2787 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2788 extra_cost = 4;
2789
2790 if (mode == DImode)
2791 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2792 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2793 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2794 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2795 ? 0 : 8));
2796
2797 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2798 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2799 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2800 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2801 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2802 ? 0 : 4));
2803
2804 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2805 return (1 + extra_cost
2806 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2807 || subcode == LSHIFTRT || subcode == ASHIFTRT
2808 || subcode == ROTATE || subcode == ROTATERT
2809 || (subcode == MULT
2810 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2811 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2812 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2813 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2814 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2815 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2816 ? 0 : 4));
2817
2818 return 8;
2819
2820 case MULT:
2821 /* There is no point basing this on the tuning, since it is always the
2822 fast variant if it exists at all. */
2823 if (arm_fast_multiply && mode == DImode
2824 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2825 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2826 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2827 return 8;
2828
2829 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2830 || mode == DImode)
2831 return 30;
2832
2833 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2834 {
2835 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2836 & (unsigned HOST_WIDE_INT) 0xffffffff);
2837 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2838 int j;
2839
2840 /* Tune as appropriate. */
2841 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2842
2843 for (j = 0; i && j < 32; j += booth_unit_size)
2844 {
2845 i >>= booth_unit_size;
2846 add_cost += 2;
2847 }
2848
2849 return add_cost;
2850 }
2851
2852 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2853 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2854 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2855
2856 case TRUNCATE:
2857 if (arm_fast_multiply && mode == SImode
2858 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2859 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2860 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2861 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2862 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2863 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2864 return 8;
2865 return 99;
2866
2867 case NEG:
2868 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2869 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2870 /* Fall through */
2871 case NOT:
2872 if (mode == DImode)
2873 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2874
2875 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2876
2877 case IF_THEN_ELSE:
2878 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2879 return 14;
2880 return 2;
2881
2882 case COMPARE:
2883 return 1;
2884
2885 case ABS:
2886 return 4 + (mode == DImode ? 4 : 0);
2887
2888 case SIGN_EXTEND:
2889 if (GET_MODE (XEXP (x, 0)) == QImode)
2890 return (4 + (mode == DImode ? 4 : 0)
2891 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2892 /* Fall through */
2893 case ZERO_EXTEND:
2894 switch (GET_MODE (XEXP (x, 0)))
2895 {
2896 case QImode:
2897 return (1 + (mode == DImode ? 4 : 0)
2898 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2899
2900 case HImode:
2901 return (4 + (mode == DImode ? 4 : 0)
2902 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2903
2904 case SImode:
2905 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2906
2907 default:
2908 break;
2909 }
2910 abort ();
2911
2912 case CONST_INT:
2913 if (const_ok_for_arm (INTVAL (x)))
2914 return outer == SET ? 2 : -1;
2915 else if (outer == AND
2916 && const_ok_for_arm (~INTVAL (x)))
2917 return -1;
2918 else if ((outer == COMPARE
2919 || outer == PLUS || outer == MINUS)
2920 && const_ok_for_arm (-INTVAL (x)))
2921 return -1;
2922 else
2923 return 5;
2924
2925 case CONST:
2926 case LABEL_REF:
2927 case SYMBOL_REF:
2928 return 6;
2929
2930 case CONST_DOUBLE:
2931 if (const_double_rtx_ok_for_fpu (x))
2932 return outer == SET ? 2 : -1;
2933 else if ((outer == COMPARE || outer == PLUS)
2934 && neg_const_double_rtx_ok_for_fpu (x))
2935 return -1;
2936 return 7;
2937
2938 default:
2939 return 99;
2940 }
2941 }
2942
2943 static int
arm_adjust_cost(insn,link,dep,cost)2944 arm_adjust_cost (insn, link, dep, cost)
2945 rtx insn;
2946 rtx link;
2947 rtx dep;
2948 int cost;
2949 {
2950 rtx i_pat, d_pat;
2951
2952 /* Some true dependencies can have a higher cost depending
2953 on precisely how certain input operands are used. */
2954 if (arm_tune_xscale
2955 && REG_NOTE_KIND (link) == 0
2956 && recog_memoized (insn) < 0
2957 && recog_memoized (dep) < 0)
2958 {
2959 int shift_opnum = get_attr_shift (insn);
2960 enum attr_type attr_type = get_attr_type (dep);
2961
2962 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2963 operand for INSN. If we have a shifted input operand and the
2964 instruction we depend on is another ALU instruction, then we may
2965 have to account for an additional stall. */
2966 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
2967 {
2968 rtx shifted_operand;
2969 int opno;
2970
2971 /* Get the shifted operand. */
2972 extract_insn (insn);
2973 shifted_operand = recog_data.operand[shift_opnum];
2974
2975 /* Iterate over all the operands in DEP. If we write an operand
2976 that overlaps with SHIFTED_OPERAND, then we have increase the
2977 cost of this dependency. */
2978 extract_insn (dep);
2979 preprocess_constraints ();
2980 for (opno = 0; opno < recog_data.n_operands; opno++)
2981 {
2982 /* We can ignore strict inputs. */
2983 if (recog_data.operand_type[opno] == OP_IN)
2984 continue;
2985
2986 if (reg_overlap_mentioned_p (recog_data.operand[opno],
2987 shifted_operand))
2988 return 2;
2989 }
2990 }
2991 }
2992
2993 /* XXX This is not strictly true for the FPA. */
2994 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
2995 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
2996 return 0;
2997
2998 /* Call insns don't incur a stall, even if they follow a load. */
2999 if (REG_NOTE_KIND (link) == 0
3000 && GET_CODE (insn) == CALL_INSN)
3001 return 1;
3002
3003 if ((i_pat = single_set (insn)) != NULL
3004 && GET_CODE (SET_SRC (i_pat)) == MEM
3005 && (d_pat = single_set (dep)) != NULL
3006 && GET_CODE (SET_DEST (d_pat)) == MEM)
3007 {
3008 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3009 /* This is a load after a store, there is no conflict if the load reads
3010 from a cached area. Assume that loads from the stack, and from the
3011 constant pool are cached, and that others will miss. This is a
3012 hack. */
3013
3014 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3015 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3016 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3017 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3018 return 1;
3019 }
3020
3021 return cost;
3022 }
3023
3024 /* This code has been fixed for cross compilation. */
3025
3026 static int fpa_consts_inited = 0;
3027
3028 static const char * const strings_fpa[8] =
3029 {
3030 "0", "1", "2", "3",
3031 "4", "5", "0.5", "10"
3032 };
3033
3034 static REAL_VALUE_TYPE values_fpa[8];
3035
3036 static void
init_fpa_table()3037 init_fpa_table ()
3038 {
3039 int i;
3040 REAL_VALUE_TYPE r;
3041
3042 for (i = 0; i < 8; i++)
3043 {
3044 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
3045 values_fpa[i] = r;
3046 }
3047
3048 fpa_consts_inited = 1;
3049 }
3050
3051 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3052
3053 int
const_double_rtx_ok_for_fpu(x)3054 const_double_rtx_ok_for_fpu (x)
3055 rtx x;
3056 {
3057 REAL_VALUE_TYPE r;
3058 int i;
3059
3060 if (!fpa_consts_inited)
3061 init_fpa_table ();
3062
3063 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3064 if (REAL_VALUE_MINUS_ZERO (r))
3065 return 0;
3066
3067 for (i = 0; i < 8; i++)
3068 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3069 return 1;
3070
3071 return 0;
3072 }
3073
3074 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3075
3076 int
neg_const_double_rtx_ok_for_fpu(x)3077 neg_const_double_rtx_ok_for_fpu (x)
3078 rtx x;
3079 {
3080 REAL_VALUE_TYPE r;
3081 int i;
3082
3083 if (!fpa_consts_inited)
3084 init_fpa_table ();
3085
3086 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3087 r = REAL_VALUE_NEGATE (r);
3088 if (REAL_VALUE_MINUS_ZERO (r))
3089 return 0;
3090
3091 for (i = 0; i < 8; i++)
3092 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3093 return 1;
3094
3095 return 0;
3096 }
3097
3098 /* Predicates for `match_operand' and `match_operator'. */
3099
3100 /* s_register_operand is the same as register_operand, but it doesn't accept
3101 (SUBREG (MEM)...).
3102
3103 This function exists because at the time it was put in it led to better
3104 code. SUBREG(MEM) always needs a reload in the places where
3105 s_register_operand is used, and this seemed to lead to excessive
3106 reloading. */
3107
3108 int
s_register_operand(op,mode)3109 s_register_operand (op, mode)
3110 rtx op;
3111 enum machine_mode mode;
3112 {
3113 if (GET_MODE (op) != mode && mode != VOIDmode)
3114 return 0;
3115
3116 if (GET_CODE (op) == SUBREG)
3117 op = SUBREG_REG (op);
3118
3119 /* We don't consider registers whose class is NO_REGS
3120 to be a register operand. */
3121 /* XXX might have to check for lo regs only for thumb ??? */
3122 return (GET_CODE (op) == REG
3123 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3124 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3125 }
3126
3127 /* A hard register operand (even before reload. */
3128
3129 int
arm_hard_register_operand(op,mode)3130 arm_hard_register_operand (op, mode)
3131 rtx op;
3132 enum machine_mode mode;
3133 {
3134 if (GET_MODE (op) != mode && mode != VOIDmode)
3135 return 0;
3136
3137 return (GET_CODE (op) == REG
3138 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3139 }
3140
3141 /* Only accept reg, subreg(reg), const_int. */
3142
3143 int
reg_or_int_operand(op,mode)3144 reg_or_int_operand (op, mode)
3145 rtx op;
3146 enum machine_mode mode;
3147 {
3148 if (GET_CODE (op) == CONST_INT)
3149 return 1;
3150
3151 if (GET_MODE (op) != mode && mode != VOIDmode)
3152 return 0;
3153
3154 if (GET_CODE (op) == SUBREG)
3155 op = SUBREG_REG (op);
3156
3157 /* We don't consider registers whose class is NO_REGS
3158 to be a register operand. */
3159 return (GET_CODE (op) == REG
3160 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3161 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3162 }
3163
3164 /* Return 1 if OP is an item in memory, given that we are in reload. */
3165
3166 int
arm_reload_memory_operand(op,mode)3167 arm_reload_memory_operand (op, mode)
3168 rtx op;
3169 enum machine_mode mode ATTRIBUTE_UNUSED;
3170 {
3171 int regno = true_regnum (op);
3172
3173 return (!CONSTANT_P (op)
3174 && (regno == -1
3175 || (GET_CODE (op) == REG
3176 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3177 }
3178
3179 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3180 memory access (architecture V4).
3181 MODE is QImode if called when computing constraints, or VOIDmode when
3182 emitting patterns. In this latter case we cannot use memory_operand()
3183 because it will fail on badly formed MEMs, which is precisly what we are
3184 trying to catch. */
3185
3186 int
bad_signed_byte_operand(op,mode)3187 bad_signed_byte_operand (op, mode)
3188 rtx op;
3189 enum machine_mode mode ATTRIBUTE_UNUSED;
3190 {
3191 #if 0
3192 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
3193 return 0;
3194 #endif
3195 if (GET_CODE (op) != MEM)
3196 return 0;
3197
3198 op = XEXP (op, 0);
3199
3200 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3201 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3202 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3203 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3204 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3205 return 1;
3206
3207 /* Big constants are also bad. */
3208 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3209 && (INTVAL (XEXP (op, 1)) > 0xff
3210 || -INTVAL (XEXP (op, 1)) > 0xff))
3211 return 1;
3212
3213 /* Everything else is good, or can will automatically be made so. */
3214 return 0;
3215 }
3216
3217 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3218
3219 int
arm_rhs_operand(op,mode)3220 arm_rhs_operand (op, mode)
3221 rtx op;
3222 enum machine_mode mode;
3223 {
3224 return (s_register_operand (op, mode)
3225 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3226 }
3227
3228 /* Return TRUE for valid operands for the
3229 rhs of an ARM instruction, or a load. */
3230
3231 int
arm_rhsm_operand(op,mode)3232 arm_rhsm_operand (op, mode)
3233 rtx op;
3234 enum machine_mode mode;
3235 {
3236 return (s_register_operand (op, mode)
3237 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3238 || memory_operand (op, mode));
3239 }
3240
3241 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3242 constant that is valid when negated. */
3243
3244 int
arm_add_operand(op,mode)3245 arm_add_operand (op, mode)
3246 rtx op;
3247 enum machine_mode mode;
3248 {
3249 if (TARGET_THUMB)
3250 return thumb_cmp_operand (op, mode);
3251
3252 return (s_register_operand (op, mode)
3253 || (GET_CODE (op) == CONST_INT
3254 && (const_ok_for_arm (INTVAL (op))
3255 || const_ok_for_arm (-INTVAL (op)))));
3256 }
3257
3258 int
arm_not_operand(op,mode)3259 arm_not_operand (op, mode)
3260 rtx op;
3261 enum machine_mode mode;
3262 {
3263 return (s_register_operand (op, mode)
3264 || (GET_CODE (op) == CONST_INT
3265 && (const_ok_for_arm (INTVAL (op))
3266 || const_ok_for_arm (~INTVAL (op)))));
3267 }
3268
3269 /* Return TRUE if the operand is a memory reference which contains an
3270 offsettable address. */
3271
3272 int
offsettable_memory_operand(op,mode)3273 offsettable_memory_operand (op, mode)
3274 rtx op;
3275 enum machine_mode mode;
3276 {
3277 if (mode == VOIDmode)
3278 mode = GET_MODE (op);
3279
3280 return (mode == GET_MODE (op)
3281 && GET_CODE (op) == MEM
3282 && offsettable_address_p (reload_completed | reload_in_progress,
3283 mode, XEXP (op, 0)));
3284 }
3285
3286 /* Return TRUE if the operand is a memory reference which is, or can be
3287 made word aligned by adjusting the offset. */
3288
3289 int
alignable_memory_operand(op,mode)3290 alignable_memory_operand (op, mode)
3291 rtx op;
3292 enum machine_mode mode;
3293 {
3294 rtx reg;
3295
3296 if (mode == VOIDmode)
3297 mode = GET_MODE (op);
3298
3299 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3300 return 0;
3301
3302 op = XEXP (op, 0);
3303
3304 return ((GET_CODE (reg = op) == REG
3305 || (GET_CODE (op) == SUBREG
3306 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3307 || (GET_CODE (op) == PLUS
3308 && GET_CODE (XEXP (op, 1)) == CONST_INT
3309 && (GET_CODE (reg = XEXP (op, 0)) == REG
3310 || (GET_CODE (XEXP (op, 0)) == SUBREG
3311 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3312 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3313 }
3314
3315 /* Similar to s_register_operand, but does not allow hard integer
3316 registers. */
3317
3318 int
f_register_operand(op,mode)3319 f_register_operand (op, mode)
3320 rtx op;
3321 enum machine_mode mode;
3322 {
3323 if (GET_MODE (op) != mode && mode != VOIDmode)
3324 return 0;
3325
3326 if (GET_CODE (op) == SUBREG)
3327 op = SUBREG_REG (op);
3328
3329 /* We don't consider registers whose class is NO_REGS
3330 to be a register operand. */
3331 return (GET_CODE (op) == REG
3332 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3333 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
3334 }
3335
3336 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3337
3338 int
fpu_rhs_operand(op,mode)3339 fpu_rhs_operand (op, mode)
3340 rtx op;
3341 enum machine_mode mode;
3342 {
3343 if (s_register_operand (op, mode))
3344 return TRUE;
3345
3346 if (GET_MODE (op) != mode && mode != VOIDmode)
3347 return FALSE;
3348
3349 if (GET_CODE (op) == CONST_DOUBLE)
3350 return const_double_rtx_ok_for_fpu (op);
3351
3352 return FALSE;
3353 }
3354
3355 int
fpu_add_operand(op,mode)3356 fpu_add_operand (op, mode)
3357 rtx op;
3358 enum machine_mode mode;
3359 {
3360 if (s_register_operand (op, mode))
3361 return TRUE;
3362
3363 if (GET_MODE (op) != mode && mode != VOIDmode)
3364 return FALSE;
3365
3366 if (GET_CODE (op) == CONST_DOUBLE)
3367 return (const_double_rtx_ok_for_fpu (op)
3368 || neg_const_double_rtx_ok_for_fpu (op));
3369
3370 return FALSE;
3371 }
3372
3373 /* Return nonzero if OP is a constant power of two. */
3374
3375 int
power_of_two_operand(op,mode)3376 power_of_two_operand (op, mode)
3377 rtx op;
3378 enum machine_mode mode ATTRIBUTE_UNUSED;
3379 {
3380 if (GET_CODE (op) == CONST_INT)
3381 {
3382 HOST_WIDE_INT value = INTVAL (op);
3383
3384 return value != 0 && (value & (value - 1)) == 0;
3385 }
3386
3387 return FALSE;
3388 }
3389
3390 /* Return TRUE for a valid operand of a DImode operation.
3391 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3392 Note that this disallows MEM(REG+REG), but allows
3393 MEM(PRE/POST_INC/DEC(REG)). */
3394
3395 int
di_operand(op,mode)3396 di_operand (op, mode)
3397 rtx op;
3398 enum machine_mode mode;
3399 {
3400 if (s_register_operand (op, mode))
3401 return TRUE;
3402
3403 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3404 return FALSE;
3405
3406 if (GET_CODE (op) == SUBREG)
3407 op = SUBREG_REG (op);
3408
3409 switch (GET_CODE (op))
3410 {
3411 case CONST_DOUBLE:
3412 case CONST_INT:
3413 return TRUE;
3414
3415 case MEM:
3416 return memory_address_p (DImode, XEXP (op, 0));
3417
3418 default:
3419 return FALSE;
3420 }
3421 }
3422
3423 /* Like di_operand, but don't accept constants. */
3424
3425 int
nonimmediate_di_operand(op,mode)3426 nonimmediate_di_operand (op, mode)
3427 rtx op;
3428 enum machine_mode mode;
3429 {
3430 if (s_register_operand (op, mode))
3431 return TRUE;
3432
3433 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3434 return FALSE;
3435
3436 if (GET_CODE (op) == SUBREG)
3437 op = SUBREG_REG (op);
3438
3439 if (GET_CODE (op) == MEM)
3440 return memory_address_p (DImode, XEXP (op, 0));
3441
3442 return FALSE;
3443 }
3444
3445 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3446 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3447 Note that this disallows MEM(REG+REG), but allows
3448 MEM(PRE/POST_INC/DEC(REG)). */
3449
3450 int
soft_df_operand(op,mode)3451 soft_df_operand (op, mode)
3452 rtx op;
3453 enum machine_mode mode;
3454 {
3455 if (s_register_operand (op, mode))
3456 return TRUE;
3457
3458 if (mode != VOIDmode && GET_MODE (op) != mode)
3459 return FALSE;
3460
3461 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
3462 return FALSE;
3463
3464 if (GET_CODE (op) == SUBREG)
3465 op = SUBREG_REG (op);
3466
3467 switch (GET_CODE (op))
3468 {
3469 case CONST_DOUBLE:
3470 return TRUE;
3471
3472 case MEM:
3473 return memory_address_p (DFmode, XEXP (op, 0));
3474
3475 default:
3476 return FALSE;
3477 }
3478 }
3479
3480 /* Like soft_df_operand, but don't accept constants. */
3481
3482 int
nonimmediate_soft_df_operand(op,mode)3483 nonimmediate_soft_df_operand (op, mode)
3484 rtx op;
3485 enum machine_mode mode;
3486 {
3487 if (s_register_operand (op, mode))
3488 return TRUE;
3489
3490 if (mode != VOIDmode && GET_MODE (op) != mode)
3491 return FALSE;
3492
3493 if (GET_CODE (op) == SUBREG)
3494 op = SUBREG_REG (op);
3495
3496 if (GET_CODE (op) == MEM)
3497 return memory_address_p (DFmode, XEXP (op, 0));
3498 return FALSE;
3499 }
3500
3501 /* Return TRUE for valid index operands. */
3502
3503 int
index_operand(op,mode)3504 index_operand (op, mode)
3505 rtx op;
3506 enum machine_mode mode;
3507 {
3508 return (s_register_operand (op, mode)
3509 || (immediate_operand (op, mode)
3510 && (GET_CODE (op) != CONST_INT
3511 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
3512 }
3513
3514 /* Return TRUE for valid shifts by a constant. This also accepts any
3515 power of two on the (somewhat overly relaxed) assumption that the
3516 shift operator in this case was a mult. */
3517
3518 int
const_shift_operand(op,mode)3519 const_shift_operand (op, mode)
3520 rtx op;
3521 enum machine_mode mode;
3522 {
3523 return (power_of_two_operand (op, mode)
3524 || (immediate_operand (op, mode)
3525 && (GET_CODE (op) != CONST_INT
3526 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
3527 }
3528
3529 /* Return TRUE for arithmetic operators which can be combined with a multiply
3530 (shift). */
3531
3532 int
shiftable_operator(x,mode)3533 shiftable_operator (x, mode)
3534 rtx x;
3535 enum machine_mode mode;
3536 {
3537 enum rtx_code code;
3538
3539 if (GET_MODE (x) != mode)
3540 return FALSE;
3541
3542 code = GET_CODE (x);
3543
3544 return (code == PLUS || code == MINUS
3545 || code == IOR || code == XOR || code == AND);
3546 }
3547
3548 /* Return TRUE for binary logical operators. */
3549
3550 int
logical_binary_operator(x,mode)3551 logical_binary_operator (x, mode)
3552 rtx x;
3553 enum machine_mode mode;
3554 {
3555 enum rtx_code code;
3556
3557 if (GET_MODE (x) != mode)
3558 return FALSE;
3559
3560 code = GET_CODE (x);
3561
3562 return (code == IOR || code == XOR || code == AND);
3563 }
3564
3565 /* Return TRUE for shift operators. */
3566
3567 int
shift_operator(x,mode)3568 shift_operator (x, mode)
3569 rtx x;
3570 enum machine_mode mode;
3571 {
3572 enum rtx_code code;
3573
3574 if (GET_MODE (x) != mode)
3575 return FALSE;
3576
3577 code = GET_CODE (x);
3578
3579 if (code == MULT)
3580 return power_of_two_operand (XEXP (x, 1), mode);
3581
3582 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
3583 || code == ROTATERT);
3584 }
3585
3586 /* Return TRUE if x is EQ or NE. */
3587
3588 int
equality_operator(x,mode)3589 equality_operator (x, mode)
3590 rtx x;
3591 enum machine_mode mode ATTRIBUTE_UNUSED;
3592 {
3593 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
3594 }
3595
3596 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3597
3598 int
arm_comparison_operator(x,mode)3599 arm_comparison_operator (x, mode)
3600 rtx x;
3601 enum machine_mode mode;
3602 {
3603 return (comparison_operator (x, mode)
3604 && GET_CODE (x) != LTGT
3605 && GET_CODE (x) != UNEQ);
3606 }
3607
3608 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3609
3610 int
minmax_operator(x,mode)3611 minmax_operator (x, mode)
3612 rtx x;
3613 enum machine_mode mode;
3614 {
3615 enum rtx_code code = GET_CODE (x);
3616
3617 if (GET_MODE (x) != mode)
3618 return FALSE;
3619
3620 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
3621 }
3622
3623 /* Return TRUE if this is the condition code register, if we aren't given
3624 a mode, accept any class CCmode register. */
3625
3626 int
cc_register(x,mode)3627 cc_register (x, mode)
3628 rtx x;
3629 enum machine_mode mode;
3630 {
3631 if (mode == VOIDmode)
3632 {
3633 mode = GET_MODE (x);
3634
3635 if (GET_MODE_CLASS (mode) != MODE_CC)
3636 return FALSE;
3637 }
3638
3639 if ( GET_MODE (x) == mode
3640 && GET_CODE (x) == REG
3641 && REGNO (x) == CC_REGNUM)
3642 return TRUE;
3643
3644 return FALSE;
3645 }
3646
3647 /* Return TRUE if this is the condition code register, if we aren't given
3648 a mode, accept any class CCmode register which indicates a dominance
3649 expression. */
3650
3651 int
dominant_cc_register(x,mode)3652 dominant_cc_register (x, mode)
3653 rtx x;
3654 enum machine_mode mode;
3655 {
3656 if (mode == VOIDmode)
3657 {
3658 mode = GET_MODE (x);
3659
3660 if (GET_MODE_CLASS (mode) != MODE_CC)
3661 return FALSE;
3662 }
3663
3664 if ( mode != CC_DNEmode && mode != CC_DEQmode
3665 && mode != CC_DLEmode && mode != CC_DLTmode
3666 && mode != CC_DGEmode && mode != CC_DGTmode
3667 && mode != CC_DLEUmode && mode != CC_DLTUmode
3668 && mode != CC_DGEUmode && mode != CC_DGTUmode)
3669 return FALSE;
3670
3671 return cc_register (x, mode);
3672 }
3673
3674 /* Return TRUE if X references a SYMBOL_REF. */
3675
3676 int
symbol_mentioned_p(x)3677 symbol_mentioned_p (x)
3678 rtx x;
3679 {
3680 const char * fmt;
3681 int i;
3682
3683 if (GET_CODE (x) == SYMBOL_REF)
3684 return 1;
3685
3686 fmt = GET_RTX_FORMAT (GET_CODE (x));
3687
3688 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3689 {
3690 if (fmt[i] == 'E')
3691 {
3692 int j;
3693
3694 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3695 if (symbol_mentioned_p (XVECEXP (x, i, j)))
3696 return 1;
3697 }
3698 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3699 return 1;
3700 }
3701
3702 return 0;
3703 }
3704
3705 /* Return TRUE if X references a LABEL_REF. */
3706
3707 int
label_mentioned_p(x)3708 label_mentioned_p (x)
3709 rtx x;
3710 {
3711 const char * fmt;
3712 int i;
3713
3714 if (GET_CODE (x) == LABEL_REF)
3715 return 1;
3716
3717 fmt = GET_RTX_FORMAT (GET_CODE (x));
3718 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3719 {
3720 if (fmt[i] == 'E')
3721 {
3722 int j;
3723
3724 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3725 if (label_mentioned_p (XVECEXP (x, i, j)))
3726 return 1;
3727 }
3728 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3729 return 1;
3730 }
3731
3732 return 0;
3733 }
3734
3735 enum rtx_code
minmax_code(x)3736 minmax_code (x)
3737 rtx x;
3738 {
3739 enum rtx_code code = GET_CODE (x);
3740
3741 if (code == SMAX)
3742 return GE;
3743 else if (code == SMIN)
3744 return LE;
3745 else if (code == UMIN)
3746 return LEU;
3747 else if (code == UMAX)
3748 return GEU;
3749
3750 abort ();
3751 }
3752
3753 /* Return 1 if memory locations are adjacent. */
3754
3755 int
adjacent_mem_locations(a,b)3756 adjacent_mem_locations (a, b)
3757 rtx a, b;
3758 {
3759 if ((GET_CODE (XEXP (a, 0)) == REG
3760 || (GET_CODE (XEXP (a, 0)) == PLUS
3761 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
3762 && (GET_CODE (XEXP (b, 0)) == REG
3763 || (GET_CODE (XEXP (b, 0)) == PLUS
3764 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
3765 {
3766 int val0 = 0, val1 = 0;
3767 int reg0, reg1;
3768
3769 if (GET_CODE (XEXP (a, 0)) == PLUS)
3770 {
3771 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
3772 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
3773 }
3774 else
3775 reg0 = REGNO (XEXP (a, 0));
3776
3777 if (GET_CODE (XEXP (b, 0)) == PLUS)
3778 {
3779 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
3780 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
3781 }
3782 else
3783 reg1 = REGNO (XEXP (b, 0));
3784
3785 /* Don't accept any offset that will require multiple instructions to handle,
3786 since this would cause the arith_adjacentmem pattern to output an overlong
3787 sequence. */
3788 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
3789 return 0;
3790
3791 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
3792 }
3793 return 0;
3794 }
3795
3796 /* Return 1 if OP is a load multiple operation. It is known to be
3797 parallel and the first section will be tested. */
3798
3799 int
load_multiple_operation(op,mode)3800 load_multiple_operation (op, mode)
3801 rtx op;
3802 enum machine_mode mode ATTRIBUTE_UNUSED;
3803 {
3804 HOST_WIDE_INT count = XVECLEN (op, 0);
3805 int dest_regno;
3806 rtx src_addr;
3807 HOST_WIDE_INT i = 1, base = 0;
3808 rtx elt;
3809
3810 if (count <= 1
3811 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3812 return 0;
3813
3814 /* Check to see if this might be a write-back. */
3815 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3816 {
3817 i++;
3818 base = 1;
3819
3820 /* Now check it more carefully. */
3821 if (GET_CODE (SET_DEST (elt)) != REG
3822 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3823 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3824 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3825 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3826 return 0;
3827 }
3828
3829 /* Perform a quick check so we don't blow up below. */
3830 if (count <= i
3831 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3832 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
3833 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
3834 return 0;
3835
3836 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
3837 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
3838
3839 for (; i < count; i++)
3840 {
3841 elt = XVECEXP (op, 0, i);
3842
3843 if (GET_CODE (elt) != SET
3844 || GET_CODE (SET_DEST (elt)) != REG
3845 || GET_MODE (SET_DEST (elt)) != SImode
3846 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
3847 || GET_CODE (SET_SRC (elt)) != MEM
3848 || GET_MODE (SET_SRC (elt)) != SImode
3849 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3850 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3851 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3852 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
3853 return 0;
3854 }
3855
3856 return 1;
3857 }
3858
3859 /* Return 1 if OP is a store multiple operation. It is known to be
3860 parallel and the first section will be tested. */
3861
3862 int
store_multiple_operation(op,mode)3863 store_multiple_operation (op, mode)
3864 rtx op;
3865 enum machine_mode mode ATTRIBUTE_UNUSED;
3866 {
3867 HOST_WIDE_INT count = XVECLEN (op, 0);
3868 int src_regno;
3869 rtx dest_addr;
3870 HOST_WIDE_INT i = 1, base = 0;
3871 rtx elt;
3872
3873 if (count <= 1
3874 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3875 return 0;
3876
3877 /* Check to see if this might be a write-back. */
3878 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3879 {
3880 i++;
3881 base = 1;
3882
3883 /* Now check it more carefully. */
3884 if (GET_CODE (SET_DEST (elt)) != REG
3885 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3886 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3887 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3888 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3889 return 0;
3890 }
3891
3892 /* Perform a quick check so we don't blow up below. */
3893 if (count <= i
3894 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3895 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3896 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3897 return 0;
3898
3899 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3900 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3901
3902 for (; i < count; i++)
3903 {
3904 elt = XVECEXP (op, 0, i);
3905
3906 if (GET_CODE (elt) != SET
3907 || GET_CODE (SET_SRC (elt)) != REG
3908 || GET_MODE (SET_SRC (elt)) != SImode
3909 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3910 || GET_CODE (SET_DEST (elt)) != MEM
3911 || GET_MODE (SET_DEST (elt)) != SImode
3912 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3913 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3914 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3915 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3916 return 0;
3917 }
3918
3919 return 1;
3920 }
3921
3922 int
load_multiple_sequence(operands,nops,regs,base,load_offset)3923 load_multiple_sequence (operands, nops, regs, base, load_offset)
3924 rtx * operands;
3925 int nops;
3926 int * regs;
3927 int * base;
3928 HOST_WIDE_INT * load_offset;
3929 {
3930 int unsorted_regs[4];
3931 HOST_WIDE_INT unsorted_offsets[4];
3932 int order[4];
3933 int base_reg = -1;
3934 int i;
3935
3936 /* Can only handle 2, 3, or 4 insns at present,
3937 though could be easily extended if required. */
3938 if (nops < 2 || nops > 4)
3939 abort ();
3940
3941 /* Loop over the operands and check that the memory references are
3942 suitable (ie immediate offsets from the same base register). At
3943 the same time, extract the target register, and the memory
3944 offsets. */
3945 for (i = 0; i < nops; i++)
3946 {
3947 rtx reg;
3948 rtx offset;
3949
3950 /* Convert a subreg of a mem into the mem itself. */
3951 if (GET_CODE (operands[nops + i]) == SUBREG)
3952 operands[nops + i] = alter_subreg (operands + (nops + i));
3953
3954 if (GET_CODE (operands[nops + i]) != MEM)
3955 abort ();
3956
3957 /* Don't reorder volatile memory references; it doesn't seem worth
3958 looking for the case where the order is ok anyway. */
3959 if (MEM_VOLATILE_P (operands[nops + i]))
3960 return 0;
3961
3962 offset = const0_rtx;
3963
3964 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3965 || (GET_CODE (reg) == SUBREG
3966 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3967 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3968 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3969 == REG)
3970 || (GET_CODE (reg) == SUBREG
3971 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3972 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3973 == CONST_INT)))
3974 {
3975 if (i == 0)
3976 {
3977 base_reg = REGNO (reg);
3978 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3979 ? REGNO (operands[i])
3980 : REGNO (SUBREG_REG (operands[i])));
3981 order[0] = 0;
3982 }
3983 else
3984 {
3985 if (base_reg != (int) REGNO (reg))
3986 /* Not addressed from the same base register. */
3987 return 0;
3988
3989 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3990 ? REGNO (operands[i])
3991 : REGNO (SUBREG_REG (operands[i])));
3992 if (unsorted_regs[i] < unsorted_regs[order[0]])
3993 order[0] = i;
3994 }
3995
3996 /* If it isn't an integer register, or if it overwrites the
3997 base register but isn't the last insn in the list, then
3998 we can't do this. */
3999 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
4000 || (i != nops - 1 && unsorted_regs[i] == base_reg))
4001 return 0;
4002
4003 unsorted_offsets[i] = INTVAL (offset);
4004 }
4005 else
4006 /* Not a suitable memory address. */
4007 return 0;
4008 }
4009
4010 /* All the useful information has now been extracted from the
4011 operands into unsorted_regs and unsorted_offsets; additionally,
4012 order[0] has been set to the lowest numbered register in the
4013 list. Sort the registers into order, and check that the memory
4014 offsets are ascending and adjacent. */
4015
4016 for (i = 1; i < nops; i++)
4017 {
4018 int j;
4019
4020 order[i] = order[i - 1];
4021 for (j = 0; j < nops; j++)
4022 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4023 && (order[i] == order[i - 1]
4024 || unsorted_regs[j] < unsorted_regs[order[i]]))
4025 order[i] = j;
4026
4027 /* Have we found a suitable register? if not, one must be used more
4028 than once. */
4029 if (order[i] == order[i - 1])
4030 return 0;
4031
4032 /* Is the memory address adjacent and ascending? */
4033 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4034 return 0;
4035 }
4036
4037 if (base)
4038 {
4039 *base = base_reg;
4040
4041 for (i = 0; i < nops; i++)
4042 regs[i] = unsorted_regs[order[i]];
4043
4044 *load_offset = unsorted_offsets[order[0]];
4045 }
4046
4047 if (unsorted_offsets[order[0]] == 0)
4048 return 1; /* ldmia */
4049
4050 if (unsorted_offsets[order[0]] == 4)
4051 return 2; /* ldmib */
4052
4053 if (unsorted_offsets[order[nops - 1]] == 0)
4054 return 3; /* ldmda */
4055
4056 if (unsorted_offsets[order[nops - 1]] == -4)
4057 return 4; /* ldmdb */
4058
4059 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4060 if the offset isn't small enough. The reason 2 ldrs are faster
4061 is because these ARMs are able to do more than one cache access
4062 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4063 whilst the ARM8 has a double bandwidth cache. This means that
4064 these cores can do both an instruction fetch and a data fetch in
4065 a single cycle, so the trick of calculating the address into a
4066 scratch register (one of the result regs) and then doing a load
4067 multiple actually becomes slower (and no smaller in code size).
4068 That is the transformation
4069
4070 ldr rd1, [rbase + offset]
4071 ldr rd2, [rbase + offset + 4]
4072
4073 to
4074
4075 add rd1, rbase, offset
4076 ldmia rd1, {rd1, rd2}
4077
4078 produces worse code -- '3 cycles + any stalls on rd2' instead of
4079 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4080 access per cycle, the first sequence could never complete in less
4081 than 6 cycles, whereas the ldm sequence would only take 5 and
4082 would make better use of sequential accesses if not hitting the
4083 cache.
4084
4085 We cheat here and test 'arm_ld_sched' which we currently know to
4086 only be true for the ARM8, ARM9 and StrongARM. If this ever
4087 changes, then the test below needs to be reworked. */
4088 if (nops == 2 && arm_ld_sched)
4089 return 0;
4090
4091 /* Can't do it without setting up the offset, only do this if it takes
4092 no more than one insn. */
4093 return (const_ok_for_arm (unsorted_offsets[order[0]])
4094 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
4095 }
4096
4097 const char *
emit_ldm_seq(operands,nops)4098 emit_ldm_seq (operands, nops)
4099 rtx * operands;
4100 int nops;
4101 {
4102 int regs[4];
4103 int base_reg;
4104 HOST_WIDE_INT offset;
4105 char buf[100];
4106 int i;
4107
4108 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4109 {
4110 case 1:
4111 strcpy (buf, "ldm%?ia\t");
4112 break;
4113
4114 case 2:
4115 strcpy (buf, "ldm%?ib\t");
4116 break;
4117
4118 case 3:
4119 strcpy (buf, "ldm%?da\t");
4120 break;
4121
4122 case 4:
4123 strcpy (buf, "ldm%?db\t");
4124 break;
4125
4126 case 5:
4127 if (offset >= 0)
4128 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4129 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4130 (long) offset);
4131 else
4132 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4133 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4134 (long) -offset);
4135 output_asm_insn (buf, operands);
4136 base_reg = regs[0];
4137 strcpy (buf, "ldm%?ia\t");
4138 break;
4139
4140 default:
4141 abort ();
4142 }
4143
4144 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4145 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4146
4147 for (i = 1; i < nops; i++)
4148 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4149 reg_names[regs[i]]);
4150
4151 strcat (buf, "}\t%@ phole ldm");
4152
4153 output_asm_insn (buf, operands);
4154 return "";
4155 }
4156
4157 int
store_multiple_sequence(operands,nops,regs,base,load_offset)4158 store_multiple_sequence (operands, nops, regs, base, load_offset)
4159 rtx * operands;
4160 int nops;
4161 int * regs;
4162 int * base;
4163 HOST_WIDE_INT * load_offset;
4164 {
4165 int unsorted_regs[4];
4166 HOST_WIDE_INT unsorted_offsets[4];
4167 int order[4];
4168 int base_reg = -1;
4169 int i;
4170
4171 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4172 extended if required. */
4173 if (nops < 2 || nops > 4)
4174 abort ();
4175
4176 /* Loop over the operands and check that the memory references are
4177 suitable (ie immediate offsets from the same base register). At
4178 the same time, extract the target register, and the memory
4179 offsets. */
4180 for (i = 0; i < nops; i++)
4181 {
4182 rtx reg;
4183 rtx offset;
4184
4185 /* Convert a subreg of a mem into the mem itself. */
4186 if (GET_CODE (operands[nops + i]) == SUBREG)
4187 operands[nops + i] = alter_subreg (operands + (nops + i));
4188
4189 if (GET_CODE (operands[nops + i]) != MEM)
4190 abort ();
4191
4192 /* Don't reorder volatile memory references; it doesn't seem worth
4193 looking for the case where the order is ok anyway. */
4194 if (MEM_VOLATILE_P (operands[nops + i]))
4195 return 0;
4196
4197 offset = const0_rtx;
4198
4199 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4200 || (GET_CODE (reg) == SUBREG
4201 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4202 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4203 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4204 == REG)
4205 || (GET_CODE (reg) == SUBREG
4206 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4207 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4208 == CONST_INT)))
4209 {
4210 if (i == 0)
4211 {
4212 base_reg = REGNO (reg);
4213 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4214 ? REGNO (operands[i])
4215 : REGNO (SUBREG_REG (operands[i])));
4216 order[0] = 0;
4217 }
4218 else
4219 {
4220 if (base_reg != (int) REGNO (reg))
4221 /* Not addressed from the same base register. */
4222 return 0;
4223
4224 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4225 ? REGNO (operands[i])
4226 : REGNO (SUBREG_REG (operands[i])));
4227 if (unsorted_regs[i] < unsorted_regs[order[0]])
4228 order[0] = i;
4229 }
4230
4231 /* If it isn't an integer register, then we can't do this. */
4232 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
4233 return 0;
4234
4235 unsorted_offsets[i] = INTVAL (offset);
4236 }
4237 else
4238 /* Not a suitable memory address. */
4239 return 0;
4240 }
4241
4242 /* All the useful information has now been extracted from the
4243 operands into unsorted_regs and unsorted_offsets; additionally,
4244 order[0] has been set to the lowest numbered register in the
4245 list. Sort the registers into order, and check that the memory
4246 offsets are ascending and adjacent. */
4247
4248 for (i = 1; i < nops; i++)
4249 {
4250 int j;
4251
4252 order[i] = order[i - 1];
4253 for (j = 0; j < nops; j++)
4254 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4255 && (order[i] == order[i - 1]
4256 || unsorted_regs[j] < unsorted_regs[order[i]]))
4257 order[i] = j;
4258
4259 /* Have we found a suitable register? if not, one must be used more
4260 than once. */
4261 if (order[i] == order[i - 1])
4262 return 0;
4263
4264 /* Is the memory address adjacent and ascending? */
4265 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4266 return 0;
4267 }
4268
4269 if (base)
4270 {
4271 *base = base_reg;
4272
4273 for (i = 0; i < nops; i++)
4274 regs[i] = unsorted_regs[order[i]];
4275
4276 *load_offset = unsorted_offsets[order[0]];
4277 }
4278
4279 if (unsorted_offsets[order[0]] == 0)
4280 return 1; /* stmia */
4281
4282 if (unsorted_offsets[order[0]] == 4)
4283 return 2; /* stmib */
4284
4285 if (unsorted_offsets[order[nops - 1]] == 0)
4286 return 3; /* stmda */
4287
4288 if (unsorted_offsets[order[nops - 1]] == -4)
4289 return 4; /* stmdb */
4290
4291 return 0;
4292 }
4293
4294 const char *
emit_stm_seq(operands,nops)4295 emit_stm_seq (operands, nops)
4296 rtx * operands;
4297 int nops;
4298 {
4299 int regs[4];
4300 int base_reg;
4301 HOST_WIDE_INT offset;
4302 char buf[100];
4303 int i;
4304
4305 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4306 {
4307 case 1:
4308 strcpy (buf, "stm%?ia\t");
4309 break;
4310
4311 case 2:
4312 strcpy (buf, "stm%?ib\t");
4313 break;
4314
4315 case 3:
4316 strcpy (buf, "stm%?da\t");
4317 break;
4318
4319 case 4:
4320 strcpy (buf, "stm%?db\t");
4321 break;
4322
4323 default:
4324 abort ();
4325 }
4326
4327 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4328 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4329
4330 for (i = 1; i < nops; i++)
4331 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4332 reg_names[regs[i]]);
4333
4334 strcat (buf, "}\t%@ phole stm");
4335
4336 output_asm_insn (buf, operands);
4337 return "";
4338 }
4339
4340 int
multi_register_push(op,mode)4341 multi_register_push (op, mode)
4342 rtx op;
4343 enum machine_mode mode ATTRIBUTE_UNUSED;
4344 {
4345 if (GET_CODE (op) != PARALLEL
4346 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
4347 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
4348 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
4349 return 0;
4350
4351 return 1;
4352 }
4353
4354 /* Routines for use in generating RTL. */
4355
4356 rtx
arm_gen_load_multiple(base_regno,count,from,up,write_back,unchanging_p,in_struct_p,scalar_p)4357 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
4358 in_struct_p, scalar_p)
4359 int base_regno;
4360 int count;
4361 rtx from;
4362 int up;
4363 int write_back;
4364 int unchanging_p;
4365 int in_struct_p;
4366 int scalar_p;
4367 {
4368 int i = 0, j;
4369 rtx result;
4370 int sign = up ? 1 : -1;
4371 rtx mem;
4372
4373 /* XScale has load-store double instructions, but they have stricter
4374 alignment requirements than load-store multiple, so we can not
4375 use them.
4376
4377 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4378 the pipeline until completion.
4379
4380 NREGS CYCLES
4381 1 3
4382 2 4
4383 3 5
4384 4 6
4385
4386 An ldr instruction takes 1-3 cycles, but does not block the
4387 pipeline.
4388
4389 NREGS CYCLES
4390 1 1-3
4391 2 2-6
4392 3 3-9
4393 4 4-12
4394
4395 Best case ldr will always win. However, the more ldr instructions
4396 we issue, the less likely we are to be able to schedule them well.
4397 Using ldr instructions also increases code size.
4398
4399 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4400 for counts of 3 or 4 regs. */
4401 if (arm_tune_xscale && count <= 2 && ! optimize_size)
4402 {
4403 rtx seq;
4404
4405 start_sequence ();
4406
4407 for (i = 0; i < count; i++)
4408 {
4409 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
4410 RTX_UNCHANGING_P (mem) = unchanging_p;
4411 MEM_IN_STRUCT_P (mem) = in_struct_p;
4412 MEM_SCALAR_P (mem) = scalar_p;
4413 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
4414 }
4415
4416 if (write_back)
4417 emit_move_insn (from, plus_constant (from, count * 4 * sign));
4418
4419 seq = get_insns ();
4420 end_sequence ();
4421
4422 return seq;
4423 }
4424
4425 result = gen_rtx_PARALLEL (VOIDmode,
4426 rtvec_alloc (count + (write_back ? 1 : 0)));
4427 if (write_back)
4428 {
4429 XVECEXP (result, 0, 0)
4430 = gen_rtx_SET (GET_MODE (from), from,
4431 plus_constant (from, count * 4 * sign));
4432 i = 1;
4433 count++;
4434 }
4435
4436 for (j = 0; i < count; i++, j++)
4437 {
4438 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
4439 RTX_UNCHANGING_P (mem) = unchanging_p;
4440 MEM_IN_STRUCT_P (mem) = in_struct_p;
4441 MEM_SCALAR_P (mem) = scalar_p;
4442 XVECEXP (result, 0, i)
4443 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
4444 }
4445
4446 return result;
4447 }
4448
4449 rtx
arm_gen_store_multiple(base_regno,count,to,up,write_back,unchanging_p,in_struct_p,scalar_p)4450 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
4451 in_struct_p, scalar_p)
4452 int base_regno;
4453 int count;
4454 rtx to;
4455 int up;
4456 int write_back;
4457 int unchanging_p;
4458 int in_struct_p;
4459 int scalar_p;
4460 {
4461 int i = 0, j;
4462 rtx result;
4463 int sign = up ? 1 : -1;
4464 rtx mem;
4465
4466 /* See arm_gen_load_multiple for discussion of
4467 the pros/cons of ldm/stm usage for XScale. */
4468 if (arm_tune_xscale && count <= 2 && ! optimize_size)
4469 {
4470 rtx seq;
4471
4472 start_sequence ();
4473
4474 for (i = 0; i < count; i++)
4475 {
4476 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
4477 RTX_UNCHANGING_P (mem) = unchanging_p;
4478 MEM_IN_STRUCT_P (mem) = in_struct_p;
4479 MEM_SCALAR_P (mem) = scalar_p;
4480 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
4481 }
4482
4483 if (write_back)
4484 emit_move_insn (to, plus_constant (to, count * 4 * sign));
4485
4486 seq = get_insns ();
4487 end_sequence ();
4488
4489 return seq;
4490 }
4491
4492 result = gen_rtx_PARALLEL (VOIDmode,
4493 rtvec_alloc (count + (write_back ? 1 : 0)));
4494 if (write_back)
4495 {
4496 XVECEXP (result, 0, 0)
4497 = gen_rtx_SET (GET_MODE (to), to,
4498 plus_constant (to, count * 4 * sign));
4499 i = 1;
4500 count++;
4501 }
4502
4503 for (j = 0; i < count; i++, j++)
4504 {
4505 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
4506 RTX_UNCHANGING_P (mem) = unchanging_p;
4507 MEM_IN_STRUCT_P (mem) = in_struct_p;
4508 MEM_SCALAR_P (mem) = scalar_p;
4509
4510 XVECEXP (result, 0, i)
4511 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
4512 }
4513
4514 return result;
4515 }
4516
4517 int
arm_gen_movstrqi(operands)4518 arm_gen_movstrqi (operands)
4519 rtx * operands;
4520 {
4521 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
4522 int i;
4523 rtx src, dst;
4524 rtx st_src, st_dst, fin_src, fin_dst;
4525 rtx part_bytes_reg = NULL;
4526 rtx mem;
4527 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
4528 int dst_scalar_p, src_scalar_p;
4529
4530 if (GET_CODE (operands[2]) != CONST_INT
4531 || GET_CODE (operands[3]) != CONST_INT
4532 || INTVAL (operands[2]) > 64
4533 || INTVAL (operands[3]) & 3)
4534 return 0;
4535
4536 st_dst = XEXP (operands[0], 0);
4537 st_src = XEXP (operands[1], 0);
4538
4539 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
4540 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
4541 dst_scalar_p = MEM_SCALAR_P (operands[0]);
4542 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
4543 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
4544 src_scalar_p = MEM_SCALAR_P (operands[1]);
4545
4546 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
4547 fin_src = src = copy_to_mode_reg (SImode, st_src);
4548
4549 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
4550 out_words_to_go = INTVAL (operands[2]) / 4;
4551 last_bytes = INTVAL (operands[2]) & 3;
4552
4553 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
4554 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
4555
4556 for (i = 0; in_words_to_go >= 2; i+=4)
4557 {
4558 if (in_words_to_go > 4)
4559 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
4560 src_unchanging_p,
4561 src_in_struct_p,
4562 src_scalar_p));
4563 else
4564 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
4565 FALSE, src_unchanging_p,
4566 src_in_struct_p, src_scalar_p));
4567
4568 if (out_words_to_go)
4569 {
4570 if (out_words_to_go > 4)
4571 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
4572 dst_unchanging_p,
4573 dst_in_struct_p,
4574 dst_scalar_p));
4575 else if (out_words_to_go != 1)
4576 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
4577 dst, TRUE,
4578 (last_bytes == 0
4579 ? FALSE : TRUE),
4580 dst_unchanging_p,
4581 dst_in_struct_p,
4582 dst_scalar_p));
4583 else
4584 {
4585 mem = gen_rtx_MEM (SImode, dst);
4586 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4587 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4588 MEM_SCALAR_P (mem) = dst_scalar_p;
4589 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
4590 if (last_bytes != 0)
4591 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
4592 }
4593 }
4594
4595 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
4596 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
4597 }
4598
4599 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4600 if (out_words_to_go)
4601 {
4602 rtx sreg;
4603
4604 mem = gen_rtx_MEM (SImode, src);
4605 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4606 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4607 MEM_SCALAR_P (mem) = src_scalar_p;
4608 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
4609 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
4610
4611 mem = gen_rtx_MEM (SImode, dst);
4612 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4613 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4614 MEM_SCALAR_P (mem) = dst_scalar_p;
4615 emit_move_insn (mem, sreg);
4616 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
4617 in_words_to_go--;
4618
4619 if (in_words_to_go) /* Sanity check */
4620 abort ();
4621 }
4622
4623 if (in_words_to_go)
4624 {
4625 if (in_words_to_go < 0)
4626 abort ();
4627
4628 mem = gen_rtx_MEM (SImode, src);
4629 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4630 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4631 MEM_SCALAR_P (mem) = src_scalar_p;
4632 part_bytes_reg = copy_to_mode_reg (SImode, mem);
4633 }
4634
4635 if (last_bytes && part_bytes_reg == NULL)
4636 abort ();
4637
4638 if (BYTES_BIG_ENDIAN && last_bytes)
4639 {
4640 rtx tmp = gen_reg_rtx (SImode);
4641
4642 /* The bytes we want are in the top end of the word. */
4643 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
4644 GEN_INT (8 * (4 - last_bytes))));
4645 part_bytes_reg = tmp;
4646
4647 while (last_bytes)
4648 {
4649 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
4650 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4651 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4652 MEM_SCALAR_P (mem) = dst_scalar_p;
4653 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
4654
4655 if (--last_bytes)
4656 {
4657 tmp = gen_reg_rtx (SImode);
4658 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
4659 part_bytes_reg = tmp;
4660 }
4661 }
4662
4663 }
4664 else
4665 {
4666 if (last_bytes > 1)
4667 {
4668 mem = gen_rtx_MEM (HImode, dst);
4669 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4670 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4671 MEM_SCALAR_P (mem) = dst_scalar_p;
4672 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
4673 last_bytes -= 2;
4674 if (last_bytes)
4675 {
4676 rtx tmp = gen_reg_rtx (SImode);
4677
4678 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
4679 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
4680 part_bytes_reg = tmp;
4681 }
4682 }
4683
4684 if (last_bytes)
4685 {
4686 mem = gen_rtx_MEM (QImode, dst);
4687 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4688 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4689 MEM_SCALAR_P (mem) = dst_scalar_p;
4690 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
4691 }
4692 }
4693
4694 return 1;
4695 }
4696
4697 /* Generate a memory reference for a half word, such that it will be loaded
4698 into the top 16 bits of the word. We can assume that the address is
4699 known to be alignable and of the form reg, or plus (reg, const). */
4700
4701 rtx
arm_gen_rotated_half_load(memref)4702 arm_gen_rotated_half_load (memref)
4703 rtx memref;
4704 {
4705 HOST_WIDE_INT offset = 0;
4706 rtx base = XEXP (memref, 0);
4707
4708 if (GET_CODE (base) == PLUS)
4709 {
4710 offset = INTVAL (XEXP (base, 1));
4711 base = XEXP (base, 0);
4712 }
4713
4714 /* If we aren't allowed to generate unaligned addresses, then fail. */
4715 if (TARGET_MMU_TRAPS
4716 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
4717 return NULL;
4718
4719 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
4720
4721 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
4722 return base;
4723
4724 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
4725 }
4726
4727 /* Select a dominance comparison mode if possible. We support three forms.
4728 COND_OR == 0 => (X && Y)
4729 COND_OR == 1 => ((! X( || Y)
4730 COND_OR == 2 => (X || Y)
4731 If we are unable to support a dominance comparsison we return CC mode.
4732 This will then fail to match for the RTL expressions that generate this
4733 call. */
4734
4735 static enum machine_mode
select_dominance_cc_mode(x,y,cond_or)4736 select_dominance_cc_mode (x, y, cond_or)
4737 rtx x;
4738 rtx y;
4739 HOST_WIDE_INT cond_or;
4740 {
4741 enum rtx_code cond1, cond2;
4742 int swapped = 0;
4743
4744 /* Currently we will probably get the wrong result if the individual
4745 comparisons are not simple. This also ensures that it is safe to
4746 reverse a comparison if necessary. */
4747 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
4748 != CCmode)
4749 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
4750 != CCmode))
4751 return CCmode;
4752
4753 /* The if_then_else variant of this tests the second condition if the
4754 first passes, but is true if the first fails. Reverse the first
4755 condition to get a true "inclusive-or" expression. */
4756 if (cond_or == 1)
4757 cond1 = reverse_condition (cond1);
4758
4759 /* If the comparisons are not equal, and one doesn't dominate the other,
4760 then we can't do this. */
4761 if (cond1 != cond2
4762 && !comparison_dominates_p (cond1, cond2)
4763 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
4764 return CCmode;
4765
4766 if (swapped)
4767 {
4768 enum rtx_code temp = cond1;
4769 cond1 = cond2;
4770 cond2 = temp;
4771 }
4772
4773 switch (cond1)
4774 {
4775 case EQ:
4776 if (cond2 == EQ || !cond_or)
4777 return CC_DEQmode;
4778
4779 switch (cond2)
4780 {
4781 case LE: return CC_DLEmode;
4782 case LEU: return CC_DLEUmode;
4783 case GE: return CC_DGEmode;
4784 case GEU: return CC_DGEUmode;
4785 default: break;
4786 }
4787
4788 break;
4789
4790 case LT:
4791 if (cond2 == LT || !cond_or)
4792 return CC_DLTmode;
4793 if (cond2 == LE)
4794 return CC_DLEmode;
4795 if (cond2 == NE)
4796 return CC_DNEmode;
4797 break;
4798
4799 case GT:
4800 if (cond2 == GT || !cond_or)
4801 return CC_DGTmode;
4802 if (cond2 == GE)
4803 return CC_DGEmode;
4804 if (cond2 == NE)
4805 return CC_DNEmode;
4806 break;
4807
4808 case LTU:
4809 if (cond2 == LTU || !cond_or)
4810 return CC_DLTUmode;
4811 if (cond2 == LEU)
4812 return CC_DLEUmode;
4813 if (cond2 == NE)
4814 return CC_DNEmode;
4815 break;
4816
4817 case GTU:
4818 if (cond2 == GTU || !cond_or)
4819 return CC_DGTUmode;
4820 if (cond2 == GEU)
4821 return CC_DGEUmode;
4822 if (cond2 == NE)
4823 return CC_DNEmode;
4824 break;
4825
4826 /* The remaining cases only occur when both comparisons are the
4827 same. */
4828 case NE:
4829 return CC_DNEmode;
4830
4831 case LE:
4832 return CC_DLEmode;
4833
4834 case GE:
4835 return CC_DGEmode;
4836
4837 case LEU:
4838 return CC_DLEUmode;
4839
4840 case GEU:
4841 return CC_DGEUmode;
4842
4843 default:
4844 break;
4845 }
4846
4847 abort ();
4848 }
4849
4850 enum machine_mode
arm_select_cc_mode(op,x,y)4851 arm_select_cc_mode (op, x, y)
4852 enum rtx_code op;
4853 rtx x;
4854 rtx y;
4855 {
4856 /* All floating point compares return CCFP if it is an equality
4857 comparison, and CCFPE otherwise. */
4858 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4859 {
4860 switch (op)
4861 {
4862 case EQ:
4863 case NE:
4864 case UNORDERED:
4865 case ORDERED:
4866 case UNLT:
4867 case UNLE:
4868 case UNGT:
4869 case UNGE:
4870 case UNEQ:
4871 case LTGT:
4872 return CCFPmode;
4873
4874 case LT:
4875 case LE:
4876 case GT:
4877 case GE:
4878 return CCFPEmode;
4879
4880 default:
4881 abort ();
4882 }
4883 }
4884
4885 /* A compare with a shifted operand. Because of canonicalization, the
4886 comparison will have to be swapped when we emit the assembler. */
4887 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
4888 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4889 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
4890 || GET_CODE (x) == ROTATERT))
4891 return CC_SWPmode;
4892
4893 /* This is a special case that is used by combine to allow a
4894 comparison of a shifted byte load to be split into a zero-extend
4895 followed by a comparison of the shifted integer (only valid for
4896 equalities and unsigned inequalities). */
4897 if (GET_MODE (x) == SImode
4898 && GET_CODE (x) == ASHIFT
4899 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
4900 && GET_CODE (XEXP (x, 0)) == SUBREG
4901 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
4902 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
4903 && (op == EQ || op == NE
4904 || op == GEU || op == GTU || op == LTU || op == LEU)
4905 && GET_CODE (y) == CONST_INT)
4906 return CC_Zmode;
4907
4908 /* A construct for a conditional compare, if the false arm contains
4909 0, then both conditions must be true, otherwise either condition
4910 must be true. Not all conditions are possible, so CCmode is
4911 returned if it can't be done. */
4912 if (GET_CODE (x) == IF_THEN_ELSE
4913 && (XEXP (x, 2) == const0_rtx
4914 || XEXP (x, 2) == const1_rtx)
4915 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4916 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4917 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4918 INTVAL (XEXP (x, 2)));
4919
4920 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4921 if (GET_CODE (x) == AND
4922 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4923 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4924 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
4925
4926 if (GET_CODE (x) == IOR
4927 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4928 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4929 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
4930
4931 /* An operation that sets the condition codes as a side-effect, the
4932 V flag is not set correctly, so we can only use comparisons where
4933 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4934 instead. */
4935 if (GET_MODE (x) == SImode
4936 && y == const0_rtx
4937 && (op == EQ || op == NE || op == LT || op == GE)
4938 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
4939 || GET_CODE (x) == AND || GET_CODE (x) == IOR
4940 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
4941 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
4942 || GET_CODE (x) == LSHIFTRT
4943 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4944 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
4945 return CC_NOOVmode;
4946
4947 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4948 return CC_Zmode;
4949
4950 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4951 && GET_CODE (x) == PLUS
4952 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4953 return CC_Cmode;
4954
4955 return CCmode;
4956 }
4957
4958 /* X and Y are two things to compare using CODE. Emit the compare insn and
4959 return the rtx for register 0 in the proper mode. FP means this is a
4960 floating point compare: I don't think that it is needed on the arm. */
4961
4962 rtx
arm_gen_compare_reg(code,x,y)4963 arm_gen_compare_reg (code, x, y)
4964 enum rtx_code code;
4965 rtx x, y;
4966 {
4967 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4968 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
4969
4970 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4971 gen_rtx_COMPARE (mode, x, y)));
4972
4973 return cc_reg;
4974 }
4975
4976 /* Generate a sequence of insns that will generate the correct return
4977 address mask depending on the physical architecture that the program
4978 is running on. */
4979
4980 rtx
arm_gen_return_addr_mask()4981 arm_gen_return_addr_mask ()
4982 {
4983 rtx reg = gen_reg_rtx (Pmode);
4984
4985 emit_insn (gen_return_addr_mask (reg));
4986 return reg;
4987 }
4988
4989 void
arm_reload_in_hi(operands)4990 arm_reload_in_hi (operands)
4991 rtx * operands;
4992 {
4993 rtx ref = operands[1];
4994 rtx base, scratch;
4995 HOST_WIDE_INT offset = 0;
4996
4997 if (GET_CODE (ref) == SUBREG)
4998 {
4999 offset = SUBREG_BYTE (ref);
5000 ref = SUBREG_REG (ref);
5001 }
5002
5003 if (GET_CODE (ref) == REG)
5004 {
5005 /* We have a pseudo which has been spilt onto the stack; there
5006 are two cases here: the first where there is a simple
5007 stack-slot replacement and a second where the stack-slot is
5008 out of range, or is used as a subreg. */
5009 if (reg_equiv_mem[REGNO (ref)])
5010 {
5011 ref = reg_equiv_mem[REGNO (ref)];
5012 base = find_replacement (&XEXP (ref, 0));
5013 }
5014 else
5015 /* The slot is out of range, or was dressed up in a SUBREG. */
5016 base = reg_equiv_address[REGNO (ref)];
5017 }
5018 else
5019 base = find_replacement (&XEXP (ref, 0));
5020
5021 /* Handle the case where the address is too complex to be offset by 1. */
5022 if (GET_CODE (base) == MINUS
5023 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5024 {
5025 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5026
5027 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5028 base = base_plus;
5029 }
5030 else if (GET_CODE (base) == PLUS)
5031 {
5032 /* The addend must be CONST_INT, or we would have dealt with it above. */
5033 HOST_WIDE_INT hi, lo;
5034
5035 offset += INTVAL (XEXP (base, 1));
5036 base = XEXP (base, 0);
5037
5038 /* Rework the address into a legal sequence of insns. */
5039 /* Valid range for lo is -4095 -> 4095 */
5040 lo = (offset >= 0
5041 ? (offset & 0xfff)
5042 : -((-offset) & 0xfff));
5043
5044 /* Corner case, if lo is the max offset then we would be out of range
5045 once we have added the additional 1 below, so bump the msb into the
5046 pre-loading insn(s). */
5047 if (lo == 4095)
5048 lo &= 0x7ff;
5049
5050 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5051 ^ (HOST_WIDE_INT) 0x80000000)
5052 - (HOST_WIDE_INT) 0x80000000);
5053
5054 if (hi + lo != offset)
5055 abort ();
5056
5057 if (hi != 0)
5058 {
5059 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5060
5061 /* Get the base address; addsi3 knows how to handle constants
5062 that require more than one insn. */
5063 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5064 base = base_plus;
5065 offset = lo;
5066 }
5067 }
5068
5069 /* Operands[2] may overlap operands[0] (though it won't overlap
5070 operands[1]), that's why we asked for a DImode reg -- so we can
5071 use the bit that does not overlap. */
5072 if (REGNO (operands[2]) == REGNO (operands[0]))
5073 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5074 else
5075 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5076
5077 emit_insn (gen_zero_extendqisi2 (scratch,
5078 gen_rtx_MEM (QImode,
5079 plus_constant (base,
5080 offset))));
5081 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
5082 gen_rtx_MEM (QImode,
5083 plus_constant (base,
5084 offset + 1))));
5085 if (!BYTES_BIG_ENDIAN)
5086 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5087 gen_rtx_IOR (SImode,
5088 gen_rtx_ASHIFT
5089 (SImode,
5090 gen_rtx_SUBREG (SImode, operands[0], 0),
5091 GEN_INT (8)),
5092 scratch)));
5093 else
5094 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5095 gen_rtx_IOR (SImode,
5096 gen_rtx_ASHIFT (SImode, scratch,
5097 GEN_INT (8)),
5098 gen_rtx_SUBREG (SImode, operands[0],
5099 0))));
5100 }
5101
5102 /* Handle storing a half-word to memory during reload by synthesising as two
5103 byte stores. Take care not to clobber the input values until after we
5104 have moved them somewhere safe. This code assumes that if the DImode
5105 scratch in operands[2] overlaps either the input value or output address
5106 in some way, then that value must die in this insn (we absolutely need
5107 two scratch registers for some corner cases). */
5108
5109 void
arm_reload_out_hi(operands)5110 arm_reload_out_hi (operands)
5111 rtx * operands;
5112 {
5113 rtx ref = operands[0];
5114 rtx outval = operands[1];
5115 rtx base, scratch;
5116 HOST_WIDE_INT offset = 0;
5117
5118 if (GET_CODE (ref) == SUBREG)
5119 {
5120 offset = SUBREG_BYTE (ref);
5121 ref = SUBREG_REG (ref);
5122 }
5123
5124 if (GET_CODE (ref) == REG)
5125 {
5126 /* We have a pseudo which has been spilt onto the stack; there
5127 are two cases here: the first where there is a simple
5128 stack-slot replacement and a second where the stack-slot is
5129 out of range, or is used as a subreg. */
5130 if (reg_equiv_mem[REGNO (ref)])
5131 {
5132 ref = reg_equiv_mem[REGNO (ref)];
5133 base = find_replacement (&XEXP (ref, 0));
5134 }
5135 else
5136 /* The slot is out of range, or was dressed up in a SUBREG. */
5137 base = reg_equiv_address[REGNO (ref)];
5138 }
5139 else
5140 base = find_replacement (&XEXP (ref, 0));
5141
5142 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5143
5144 /* Handle the case where the address is too complex to be offset by 1. */
5145 if (GET_CODE (base) == MINUS
5146 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5147 {
5148 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5149
5150 /* Be careful not to destroy OUTVAL. */
5151 if (reg_overlap_mentioned_p (base_plus, outval))
5152 {
5153 /* Updating base_plus might destroy outval, see if we can
5154 swap the scratch and base_plus. */
5155 if (!reg_overlap_mentioned_p (scratch, outval))
5156 {
5157 rtx tmp = scratch;
5158 scratch = base_plus;
5159 base_plus = tmp;
5160 }
5161 else
5162 {
5163 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5164
5165 /* Be conservative and copy OUTVAL into the scratch now,
5166 this should only be necessary if outval is a subreg
5167 of something larger than a word. */
5168 /* XXX Might this clobber base? I can't see how it can,
5169 since scratch is known to overlap with OUTVAL, and
5170 must be wider than a word. */
5171 emit_insn (gen_movhi (scratch_hi, outval));
5172 outval = scratch_hi;
5173 }
5174 }
5175
5176 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5177 base = base_plus;
5178 }
5179 else if (GET_CODE (base) == PLUS)
5180 {
5181 /* The addend must be CONST_INT, or we would have dealt with it above. */
5182 HOST_WIDE_INT hi, lo;
5183
5184 offset += INTVAL (XEXP (base, 1));
5185 base = XEXP (base, 0);
5186
5187 /* Rework the address into a legal sequence of insns. */
5188 /* Valid range for lo is -4095 -> 4095 */
5189 lo = (offset >= 0
5190 ? (offset & 0xfff)
5191 : -((-offset) & 0xfff));
5192
5193 /* Corner case, if lo is the max offset then we would be out of range
5194 once we have added the additional 1 below, so bump the msb into the
5195 pre-loading insn(s). */
5196 if (lo == 4095)
5197 lo &= 0x7ff;
5198
5199 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5200 ^ (HOST_WIDE_INT) 0x80000000)
5201 - (HOST_WIDE_INT) 0x80000000);
5202
5203 if (hi + lo != offset)
5204 abort ();
5205
5206 if (hi != 0)
5207 {
5208 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5209
5210 /* Be careful not to destroy OUTVAL. */
5211 if (reg_overlap_mentioned_p (base_plus, outval))
5212 {
5213 /* Updating base_plus might destroy outval, see if we
5214 can swap the scratch and base_plus. */
5215 if (!reg_overlap_mentioned_p (scratch, outval))
5216 {
5217 rtx tmp = scratch;
5218 scratch = base_plus;
5219 base_plus = tmp;
5220 }
5221 else
5222 {
5223 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5224
5225 /* Be conservative and copy outval into scratch now,
5226 this should only be necessary if outval is a
5227 subreg of something larger than a word. */
5228 /* XXX Might this clobber base? I can't see how it
5229 can, since scratch is known to overlap with
5230 outval. */
5231 emit_insn (gen_movhi (scratch_hi, outval));
5232 outval = scratch_hi;
5233 }
5234 }
5235
5236 /* Get the base address; addsi3 knows how to handle constants
5237 that require more than one insn. */
5238 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5239 base = base_plus;
5240 offset = lo;
5241 }
5242 }
5243
5244 if (BYTES_BIG_ENDIAN)
5245 {
5246 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5247 plus_constant (base, offset + 1)),
5248 gen_lowpart (QImode, outval)));
5249 emit_insn (gen_lshrsi3 (scratch,
5250 gen_rtx_SUBREG (SImode, outval, 0),
5251 GEN_INT (8)));
5252 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5253 gen_lowpart (QImode, scratch)));
5254 }
5255 else
5256 {
5257 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5258 gen_lowpart (QImode, outval)));
5259 emit_insn (gen_lshrsi3 (scratch,
5260 gen_rtx_SUBREG (SImode, outval, 0),
5261 GEN_INT (8)));
5262 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5263 plus_constant (base, offset + 1)),
5264 gen_lowpart (QImode, scratch)));
5265 }
5266 }
5267
5268 /* Print a symbolic form of X to the debug file, F. */
5269
5270 static void
arm_print_value(f,x)5271 arm_print_value (f, x)
5272 FILE * f;
5273 rtx x;
5274 {
5275 switch (GET_CODE (x))
5276 {
5277 case CONST_INT:
5278 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5279 return;
5280
5281 case CONST_DOUBLE:
5282 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5283 return;
5284
5285 case CONST_STRING:
5286 fprintf (f, "\"%s\"", XSTR (x, 0));
5287 return;
5288
5289 case SYMBOL_REF:
5290 fprintf (f, "`%s'", XSTR (x, 0));
5291 return;
5292
5293 case LABEL_REF:
5294 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5295 return;
5296
5297 case CONST:
5298 arm_print_value (f, XEXP (x, 0));
5299 return;
5300
5301 case PLUS:
5302 arm_print_value (f, XEXP (x, 0));
5303 fprintf (f, "+");
5304 arm_print_value (f, XEXP (x, 1));
5305 return;
5306
5307 case PC:
5308 fprintf (f, "pc");
5309 return;
5310
5311 default:
5312 fprintf (f, "????");
5313 return;
5314 }
5315 }
5316
5317 /* Routines for manipulation of the constant pool. */
5318
5319 /* Arm instructions cannot load a large constant directly into a
5320 register; they have to come from a pc relative load. The constant
5321 must therefore be placed in the addressable range of the pc
5322 relative load. Depending on the precise pc relative load
5323 instruction the range is somewhere between 256 bytes and 4k. This
5324 means that we often have to dump a constant inside a function, and
5325 generate code to branch around it.
5326
5327 It is important to minimize this, since the branches will slow
5328 things down and make the code larger.
5329
5330 Normally we can hide the table after an existing unconditional
5331 branch so that there is no interruption of the flow, but in the
5332 worst case the code looks like this:
5333
5334 ldr rn, L1
5335 ...
5336 b L2
5337 align
5338 L1: .long value
5339 L2:
5340 ...
5341
5342 ldr rn, L3
5343 ...
5344 b L4
5345 align
5346 L3: .long value
5347 L4:
5348 ...
5349
5350 We fix this by performing a scan after scheduling, which notices
5351 which instructions need to have their operands fetched from the
5352 constant table and builds the table.
5353
5354 The algorithm starts by building a table of all the constants that
5355 need fixing up and all the natural barriers in the function (places
5356 where a constant table can be dropped without breaking the flow).
5357 For each fixup we note how far the pc-relative replacement will be
5358 able to reach and the offset of the instruction into the function.
5359
5360 Having built the table we then group the fixes together to form
5361 tables that are as large as possible (subject to addressing
5362 constraints) and emit each table of constants after the last
5363 barrier that is within range of all the instructions in the group.
5364 If a group does not contain a barrier, then we forcibly create one
5365 by inserting a jump instruction into the flow. Once the table has
5366 been inserted, the insns are then modified to reference the
5367 relevant entry in the pool.
5368
5369 Possible enhancements to the algorithm (not implemented) are:
5370
5371 1) For some processors and object formats, there may be benefit in
5372 aligning the pools to the start of cache lines; this alignment
5373 would need to be taken into account when calculating addressability
5374 of a pool. */
5375
5376 /* These typedefs are located at the start of this file, so that
5377 they can be used in the prototypes there. This comment is to
5378 remind readers of that fact so that the following structures
5379 can be understood more easily.
5380
5381 typedef struct minipool_node Mnode;
5382 typedef struct minipool_fixup Mfix; */
5383
5384 struct minipool_node
5385 {
5386 /* Doubly linked chain of entries. */
5387 Mnode * next;
5388 Mnode * prev;
5389 /* The maximum offset into the code that this entry can be placed. While
5390 pushing fixes for forward references, all entries are sorted in order
5391 of increasing max_address. */
5392 HOST_WIDE_INT max_address;
5393 /* Similarly for an entry inserted for a backwards ref. */
5394 HOST_WIDE_INT min_address;
5395 /* The number of fixes referencing this entry. This can become zero
5396 if we "unpush" an entry. In this case we ignore the entry when we
5397 come to emit the code. */
5398 int refcount;
5399 /* The offset from the start of the minipool. */
5400 HOST_WIDE_INT offset;
5401 /* The value in table. */
5402 rtx value;
5403 /* The mode of value. */
5404 enum machine_mode mode;
5405 int fix_size;
5406 };
5407
5408 struct minipool_fixup
5409 {
5410 Mfix * next;
5411 rtx insn;
5412 HOST_WIDE_INT address;
5413 rtx * loc;
5414 enum machine_mode mode;
5415 int fix_size;
5416 rtx value;
5417 Mnode * minipool;
5418 HOST_WIDE_INT forwards;
5419 HOST_WIDE_INT backwards;
5420 };
5421
5422 /* Fixes less than a word need padding out to a word boundary. */
5423 #define MINIPOOL_FIX_SIZE(mode) \
5424 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5425
5426 static Mnode * minipool_vector_head;
5427 static Mnode * minipool_vector_tail;
5428 static rtx minipool_vector_label;
5429
5430 /* The linked list of all minipool fixes required for this function. */
5431 Mfix * minipool_fix_head;
5432 Mfix * minipool_fix_tail;
5433 /* The fix entry for the current minipool, once it has been placed. */
5434 Mfix * minipool_barrier;
5435
5436 /* Determines if INSN is the start of a jump table. Returns the end
5437 of the TABLE or NULL_RTX. */
5438
5439 static rtx
is_jump_table(insn)5440 is_jump_table (insn)
5441 rtx insn;
5442 {
5443 rtx table;
5444
5445 if (GET_CODE (insn) == JUMP_INSN
5446 && JUMP_LABEL (insn) != NULL
5447 && ((table = next_real_insn (JUMP_LABEL (insn)))
5448 == next_real_insn (insn))
5449 && table != NULL
5450 && GET_CODE (table) == JUMP_INSN
5451 && (GET_CODE (PATTERN (table)) == ADDR_VEC
5452 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
5453 return table;
5454
5455 return NULL_RTX;
5456 }
5457
5458 #ifndef JUMP_TABLES_IN_TEXT_SECTION
5459 #define JUMP_TABLES_IN_TEXT_SECTION 0
5460 #endif
5461
5462 static HOST_WIDE_INT
get_jump_table_size(insn)5463 get_jump_table_size (insn)
5464 rtx insn;
5465 {
5466 /* ADDR_VECs only take room if read-only data does into the text
5467 section. */
5468 if (JUMP_TABLES_IN_TEXT_SECTION
5469 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
5470 || 1
5471 #endif
5472 )
5473 {
5474 rtx body = PATTERN (insn);
5475 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5476
5477 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5478 }
5479
5480 return 0;
5481 }
5482
5483 /* Move a minipool fix MP from its current location to before MAX_MP.
5484 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5485 contrains may need updating. */
5486
5487 static Mnode *
move_minipool_fix_forward_ref(mp,max_mp,max_address)5488 move_minipool_fix_forward_ref (mp, max_mp, max_address)
5489 Mnode * mp;
5490 Mnode * max_mp;
5491 HOST_WIDE_INT max_address;
5492 {
5493 /* This should never be true and the code below assumes these are
5494 different. */
5495 if (mp == max_mp)
5496 abort ();
5497
5498 if (max_mp == NULL)
5499 {
5500 if (max_address < mp->max_address)
5501 mp->max_address = max_address;
5502 }
5503 else
5504 {
5505 if (max_address > max_mp->max_address - mp->fix_size)
5506 mp->max_address = max_mp->max_address - mp->fix_size;
5507 else
5508 mp->max_address = max_address;
5509
5510 /* Unlink MP from its current position. Since max_mp is non-null,
5511 mp->prev must be non-null. */
5512 mp->prev->next = mp->next;
5513 if (mp->next != NULL)
5514 mp->next->prev = mp->prev;
5515 else
5516 minipool_vector_tail = mp->prev;
5517
5518 /* Re-insert it before MAX_MP. */
5519 mp->next = max_mp;
5520 mp->prev = max_mp->prev;
5521 max_mp->prev = mp;
5522
5523 if (mp->prev != NULL)
5524 mp->prev->next = mp;
5525 else
5526 minipool_vector_head = mp;
5527 }
5528
5529 /* Save the new entry. */
5530 max_mp = mp;
5531
5532 /* Scan over the preceding entries and adjust their addresses as
5533 required. */
5534 while (mp->prev != NULL
5535 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5536 {
5537 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5538 mp = mp->prev;
5539 }
5540
5541 return max_mp;
5542 }
5543
5544 /* Add a constant to the minipool for a forward reference. Returns the
5545 node added or NULL if the constant will not fit in this pool. */
5546
5547 static Mnode *
add_minipool_forward_ref(fix)5548 add_minipool_forward_ref (fix)
5549 Mfix * fix;
5550 {
5551 /* If set, max_mp is the first pool_entry that has a lower
5552 constraint than the one we are trying to add. */
5553 Mnode * max_mp = NULL;
5554 HOST_WIDE_INT max_address = fix->address + fix->forwards;
5555 Mnode * mp;
5556
5557 /* If this fix's address is greater than the address of the first
5558 entry, then we can't put the fix in this pool. We subtract the
5559 size of the current fix to ensure that if the table is fully
5560 packed we still have enough room to insert this value by suffling
5561 the other fixes forwards. */
5562 if (minipool_vector_head &&
5563 fix->address >= minipool_vector_head->max_address - fix->fix_size)
5564 return NULL;
5565
5566 /* Scan the pool to see if a constant with the same value has
5567 already been added. While we are doing this, also note the
5568 location where we must insert the constant if it doesn't already
5569 exist. */
5570 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5571 {
5572 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5573 && fix->mode == mp->mode
5574 && (GET_CODE (fix->value) != CODE_LABEL
5575 || (CODE_LABEL_NUMBER (fix->value)
5576 == CODE_LABEL_NUMBER (mp->value)))
5577 && rtx_equal_p (fix->value, mp->value))
5578 {
5579 /* More than one fix references this entry. */
5580 mp->refcount++;
5581 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5582 }
5583
5584 /* Note the insertion point if necessary. */
5585 if (max_mp == NULL
5586 && mp->max_address > max_address)
5587 max_mp = mp;
5588 }
5589
5590 /* The value is not currently in the minipool, so we need to create
5591 a new entry for it. If MAX_MP is NULL, the entry will be put on
5592 the end of the list since the placement is less constrained than
5593 any existing entry. Otherwise, we insert the new fix before
5594 MAX_MP and, if neceesary, adjust the constraints on the other
5595 entries. */
5596 mp = xmalloc (sizeof (* mp));
5597 mp->fix_size = fix->fix_size;
5598 mp->mode = fix->mode;
5599 mp->value = fix->value;
5600 mp->refcount = 1;
5601 /* Not yet required for a backwards ref. */
5602 mp->min_address = -65536;
5603
5604 if (max_mp == NULL)
5605 {
5606 mp->max_address = max_address;
5607 mp->next = NULL;
5608 mp->prev = minipool_vector_tail;
5609
5610 if (mp->prev == NULL)
5611 {
5612 minipool_vector_head = mp;
5613 minipool_vector_label = gen_label_rtx ();
5614 }
5615 else
5616 mp->prev->next = mp;
5617
5618 minipool_vector_tail = mp;
5619 }
5620 else
5621 {
5622 if (max_address > max_mp->max_address - mp->fix_size)
5623 mp->max_address = max_mp->max_address - mp->fix_size;
5624 else
5625 mp->max_address = max_address;
5626
5627 mp->next = max_mp;
5628 mp->prev = max_mp->prev;
5629 max_mp->prev = mp;
5630 if (mp->prev != NULL)
5631 mp->prev->next = mp;
5632 else
5633 minipool_vector_head = mp;
5634 }
5635
5636 /* Save the new entry. */
5637 max_mp = mp;
5638
5639 /* Scan over the preceding entries and adjust their addresses as
5640 required. */
5641 while (mp->prev != NULL
5642 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5643 {
5644 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5645 mp = mp->prev;
5646 }
5647
5648 return max_mp;
5649 }
5650
5651 static Mnode *
move_minipool_fix_backward_ref(mp,min_mp,min_address)5652 move_minipool_fix_backward_ref (mp, min_mp, min_address)
5653 Mnode * mp;
5654 Mnode * min_mp;
5655 HOST_WIDE_INT min_address;
5656 {
5657 HOST_WIDE_INT offset;
5658
5659 /* This should never be true, and the code below assumes these are
5660 different. */
5661 if (mp == min_mp)
5662 abort ();
5663
5664 if (min_mp == NULL)
5665 {
5666 if (min_address > mp->min_address)
5667 mp->min_address = min_address;
5668 }
5669 else
5670 {
5671 /* We will adjust this below if it is too loose. */
5672 mp->min_address = min_address;
5673
5674 /* Unlink MP from its current position. Since min_mp is non-null,
5675 mp->next must be non-null. */
5676 mp->next->prev = mp->prev;
5677 if (mp->prev != NULL)
5678 mp->prev->next = mp->next;
5679 else
5680 minipool_vector_head = mp->next;
5681
5682 /* Reinsert it after MIN_MP. */
5683 mp->prev = min_mp;
5684 mp->next = min_mp->next;
5685 min_mp->next = mp;
5686 if (mp->next != NULL)
5687 mp->next->prev = mp;
5688 else
5689 minipool_vector_tail = mp;
5690 }
5691
5692 min_mp = mp;
5693
5694 offset = 0;
5695 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5696 {
5697 mp->offset = offset;
5698 if (mp->refcount > 0)
5699 offset += mp->fix_size;
5700
5701 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5702 mp->next->min_address = mp->min_address + mp->fix_size;
5703 }
5704
5705 return min_mp;
5706 }
5707
5708 /* Add a constant to the minipool for a backward reference. Returns the
5709 node added or NULL if the constant will not fit in this pool.
5710
5711 Note that the code for insertion for a backwards reference can be
5712 somewhat confusing because the calculated offsets for each fix do
5713 not take into account the size of the pool (which is still under
5714 construction. */
5715
5716 static Mnode *
add_minipool_backward_ref(fix)5717 add_minipool_backward_ref (fix)
5718 Mfix * fix;
5719 {
5720 /* If set, min_mp is the last pool_entry that has a lower constraint
5721 than the one we are trying to add. */
5722 Mnode * min_mp = NULL;
5723 /* This can be negative, since it is only a constraint. */
5724 HOST_WIDE_INT min_address = fix->address - fix->backwards;
5725 Mnode * mp;
5726
5727 /* If we can't reach the current pool from this insn, or if we can't
5728 insert this entry at the end of the pool without pushing other
5729 fixes out of range, then we don't try. This ensures that we
5730 can't fail later on. */
5731 if (min_address >= minipool_barrier->address
5732 || (minipool_vector_tail->min_address + fix->fix_size
5733 >= minipool_barrier->address))
5734 return NULL;
5735
5736 /* Scan the pool to see if a constant with the same value has
5737 already been added. While we are doing this, also note the
5738 location where we must insert the constant if it doesn't already
5739 exist. */
5740 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5741 {
5742 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5743 && fix->mode == mp->mode
5744 && (GET_CODE (fix->value) != CODE_LABEL
5745 || (CODE_LABEL_NUMBER (fix->value)
5746 == CODE_LABEL_NUMBER (mp->value)))
5747 && rtx_equal_p (fix->value, mp->value)
5748 /* Check that there is enough slack to move this entry to the
5749 end of the table (this is conservative). */
5750 && (mp->max_address
5751 > (minipool_barrier->address
5752 + minipool_vector_tail->offset
5753 + minipool_vector_tail->fix_size)))
5754 {
5755 mp->refcount++;
5756 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5757 }
5758
5759 if (min_mp != NULL)
5760 mp->min_address += fix->fix_size;
5761 else
5762 {
5763 /* Note the insertion point if necessary. */
5764 if (mp->min_address < min_address)
5765 min_mp = mp;
5766 else if (mp->max_address
5767 < minipool_barrier->address + mp->offset + fix->fix_size)
5768 {
5769 /* Inserting before this entry would push the fix beyond
5770 its maximum address (which can happen if we have
5771 re-located a forwards fix); force the new fix to come
5772 after it. */
5773 min_mp = mp;
5774 min_address = mp->min_address + fix->fix_size;
5775 }
5776 }
5777 }
5778
5779 /* We need to create a new entry. */
5780 mp = xmalloc (sizeof (* mp));
5781 mp->fix_size = fix->fix_size;
5782 mp->mode = fix->mode;
5783 mp->value = fix->value;
5784 mp->refcount = 1;
5785 mp->max_address = minipool_barrier->address + 65536;
5786
5787 mp->min_address = min_address;
5788
5789 if (min_mp == NULL)
5790 {
5791 mp->prev = NULL;
5792 mp->next = minipool_vector_head;
5793
5794 if (mp->next == NULL)
5795 {
5796 minipool_vector_tail = mp;
5797 minipool_vector_label = gen_label_rtx ();
5798 }
5799 else
5800 mp->next->prev = mp;
5801
5802 minipool_vector_head = mp;
5803 }
5804 else
5805 {
5806 mp->next = min_mp->next;
5807 mp->prev = min_mp;
5808 min_mp->next = mp;
5809
5810 if (mp->next != NULL)
5811 mp->next->prev = mp;
5812 else
5813 minipool_vector_tail = mp;
5814 }
5815
5816 /* Save the new entry. */
5817 min_mp = mp;
5818
5819 if (mp->prev)
5820 mp = mp->prev;
5821 else
5822 mp->offset = 0;
5823
5824 /* Scan over the following entries and adjust their offsets. */
5825 while (mp->next != NULL)
5826 {
5827 if (mp->next->min_address < mp->min_address + mp->fix_size)
5828 mp->next->min_address = mp->min_address + mp->fix_size;
5829
5830 if (mp->refcount)
5831 mp->next->offset = mp->offset + mp->fix_size;
5832 else
5833 mp->next->offset = mp->offset;
5834
5835 mp = mp->next;
5836 }
5837
5838 return min_mp;
5839 }
5840
5841 static void
assign_minipool_offsets(barrier)5842 assign_minipool_offsets (barrier)
5843 Mfix * barrier;
5844 {
5845 HOST_WIDE_INT offset = 0;
5846 Mnode * mp;
5847
5848 minipool_barrier = barrier;
5849
5850 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5851 {
5852 mp->offset = offset;
5853
5854 if (mp->refcount > 0)
5855 offset += mp->fix_size;
5856 }
5857 }
5858
5859 /* Output the literal table */
5860 static void
dump_minipool(scan)5861 dump_minipool (scan)
5862 rtx scan;
5863 {
5864 Mnode * mp;
5865 Mnode * nmp;
5866
5867 if (rtl_dump_file)
5868 fprintf (rtl_dump_file,
5869 ";; Emitting minipool after insn %u; address %ld\n",
5870 INSN_UID (scan), (unsigned long) minipool_barrier->address);
5871
5872 scan = emit_label_after (gen_label_rtx (), scan);
5873 scan = emit_insn_after (gen_align_4 (), scan);
5874 scan = emit_label_after (minipool_vector_label, scan);
5875
5876 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
5877 {
5878 if (mp->refcount > 0)
5879 {
5880 if (rtl_dump_file)
5881 {
5882 fprintf (rtl_dump_file,
5883 ";; Offset %u, min %ld, max %ld ",
5884 (unsigned) mp->offset, (unsigned long) mp->min_address,
5885 (unsigned long) mp->max_address);
5886 arm_print_value (rtl_dump_file, mp->value);
5887 fputc ('\n', rtl_dump_file);
5888 }
5889
5890 switch (mp->fix_size)
5891 {
5892 #ifdef HAVE_consttable_1
5893 case 1:
5894 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
5895 break;
5896
5897 #endif
5898 #ifdef HAVE_consttable_2
5899 case 2:
5900 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
5901 break;
5902
5903 #endif
5904 #ifdef HAVE_consttable_4
5905 case 4:
5906 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
5907 break;
5908
5909 #endif
5910 #ifdef HAVE_consttable_8
5911 case 8:
5912 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
5913 break;
5914
5915 #endif
5916 default:
5917 abort ();
5918 break;
5919 }
5920 }
5921
5922 nmp = mp->next;
5923 free (mp);
5924 }
5925
5926 minipool_vector_head = minipool_vector_tail = NULL;
5927 scan = emit_insn_after (gen_consttable_end (), scan);
5928 scan = emit_barrier_after (scan);
5929 }
5930
5931 /* Return the cost of forcibly inserting a barrier after INSN. */
5932
5933 static int
arm_barrier_cost(insn)5934 arm_barrier_cost (insn)
5935 rtx insn;
5936 {
5937 /* Basing the location of the pool on the loop depth is preferable,
5938 but at the moment, the basic block information seems to be
5939 corrupt by this stage of the compilation. */
5940 int base_cost = 50;
5941 rtx next = next_nonnote_insn (insn);
5942
5943 if (next != NULL && GET_CODE (next) == CODE_LABEL)
5944 base_cost -= 20;
5945
5946 switch (GET_CODE (insn))
5947 {
5948 case CODE_LABEL:
5949 /* It will always be better to place the table before the label, rather
5950 than after it. */
5951 return 50;
5952
5953 case INSN:
5954 case CALL_INSN:
5955 return base_cost;
5956
5957 case JUMP_INSN:
5958 return base_cost - 10;
5959
5960 default:
5961 return base_cost + 10;
5962 }
5963 }
5964
5965 /* Find the best place in the insn stream in the range
5966 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5967 Create the barrier by inserting a jump and add a new fix entry for
5968 it. */
5969
5970 static Mfix *
create_fix_barrier(fix,max_address)5971 create_fix_barrier (fix, max_address)
5972 Mfix * fix;
5973 HOST_WIDE_INT max_address;
5974 {
5975 HOST_WIDE_INT count = 0;
5976 rtx barrier;
5977 rtx from = fix->insn;
5978 rtx selected = from;
5979 int selected_cost;
5980 HOST_WIDE_INT selected_address;
5981 Mfix * new_fix;
5982 HOST_WIDE_INT max_count = max_address - fix->address;
5983 rtx label = gen_label_rtx ();
5984
5985 selected_cost = arm_barrier_cost (from);
5986 selected_address = fix->address;
5987
5988 while (from && count < max_count)
5989 {
5990 rtx tmp;
5991 int new_cost;
5992
5993 /* This code shouldn't have been called if there was a natural barrier
5994 within range. */
5995 if (GET_CODE (from) == BARRIER)
5996 abort ();
5997
5998 /* Count the length of this insn. */
5999 count += get_attr_length (from);
6000
6001 /* If there is a jump table, add its length. */
6002 tmp = is_jump_table (from);
6003 if (tmp != NULL)
6004 {
6005 count += get_jump_table_size (tmp);
6006
6007 /* Jump tables aren't in a basic block, so base the cost on
6008 the dispatch insn. If we select this location, we will
6009 still put the pool after the table. */
6010 new_cost = arm_barrier_cost (from);
6011
6012 if (count < max_count && new_cost <= selected_cost)
6013 {
6014 selected = tmp;
6015 selected_cost = new_cost;
6016 selected_address = fix->address + count;
6017 }
6018
6019 /* Continue after the dispatch table. */
6020 from = NEXT_INSN (tmp);
6021 continue;
6022 }
6023
6024 new_cost = arm_barrier_cost (from);
6025
6026 if (count < max_count && new_cost <= selected_cost)
6027 {
6028 selected = from;
6029 selected_cost = new_cost;
6030 selected_address = fix->address + count;
6031 }
6032
6033 from = NEXT_INSN (from);
6034 }
6035
6036 /* Create a new JUMP_INSN that branches around a barrier. */
6037 from = emit_jump_insn_after (gen_jump (label), selected);
6038 JUMP_LABEL (from) = label;
6039 barrier = emit_barrier_after (from);
6040 emit_label_after (label, barrier);
6041
6042 /* Create a minipool barrier entry for the new barrier. */
6043 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
6044 new_fix->insn = barrier;
6045 new_fix->address = selected_address;
6046 new_fix->next = fix->next;
6047 fix->next = new_fix;
6048
6049 return new_fix;
6050 }
6051
6052 /* Record that there is a natural barrier in the insn stream at
6053 ADDRESS. */
6054 static void
push_minipool_barrier(insn,address)6055 push_minipool_barrier (insn, address)
6056 rtx insn;
6057 HOST_WIDE_INT address;
6058 {
6059 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6060
6061 fix->insn = insn;
6062 fix->address = address;
6063
6064 fix->next = NULL;
6065 if (minipool_fix_head != NULL)
6066 minipool_fix_tail->next = fix;
6067 else
6068 minipool_fix_head = fix;
6069
6070 minipool_fix_tail = fix;
6071 }
6072
6073 /* Record INSN, which will need fixing up to load a value from the
6074 minipool. ADDRESS is the offset of the insn since the start of the
6075 function; LOC is a pointer to the part of the insn which requires
6076 fixing; VALUE is the constant that must be loaded, which is of type
6077 MODE. */
6078 static void
push_minipool_fix(insn,address,loc,mode,value)6079 push_minipool_fix (insn, address, loc, mode, value)
6080 rtx insn;
6081 HOST_WIDE_INT address;
6082 rtx * loc;
6083 enum machine_mode mode;
6084 rtx value;
6085 {
6086 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6087
6088 #ifdef AOF_ASSEMBLER
6089 /* PIC symbol refereneces need to be converted into offsets into the
6090 based area. */
6091 /* XXX This shouldn't be done here. */
6092 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
6093 value = aof_pic_entry (value);
6094 #endif /* AOF_ASSEMBLER */
6095
6096 fix->insn = insn;
6097 fix->address = address;
6098 fix->loc = loc;
6099 fix->mode = mode;
6100 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
6101 fix->value = value;
6102 fix->forwards = get_attr_pool_range (insn);
6103 fix->backwards = get_attr_neg_pool_range (insn);
6104 fix->minipool = NULL;
6105
6106 /* If an insn doesn't have a range defined for it, then it isn't
6107 expecting to be reworked by this code. Better to abort now than
6108 to generate duff assembly code. */
6109 if (fix->forwards == 0 && fix->backwards == 0)
6110 abort ();
6111
6112 if (rtl_dump_file)
6113 {
6114 fprintf (rtl_dump_file,
6115 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6116 GET_MODE_NAME (mode),
6117 INSN_UID (insn), (unsigned long) address,
6118 -1 * (long)fix->backwards, (long)fix->forwards);
6119 arm_print_value (rtl_dump_file, fix->value);
6120 fprintf (rtl_dump_file, "\n");
6121 }
6122
6123 /* Add it to the chain of fixes. */
6124 fix->next = NULL;
6125
6126 if (minipool_fix_head != NULL)
6127 minipool_fix_tail->next = fix;
6128 else
6129 minipool_fix_head = fix;
6130
6131 minipool_fix_tail = fix;
6132 }
6133
6134 /* Scan INSN and note any of its operands that need fixing. */
6135
6136 static void
note_invalid_constants(insn,address)6137 note_invalid_constants (insn, address)
6138 rtx insn;
6139 HOST_WIDE_INT address;
6140 {
6141 int opno;
6142
6143 extract_insn (insn);
6144
6145 if (!constrain_operands (1))
6146 fatal_insn_not_found (insn);
6147
6148 /* Fill in recog_op_alt with information about the constraints of this
6149 insn. */
6150 preprocess_constraints ();
6151
6152 for (opno = 0; opno < recog_data.n_operands; opno++)
6153 {
6154 /* Things we need to fix can only occur in inputs. */
6155 if (recog_data.operand_type[opno] != OP_IN)
6156 continue;
6157
6158 /* If this alternative is a memory reference, then any mention
6159 of constants in this alternative is really to fool reload
6160 into allowing us to accept one there. We need to fix them up
6161 now so that we output the right code. */
6162 if (recog_op_alt[opno][which_alternative].memory_ok)
6163 {
6164 rtx op = recog_data.operand[opno];
6165
6166 if (CONSTANT_P (op))
6167 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6168 recog_data.operand_mode[opno], op);
6169 #if 0
6170 /* RWE: Now we look correctly at the operands for the insn,
6171 this shouldn't be needed any more. */
6172 #ifndef AOF_ASSEMBLER
6173 /* XXX Is this still needed? */
6174 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
6175 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6176 recog_data.operand_mode[opno],
6177 XVECEXP (op, 0, 0));
6178 #endif
6179 #endif
6180 else if (GET_CODE (op) == MEM
6181 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
6182 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
6183 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6184 recog_data.operand_mode[opno],
6185 get_pool_constant (XEXP (op, 0)));
6186 }
6187 }
6188 }
6189
6190 void
arm_reorg(first)6191 arm_reorg (first)
6192 rtx first;
6193 {
6194 rtx insn;
6195 HOST_WIDE_INT address = 0;
6196 Mfix * fix;
6197
6198 minipool_fix_head = minipool_fix_tail = NULL;
6199
6200 /* The first insn must always be a note, or the code below won't
6201 scan it properly. */
6202 if (GET_CODE (first) != NOTE)
6203 abort ();
6204
6205 /* Scan all the insns and record the operands that will need fixing. */
6206 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
6207 {
6208 if (GET_CODE (insn) == BARRIER)
6209 push_minipool_barrier (insn, address);
6210 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
6211 || GET_CODE (insn) == JUMP_INSN)
6212 {
6213 rtx table;
6214
6215 note_invalid_constants (insn, address);
6216 address += get_attr_length (insn);
6217
6218 /* If the insn is a vector jump, add the size of the table
6219 and skip the table. */
6220 if ((table = is_jump_table (insn)) != NULL)
6221 {
6222 address += get_jump_table_size (table);
6223 insn = table;
6224 }
6225 }
6226 }
6227
6228 fix = minipool_fix_head;
6229
6230 /* Now scan the fixups and perform the required changes. */
6231 while (fix)
6232 {
6233 Mfix * ftmp;
6234 Mfix * fdel;
6235 Mfix * last_added_fix;
6236 Mfix * last_barrier = NULL;
6237 Mfix * this_fix;
6238
6239 /* Skip any further barriers before the next fix. */
6240 while (fix && GET_CODE (fix->insn) == BARRIER)
6241 fix = fix->next;
6242
6243 /* No more fixes. */
6244 if (fix == NULL)
6245 break;
6246
6247 last_added_fix = NULL;
6248
6249 for (ftmp = fix; ftmp; ftmp = ftmp->next)
6250 {
6251 if (GET_CODE (ftmp->insn) == BARRIER)
6252 {
6253 if (ftmp->address >= minipool_vector_head->max_address)
6254 break;
6255
6256 last_barrier = ftmp;
6257 }
6258 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
6259 break;
6260
6261 last_added_fix = ftmp; /* Keep track of the last fix added. */
6262 }
6263
6264 /* If we found a barrier, drop back to that; any fixes that we
6265 could have reached but come after the barrier will now go in
6266 the next mini-pool. */
6267 if (last_barrier != NULL)
6268 {
6269 /* Reduce the refcount for those fixes that won't go into this
6270 pool after all. */
6271 for (fdel = last_barrier->next;
6272 fdel && fdel != ftmp;
6273 fdel = fdel->next)
6274 {
6275 fdel->minipool->refcount--;
6276 fdel->minipool = NULL;
6277 }
6278
6279 ftmp = last_barrier;
6280 }
6281 else
6282 {
6283 /* ftmp is first fix that we can't fit into this pool and
6284 there no natural barriers that we could use. Insert a
6285 new barrier in the code somewhere between the previous
6286 fix and this one, and arrange to jump around it. */
6287 HOST_WIDE_INT max_address;
6288
6289 /* The last item on the list of fixes must be a barrier, so
6290 we can never run off the end of the list of fixes without
6291 last_barrier being set. */
6292 if (ftmp == NULL)
6293 abort ();
6294
6295 max_address = minipool_vector_head->max_address;
6296 /* Check that there isn't another fix that is in range that
6297 we couldn't fit into this pool because the pool was
6298 already too large: we need to put the pool before such an
6299 instruction. */
6300 if (ftmp->address < max_address)
6301 max_address = ftmp->address;
6302
6303 last_barrier = create_fix_barrier (last_added_fix, max_address);
6304 }
6305
6306 assign_minipool_offsets (last_barrier);
6307
6308 while (ftmp)
6309 {
6310 if (GET_CODE (ftmp->insn) != BARRIER
6311 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
6312 == NULL))
6313 break;
6314
6315 ftmp = ftmp->next;
6316 }
6317
6318 /* Scan over the fixes we have identified for this pool, fixing them
6319 up and adding the constants to the pool itself. */
6320 for (this_fix = fix; this_fix && ftmp != this_fix;
6321 this_fix = this_fix->next)
6322 if (GET_CODE (this_fix->insn) != BARRIER)
6323 {
6324 rtx addr
6325 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
6326 minipool_vector_label),
6327 this_fix->minipool->offset);
6328 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
6329 }
6330
6331 dump_minipool (last_barrier->insn);
6332 fix = ftmp;
6333 }
6334
6335 /* From now on we must synthesize any constants that we can't handle
6336 directly. This can happen if the RTL gets split during final
6337 instruction generation. */
6338 after_arm_reorg = 1;
6339
6340 /* Free the minipool memory. */
6341 obstack_free (&minipool_obstack, minipool_startobj);
6342 }
6343
6344 /* Routines to output assembly language. */
6345
6346 /* If the rtx is the correct value then return the string of the number.
6347 In this way we can ensure that valid double constants are generated even
6348 when cross compiling. */
6349
6350 const char *
fp_immediate_constant(x)6351 fp_immediate_constant (x)
6352 rtx x;
6353 {
6354 REAL_VALUE_TYPE r;
6355 int i;
6356
6357 if (!fpa_consts_inited)
6358 init_fpa_table ();
6359
6360 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6361 for (i = 0; i < 8; i++)
6362 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
6363 return strings_fpa[i];
6364
6365 abort ();
6366 }
6367
6368 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6369
6370 static const char *
fp_const_from_val(r)6371 fp_const_from_val (r)
6372 REAL_VALUE_TYPE * r;
6373 {
6374 int i;
6375
6376 if (!fpa_consts_inited)
6377 init_fpa_table ();
6378
6379 for (i = 0; i < 8; i++)
6380 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
6381 return strings_fpa[i];
6382
6383 abort ();
6384 }
6385
6386 /* Output the operands of a LDM/STM instruction to STREAM.
6387 MASK is the ARM register set mask of which only bits 0-15 are important.
6388 REG is the base register, either the frame pointer or the stack pointer,
6389 INSTR is the possibly suffixed load or store instruction. */
6390
6391 static void
print_multi_reg(stream,instr,reg,mask)6392 print_multi_reg (stream, instr, reg, mask)
6393 FILE * stream;
6394 const char * instr;
6395 int reg;
6396 int mask;
6397 {
6398 int i;
6399 int not_first = FALSE;
6400
6401 fputc ('\t', stream);
6402 asm_fprintf (stream, instr, reg);
6403 fputs (", {", stream);
6404
6405 for (i = 0; i <= LAST_ARM_REGNUM; i++)
6406 if (mask & (1 << i))
6407 {
6408 if (not_first)
6409 fprintf (stream, ", ");
6410
6411 asm_fprintf (stream, "%r", i);
6412 not_first = TRUE;
6413 }
6414
6415 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^");
6416 }
6417
6418 /* Output a 'call' insn. */
6419
6420 const char *
output_call(operands)6421 output_call (operands)
6422 rtx * operands;
6423 {
6424 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6425
6426 if (REGNO (operands[0]) == LR_REGNUM)
6427 {
6428 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
6429 output_asm_insn ("mov%?\t%0, %|lr", operands);
6430 }
6431
6432 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6433
6434 if (TARGET_INTERWORK)
6435 output_asm_insn ("bx%?\t%0", operands);
6436 else
6437 output_asm_insn ("mov%?\t%|pc, %0", operands);
6438
6439 return "";
6440 }
6441
6442 /* Output a 'call' insn that is a reference in memory. */
6443
6444 const char *
output_call_mem(operands)6445 output_call_mem (operands)
6446 rtx * operands;
6447 {
6448 if (TARGET_INTERWORK)
6449 {
6450 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6451 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6452 output_asm_insn ("bx%?\t%|ip", operands);
6453 }
6454 else if (regno_use_in (LR_REGNUM, operands[0]))
6455 {
6456 /* LR is used in the memory address. We load the address in the
6457 first instruction. It's safe to use IP as the target of the
6458 load since the call will kill it anyway. */
6459 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6460 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6461 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
6462 }
6463 else
6464 {
6465 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6466 output_asm_insn ("ldr%?\t%|pc, %0", operands);
6467 }
6468
6469 return "";
6470 }
6471
6472
6473 /* Output a move from arm registers to an fpu registers.
6474 OPERANDS[0] is an fpu register.
6475 OPERANDS[1] is the first registers of an arm register pair. */
6476
6477 const char *
output_mov_long_double_fpu_from_arm(operands)6478 output_mov_long_double_fpu_from_arm (operands)
6479 rtx * operands;
6480 {
6481 int arm_reg0 = REGNO (operands[1]);
6482 rtx ops[3];
6483
6484 if (arm_reg0 == IP_REGNUM)
6485 abort ();
6486
6487 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6488 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6489 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6490
6491 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
6492 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
6493
6494 return "";
6495 }
6496
6497 /* Output a move from an fpu register to arm registers.
6498 OPERANDS[0] is the first registers of an arm register pair.
6499 OPERANDS[1] is an fpu register. */
6500
6501 const char *
output_mov_long_double_arm_from_fpu(operands)6502 output_mov_long_double_arm_from_fpu (operands)
6503 rtx * operands;
6504 {
6505 int arm_reg0 = REGNO (operands[0]);
6506 rtx ops[3];
6507
6508 if (arm_reg0 == IP_REGNUM)
6509 abort ();
6510
6511 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6512 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6513 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6514
6515 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
6516 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
6517 return "";
6518 }
6519
6520 /* Output a move from arm registers to arm registers of a long double
6521 OPERANDS[0] is the destination.
6522 OPERANDS[1] is the source. */
6523
6524 const char *
output_mov_long_double_arm_from_arm(operands)6525 output_mov_long_double_arm_from_arm (operands)
6526 rtx * operands;
6527 {
6528 /* We have to be careful here because the two might overlap. */
6529 int dest_start = REGNO (operands[0]);
6530 int src_start = REGNO (operands[1]);
6531 rtx ops[2];
6532 int i;
6533
6534 if (dest_start < src_start)
6535 {
6536 for (i = 0; i < 3; i++)
6537 {
6538 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6539 ops[1] = gen_rtx_REG (SImode, src_start + i);
6540 output_asm_insn ("mov%?\t%0, %1", ops);
6541 }
6542 }
6543 else
6544 {
6545 for (i = 2; i >= 0; i--)
6546 {
6547 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6548 ops[1] = gen_rtx_REG (SImode, src_start + i);
6549 output_asm_insn ("mov%?\t%0, %1", ops);
6550 }
6551 }
6552
6553 return "";
6554 }
6555
6556
6557 /* Output a move from arm registers to an fpu registers.
6558 OPERANDS[0] is an fpu register.
6559 OPERANDS[1] is the first registers of an arm register pair. */
6560
6561 const char *
output_mov_double_fpu_from_arm(operands)6562 output_mov_double_fpu_from_arm (operands)
6563 rtx * operands;
6564 {
6565 int arm_reg0 = REGNO (operands[1]);
6566 rtx ops[2];
6567
6568 if (arm_reg0 == IP_REGNUM)
6569 abort ();
6570
6571 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6572 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6573 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
6574 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
6575 return "";
6576 }
6577
6578 /* Output a move from an fpu register to arm registers.
6579 OPERANDS[0] is the first registers of an arm register pair.
6580 OPERANDS[1] is an fpu register. */
6581
6582 const char *
output_mov_double_arm_from_fpu(operands)6583 output_mov_double_arm_from_fpu (operands)
6584 rtx * operands;
6585 {
6586 int arm_reg0 = REGNO (operands[0]);
6587 rtx ops[2];
6588
6589 if (arm_reg0 == IP_REGNUM)
6590 abort ();
6591
6592 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6593 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6594 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
6595 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
6596 return "";
6597 }
6598
6599 /* Output a move between double words.
6600 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6601 or MEM<-REG and all MEMs must be offsettable addresses. */
6602
6603 const char *
output_move_double(operands)6604 output_move_double (operands)
6605 rtx * operands;
6606 {
6607 enum rtx_code code0 = GET_CODE (operands[0]);
6608 enum rtx_code code1 = GET_CODE (operands[1]);
6609 rtx otherops[3];
6610
6611 if (code0 == REG)
6612 {
6613 int reg0 = REGNO (operands[0]);
6614
6615 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
6616
6617 if (code1 == REG)
6618 {
6619 int reg1 = REGNO (operands[1]);
6620 if (reg1 == IP_REGNUM)
6621 abort ();
6622
6623 /* Ensure the second source is not overwritten. */
6624 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
6625 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
6626 else
6627 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
6628 }
6629 else if (code1 == CONST_DOUBLE)
6630 {
6631 if (GET_MODE (operands[1]) == DFmode)
6632 {
6633 REAL_VALUE_TYPE r;
6634 long l[2];
6635
6636 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
6637 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
6638 otherops[1] = GEN_INT (l[1]);
6639 operands[1] = GEN_INT (l[0]);
6640 }
6641 else if (GET_MODE (operands[1]) != VOIDmode)
6642 abort ();
6643 else if (WORDS_BIG_ENDIAN)
6644 {
6645 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6646 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6647 }
6648 else
6649 {
6650 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6651 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6652 }
6653
6654 output_mov_immediate (operands);
6655 output_mov_immediate (otherops);
6656 }
6657 else if (code1 == CONST_INT)
6658 {
6659 #if HOST_BITS_PER_WIDE_INT > 32
6660 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6661 what the upper word is. */
6662 if (WORDS_BIG_ENDIAN)
6663 {
6664 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6665 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6666 }
6667 else
6668 {
6669 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6670 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6671 }
6672 #else
6673 /* Sign extend the intval into the high-order word. */
6674 if (WORDS_BIG_ENDIAN)
6675 {
6676 otherops[1] = operands[1];
6677 operands[1] = (INTVAL (operands[1]) < 0
6678 ? constm1_rtx : const0_rtx);
6679 }
6680 else
6681 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
6682 #endif
6683 output_mov_immediate (otherops);
6684 output_mov_immediate (operands);
6685 }
6686 else if (code1 == MEM)
6687 {
6688 switch (GET_CODE (XEXP (operands[1], 0)))
6689 {
6690 case REG:
6691 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
6692 break;
6693
6694 case PRE_INC:
6695 abort (); /* Should never happen now. */
6696 break;
6697
6698 case PRE_DEC:
6699 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
6700 break;
6701
6702 case POST_INC:
6703 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
6704 break;
6705
6706 case POST_DEC:
6707 abort (); /* Should never happen now. */
6708 break;
6709
6710 case LABEL_REF:
6711 case CONST:
6712 output_asm_insn ("adr%?\t%0, %1", operands);
6713 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
6714 break;
6715
6716 default:
6717 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
6718 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
6719 {
6720 otherops[0] = operands[0];
6721 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
6722 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
6723
6724 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
6725 {
6726 if (GET_CODE (otherops[2]) == CONST_INT)
6727 {
6728 switch (INTVAL (otherops[2]))
6729 {
6730 case -8:
6731 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
6732 return "";
6733 case -4:
6734 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
6735 return "";
6736 case 4:
6737 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
6738 return "";
6739 }
6740
6741 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
6742 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
6743 else
6744 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6745 }
6746 else
6747 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6748 }
6749 else
6750 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
6751
6752 return "ldm%?ia\t%0, %M0";
6753 }
6754 else
6755 {
6756 otherops[1] = adjust_address (operands[1], SImode, 4);
6757 /* Take care of overlapping base/data reg. */
6758 if (reg_mentioned_p (operands[0], operands[1]))
6759 {
6760 output_asm_insn ("ldr%?\t%0, %1", otherops);
6761 output_asm_insn ("ldr%?\t%0, %1", operands);
6762 }
6763 else
6764 {
6765 output_asm_insn ("ldr%?\t%0, %1", operands);
6766 output_asm_insn ("ldr%?\t%0, %1", otherops);
6767 }
6768 }
6769 }
6770 }
6771 else
6772 abort (); /* Constraints should prevent this. */
6773 }
6774 else if (code0 == MEM && code1 == REG)
6775 {
6776 if (REGNO (operands[1]) == IP_REGNUM)
6777 abort ();
6778
6779 switch (GET_CODE (XEXP (operands[0], 0)))
6780 {
6781 case REG:
6782 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
6783 break;
6784
6785 case PRE_INC:
6786 abort (); /* Should never happen now. */
6787 break;
6788
6789 case PRE_DEC:
6790 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
6791 break;
6792
6793 case POST_INC:
6794 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
6795 break;
6796
6797 case POST_DEC:
6798 abort (); /* Should never happen now. */
6799 break;
6800
6801 case PLUS:
6802 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
6803 {
6804 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
6805 {
6806 case -8:
6807 output_asm_insn ("stm%?db\t%m0, %M1", operands);
6808 return "";
6809
6810 case -4:
6811 output_asm_insn ("stm%?da\t%m0, %M1", operands);
6812 return "";
6813
6814 case 4:
6815 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
6816 return "";
6817 }
6818 }
6819 /* Fall through */
6820
6821 default:
6822 otherops[0] = adjust_address (operands[0], SImode, 4);
6823 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
6824 output_asm_insn ("str%?\t%1, %0", operands);
6825 output_asm_insn ("str%?\t%1, %0", otherops);
6826 }
6827 }
6828 else
6829 /* Constraints should prevent this. */
6830 abort ();
6831
6832 return "";
6833 }
6834
6835
6836 /* Output an arbitrary MOV reg, #n.
6837 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6838
6839 const char *
output_mov_immediate(operands)6840 output_mov_immediate (operands)
6841 rtx * operands;
6842 {
6843 HOST_WIDE_INT n = INTVAL (operands[1]);
6844
6845 /* Try to use one MOV. */
6846 if (const_ok_for_arm (n))
6847 output_asm_insn ("mov%?\t%0, %1", operands);
6848
6849 /* Try to use one MVN. */
6850 else if (const_ok_for_arm (~n))
6851 {
6852 operands[1] = GEN_INT (~n);
6853 output_asm_insn ("mvn%?\t%0, %1", operands);
6854 }
6855 else
6856 {
6857 int n_ones = 0;
6858 int i;
6859
6860 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6861 for (i = 0; i < 32; i ++)
6862 if (n & 1 << i)
6863 n_ones ++;
6864
6865 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
6866 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
6867 else
6868 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
6869 }
6870
6871 return "";
6872 }
6873
6874 /* Output an ADD r, s, #n where n may be too big for one instruction.
6875 If adding zero to one register, output nothing. */
6876
6877 const char *
output_add_immediate(operands)6878 output_add_immediate (operands)
6879 rtx * operands;
6880 {
6881 HOST_WIDE_INT n = INTVAL (operands[2]);
6882
6883 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
6884 {
6885 if (n < 0)
6886 output_multi_immediate (operands,
6887 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6888 -n);
6889 else
6890 output_multi_immediate (operands,
6891 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6892 n);
6893 }
6894
6895 return "";
6896 }
6897
6898 /* Output a multiple immediate operation.
6899 OPERANDS is the vector of operands referred to in the output patterns.
6900 INSTR1 is the output pattern to use for the first constant.
6901 INSTR2 is the output pattern to use for subsequent constants.
6902 IMMED_OP is the index of the constant slot in OPERANDS.
6903 N is the constant value. */
6904
6905 static const char *
output_multi_immediate(operands,instr1,instr2,immed_op,n)6906 output_multi_immediate (operands, instr1, instr2, immed_op, n)
6907 rtx * operands;
6908 const char * instr1;
6909 const char * instr2;
6910 int immed_op;
6911 HOST_WIDE_INT n;
6912 {
6913 #if HOST_BITS_PER_WIDE_INT > 32
6914 n &= 0xffffffff;
6915 #endif
6916
6917 if (n == 0)
6918 {
6919 /* Quick and easy output. */
6920 operands[immed_op] = const0_rtx;
6921 output_asm_insn (instr1, operands);
6922 }
6923 else
6924 {
6925 int i;
6926 const char * instr = instr1;
6927
6928 /* Note that n is never zero here (which would give no output). */
6929 for (i = 0; i < 32; i += 2)
6930 {
6931 if (n & (3 << i))
6932 {
6933 operands[immed_op] = GEN_INT (n & (255 << i));
6934 output_asm_insn (instr, operands);
6935 instr = instr2;
6936 i += 6;
6937 }
6938 }
6939 }
6940
6941 return "";
6942 }
6943
6944 /* Return the appropriate ARM instruction for the operation code.
6945 The returned result should not be overwritten. OP is the rtx of the
6946 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6947 was shifted. */
6948
6949 const char *
arithmetic_instr(op,shift_first_arg)6950 arithmetic_instr (op, shift_first_arg)
6951 rtx op;
6952 int shift_first_arg;
6953 {
6954 switch (GET_CODE (op))
6955 {
6956 case PLUS:
6957 return "add";
6958
6959 case MINUS:
6960 return shift_first_arg ? "rsb" : "sub";
6961
6962 case IOR:
6963 return "orr";
6964
6965 case XOR:
6966 return "eor";
6967
6968 case AND:
6969 return "and";
6970
6971 default:
6972 abort ();
6973 }
6974 }
6975
6976 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6977 for the operation code. The returned result should not be overwritten.
6978 OP is the rtx code of the shift.
6979 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6980 shift. */
6981
6982 static const char *
shift_op(op,amountp)6983 shift_op (op, amountp)
6984 rtx op;
6985 HOST_WIDE_INT *amountp;
6986 {
6987 const char * mnem;
6988 enum rtx_code code = GET_CODE (op);
6989
6990 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
6991 *amountp = -1;
6992 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
6993 *amountp = INTVAL (XEXP (op, 1));
6994 else
6995 abort ();
6996
6997 switch (code)
6998 {
6999 case ASHIFT:
7000 mnem = "asl";
7001 break;
7002
7003 case ASHIFTRT:
7004 mnem = "asr";
7005 break;
7006
7007 case LSHIFTRT:
7008 mnem = "lsr";
7009 break;
7010
7011 case ROTATERT:
7012 mnem = "ror";
7013 break;
7014
7015 case MULT:
7016 /* We never have to worry about the amount being other than a
7017 power of 2, since this case can never be reloaded from a reg. */
7018 if (*amountp != -1)
7019 *amountp = int_log2 (*amountp);
7020 else
7021 abort ();
7022 return "asl";
7023
7024 default:
7025 abort ();
7026 }
7027
7028 if (*amountp != -1)
7029 {
7030 /* This is not 100% correct, but follows from the desire to merge
7031 multiplication by a power of 2 with the recognizer for a
7032 shift. >=32 is not a valid shift for "asl", so we must try and
7033 output a shift that produces the correct arithmetical result.
7034 Using lsr #32 is identical except for the fact that the carry bit
7035 is not set correctly if we set the flags; but we never use the
7036 carry bit from such an operation, so we can ignore that. */
7037 if (code == ROTATERT)
7038 /* Rotate is just modulo 32. */
7039 *amountp &= 31;
7040 else if (*amountp != (*amountp & 31))
7041 {
7042 if (code == ASHIFT)
7043 mnem = "lsr";
7044 *amountp = 32;
7045 }
7046
7047 /* Shifts of 0 are no-ops. */
7048 if (*amountp == 0)
7049 return NULL;
7050 }
7051
7052 return mnem;
7053 }
7054
7055 /* Obtain the shift from the POWER of two. */
7056
7057 static HOST_WIDE_INT
int_log2(power)7058 int_log2 (power)
7059 HOST_WIDE_INT power;
7060 {
7061 HOST_WIDE_INT shift = 0;
7062
7063 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
7064 {
7065 if (shift > 31)
7066 abort ();
7067 shift ++;
7068 }
7069
7070 return shift;
7071 }
7072
7073 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7074 /bin/as is horribly restrictive. */
7075 #define MAX_ASCII_LEN 51
7076
7077 void
output_ascii_pseudo_op(stream,p,len)7078 output_ascii_pseudo_op (stream, p, len)
7079 FILE * stream;
7080 const unsigned char * p;
7081 int len;
7082 {
7083 int i;
7084 int len_so_far = 0;
7085
7086 fputs ("\t.ascii\t\"", stream);
7087
7088 for (i = 0; i < len; i++)
7089 {
7090 int c = p[i];
7091
7092 if (len_so_far >= MAX_ASCII_LEN)
7093 {
7094 fputs ("\"\n\t.ascii\t\"", stream);
7095 len_so_far = 0;
7096 }
7097
7098 switch (c)
7099 {
7100 case TARGET_TAB:
7101 fputs ("\\t", stream);
7102 len_so_far += 2;
7103 break;
7104
7105 case TARGET_FF:
7106 fputs ("\\f", stream);
7107 len_so_far += 2;
7108 break;
7109
7110 case TARGET_BS:
7111 fputs ("\\b", stream);
7112 len_so_far += 2;
7113 break;
7114
7115 case TARGET_CR:
7116 fputs ("\\r", stream);
7117 len_so_far += 2;
7118 break;
7119
7120 case TARGET_NEWLINE:
7121 fputs ("\\n", stream);
7122 c = p [i + 1];
7123 if ((c >= ' ' && c <= '~')
7124 || c == TARGET_TAB)
7125 /* This is a good place for a line break. */
7126 len_so_far = MAX_ASCII_LEN;
7127 else
7128 len_so_far += 2;
7129 break;
7130
7131 case '\"':
7132 case '\\':
7133 putc ('\\', stream);
7134 len_so_far++;
7135 /* drop through. */
7136
7137 default:
7138 if (c >= ' ' && c <= '~')
7139 {
7140 putc (c, stream);
7141 len_so_far++;
7142 }
7143 else
7144 {
7145 fprintf (stream, "\\%03o", c);
7146 len_so_far += 4;
7147 }
7148 break;
7149 }
7150 }
7151
7152 fputs ("\"\n", stream);
7153 }
7154
7155 /* Compute the register sabe mask for registers 0 through 12
7156 inclusive. This code is used by both arm_compute_save_reg_mask
7157 and arm_compute_initial_elimination_offset. */
7158
7159 static unsigned long
arm_compute_save_reg0_reg12_mask()7160 arm_compute_save_reg0_reg12_mask ()
7161 {
7162 unsigned long func_type = arm_current_func_type ();
7163 unsigned int save_reg_mask = 0;
7164 unsigned int reg;
7165
7166 if (IS_INTERRUPT (func_type))
7167 {
7168 unsigned int max_reg;
7169 /* Interrupt functions must not corrupt any registers,
7170 even call clobbered ones. If this is a leaf function
7171 we can just examine the registers used by the RTL, but
7172 otherwise we have to assume that whatever function is
7173 called might clobber anything, and so we have to save
7174 all the call-clobbered registers as well. */
7175 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7176 /* FIQ handlers have registers r8 - r12 banked, so
7177 we only need to check r0 - r7, Normal ISRs only
7178 bank r14 and r15, so we must check up to r12.
7179 r13 is the stack pointer which is always preserved,
7180 so we do not need to consider it here. */
7181 max_reg = 7;
7182 else
7183 max_reg = 12;
7184
7185 for (reg = 0; reg <= max_reg; reg++)
7186 if (regs_ever_live[reg]
7187 || (! current_function_is_leaf && call_used_regs [reg]))
7188 save_reg_mask |= (1 << reg);
7189 }
7190 else
7191 {
7192 /* In the normal case we only need to save those registers
7193 which are call saved and which are used by this function. */
7194 for (reg = 0; reg <= 10; reg++)
7195 if (regs_ever_live[reg] && ! call_used_regs [reg])
7196 save_reg_mask |= (1 << reg);
7197
7198 /* Handle the frame pointer as a special case. */
7199 if (! TARGET_APCS_FRAME
7200 && ! frame_pointer_needed
7201 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7202 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
7203 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
7204
7205 /* If we aren't loading the PIC register,
7206 don't stack it even though it may be live. */
7207 if (flag_pic
7208 && ! TARGET_SINGLE_PIC_BASE
7209 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7210 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
7211 }
7212
7213 return save_reg_mask;
7214 }
7215
7216 /* Compute a bit mask of which registers need to be
7217 saved on the stack for the current function. */
7218
7219 static unsigned long
arm_compute_save_reg_mask()7220 arm_compute_save_reg_mask ()
7221 {
7222 unsigned int save_reg_mask = 0;
7223 unsigned long func_type = arm_current_func_type ();
7224
7225 if (IS_NAKED (func_type))
7226 /* This should never really happen. */
7227 return 0;
7228
7229 /* If we are creating a stack frame, then we must save the frame pointer,
7230 IP (which will hold the old stack pointer), LR and the PC. */
7231 if (frame_pointer_needed)
7232 save_reg_mask |=
7233 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
7234 | (1 << IP_REGNUM)
7235 | (1 << LR_REGNUM)
7236 | (1 << PC_REGNUM);
7237
7238 /* Volatile functions do not return, so there
7239 is no need to save any other registers. */
7240 if (IS_VOLATILE (func_type))
7241 return save_reg_mask;
7242
7243 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
7244
7245 /* Decide if we need to save the link register.
7246 Interrupt routines have their own banked link register,
7247 so they never need to save it.
7248 Otherwise if we do not use the link register we do not need to save
7249 it. If we are pushing other registers onto the stack however, we
7250 can save an instruction in the epilogue by pushing the link register
7251 now and then popping it back into the PC. This incurs extra memory
7252 accesses though, so we only do it when optimising for size, and only
7253 if we know that we will not need a fancy return sequence. */
7254 if (regs_ever_live [LR_REGNUM]
7255 || (save_reg_mask
7256 && optimize_size
7257 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
7258 save_reg_mask |= 1 << LR_REGNUM;
7259
7260 if (cfun->machine->lr_save_eliminated)
7261 save_reg_mask &= ~ (1 << LR_REGNUM);
7262
7263 return save_reg_mask;
7264 }
7265
7266 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7267 everything bar the final return instruction. */
7268
7269 const char *
output_return_instruction(operand,really_return,reverse)7270 output_return_instruction (operand, really_return, reverse)
7271 rtx operand;
7272 int really_return;
7273 int reverse;
7274 {
7275 char conditional[10];
7276 char instr[100];
7277 int reg;
7278 unsigned long live_regs_mask;
7279 unsigned long func_type;
7280
7281 func_type = arm_current_func_type ();
7282
7283 if (IS_NAKED (func_type))
7284 return "";
7285
7286 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7287 {
7288 /* If this function was declared non-returning, and we have found a tail
7289 call, then we have to trust that the called function won't return. */
7290 if (really_return)
7291 {
7292 rtx ops[2];
7293
7294 /* Otherwise, trap an attempted return by aborting. */
7295 ops[0] = operand;
7296 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
7297 : "abort");
7298 assemble_external_libcall (ops[1]);
7299 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
7300 }
7301
7302 return "";
7303 }
7304
7305 if (current_function_calls_alloca && !really_return)
7306 abort ();
7307
7308 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
7309
7310 return_used_this_function = 1;
7311
7312 live_regs_mask = arm_compute_save_reg_mask ();
7313
7314 if (live_regs_mask)
7315 {
7316 const char * return_reg;
7317
7318 /* If we do not have any special requirements for function exit
7319 (eg interworking, or ISR) then we can load the return address
7320 directly into the PC. Otherwise we must load it into LR. */
7321 if (really_return
7322 && ! TARGET_INTERWORK)
7323 return_reg = reg_names[PC_REGNUM];
7324 else
7325 return_reg = reg_names[LR_REGNUM];
7326
7327 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
7328 /* There are two possible reasons for the IP register being saved.
7329 Either a stack frame was created, in which case IP contains the
7330 old stack pointer, or an ISR routine corrupted it. If this in an
7331 ISR routine then just restore IP, otherwise restore IP into SP. */
7332 if (! IS_INTERRUPT (func_type))
7333 {
7334 live_regs_mask &= ~ (1 << IP_REGNUM);
7335 live_regs_mask |= (1 << SP_REGNUM);
7336 }
7337
7338 /* On some ARM architectures it is faster to use LDR rather than
7339 LDM to load a single register. On other architectures, the
7340 cost is the same. In 26 bit mode, or for exception handlers,
7341 we have to use LDM to load the PC so that the CPSR is also
7342 restored. */
7343 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
7344 {
7345 if (live_regs_mask == (unsigned int)(1 << reg))
7346 break;
7347 }
7348 if (reg <= LAST_ARM_REGNUM
7349 && (reg != LR_REGNUM
7350 || ! really_return
7351 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
7352 {
7353 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
7354 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
7355 }
7356 else
7357 {
7358 char *p;
7359 int first = 1;
7360
7361 /* Generate the load multiple instruction to restore the registers. */
7362 if (frame_pointer_needed)
7363 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
7364 else if (live_regs_mask & (1 << SP_REGNUM))
7365 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
7366 else
7367 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
7368
7369 p = instr + strlen (instr);
7370
7371 for (reg = 0; reg <= SP_REGNUM; reg++)
7372 if (live_regs_mask & (1 << reg))
7373 {
7374 int l = strlen (reg_names[reg]);
7375
7376 if (first)
7377 first = 0;
7378 else
7379 {
7380 memcpy (p, ", ", 2);
7381 p += 2;
7382 }
7383
7384 memcpy (p, "%|", 2);
7385 memcpy (p + 2, reg_names[reg], l);
7386 p += l + 2;
7387 }
7388
7389 if (live_regs_mask & (1 << LR_REGNUM))
7390 {
7391 int l = strlen (return_reg);
7392
7393 if (! first)
7394 {
7395 memcpy (p, ", ", 2);
7396 p += 2;
7397 }
7398
7399 memcpy (p, "%|", 2);
7400 memcpy (p + 2, return_reg, l);
7401 strcpy (p + 2 + l, ((TARGET_APCS_32
7402 && !IS_INTERRUPT (func_type))
7403 || !really_return)
7404 ? "}" : "}^");
7405 }
7406 else
7407 strcpy (p, "}");
7408 }
7409
7410 output_asm_insn (instr, & operand);
7411
7412 /* See if we need to generate an extra instruction to
7413 perform the actual function return. */
7414 if (really_return
7415 && func_type != ARM_FT_INTERWORKED
7416 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
7417 {
7418 /* The return has already been handled
7419 by loading the LR into the PC. */
7420 really_return = 0;
7421 }
7422 }
7423
7424 if (really_return)
7425 {
7426 switch ((int) ARM_FUNC_TYPE (func_type))
7427 {
7428 case ARM_FT_ISR:
7429 case ARM_FT_FIQ:
7430 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
7431 break;
7432
7433 case ARM_FT_INTERWORKED:
7434 sprintf (instr, "bx%s\t%%|lr", conditional);
7435 break;
7436
7437 case ARM_FT_EXCEPTION:
7438 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
7439 break;
7440
7441 default:
7442 /* ARMv5 implementations always provide BX, so interworking
7443 is the default unless APCS-26 is in use. */
7444 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
7445 sprintf (instr, "bx%s\t%%|lr", conditional);
7446 else
7447 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
7448 conditional, TARGET_APCS_32 ? "" : "s");
7449 break;
7450 }
7451
7452 output_asm_insn (instr, & operand);
7453 }
7454
7455 return "";
7456 }
7457
7458 /* Write the function name into the code section, directly preceding
7459 the function prologue.
7460
7461 Code will be output similar to this:
7462 t0
7463 .ascii "arm_poke_function_name", 0
7464 .align
7465 t1
7466 .word 0xff000000 + (t1 - t0)
7467 arm_poke_function_name
7468 mov ip, sp
7469 stmfd sp!, {fp, ip, lr, pc}
7470 sub fp, ip, #4
7471
7472 When performing a stack backtrace, code can inspect the value
7473 of 'pc' stored at 'fp' + 0. If the trace function then looks
7474 at location pc - 12 and the top 8 bits are set, then we know
7475 that there is a function name embedded immediately preceding this
7476 location and has length ((pc[-3]) & 0xff000000).
7477
7478 We assume that pc is declared as a pointer to an unsigned long.
7479
7480 It is of no benefit to output the function name if we are assembling
7481 a leaf function. These function types will not contain a stack
7482 backtrace structure, therefore it is not possible to determine the
7483 function name. */
7484
7485 void
arm_poke_function_name(stream,name)7486 arm_poke_function_name (stream, name)
7487 FILE * stream;
7488 const char * name;
7489 {
7490 unsigned long alignlength;
7491 unsigned long length;
7492 rtx x;
7493
7494 length = strlen (name) + 1;
7495 alignlength = ROUND_UP (length);
7496
7497 ASM_OUTPUT_ASCII (stream, name, length);
7498 ASM_OUTPUT_ALIGN (stream, 2);
7499 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
7500 assemble_aligned_integer (UNITS_PER_WORD, x);
7501 }
7502
7503 /* Place some comments into the assembler stream
7504 describing the current function. */
7505
7506 static void
arm_output_function_prologue(f,frame_size)7507 arm_output_function_prologue (f, frame_size)
7508 FILE * f;
7509 HOST_WIDE_INT frame_size;
7510 {
7511 unsigned long func_type;
7512
7513 if (!TARGET_ARM)
7514 {
7515 thumb_output_function_prologue (f, frame_size);
7516 return;
7517 }
7518
7519 /* Sanity check. */
7520 if (arm_ccfsm_state || arm_target_insn)
7521 abort ();
7522
7523 func_type = arm_current_func_type ();
7524
7525 switch ((int) ARM_FUNC_TYPE (func_type))
7526 {
7527 default:
7528 case ARM_FT_NORMAL:
7529 break;
7530 case ARM_FT_INTERWORKED:
7531 asm_fprintf (f, "\t%@ Function supports interworking.\n");
7532 break;
7533 case ARM_FT_EXCEPTION_HANDLER:
7534 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
7535 break;
7536 case ARM_FT_ISR:
7537 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
7538 break;
7539 case ARM_FT_FIQ:
7540 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
7541 break;
7542 case ARM_FT_EXCEPTION:
7543 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
7544 break;
7545 }
7546
7547 if (IS_NAKED (func_type))
7548 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7549
7550 if (IS_VOLATILE (func_type))
7551 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
7552
7553 if (IS_NESTED (func_type))
7554 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
7555
7556 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
7557 current_function_args_size,
7558 current_function_pretend_args_size, frame_size);
7559
7560 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
7561 frame_pointer_needed,
7562 cfun->machine->uses_anonymous_args);
7563
7564 if (cfun->machine->lr_save_eliminated)
7565 asm_fprintf (f, "\t%@ link register save eliminated.\n");
7566
7567 #ifdef AOF_ASSEMBLER
7568 if (flag_pic)
7569 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
7570 #endif
7571
7572 return_used_this_function = 0;
7573 }
7574
7575 const char *
arm_output_epilogue(really_return)7576 arm_output_epilogue (really_return)
7577 int really_return;
7578 {
7579 int reg;
7580 unsigned long saved_regs_mask;
7581 unsigned long func_type;
7582 /* Floats_offset is the offset from the "virtual" frame. In an APCS
7583 frame that is $fp + 4 for a non-variadic function. */
7584 int floats_offset = 0;
7585 rtx operands[3];
7586 int frame_size = arm_get_frame_size ();
7587 FILE * f = asm_out_file;
7588 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
7589
7590 /* If we have already generated the return instruction
7591 then it is futile to generate anything else. */
7592 if (use_return_insn (FALSE) && return_used_this_function)
7593 return "";
7594
7595 func_type = arm_current_func_type ();
7596
7597 if (IS_NAKED (func_type))
7598 /* Naked functions don't have epilogues. */
7599 return "";
7600
7601 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7602 {
7603 rtx op;
7604
7605 /* A volatile function should never return. Call abort. */
7606 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
7607 assemble_external_libcall (op);
7608 output_asm_insn ("bl\t%a0", &op);
7609
7610 return "";
7611 }
7612
7613 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
7614 && ! really_return)
7615 /* If we are throwing an exception, then we really must
7616 be doing a return, so we can't tail-call. */
7617 abort ();
7618
7619 saved_regs_mask = arm_compute_save_reg_mask ();
7620
7621 /* XXX We should adjust floats_offset for any anonymous args, and then
7622 re-adjust vfp_offset below to compensate. */
7623
7624 /* Compute how far away the floats will be. */
7625 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++)
7626 if (saved_regs_mask & (1 << reg))
7627 floats_offset += 4;
7628
7629 if (frame_pointer_needed)
7630 {
7631 int vfp_offset = 4;
7632
7633 if (arm_fpu_arch == FP_SOFT2)
7634 {
7635 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7636 if (regs_ever_live[reg] && !call_used_regs[reg])
7637 {
7638 floats_offset += 12;
7639 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
7640 reg, FP_REGNUM, floats_offset - vfp_offset);
7641 }
7642 }
7643 else
7644 {
7645 int start_reg = LAST_ARM_FP_REGNUM;
7646
7647 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7648 {
7649 if (regs_ever_live[reg] && !call_used_regs[reg])
7650 {
7651 floats_offset += 12;
7652
7653 /* We can't unstack more than four registers at once. */
7654 if (start_reg - reg == 3)
7655 {
7656 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
7657 reg, FP_REGNUM, floats_offset - vfp_offset);
7658 start_reg = reg - 1;
7659 }
7660 }
7661 else
7662 {
7663 if (reg != start_reg)
7664 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7665 reg + 1, start_reg - reg,
7666 FP_REGNUM, floats_offset - vfp_offset);
7667 start_reg = reg - 1;
7668 }
7669 }
7670
7671 /* Just in case the last register checked also needs unstacking. */
7672 if (reg != start_reg)
7673 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7674 reg + 1, start_reg - reg,
7675 FP_REGNUM, floats_offset - vfp_offset);
7676 }
7677
7678 /* saved_regs_mask should contain the IP, which at the time of stack
7679 frame generation actually contains the old stack pointer. So a
7680 quick way to unwind the stack is just pop the IP register directly
7681 into the stack pointer. */
7682 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
7683 abort ();
7684 saved_regs_mask &= ~ (1 << IP_REGNUM);
7685 saved_regs_mask |= (1 << SP_REGNUM);
7686
7687 /* There are two registers left in saved_regs_mask - LR and PC. We
7688 only need to restore the LR register (the return address), but to
7689 save time we can load it directly into the PC, unless we need a
7690 special function exit sequence, or we are not really returning. */
7691 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
7692 /* Delete the LR from the register mask, so that the LR on
7693 the stack is loaded into the PC in the register mask. */
7694 saved_regs_mask &= ~ (1 << LR_REGNUM);
7695 else
7696 saved_regs_mask &= ~ (1 << PC_REGNUM);
7697
7698 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask);
7699
7700 if (IS_INTERRUPT (func_type))
7701 /* Interrupt handlers will have pushed the
7702 IP onto the stack, so restore it now. */
7703 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
7704 }
7705 else
7706 {
7707 /* Restore stack pointer if necessary. */
7708 if (frame_size + current_function_outgoing_args_size != 0)
7709 {
7710 operands[0] = operands[1] = stack_pointer_rtx;
7711 operands[2] = GEN_INT (frame_size
7712 + current_function_outgoing_args_size);
7713 output_add_immediate (operands);
7714 }
7715
7716 if (arm_fpu_arch == FP_SOFT2)
7717 {
7718 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7719 if (regs_ever_live[reg] && !call_used_regs[reg])
7720 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
7721 reg, SP_REGNUM);
7722 }
7723 else
7724 {
7725 int start_reg = FIRST_ARM_FP_REGNUM;
7726
7727 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7728 {
7729 if (regs_ever_live[reg] && !call_used_regs[reg])
7730 {
7731 if (reg - start_reg == 3)
7732 {
7733 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
7734 start_reg, SP_REGNUM);
7735 start_reg = reg + 1;
7736 }
7737 }
7738 else
7739 {
7740 if (reg != start_reg)
7741 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7742 start_reg, reg - start_reg,
7743 SP_REGNUM);
7744
7745 start_reg = reg + 1;
7746 }
7747 }
7748
7749 /* Just in case the last register checked also needs unstacking. */
7750 if (reg != start_reg)
7751 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7752 start_reg, reg - start_reg, SP_REGNUM);
7753 }
7754
7755 /* If we can, restore the LR into the PC. */
7756 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
7757 && really_return
7758 && current_function_pretend_args_size == 0
7759 && saved_regs_mask & (1 << LR_REGNUM))
7760 {
7761 saved_regs_mask &= ~ (1 << LR_REGNUM);
7762 saved_regs_mask |= (1 << PC_REGNUM);
7763 }
7764
7765 /* Load the registers off the stack. If we only have one register
7766 to load use the LDR instruction - it is faster. */
7767 if (saved_regs_mask == (1 << LR_REGNUM))
7768 {
7769 /* The exception handler ignores the LR, so we do
7770 not really need to load it off the stack. */
7771 if (eh_ofs)
7772 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
7773 else
7774 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
7775 }
7776 else if (saved_regs_mask)
7777 {
7778 if (saved_regs_mask & (1 << SP_REGNUM))
7779 /* Note - write back to the stack register is not enabled
7780 (ie "ldmfd sp!..."). We know that the stack pointer is
7781 in the list of registers and if we add writeback the
7782 instruction becomes UNPREDICTABLE. */
7783 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
7784 else
7785 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
7786 }
7787
7788 if (current_function_pretend_args_size)
7789 {
7790 /* Unwind the pre-pushed regs. */
7791 operands[0] = operands[1] = stack_pointer_rtx;
7792 operands[2] = GEN_INT (current_function_pretend_args_size);
7793 output_add_immediate (operands);
7794 }
7795 }
7796
7797 #if 0
7798 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER)
7799 /* Adjust the stack to remove the exception handler stuff. */
7800 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7801 REGNO (eh_ofs));
7802 #endif
7803
7804 if (! really_return
7805 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
7806 && current_function_pretend_args_size == 0
7807 && saved_regs_mask & (1 << PC_REGNUM)))
7808 return "";
7809
7810 /* Generate the return instruction. */
7811 switch ((int) ARM_FUNC_TYPE (func_type))
7812 {
7813 case ARM_FT_EXCEPTION_HANDLER:
7814 /* Even in 26-bit mode we do a mov (rather than a movs)
7815 because we don't have the PSR bits set in the address. */
7816 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
7817 break;
7818
7819 case ARM_FT_ISR:
7820 case ARM_FT_FIQ:
7821 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
7822 break;
7823
7824 case ARM_FT_EXCEPTION:
7825 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7826 break;
7827
7828 case ARM_FT_INTERWORKED:
7829 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
7830 break;
7831
7832 default:
7833 if (frame_pointer_needed)
7834 /* If we used the frame pointer then the return address
7835 will have been loaded off the stack directly into the
7836 PC, so there is no need to issue a MOV instruction
7837 here. */
7838 ;
7839 else if (current_function_pretend_args_size == 0
7840 && (saved_regs_mask & (1 << LR_REGNUM)))
7841 /* Similarly we may have been able to load LR into the PC
7842 even if we did not create a stack frame. */
7843 ;
7844 else if (TARGET_APCS_32)
7845 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7846 else
7847 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7848 break;
7849 }
7850
7851 return "";
7852 }
7853
7854 static void
arm_output_function_epilogue(file,frame_size)7855 arm_output_function_epilogue (file, frame_size)
7856 FILE *file ATTRIBUTE_UNUSED;
7857 HOST_WIDE_INT frame_size;
7858 {
7859 if (TARGET_THUMB)
7860 {
7861 /* ??? Probably not safe to set this here, since it assumes that a
7862 function will be emitted as assembly immediately after we generate
7863 RTL for it. This does not happen for inline functions. */
7864 return_used_this_function = 0;
7865 }
7866 else
7867 {
7868 /* We need to take into account any stack-frame rounding. */
7869 frame_size = arm_get_frame_size ();
7870
7871 if (use_return_insn (FALSE)
7872 && return_used_this_function
7873 && (frame_size + current_function_outgoing_args_size) != 0
7874 && !frame_pointer_needed)
7875 abort ();
7876
7877 /* Reset the ARM-specific per-function variables. */
7878 after_arm_reorg = 0;
7879 }
7880 }
7881
7882 /* Generate and emit an insn that we will recognize as a push_multi.
7883 Unfortunately, since this insn does not reflect very well the actual
7884 semantics of the operation, we need to annotate the insn for the benefit
7885 of DWARF2 frame unwind information. */
7886
7887 static rtx
emit_multi_reg_push(mask)7888 emit_multi_reg_push (mask)
7889 int mask;
7890 {
7891 int num_regs = 0;
7892 int num_dwarf_regs;
7893 int i, j;
7894 rtx par;
7895 rtx dwarf;
7896 int dwarf_par_index;
7897 rtx tmp, reg;
7898
7899 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7900 if (mask & (1 << i))
7901 num_regs++;
7902
7903 if (num_regs == 0 || num_regs > 16)
7904 abort ();
7905
7906 /* We don't record the PC in the dwarf frame information. */
7907 num_dwarf_regs = num_regs;
7908 if (mask & (1 << PC_REGNUM))
7909 num_dwarf_regs--;
7910
7911 /* For the body of the insn we are going to generate an UNSPEC in
7912 parallel with several USEs. This allows the insn to be recognized
7913 by the push_multi pattern in the arm.md file. The insn looks
7914 something like this:
7915
7916 (parallel [
7917 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7918 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7919 (use (reg:SI 11 fp))
7920 (use (reg:SI 12 ip))
7921 (use (reg:SI 14 lr))
7922 (use (reg:SI 15 pc))
7923 ])
7924
7925 For the frame note however, we try to be more explicit and actually
7926 show each register being stored into the stack frame, plus a (single)
7927 decrement of the stack pointer. We do it this way in order to be
7928 friendly to the stack unwinding code, which only wants to see a single
7929 stack decrement per instruction. The RTL we generate for the note looks
7930 something like this:
7931
7932 (sequence [
7933 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7934 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7935 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7936 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7937 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7938 ])
7939
7940 This sequence is used both by the code to support stack unwinding for
7941 exceptions handlers and the code to generate dwarf2 frame debugging. */
7942
7943 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
7944 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
7945 dwarf_par_index = 1;
7946
7947 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7948 {
7949 if (mask & (1 << i))
7950 {
7951 reg = gen_rtx_REG (SImode, i);
7952
7953 XVECEXP (par, 0, 0)
7954 = gen_rtx_SET (VOIDmode,
7955 gen_rtx_MEM (BLKmode,
7956 gen_rtx_PRE_DEC (BLKmode,
7957 stack_pointer_rtx)),
7958 gen_rtx_UNSPEC (BLKmode,
7959 gen_rtvec (1, reg),
7960 UNSPEC_PUSH_MULT));
7961
7962 if (i != PC_REGNUM)
7963 {
7964 tmp = gen_rtx_SET (VOIDmode,
7965 gen_rtx_MEM (SImode, stack_pointer_rtx),
7966 reg);
7967 RTX_FRAME_RELATED_P (tmp) = 1;
7968 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
7969 dwarf_par_index++;
7970 }
7971
7972 break;
7973 }
7974 }
7975
7976 for (j = 1, i++; j < num_regs; i++)
7977 {
7978 if (mask & (1 << i))
7979 {
7980 reg = gen_rtx_REG (SImode, i);
7981
7982 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
7983
7984 if (i != PC_REGNUM)
7985 {
7986 tmp = gen_rtx_SET (VOIDmode,
7987 gen_rtx_MEM (SImode,
7988 plus_constant (stack_pointer_rtx,
7989 4 * j)),
7990 reg);
7991 RTX_FRAME_RELATED_P (tmp) = 1;
7992 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
7993 }
7994
7995 j++;
7996 }
7997 }
7998
7999 par = emit_insn (par);
8000
8001 tmp = gen_rtx_SET (SImode,
8002 stack_pointer_rtx,
8003 gen_rtx_PLUS (SImode,
8004 stack_pointer_rtx,
8005 GEN_INT (-4 * num_regs)));
8006 RTX_FRAME_RELATED_P (tmp) = 1;
8007 XVECEXP (dwarf, 0, 0) = tmp;
8008
8009 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8010 REG_NOTES (par));
8011 return par;
8012 }
8013
8014 static rtx
emit_sfm(base_reg,count)8015 emit_sfm (base_reg, count)
8016 int base_reg;
8017 int count;
8018 {
8019 rtx par;
8020 rtx dwarf;
8021 rtx tmp, reg;
8022 int i;
8023
8024 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8025 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8026
8027 reg = gen_rtx_REG (XFmode, base_reg++);
8028
8029 XVECEXP (par, 0, 0)
8030 = gen_rtx_SET (VOIDmode,
8031 gen_rtx_MEM (BLKmode,
8032 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8033 gen_rtx_UNSPEC (BLKmode,
8034 gen_rtvec (1, reg),
8035 UNSPEC_PUSH_MULT));
8036 tmp
8037 = gen_rtx_SET (VOIDmode,
8038 gen_rtx_MEM (XFmode,
8039 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8040 reg);
8041 RTX_FRAME_RELATED_P (tmp) = 1;
8042 XVECEXP (dwarf, 0, count - 1) = tmp;
8043
8044 for (i = 1; i < count; i++)
8045 {
8046 reg = gen_rtx_REG (XFmode, base_reg++);
8047 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8048
8049 tmp = gen_rtx_SET (VOIDmode,
8050 gen_rtx_MEM (XFmode,
8051 gen_rtx_PRE_DEC (BLKmode,
8052 stack_pointer_rtx)),
8053 reg);
8054 RTX_FRAME_RELATED_P (tmp) = 1;
8055 XVECEXP (dwarf, 0, count - i - 1) = tmp;
8056 }
8057
8058 par = emit_insn (par);
8059 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8060 REG_NOTES (par));
8061 return par;
8062 }
8063
8064 /* Compute the distance from register FROM to register TO.
8065 These can be the arg pointer (26), the soft frame pointer (25),
8066 the stack pointer (13) or the hard frame pointer (11).
8067 Typical stack layout looks like this:
8068
8069 old stack pointer -> | |
8070 ----
8071 | | \
8072 | | saved arguments for
8073 | | vararg functions
8074 | | /
8075 --
8076 hard FP & arg pointer -> | | \
8077 | | stack
8078 | | frame
8079 | | /
8080 --
8081 | | \
8082 | | call saved
8083 | | registers
8084 soft frame pointer -> | | /
8085 --
8086 | | \
8087 | | local
8088 | | variables
8089 | | /
8090 --
8091 | | \
8092 | | outgoing
8093 | | arguments
8094 current stack pointer -> | | /
8095 --
8096
8097 For a given function some or all of these stack components
8098 may not be needed, giving rise to the possibility of
8099 eliminating some of the registers.
8100
8101 The values returned by this function must reflect the behavior
8102 of arm_expand_prologue() and arm_compute_save_reg_mask().
8103
8104 The sign of the number returned reflects the direction of stack
8105 growth, so the values are positive for all eliminations except
8106 from the soft frame pointer to the hard frame pointer. */
8107
8108 unsigned int
arm_compute_initial_elimination_offset(from,to)8109 arm_compute_initial_elimination_offset (from, to)
8110 unsigned int from;
8111 unsigned int to;
8112 {
8113 unsigned int local_vars = arm_get_frame_size ();
8114 unsigned int outgoing_args = current_function_outgoing_args_size;
8115 unsigned int stack_frame;
8116 unsigned int call_saved_registers;
8117 unsigned long func_type;
8118
8119 func_type = arm_current_func_type ();
8120
8121 /* Volatile functions never return, so there is
8122 no need to save call saved registers. */
8123 call_saved_registers = 0;
8124 if (! IS_VOLATILE (func_type))
8125 {
8126 unsigned int reg_mask;
8127 unsigned int reg;
8128
8129 /* Make sure that we compute which registers will be saved
8130 on the stack using the same algorithm that is used by
8131 arm_compute_save_reg_mask(). */
8132 reg_mask = arm_compute_save_reg0_reg12_mask ();
8133
8134 /* Now count the number of bits set in save_reg_mask.
8135 For each set bit we need 4 bytes of stack space. */
8136 while (reg_mask)
8137 {
8138 call_saved_registers += 4;
8139 reg_mask = reg_mask & ~ (reg_mask & - reg_mask);
8140 }
8141
8142 if ((regs_ever_live[LR_REGNUM]
8143 /* If optimizing for size, then we save the link register if
8144 any other integer register is saved. This gives a smaller
8145 return sequence. */
8146 || (optimize_size && call_saved_registers > 0))
8147 /* But if a stack frame is going to be created, the LR will
8148 be saved as part of that, so we do not need to allow for
8149 it here. */
8150 && ! frame_pointer_needed)
8151 call_saved_registers += 4;
8152
8153 /* If the hard floating point registers are going to be
8154 used then they must be saved on the stack as well.
8155 Each register occupies 12 bytes of stack space. */
8156 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg ++)
8157 if (regs_ever_live[reg] && ! call_used_regs[reg])
8158 call_saved_registers += 12;
8159 }
8160
8161 /* The stack frame contains 4 registers - the old frame pointer,
8162 the old stack pointer, the return address and PC of the start
8163 of the function. */
8164 stack_frame = frame_pointer_needed ? 16 : 0;
8165
8166 /* OK, now we have enough information to compute the distances.
8167 There must be an entry in these switch tables for each pair
8168 of registers in ELIMINABLE_REGS, even if some of the entries
8169 seem to be redundant or useless. */
8170 switch (from)
8171 {
8172 case ARG_POINTER_REGNUM:
8173 switch (to)
8174 {
8175 case THUMB_HARD_FRAME_POINTER_REGNUM:
8176 return 0;
8177
8178 case FRAME_POINTER_REGNUM:
8179 /* This is the reverse of the soft frame pointer
8180 to hard frame pointer elimination below. */
8181 if (call_saved_registers == 0 && stack_frame == 0)
8182 return 0;
8183 return (call_saved_registers + stack_frame - 4);
8184
8185 case ARM_HARD_FRAME_POINTER_REGNUM:
8186 /* If there is no stack frame then the hard
8187 frame pointer and the arg pointer coincide. */
8188 if (stack_frame == 0 && call_saved_registers != 0)
8189 return 0;
8190 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8191 return (frame_pointer_needed
8192 && current_function_needs_context
8193 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
8194
8195 case STACK_POINTER_REGNUM:
8196 /* If nothing has been pushed on the stack at all
8197 then this will return -4. This *is* correct! */
8198 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
8199
8200 default:
8201 abort ();
8202 }
8203 break;
8204
8205 case FRAME_POINTER_REGNUM:
8206 switch (to)
8207 {
8208 case THUMB_HARD_FRAME_POINTER_REGNUM:
8209 return 0;
8210
8211 case ARM_HARD_FRAME_POINTER_REGNUM:
8212 /* The hard frame pointer points to the top entry in the
8213 stack frame. The soft frame pointer to the bottom entry
8214 in the stack frame. If there is no stack frame at all,
8215 then they are identical. */
8216 if (call_saved_registers == 0 && stack_frame == 0)
8217 return 0;
8218 return - (call_saved_registers + stack_frame - 4);
8219
8220 case STACK_POINTER_REGNUM:
8221 return local_vars + outgoing_args;
8222
8223 default:
8224 abort ();
8225 }
8226 break;
8227
8228 default:
8229 /* You cannot eliminate from the stack pointer.
8230 In theory you could eliminate from the hard frame
8231 pointer to the stack pointer, but this will never
8232 happen, since if a stack frame is not needed the
8233 hard frame pointer will never be used. */
8234 abort ();
8235 }
8236 }
8237
8238 /* Calculate the size of the stack frame, taking into account any
8239 padding that is required to ensure stack-alignment. */
8240
8241 HOST_WIDE_INT
arm_get_frame_size()8242 arm_get_frame_size ()
8243 {
8244 int regno;
8245
8246 int base_size = ROUND_UP (get_frame_size ());
8247 int entry_size = 0;
8248 unsigned long func_type = arm_current_func_type ();
8249 int leaf;
8250
8251 if (! TARGET_ARM)
8252 abort();
8253
8254 if (! TARGET_ATPCS)
8255 return base_size;
8256
8257 /* We need to know if we are a leaf function. Unfortunately, it
8258 is possible to be called after start_sequence has been called,
8259 which causes get_insns to return the insns for the sequence,
8260 not the function, which will cause leaf_function_p to return
8261 the incorrect result.
8262
8263 To work around this, we cache the computed frame size. This
8264 works because we will only be calling RTL expanders that need
8265 to know about leaf functions once reload has completed, and the
8266 frame size cannot be changed after that time, so we can safely
8267 use the cached value. */
8268
8269 if (reload_completed)
8270 return cfun->machine->frame_size;
8271
8272 leaf = leaf_function_p ();
8273
8274 /* A leaf function does not need any stack alignment if it has nothing
8275 on the stack. */
8276 if (leaf && base_size == 0)
8277 {
8278 cfun->machine->frame_size = 0;
8279 return 0;
8280 }
8281
8282 /* We know that SP will be word aligned on entry, and we must
8283 preserve that condition at any subroutine call. But those are
8284 the only constraints. */
8285
8286 /* Space for variadic functions. */
8287 if (current_function_pretend_args_size)
8288 entry_size += current_function_pretend_args_size;
8289
8290 /* Space for saved registers. */
8291 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
8292
8293 /* Space for saved FPA registers. */
8294 if (! IS_VOLATILE (func_type))
8295 {
8296 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
8297 if (regs_ever_live[regno] && ! call_used_regs[regno])
8298 entry_size += 12;
8299 }
8300
8301 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
8302 base_size += 4;
8303 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
8304 abort ();
8305
8306 cfun->machine->frame_size = base_size;
8307
8308 return base_size;
8309 }
8310
8311 /* Generate the prologue instructions for entry into an ARM function. */
8312
8313 void
arm_expand_prologue()8314 arm_expand_prologue ()
8315 {
8316 int size;
8317 int reg;
8318 rtx amount;
8319 rtx insn;
8320 rtx ip_rtx;
8321 unsigned long live_regs_mask;
8322 unsigned long func_type;
8323 int fp_offset = 0;
8324 int saved_pretend_args = 0;
8325 unsigned int args_to_push;
8326
8327 func_type = arm_current_func_type ();
8328
8329 /* Naked functions don't have prologues. */
8330 if (IS_NAKED (func_type))
8331 return;
8332
8333 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
8334 args_to_push = current_function_pretend_args_size;
8335
8336 /* Compute which register we will have to save onto the stack. */
8337 live_regs_mask = arm_compute_save_reg_mask ();
8338
8339 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
8340
8341 if (frame_pointer_needed)
8342 {
8343 if (IS_INTERRUPT (func_type))
8344 {
8345 /* Interrupt functions must not corrupt any registers.
8346 Creating a frame pointer however, corrupts the IP
8347 register, so we must push it first. */
8348 insn = emit_multi_reg_push (1 << IP_REGNUM);
8349
8350 /* Do not set RTX_FRAME_RELATED_P on this insn.
8351 The dwarf stack unwinding code only wants to see one
8352 stack decrement per function, and this is not it. If
8353 this instruction is labeled as being part of the frame
8354 creation sequence then dwarf2out_frame_debug_expr will
8355 abort when it encounters the assignment of IP to FP
8356 later on, since the use of SP here establishes SP as
8357 the CFA register and not IP.
8358
8359 Anyway this instruction is not really part of the stack
8360 frame creation although it is part of the prologue. */
8361 }
8362 else if (IS_NESTED (func_type))
8363 {
8364 /* The Static chain register is the same as the IP register
8365 used as a scratch register during stack frame creation.
8366 To get around this need to find somewhere to store IP
8367 whilst the frame is being created. We try the following
8368 places in order:
8369
8370 1. The last argument register.
8371 2. A slot on the stack above the frame. (This only
8372 works if the function is not a varargs function).
8373 3. Register r3, after pushing the argument registers
8374 onto the stack.
8375
8376 Note - we only need to tell the dwarf2 backend about the SP
8377 adjustment in the second variant; the static chain register
8378 doesn't need to be unwound, as it doesn't contain a value
8379 inherited from the caller. */
8380
8381 if (regs_ever_live[3] == 0)
8382 {
8383 insn = gen_rtx_REG (SImode, 3);
8384 insn = gen_rtx_SET (SImode, insn, ip_rtx);
8385 insn = emit_insn (insn);
8386 }
8387 else if (args_to_push == 0)
8388 {
8389 rtx dwarf;
8390 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
8391 insn = gen_rtx_MEM (SImode, insn);
8392 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
8393 insn = emit_insn (insn);
8394
8395 fp_offset = 4;
8396
8397 /* Just tell the dwarf backend that we adjusted SP. */
8398 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8399 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8400 GEN_INT (-fp_offset)));
8401 RTX_FRAME_RELATED_P (insn) = 1;
8402 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8403 dwarf, REG_NOTES (insn));
8404 }
8405 else
8406 {
8407 /* Store the args on the stack. */
8408 if (cfun->machine->uses_anonymous_args)
8409 insn = emit_multi_reg_push
8410 ((0xf0 >> (args_to_push / 4)) & 0xf);
8411 else
8412 insn = emit_insn
8413 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8414 GEN_INT (- args_to_push)));
8415
8416 RTX_FRAME_RELATED_P (insn) = 1;
8417
8418 saved_pretend_args = 1;
8419 fp_offset = args_to_push;
8420 args_to_push = 0;
8421
8422 /* Now reuse r3 to preserve IP. */
8423 insn = gen_rtx_REG (SImode, 3);
8424 insn = gen_rtx_SET (SImode, insn, ip_rtx);
8425 (void) emit_insn (insn);
8426 }
8427 }
8428
8429 if (fp_offset)
8430 {
8431 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
8432 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8433 }
8434 else
8435 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
8436
8437 insn = emit_insn (insn);
8438 RTX_FRAME_RELATED_P (insn) = 1;
8439 }
8440
8441 if (args_to_push)
8442 {
8443 /* Push the argument registers, or reserve space for them. */
8444 if (cfun->machine->uses_anonymous_args)
8445 insn = emit_multi_reg_push
8446 ((0xf0 >> (args_to_push / 4)) & 0xf);
8447 else
8448 insn = emit_insn
8449 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8450 GEN_INT (- args_to_push)));
8451 RTX_FRAME_RELATED_P (insn) = 1;
8452 }
8453
8454 /* If this is an interrupt service routine, and the link register
8455 is going to be pushed, and we are not creating a stack frame,
8456 (which would involve an extra push of IP and a pop in the epilogue)
8457 subtracting four from LR now will mean that the function return
8458 can be done with a single instruction. */
8459 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
8460 && (live_regs_mask & (1 << LR_REGNUM)) != 0
8461 && ! frame_pointer_needed)
8462 emit_insn (gen_rtx_SET (SImode,
8463 gen_rtx_REG (SImode, LR_REGNUM),
8464 gen_rtx_PLUS (SImode,
8465 gen_rtx_REG (SImode, LR_REGNUM),
8466 GEN_INT (-4))));
8467
8468 if (live_regs_mask)
8469 {
8470 insn = emit_multi_reg_push (live_regs_mask);
8471 RTX_FRAME_RELATED_P (insn) = 1;
8472 }
8473
8474 if (! IS_VOLATILE (func_type))
8475 {
8476 /* Save any floating point call-saved registers used by this function. */
8477 if (arm_fpu_arch == FP_SOFT2)
8478 {
8479 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
8480 if (regs_ever_live[reg] && !call_used_regs[reg])
8481 {
8482 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
8483 insn = gen_rtx_MEM (XFmode, insn);
8484 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
8485 gen_rtx_REG (XFmode, reg)));
8486 RTX_FRAME_RELATED_P (insn) = 1;
8487 }
8488 }
8489 else
8490 {
8491 int start_reg = LAST_ARM_FP_REGNUM;
8492
8493 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
8494 {
8495 if (regs_ever_live[reg] && !call_used_regs[reg])
8496 {
8497 if (start_reg - reg == 3)
8498 {
8499 insn = emit_sfm (reg, 4);
8500 RTX_FRAME_RELATED_P (insn) = 1;
8501 start_reg = reg - 1;
8502 }
8503 }
8504 else
8505 {
8506 if (start_reg != reg)
8507 {
8508 insn = emit_sfm (reg + 1, start_reg - reg);
8509 RTX_FRAME_RELATED_P (insn) = 1;
8510 }
8511 start_reg = reg - 1;
8512 }
8513 }
8514
8515 if (start_reg != reg)
8516 {
8517 insn = emit_sfm (reg + 1, start_reg - reg);
8518 RTX_FRAME_RELATED_P (insn) = 1;
8519 }
8520 }
8521 }
8522
8523 if (frame_pointer_needed)
8524 {
8525 /* Create the new frame pointer. */
8526 insn = GEN_INT (-(4 + args_to_push + fp_offset));
8527 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
8528 RTX_FRAME_RELATED_P (insn) = 1;
8529
8530 if (IS_NESTED (func_type))
8531 {
8532 /* Recover the static chain register. */
8533 if (regs_ever_live [3] == 0
8534 || saved_pretend_args)
8535 insn = gen_rtx_REG (SImode, 3);
8536 else /* if (current_function_pretend_args_size == 0) */
8537 {
8538 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
8539 insn = gen_rtx_MEM (SImode, insn);
8540 }
8541
8542 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
8543 /* Add a USE to stop propagate_one_insn() from barfing. */
8544 emit_insn (gen_prologue_use (ip_rtx));
8545 }
8546 }
8547
8548 size = arm_get_frame_size ();
8549
8550 if (warn_stack_larger_than && size > stack_larger_than_size)
8551 warning ("stack usage is %d bytes", size);
8552
8553 amount = GEN_INT (-(size + current_function_outgoing_args_size));
8554
8555 if (amount != const0_rtx)
8556 {
8557 /* This add can produce multiple insns for a large constant, so we
8558 need to get tricky. */
8559 rtx last = get_last_insn ();
8560 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8561 amount));
8562 do
8563 {
8564 last = last ? NEXT_INSN (last) : get_insns ();
8565 RTX_FRAME_RELATED_P (last) = 1;
8566 }
8567 while (last != insn);
8568
8569 /* If the frame pointer is needed, emit a special barrier that
8570 will prevent the scheduler from moving stores to the frame
8571 before the stack adjustment. */
8572 if (frame_pointer_needed)
8573 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
8574 hard_frame_pointer_rtx));
8575 }
8576
8577 /* If we are profiling, make sure no instructions are scheduled before
8578 the call to mcount. Similarly if the user has requested no
8579 scheduling in the prolog. */
8580 if (current_function_profile || TARGET_NO_SCHED_PRO)
8581 emit_insn (gen_blockage ());
8582
8583 /* If the link register is being kept alive, with the return address in it,
8584 then make sure that it does not get reused by the ce2 pass. */
8585 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
8586 {
8587 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
8588 cfun->machine->lr_save_eliminated = 1;
8589 }
8590 }
8591
8592 /* If CODE is 'd', then the X is a condition operand and the instruction
8593 should only be executed if the condition is true.
8594 if CODE is 'D', then the X is a condition operand and the instruction
8595 should only be executed if the condition is false: however, if the mode
8596 of the comparison is CCFPEmode, then always execute the instruction -- we
8597 do this because in these circumstances !GE does not necessarily imply LT;
8598 in these cases the instruction pattern will take care to make sure that
8599 an instruction containing %d will follow, thereby undoing the effects of
8600 doing this instruction unconditionally.
8601 If CODE is 'N' then X is a floating point operand that must be negated
8602 before output.
8603 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8604 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8605
8606 void
arm_print_operand(stream,x,code)8607 arm_print_operand (stream, x, code)
8608 FILE * stream;
8609 rtx x;
8610 int code;
8611 {
8612 switch (code)
8613 {
8614 case '@':
8615 fputs (ASM_COMMENT_START, stream);
8616 return;
8617
8618 case '_':
8619 fputs (user_label_prefix, stream);
8620 return;
8621
8622 case '|':
8623 fputs (REGISTER_PREFIX, stream);
8624 return;
8625
8626 case '?':
8627 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
8628 {
8629 if (TARGET_THUMB || current_insn_predicate != NULL)
8630 abort ();
8631
8632 fputs (arm_condition_codes[arm_current_cc], stream);
8633 }
8634 else if (current_insn_predicate)
8635 {
8636 enum arm_cond_code code;
8637
8638 if (TARGET_THUMB)
8639 abort ();
8640
8641 code = get_arm_condition_code (current_insn_predicate);
8642 fputs (arm_condition_codes[code], stream);
8643 }
8644 return;
8645
8646 case 'N':
8647 {
8648 REAL_VALUE_TYPE r;
8649 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8650 r = REAL_VALUE_NEGATE (r);
8651 fprintf (stream, "%s", fp_const_from_val (&r));
8652 }
8653 return;
8654
8655 case 'B':
8656 if (GET_CODE (x) == CONST_INT)
8657 {
8658 HOST_WIDE_INT val;
8659 val = ARM_SIGN_EXTEND (~INTVAL (x));
8660 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8661 }
8662 else
8663 {
8664 putc ('~', stream);
8665 output_addr_const (stream, x);
8666 }
8667 return;
8668
8669 case 'i':
8670 fprintf (stream, "%s", arithmetic_instr (x, 1));
8671 return;
8672
8673 case 'I':
8674 fprintf (stream, "%s", arithmetic_instr (x, 0));
8675 return;
8676
8677 case 'S':
8678 {
8679 HOST_WIDE_INT val;
8680 const char * shift = shift_op (x, &val);
8681
8682 if (shift)
8683 {
8684 fprintf (stream, ", %s ", shift_op (x, &val));
8685 if (val == -1)
8686 arm_print_operand (stream, XEXP (x, 1), 0);
8687 else
8688 {
8689 fputc ('#', stream);
8690 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8691 }
8692 }
8693 }
8694 return;
8695
8696 /* An explanation of the 'Q', 'R' and 'H' register operands:
8697
8698 In a pair of registers containing a DI or DF value the 'Q'
8699 operand returns the register number of the register containing
8700 the least signficant part of the value. The 'R' operand returns
8701 the register number of the register containing the most
8702 significant part of the value.
8703
8704 The 'H' operand returns the higher of the two register numbers.
8705 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8706 same as the 'Q' operand, since the most signficant part of the
8707 value is held in the lower number register. The reverse is true
8708 on systems where WORDS_BIG_ENDIAN is false.
8709
8710 The purpose of these operands is to distinguish between cases
8711 where the endian-ness of the values is important (for example
8712 when they are added together), and cases where the endian-ness
8713 is irrelevant, but the order of register operations is important.
8714 For example when loading a value from memory into a register
8715 pair, the endian-ness does not matter. Provided that the value
8716 from the lower memory address is put into the lower numbered
8717 register, and the value from the higher address is put into the
8718 higher numbered register, the load will work regardless of whether
8719 the value being loaded is big-wordian or little-wordian. The
8720 order of the two register loads can matter however, if the address
8721 of the memory location is actually held in one of the registers
8722 being overwritten by the load. */
8723 case 'Q':
8724 if (REGNO (x) > LAST_ARM_REGNUM)
8725 abort ();
8726 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
8727 return;
8728
8729 case 'R':
8730 if (REGNO (x) > LAST_ARM_REGNUM)
8731 abort ();
8732 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
8733 return;
8734
8735 case 'H':
8736 if (REGNO (x) > LAST_ARM_REGNUM)
8737 abort ();
8738 asm_fprintf (stream, "%r", REGNO (x) + 1);
8739 return;
8740
8741 case 'm':
8742 asm_fprintf (stream, "%r",
8743 GET_CODE (XEXP (x, 0)) == REG
8744 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
8745 return;
8746
8747 case 'M':
8748 asm_fprintf (stream, "{%r-%r}",
8749 REGNO (x),
8750 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
8751 return;
8752
8753 case 'd':
8754 /* CONST_TRUE_RTX means always -- that's the default. */
8755 if (x == const_true_rtx)
8756 return;
8757
8758 if (TARGET_ARM)
8759 fputs (arm_condition_codes[get_arm_condition_code (x)],
8760 stream);
8761 else
8762 fputs (thumb_condition_code (x, 0), stream);
8763 return;
8764
8765 case 'D':
8766 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
8767 want to do that. */
8768 if (x == const_true_rtx)
8769 abort ();
8770
8771 if (TARGET_ARM)
8772 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
8773 (get_arm_condition_code (x))],
8774 stream);
8775 else
8776 fputs (thumb_condition_code (x, 1), stream);
8777 return;
8778
8779 default:
8780 if (x == 0)
8781 abort ();
8782
8783 if (GET_CODE (x) == REG)
8784 asm_fprintf (stream, "%r", REGNO (x));
8785 else if (GET_CODE (x) == MEM)
8786 {
8787 output_memory_reference_mode = GET_MODE (x);
8788 output_address (XEXP (x, 0));
8789 }
8790 else if (GET_CODE (x) == CONST_DOUBLE)
8791 fprintf (stream, "#%s", fp_immediate_constant (x));
8792 else if (GET_CODE (x) == NEG)
8793 abort (); /* This should never happen now. */
8794 else
8795 {
8796 fputc ('#', stream);
8797 output_addr_const (stream, x);
8798 }
8799 }
8800 }
8801
8802 #ifndef AOF_ASSEMBLER
8803 /* Target hook for assembling integer objects. The ARM version needs to
8804 handle word-sized values specially. */
8805
8806 static bool
arm_assemble_integer(x,size,aligned_p)8807 arm_assemble_integer (x, size, aligned_p)
8808 rtx x;
8809 unsigned int size;
8810 int aligned_p;
8811 {
8812 if (size == UNITS_PER_WORD && aligned_p)
8813 {
8814 fputs ("\t.word\t", asm_out_file);
8815 output_addr_const (asm_out_file, x);
8816
8817 /* Mark symbols as position independent. We only do this in the
8818 .text segment, not in the .data segment. */
8819 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
8820 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
8821 {
8822 if (GET_CODE (x) == SYMBOL_REF
8823 && (CONSTANT_POOL_ADDRESS_P (x)
8824 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x, 0))))
8825 fputs ("(GOTOFF)", asm_out_file);
8826 else if (GET_CODE (x) == LABEL_REF)
8827 fputs ("(GOTOFF)", asm_out_file);
8828 else
8829 fputs ("(GOT)", asm_out_file);
8830 }
8831 fputc ('\n', asm_out_file);
8832 return true;
8833 }
8834
8835 return default_assemble_integer (x, size, aligned_p);
8836 }
8837 #endif
8838
8839 /* A finite state machine takes care of noticing whether or not instructions
8840 can be conditionally executed, and thus decrease execution time and code
8841 size by deleting branch instructions. The fsm is controlled by
8842 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8843
8844 /* The state of the fsm controlling condition codes are:
8845 0: normal, do nothing special
8846 1: make ASM_OUTPUT_OPCODE not output this instruction
8847 2: make ASM_OUTPUT_OPCODE not output this instruction
8848 3: make instructions conditional
8849 4: make instructions conditional
8850
8851 State transitions (state->state by whom under condition):
8852 0 -> 1 final_prescan_insn if the `target' is a label
8853 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8854 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8855 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8856 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8857 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8858 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8859 (the target insn is arm_target_insn).
8860
8861 If the jump clobbers the conditions then we use states 2 and 4.
8862
8863 A similar thing can be done with conditional return insns.
8864
8865 XXX In case the `target' is an unconditional branch, this conditionalising
8866 of the instructions always reduces code size, but not always execution
8867 time. But then, I want to reduce the code size to somewhere near what
8868 /bin/cc produces. */
8869
8870 /* Returns the index of the ARM condition code string in
8871 `arm_condition_codes'. COMPARISON should be an rtx like
8872 `(eq (...) (...))'. */
8873
8874 static enum arm_cond_code
get_arm_condition_code(comparison)8875 get_arm_condition_code (comparison)
8876 rtx comparison;
8877 {
8878 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
8879 int code;
8880 enum rtx_code comp_code = GET_CODE (comparison);
8881
8882 if (GET_MODE_CLASS (mode) != MODE_CC)
8883 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
8884 XEXP (comparison, 1));
8885
8886 switch (mode)
8887 {
8888 case CC_DNEmode: code = ARM_NE; goto dominance;
8889 case CC_DEQmode: code = ARM_EQ; goto dominance;
8890 case CC_DGEmode: code = ARM_GE; goto dominance;
8891 case CC_DGTmode: code = ARM_GT; goto dominance;
8892 case CC_DLEmode: code = ARM_LE; goto dominance;
8893 case CC_DLTmode: code = ARM_LT; goto dominance;
8894 case CC_DGEUmode: code = ARM_CS; goto dominance;
8895 case CC_DGTUmode: code = ARM_HI; goto dominance;
8896 case CC_DLEUmode: code = ARM_LS; goto dominance;
8897 case CC_DLTUmode: code = ARM_CC;
8898
8899 dominance:
8900 if (comp_code != EQ && comp_code != NE)
8901 abort ();
8902
8903 if (comp_code == EQ)
8904 return ARM_INVERSE_CONDITION_CODE (code);
8905 return code;
8906
8907 case CC_NOOVmode:
8908 switch (comp_code)
8909 {
8910 case NE: return ARM_NE;
8911 case EQ: return ARM_EQ;
8912 case GE: return ARM_PL;
8913 case LT: return ARM_MI;
8914 default: abort ();
8915 }
8916
8917 case CC_Zmode:
8918 switch (comp_code)
8919 {
8920 case NE: return ARM_NE;
8921 case EQ: return ARM_EQ;
8922 default: abort ();
8923 }
8924
8925 case CCFPEmode:
8926 case CCFPmode:
8927 /* These encodings assume that AC=1 in the FPA system control
8928 byte. This allows us to handle all cases except UNEQ and
8929 LTGT. */
8930 switch (comp_code)
8931 {
8932 case GE: return ARM_GE;
8933 case GT: return ARM_GT;
8934 case LE: return ARM_LS;
8935 case LT: return ARM_MI;
8936 case NE: return ARM_NE;
8937 case EQ: return ARM_EQ;
8938 case ORDERED: return ARM_VC;
8939 case UNORDERED: return ARM_VS;
8940 case UNLT: return ARM_LT;
8941 case UNLE: return ARM_LE;
8942 case UNGT: return ARM_HI;
8943 case UNGE: return ARM_PL;
8944 /* UNEQ and LTGT do not have a representation. */
8945 case UNEQ: /* Fall through. */
8946 case LTGT: /* Fall through. */
8947 default: abort ();
8948 }
8949
8950 case CC_SWPmode:
8951 switch (comp_code)
8952 {
8953 case NE: return ARM_NE;
8954 case EQ: return ARM_EQ;
8955 case GE: return ARM_LE;
8956 case GT: return ARM_LT;
8957 case LE: return ARM_GE;
8958 case LT: return ARM_GT;
8959 case GEU: return ARM_LS;
8960 case GTU: return ARM_CC;
8961 case LEU: return ARM_CS;
8962 case LTU: return ARM_HI;
8963 default: abort ();
8964 }
8965
8966 case CC_Cmode:
8967 switch (comp_code)
8968 {
8969 case LTU: return ARM_CS;
8970 case GEU: return ARM_CC;
8971 default: abort ();
8972 }
8973
8974 case CCmode:
8975 switch (comp_code)
8976 {
8977 case NE: return ARM_NE;
8978 case EQ: return ARM_EQ;
8979 case GE: return ARM_GE;
8980 case GT: return ARM_GT;
8981 case LE: return ARM_LE;
8982 case LT: return ARM_LT;
8983 case GEU: return ARM_CS;
8984 case GTU: return ARM_HI;
8985 case LEU: return ARM_LS;
8986 case LTU: return ARM_CC;
8987 default: abort ();
8988 }
8989
8990 default: abort ();
8991 }
8992
8993 abort ();
8994 }
8995
8996
8997 void
arm_final_prescan_insn(insn)8998 arm_final_prescan_insn (insn)
8999 rtx insn;
9000 {
9001 /* BODY will hold the body of INSN. */
9002 rtx body = PATTERN (insn);
9003
9004 /* This will be 1 if trying to repeat the trick, and things need to be
9005 reversed if it appears to fail. */
9006 int reverse = 0;
9007
9008 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9009 taken are clobbered, even if the rtl suggests otherwise. It also
9010 means that we have to grub around within the jump expression to find
9011 out what the conditions are when the jump isn't taken. */
9012 int jump_clobbers = 0;
9013
9014 /* If we start with a return insn, we only succeed if we find another one. */
9015 int seeking_return = 0;
9016
9017 /* START_INSN will hold the insn from where we start looking. This is the
9018 first insn after the following code_label if REVERSE is true. */
9019 rtx start_insn = insn;
9020
9021 /* If in state 4, check if the target branch is reached, in order to
9022 change back to state 0. */
9023 if (arm_ccfsm_state == 4)
9024 {
9025 if (insn == arm_target_insn)
9026 {
9027 arm_target_insn = NULL;
9028 arm_ccfsm_state = 0;
9029 }
9030 return;
9031 }
9032
9033 /* If in state 3, it is possible to repeat the trick, if this insn is an
9034 unconditional branch to a label, and immediately following this branch
9035 is the previous target label which is only used once, and the label this
9036 branch jumps to is not too far off. */
9037 if (arm_ccfsm_state == 3)
9038 {
9039 if (simplejump_p (insn))
9040 {
9041 start_insn = next_nonnote_insn (start_insn);
9042 if (GET_CODE (start_insn) == BARRIER)
9043 {
9044 /* XXX Isn't this always a barrier? */
9045 start_insn = next_nonnote_insn (start_insn);
9046 }
9047 if (GET_CODE (start_insn) == CODE_LABEL
9048 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
9049 && LABEL_NUSES (start_insn) == 1)
9050 reverse = TRUE;
9051 else
9052 return;
9053 }
9054 else if (GET_CODE (body) == RETURN)
9055 {
9056 start_insn = next_nonnote_insn (start_insn);
9057 if (GET_CODE (start_insn) == BARRIER)
9058 start_insn = next_nonnote_insn (start_insn);
9059 if (GET_CODE (start_insn) == CODE_LABEL
9060 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
9061 && LABEL_NUSES (start_insn) == 1)
9062 {
9063 reverse = TRUE;
9064 seeking_return = 1;
9065 }
9066 else
9067 return;
9068 }
9069 else
9070 return;
9071 }
9072
9073 if (arm_ccfsm_state != 0 && !reverse)
9074 abort ();
9075 if (GET_CODE (insn) != JUMP_INSN)
9076 return;
9077
9078 /* This jump might be paralleled with a clobber of the condition codes
9079 the jump should always come first */
9080 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
9081 body = XVECEXP (body, 0, 0);
9082
9083 #if 0
9084 /* If this is a conditional return then we don't want to know */
9085 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
9086 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
9087 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
9088 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
9089 return;
9090 #endif
9091
9092 if (reverse
9093 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
9094 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
9095 {
9096 int insns_skipped;
9097 int fail = FALSE, succeed = FALSE;
9098 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
9099 int then_not_else = TRUE;
9100 rtx this_insn = start_insn, label = 0;
9101
9102 /* If the jump cannot be done with one instruction, we cannot
9103 conditionally execute the instruction in the inverse case. */
9104 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
9105 {
9106 jump_clobbers = 1;
9107 return;
9108 }
9109
9110 /* Register the insn jumped to. */
9111 if (reverse)
9112 {
9113 if (!seeking_return)
9114 label = XEXP (SET_SRC (body), 0);
9115 }
9116 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
9117 label = XEXP (XEXP (SET_SRC (body), 1), 0);
9118 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
9119 {
9120 label = XEXP (XEXP (SET_SRC (body), 2), 0);
9121 then_not_else = FALSE;
9122 }
9123 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
9124 seeking_return = 1;
9125 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
9126 {
9127 seeking_return = 1;
9128 then_not_else = FALSE;
9129 }
9130 else
9131 abort ();
9132
9133 /* See how many insns this branch skips, and what kind of insns. If all
9134 insns are okay, and the label or unconditional branch to the same
9135 label is not too far away, succeed. */
9136 for (insns_skipped = 0;
9137 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
9138 {
9139 rtx scanbody;
9140
9141 this_insn = next_nonnote_insn (this_insn);
9142 if (!this_insn)
9143 break;
9144
9145 switch (GET_CODE (this_insn))
9146 {
9147 case CODE_LABEL:
9148 /* Succeed if it is the target label, otherwise fail since
9149 control falls in from somewhere else. */
9150 if (this_insn == label)
9151 {
9152 if (jump_clobbers)
9153 {
9154 arm_ccfsm_state = 2;
9155 this_insn = next_nonnote_insn (this_insn);
9156 }
9157 else
9158 arm_ccfsm_state = 1;
9159 succeed = TRUE;
9160 }
9161 else
9162 fail = TRUE;
9163 break;
9164
9165 case BARRIER:
9166 /* Succeed if the following insn is the target label.
9167 Otherwise fail.
9168 If return insns are used then the last insn in a function
9169 will be a barrier. */
9170 this_insn = next_nonnote_insn (this_insn);
9171 if (this_insn && this_insn == label)
9172 {
9173 if (jump_clobbers)
9174 {
9175 arm_ccfsm_state = 2;
9176 this_insn = next_nonnote_insn (this_insn);
9177 }
9178 else
9179 arm_ccfsm_state = 1;
9180 succeed = TRUE;
9181 }
9182 else
9183 fail = TRUE;
9184 break;
9185
9186 case CALL_INSN:
9187 /* If using 32-bit addresses the cc is not preserved over
9188 calls. */
9189 if (TARGET_APCS_32)
9190 {
9191 /* Succeed if the following insn is the target label,
9192 or if the following two insns are a barrier and
9193 the target label. */
9194 this_insn = next_nonnote_insn (this_insn);
9195 if (this_insn && GET_CODE (this_insn) == BARRIER)
9196 this_insn = next_nonnote_insn (this_insn);
9197
9198 if (this_insn && this_insn == label
9199 && insns_skipped < max_insns_skipped)
9200 {
9201 if (jump_clobbers)
9202 {
9203 arm_ccfsm_state = 2;
9204 this_insn = next_nonnote_insn (this_insn);
9205 }
9206 else
9207 arm_ccfsm_state = 1;
9208 succeed = TRUE;
9209 }
9210 else
9211 fail = TRUE;
9212 }
9213 break;
9214
9215 case JUMP_INSN:
9216 /* If this is an unconditional branch to the same label, succeed.
9217 If it is to another label, do nothing. If it is conditional,
9218 fail. */
9219 /* XXX Probably, the tests for SET and the PC are unnecessary. */
9220
9221 scanbody = PATTERN (this_insn);
9222 if (GET_CODE (scanbody) == SET
9223 && GET_CODE (SET_DEST (scanbody)) == PC)
9224 {
9225 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
9226 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
9227 {
9228 arm_ccfsm_state = 2;
9229 succeed = TRUE;
9230 }
9231 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
9232 fail = TRUE;
9233 }
9234 /* Fail if a conditional return is undesirable (eg on a
9235 StrongARM), but still allow this if optimizing for size. */
9236 else if (GET_CODE (scanbody) == RETURN
9237 && !use_return_insn (TRUE)
9238 && !optimize_size)
9239 fail = TRUE;
9240 else if (GET_CODE (scanbody) == RETURN
9241 && seeking_return)
9242 {
9243 arm_ccfsm_state = 2;
9244 succeed = TRUE;
9245 }
9246 else if (GET_CODE (scanbody) == PARALLEL)
9247 {
9248 switch (get_attr_conds (this_insn))
9249 {
9250 case CONDS_NOCOND:
9251 break;
9252 default:
9253 fail = TRUE;
9254 break;
9255 }
9256 }
9257 else
9258 fail = TRUE; /* Unrecognized jump (eg epilogue). */
9259
9260 break;
9261
9262 case INSN:
9263 /* Instructions using or affecting the condition codes make it
9264 fail. */
9265 scanbody = PATTERN (this_insn);
9266 if (!(GET_CODE (scanbody) == SET
9267 || GET_CODE (scanbody) == PARALLEL)
9268 || get_attr_conds (this_insn) != CONDS_NOCOND)
9269 fail = TRUE;
9270 break;
9271
9272 default:
9273 break;
9274 }
9275 }
9276 if (succeed)
9277 {
9278 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
9279 arm_target_label = CODE_LABEL_NUMBER (label);
9280 else if (seeking_return || arm_ccfsm_state == 2)
9281 {
9282 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
9283 {
9284 this_insn = next_nonnote_insn (this_insn);
9285 if (this_insn && (GET_CODE (this_insn) == BARRIER
9286 || GET_CODE (this_insn) == CODE_LABEL))
9287 abort ();
9288 }
9289 if (!this_insn)
9290 {
9291 /* Oh, dear! we ran off the end.. give up */
9292 recog (PATTERN (insn), insn, NULL);
9293 arm_ccfsm_state = 0;
9294 arm_target_insn = NULL;
9295 return;
9296 }
9297 arm_target_insn = this_insn;
9298 }
9299 else
9300 abort ();
9301 if (jump_clobbers)
9302 {
9303 if (reverse)
9304 abort ();
9305 arm_current_cc =
9306 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
9307 0), 0), 1));
9308 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
9309 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
9310 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
9311 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
9312 }
9313 else
9314 {
9315 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
9316 what it was. */
9317 if (!reverse)
9318 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
9319 0));
9320 }
9321
9322 if (reverse || then_not_else)
9323 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
9324 }
9325
9326 /* Restore recog_data (getting the attributes of other insns can
9327 destroy this array, but final.c assumes that it remains intact
9328 across this call; since the insn has been recognized already we
9329 call recog direct). */
9330 recog (PATTERN (insn), insn, NULL);
9331 }
9332 }
9333
9334 /* Returns true if REGNO is a valid register
9335 for holding a quantity of tyoe MODE. */
9336
9337 int
arm_hard_regno_mode_ok(regno,mode)9338 arm_hard_regno_mode_ok (regno, mode)
9339 unsigned int regno;
9340 enum machine_mode mode;
9341 {
9342 if (GET_MODE_CLASS (mode) == MODE_CC)
9343 return regno == CC_REGNUM;
9344
9345 if (TARGET_THUMB)
9346 /* For the Thumb we only allow values bigger than SImode in
9347 registers 0 - 6, so that there is always a second low
9348 register available to hold the upper part of the value.
9349 We probably we ought to ensure that the register is the
9350 start of an even numbered register pair. */
9351 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
9352
9353 if (regno <= LAST_ARM_REGNUM)
9354 /* We allow any value to be stored in the general regisetrs. */
9355 return 1;
9356
9357 if ( regno == FRAME_POINTER_REGNUM
9358 || regno == ARG_POINTER_REGNUM)
9359 /* We only allow integers in the fake hard registers. */
9360 return GET_MODE_CLASS (mode) == MODE_INT;
9361
9362 /* The only registers left are the FPU registers
9363 which we only allow to hold FP values. */
9364 return GET_MODE_CLASS (mode) == MODE_FLOAT
9365 && regno >= FIRST_ARM_FP_REGNUM
9366 && regno <= LAST_ARM_FP_REGNUM;
9367 }
9368
9369 int
arm_regno_class(regno)9370 arm_regno_class (regno)
9371 int regno;
9372 {
9373 if (TARGET_THUMB)
9374 {
9375 if (regno == STACK_POINTER_REGNUM)
9376 return STACK_REG;
9377 if (regno == CC_REGNUM)
9378 return CC_REG;
9379 if (regno < 8)
9380 return LO_REGS;
9381 return HI_REGS;
9382 }
9383
9384 if ( regno <= LAST_ARM_REGNUM
9385 || regno == FRAME_POINTER_REGNUM
9386 || regno == ARG_POINTER_REGNUM)
9387 return GENERAL_REGS;
9388
9389 if (regno == CC_REGNUM)
9390 return NO_REGS;
9391
9392 return FPU_REGS;
9393 }
9394
9395 /* Handle a special case when computing the offset
9396 of an argument from the frame pointer. */
9397
9398 int
arm_debugger_arg_offset(value,addr)9399 arm_debugger_arg_offset (value, addr)
9400 int value;
9401 rtx addr;
9402 {
9403 rtx insn;
9404
9405 /* We are only interested if dbxout_parms() failed to compute the offset. */
9406 if (value != 0)
9407 return 0;
9408
9409 /* We can only cope with the case where the address is held in a register. */
9410 if (GET_CODE (addr) != REG)
9411 return 0;
9412
9413 /* If we are using the frame pointer to point at the argument, then
9414 an offset of 0 is correct. */
9415 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
9416 return 0;
9417
9418 /* If we are using the stack pointer to point at the
9419 argument, then an offset of 0 is correct. */
9420 if ((TARGET_THUMB || !frame_pointer_needed)
9421 && REGNO (addr) == SP_REGNUM)
9422 return 0;
9423
9424 /* Oh dear. The argument is pointed to by a register rather
9425 than being held in a register, or being stored at a known
9426 offset from the frame pointer. Since GDB only understands
9427 those two kinds of argument we must translate the address
9428 held in the register into an offset from the frame pointer.
9429 We do this by searching through the insns for the function
9430 looking to see where this register gets its value. If the
9431 register is initialized from the frame pointer plus an offset
9432 then we are in luck and we can continue, otherwise we give up.
9433
9434 This code is exercised by producing debugging information
9435 for a function with arguments like this:
9436
9437 double func (double a, double b, int c, double d) {return d;}
9438
9439 Without this code the stab for parameter 'd' will be set to
9440 an offset of 0 from the frame pointer, rather than 8. */
9441
9442 /* The if() statement says:
9443
9444 If the insn is a normal instruction
9445 and if the insn is setting the value in a register
9446 and if the register being set is the register holding the address of the argument
9447 and if the address is computing by an addition
9448 that involves adding to a register
9449 which is the frame pointer
9450 a constant integer
9451
9452 then... */
9453
9454 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9455 {
9456 if ( GET_CODE (insn) == INSN
9457 && GET_CODE (PATTERN (insn)) == SET
9458 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
9459 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
9460 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
9461 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
9462 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
9463 )
9464 {
9465 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
9466
9467 break;
9468 }
9469 }
9470
9471 if (value == 0)
9472 {
9473 debug_rtx (addr);
9474 warning ("unable to compute real location of stacked parameter");
9475 value = 8; /* XXX magic hack */
9476 }
9477
9478 return value;
9479 }
9480
9481 #define def_builtin(NAME, TYPE, CODE) \
9482 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE)
9483
9484 void
arm_init_builtins()9485 arm_init_builtins ()
9486 {
9487 tree endlink = void_list_node;
9488 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
9489 tree pchar_type_node = build_pointer_type (char_type_node);
9490
9491 tree int_ftype_int, void_ftype_pchar;
9492
9493 /* void func (char *) */
9494 void_ftype_pchar
9495 = build_function_type_list (void_type_node, pchar_type_node, NULL_TREE);
9496
9497 /* int func (int) */
9498 int_ftype_int
9499 = build_function_type (integer_type_node, int_endlink);
9500
9501 /* Initialize arm V5 builtins. */
9502 if (arm_arch5)
9503 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
9504 }
9505
9506 /* Expand an expression EXP that calls a built-in function,
9507 with result going to TARGET if that's convenient
9508 (and in mode MODE if that's convenient).
9509 SUBTARGET may be used as the target for computing one of EXP's operands.
9510 IGNORE is nonzero if the value is to be ignored. */
9511
9512 rtx
arm_expand_builtin(exp,target,subtarget,mode,ignore)9513 arm_expand_builtin (exp, target, subtarget, mode, ignore)
9514 tree exp;
9515 rtx target;
9516 rtx subtarget ATTRIBUTE_UNUSED;
9517 enum machine_mode mode ATTRIBUTE_UNUSED;
9518 int ignore ATTRIBUTE_UNUSED;
9519 {
9520 enum insn_code icode;
9521 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9522 tree arglist = TREE_OPERAND (exp, 1);
9523 tree arg0;
9524 rtx op0, pat;
9525 enum machine_mode tmode, mode0;
9526 int fcode = DECL_FUNCTION_CODE (fndecl);
9527
9528 switch (fcode)
9529 {
9530 default:
9531 break;
9532
9533 case ARM_BUILTIN_CLZ:
9534 icode = CODE_FOR_clz;
9535 arg0 = TREE_VALUE (arglist);
9536 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
9537 tmode = insn_data[icode].operand[0].mode;
9538 mode0 = insn_data[icode].operand[1].mode;
9539
9540 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9541 op0 = copy_to_mode_reg (mode0, op0);
9542 if (target == 0
9543 || GET_MODE (target) != tmode
9544 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9545 target = gen_reg_rtx (tmode);
9546 pat = GEN_FCN (icode) (target, op0);
9547 if (! pat)
9548 return 0;
9549 emit_insn (pat);
9550 return target;
9551 }
9552
9553 /* @@@ Should really do something sensible here. */
9554 return NULL_RTX;
9555 }
9556
9557 /* Recursively search through all of the blocks in a function
9558 checking to see if any of the variables created in that
9559 function match the RTX called 'orig'. If they do then
9560 replace them with the RTX called 'new'. */
9561
9562 static void
replace_symbols_in_block(block,orig,new)9563 replace_symbols_in_block (block, orig, new)
9564 tree block;
9565 rtx orig;
9566 rtx new;
9567 {
9568 for (; block; block = BLOCK_CHAIN (block))
9569 {
9570 tree sym;
9571
9572 if (!TREE_USED (block))
9573 continue;
9574
9575 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
9576 {
9577 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
9578 || DECL_IGNORED_P (sym)
9579 || TREE_CODE (sym) != VAR_DECL
9580 || DECL_EXTERNAL (sym)
9581 || !rtx_equal_p (DECL_RTL (sym), orig)
9582 )
9583 continue;
9584
9585 SET_DECL_RTL (sym, new);
9586 }
9587
9588 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
9589 }
9590 }
9591
9592 /* Return the number (counting from 0) of
9593 the least significant set bit in MASK. */
9594
9595 #ifdef __GNUC__
9596 inline
9597 #endif
9598 static int
number_of_first_bit_set(mask)9599 number_of_first_bit_set (mask)
9600 int mask;
9601 {
9602 int bit;
9603
9604 for (bit = 0;
9605 (mask & (1 << bit)) == 0;
9606 ++bit)
9607 continue;
9608
9609 return bit;
9610 }
9611
9612 /* Generate code to return from a thumb function.
9613 If 'reg_containing_return_addr' is -1, then the return address is
9614 actually on the stack, at the stack pointer. */
9615 static void
thumb_exit(f,reg_containing_return_addr,eh_ofs)9616 thumb_exit (f, reg_containing_return_addr, eh_ofs)
9617 FILE * f;
9618 int reg_containing_return_addr;
9619 rtx eh_ofs;
9620 {
9621 unsigned regs_available_for_popping;
9622 unsigned regs_to_pop;
9623 int pops_needed;
9624 unsigned available;
9625 unsigned required;
9626 int mode;
9627 int size;
9628 int restore_a4 = FALSE;
9629
9630 /* Compute the registers we need to pop. */
9631 regs_to_pop = 0;
9632 pops_needed = 0;
9633
9634 /* There is an assumption here, that if eh_ofs is not NULL, the
9635 normal return address will have been pushed. */
9636 if (reg_containing_return_addr == -1 || eh_ofs)
9637 {
9638 /* When we are generating a return for __builtin_eh_return,
9639 reg_containing_return_addr must specify the return regno. */
9640 if (eh_ofs && reg_containing_return_addr == -1)
9641 abort ();
9642
9643 regs_to_pop |= 1 << LR_REGNUM;
9644 ++pops_needed;
9645 }
9646
9647 if (TARGET_BACKTRACE)
9648 {
9649 /* Restore the (ARM) frame pointer and stack pointer. */
9650 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
9651 pops_needed += 2;
9652 }
9653
9654 /* If there is nothing to pop then just emit the BX instruction and
9655 return. */
9656 if (pops_needed == 0)
9657 {
9658 if (eh_ofs)
9659 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9660
9661 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9662 return;
9663 }
9664 /* Otherwise if we are not supporting interworking and we have not created
9665 a backtrace structure and the function was not entered in ARM mode then
9666 just pop the return address straight into the PC. */
9667 else if (!TARGET_INTERWORK
9668 && !TARGET_BACKTRACE
9669 && !is_called_in_ARM_mode (current_function_decl))
9670 {
9671 if (eh_ofs)
9672 {
9673 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
9674 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9675 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9676 }
9677 else
9678 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
9679
9680 return;
9681 }
9682
9683 /* Find out how many of the (return) argument registers we can corrupt. */
9684 regs_available_for_popping = 0;
9685
9686 /* If returning via __builtin_eh_return, the bottom three registers
9687 all contain information needed for the return. */
9688 if (eh_ofs)
9689 size = 12;
9690 else
9691 {
9692 #ifdef RTX_CODE
9693 /* If we can deduce the registers used from the function's
9694 return value. This is more reliable that examining
9695 regs_ever_live[] because that will be set if the register is
9696 ever used in the function, not just if the register is used
9697 to hold a return value. */
9698
9699 if (current_function_return_rtx != 0)
9700 mode = GET_MODE (current_function_return_rtx);
9701 else
9702 #endif
9703 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9704
9705 size = GET_MODE_SIZE (mode);
9706
9707 if (size == 0)
9708 {
9709 /* In a void function we can use any argument register.
9710 In a function that returns a structure on the stack
9711 we can use the second and third argument registers. */
9712 if (mode == VOIDmode)
9713 regs_available_for_popping =
9714 (1 << ARG_REGISTER (1))
9715 | (1 << ARG_REGISTER (2))
9716 | (1 << ARG_REGISTER (3));
9717 else
9718 regs_available_for_popping =
9719 (1 << ARG_REGISTER (2))
9720 | (1 << ARG_REGISTER (3));
9721 }
9722 else if (size <= 4)
9723 regs_available_for_popping =
9724 (1 << ARG_REGISTER (2))
9725 | (1 << ARG_REGISTER (3));
9726 else if (size <= 8)
9727 regs_available_for_popping =
9728 (1 << ARG_REGISTER (3));
9729 }
9730
9731 /* Match registers to be popped with registers into which we pop them. */
9732 for (available = regs_available_for_popping,
9733 required = regs_to_pop;
9734 required != 0 && available != 0;
9735 available &= ~(available & - available),
9736 required &= ~(required & - required))
9737 -- pops_needed;
9738
9739 /* If we have any popping registers left over, remove them. */
9740 if (available > 0)
9741 regs_available_for_popping &= ~available;
9742
9743 /* Otherwise if we need another popping register we can use
9744 the fourth argument register. */
9745 else if (pops_needed)
9746 {
9747 /* If we have not found any free argument registers and
9748 reg a4 contains the return address, we must move it. */
9749 if (regs_available_for_popping == 0
9750 && reg_containing_return_addr == LAST_ARG_REGNUM)
9751 {
9752 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9753 reg_containing_return_addr = LR_REGNUM;
9754 }
9755 else if (size > 12)
9756 {
9757 /* Register a4 is being used to hold part of the return value,
9758 but we have dire need of a free, low register. */
9759 restore_a4 = TRUE;
9760
9761 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
9762 }
9763
9764 if (reg_containing_return_addr != LAST_ARG_REGNUM)
9765 {
9766 /* The fourth argument register is available. */
9767 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
9768
9769 --pops_needed;
9770 }
9771 }
9772
9773 /* Pop as many registers as we can. */
9774 thumb_pushpop (f, regs_available_for_popping, FALSE);
9775
9776 /* Process the registers we popped. */
9777 if (reg_containing_return_addr == -1)
9778 {
9779 /* The return address was popped into the lowest numbered register. */
9780 regs_to_pop &= ~(1 << LR_REGNUM);
9781
9782 reg_containing_return_addr =
9783 number_of_first_bit_set (regs_available_for_popping);
9784
9785 /* Remove this register for the mask of available registers, so that
9786 the return address will not be corrupted by futher pops. */
9787 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
9788 }
9789
9790 /* If we popped other registers then handle them here. */
9791 if (regs_available_for_popping)
9792 {
9793 int frame_pointer;
9794
9795 /* Work out which register currently contains the frame pointer. */
9796 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
9797
9798 /* Move it into the correct place. */
9799 asm_fprintf (f, "\tmov\t%r, %r\n",
9800 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
9801
9802 /* (Temporarily) remove it from the mask of popped registers. */
9803 regs_available_for_popping &= ~(1 << frame_pointer);
9804 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
9805
9806 if (regs_available_for_popping)
9807 {
9808 int stack_pointer;
9809
9810 /* We popped the stack pointer as well,
9811 find the register that contains it. */
9812 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
9813
9814 /* Move it into the stack register. */
9815 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
9816
9817 /* At this point we have popped all necessary registers, so
9818 do not worry about restoring regs_available_for_popping
9819 to its correct value:
9820
9821 assert (pops_needed == 0)
9822 assert (regs_available_for_popping == (1 << frame_pointer))
9823 assert (regs_to_pop == (1 << STACK_POINTER)) */
9824 }
9825 else
9826 {
9827 /* Since we have just move the popped value into the frame
9828 pointer, the popping register is available for reuse, and
9829 we know that we still have the stack pointer left to pop. */
9830 regs_available_for_popping |= (1 << frame_pointer);
9831 }
9832 }
9833
9834 /* If we still have registers left on the stack, but we no longer have
9835 any registers into which we can pop them, then we must move the return
9836 address into the link register and make available the register that
9837 contained it. */
9838 if (regs_available_for_popping == 0 && pops_needed > 0)
9839 {
9840 regs_available_for_popping |= 1 << reg_containing_return_addr;
9841
9842 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
9843 reg_containing_return_addr);
9844
9845 reg_containing_return_addr = LR_REGNUM;
9846 }
9847
9848 /* If we have registers left on the stack then pop some more.
9849 We know that at most we will want to pop FP and SP. */
9850 if (pops_needed > 0)
9851 {
9852 int popped_into;
9853 int move_to;
9854
9855 thumb_pushpop (f, regs_available_for_popping, FALSE);
9856
9857 /* We have popped either FP or SP.
9858 Move whichever one it is into the correct register. */
9859 popped_into = number_of_first_bit_set (regs_available_for_popping);
9860 move_to = number_of_first_bit_set (regs_to_pop);
9861
9862 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
9863
9864 regs_to_pop &= ~(1 << move_to);
9865
9866 --pops_needed;
9867 }
9868
9869 /* If we still have not popped everything then we must have only
9870 had one register available to us and we are now popping the SP. */
9871 if (pops_needed > 0)
9872 {
9873 int popped_into;
9874
9875 thumb_pushpop (f, regs_available_for_popping, FALSE);
9876
9877 popped_into = number_of_first_bit_set (regs_available_for_popping);
9878
9879 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
9880 /*
9881 assert (regs_to_pop == (1 << STACK_POINTER))
9882 assert (pops_needed == 1)
9883 */
9884 }
9885
9886 /* If necessary restore the a4 register. */
9887 if (restore_a4)
9888 {
9889 if (reg_containing_return_addr != LR_REGNUM)
9890 {
9891 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9892 reg_containing_return_addr = LR_REGNUM;
9893 }
9894
9895 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
9896 }
9897
9898 if (eh_ofs)
9899 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9900
9901 /* Return to caller. */
9902 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9903 }
9904
9905 /* Emit code to push or pop registers to or from the stack. */
9906
9907 static void
thumb_pushpop(f,mask,push)9908 thumb_pushpop (f, mask, push)
9909 FILE * f;
9910 int mask;
9911 int push;
9912 {
9913 int regno;
9914 int lo_mask = mask & 0xFF;
9915
9916 if (lo_mask == 0 && !push && (mask & (1 << 15)))
9917 {
9918 /* Special case. Do not generate a POP PC statement here, do it in
9919 thumb_exit() */
9920 thumb_exit (f, -1, NULL_RTX);
9921 return;
9922 }
9923
9924 fprintf (f, "\t%s\t{", push ? "push" : "pop");
9925
9926 /* Look at the low registers first. */
9927 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
9928 {
9929 if (lo_mask & 1)
9930 {
9931 asm_fprintf (f, "%r", regno);
9932
9933 if ((lo_mask & ~1) != 0)
9934 fprintf (f, ", ");
9935 }
9936 }
9937
9938 if (push && (mask & (1 << LR_REGNUM)))
9939 {
9940 /* Catch pushing the LR. */
9941 if (mask & 0xFF)
9942 fprintf (f, ", ");
9943
9944 asm_fprintf (f, "%r", LR_REGNUM);
9945 }
9946 else if (!push && (mask & (1 << PC_REGNUM)))
9947 {
9948 /* Catch popping the PC. */
9949 if (TARGET_INTERWORK || TARGET_BACKTRACE)
9950 {
9951 /* The PC is never poped directly, instead
9952 it is popped into r3 and then BX is used. */
9953 fprintf (f, "}\n");
9954
9955 thumb_exit (f, -1, NULL_RTX);
9956
9957 return;
9958 }
9959 else
9960 {
9961 if (mask & 0xFF)
9962 fprintf (f, ", ");
9963
9964 asm_fprintf (f, "%r", PC_REGNUM);
9965 }
9966 }
9967
9968 fprintf (f, "}\n");
9969 }
9970
9971 void
thumb_final_prescan_insn(insn)9972 thumb_final_prescan_insn (insn)
9973 rtx insn;
9974 {
9975 if (flag_print_asm_name)
9976 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
9977 INSN_ADDRESSES (INSN_UID (insn)));
9978 }
9979
9980 int
thumb_shiftable_const(val)9981 thumb_shiftable_const (val)
9982 unsigned HOST_WIDE_INT val;
9983 {
9984 unsigned HOST_WIDE_INT mask = 0xff;
9985 int i;
9986
9987 if (val == 0) /* XXX */
9988 return 0;
9989
9990 for (i = 0; i < 25; i++)
9991 if ((val & (mask << i)) == val)
9992 return 1;
9993
9994 return 0;
9995 }
9996
9997 /* Returns nonzero if the current function contains,
9998 or might contain a far jump. */
9999
10000 int
thumb_far_jump_used_p(in_prologue)10001 thumb_far_jump_used_p (in_prologue)
10002 int in_prologue;
10003 {
10004 rtx insn;
10005
10006 /* This test is only important for leaf functions. */
10007 /* assert (!leaf_function_p ()); */
10008
10009 /* If we have already decided that far jumps may be used,
10010 do not bother checking again, and always return true even if
10011 it turns out that they are not being used. Once we have made
10012 the decision that far jumps are present (and that hence the link
10013 register will be pushed onto the stack) we cannot go back on it. */
10014 if (cfun->machine->far_jump_used)
10015 return 1;
10016
10017 /* If this function is not being called from the prologue/epilogue
10018 generation code then it must be being called from the
10019 INITIAL_ELIMINATION_OFFSET macro. */
10020 if (!in_prologue)
10021 {
10022 /* In this case we know that we are being asked about the elimination
10023 of the arg pointer register. If that register is not being used,
10024 then there are no arguments on the stack, and we do not have to
10025 worry that a far jump might force the prologue to push the link
10026 register, changing the stack offsets. In this case we can just
10027 return false, since the presence of far jumps in the function will
10028 not affect stack offsets.
10029
10030 If the arg pointer is live (or if it was live, but has now been
10031 eliminated and so set to dead) then we do have to test to see if
10032 the function might contain a far jump. This test can lead to some
10033 false negatives, since before reload is completed, then length of
10034 branch instructions is not known, so gcc defaults to returning their
10035 longest length, which in turn sets the far jump attribute to true.
10036
10037 A false negative will not result in bad code being generated, but it
10038 will result in a needless push and pop of the link register. We
10039 hope that this does not occur too often. */
10040 if (regs_ever_live [ARG_POINTER_REGNUM])
10041 cfun->machine->arg_pointer_live = 1;
10042 else if (!cfun->machine->arg_pointer_live)
10043 return 0;
10044 }
10045
10046 /* Check to see if the function contains a branch
10047 insn with the far jump attribute set. */
10048 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10049 {
10050 if (GET_CODE (insn) == JUMP_INSN
10051 /* Ignore tablejump patterns. */
10052 && GET_CODE (PATTERN (insn)) != ADDR_VEC
10053 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
10054 && get_attr_far_jump (insn) == FAR_JUMP_YES
10055 )
10056 {
10057 /* Record the fact that we have decied that
10058 the function does use far jumps. */
10059 cfun->machine->far_jump_used = 1;
10060 return 1;
10061 }
10062 }
10063
10064 return 0;
10065 }
10066
10067 /* Return nonzero if FUNC must be entered in ARM mode. */
10068
10069 int
is_called_in_ARM_mode(func)10070 is_called_in_ARM_mode (func)
10071 tree func;
10072 {
10073 if (TREE_CODE (func) != FUNCTION_DECL)
10074 abort ();
10075
10076 /* Ignore the problem about functions whoes address is taken. */
10077 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
10078 return TRUE;
10079
10080 #ifdef ARM_PE
10081 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
10082 #else
10083 return FALSE;
10084 #endif
10085 }
10086
10087 /* The bits which aren't usefully expanded as rtl. */
10088
10089 const char *
thumb_unexpanded_epilogue()10090 thumb_unexpanded_epilogue ()
10091 {
10092 int regno;
10093 int live_regs_mask = 0;
10094 int high_regs_pushed = 0;
10095 int leaf_function = leaf_function_p ();
10096 int had_to_push_lr;
10097 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
10098
10099 if (return_used_this_function)
10100 return "";
10101
10102 if (IS_NAKED (arm_current_func_type ()))
10103 return "";
10104
10105 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10106 if (THUMB_REG_PUSHED_P (regno))
10107 live_regs_mask |= 1 << regno;
10108
10109 for (regno = 8; regno < 13; regno++)
10110 if (THUMB_REG_PUSHED_P (regno))
10111 high_regs_pushed++;
10112
10113 /* The prolog may have pushed some high registers to use as
10114 work registers. eg the testuite file:
10115 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
10116 compiles to produce:
10117 push {r4, r5, r6, r7, lr}
10118 mov r7, r9
10119 mov r6, r8
10120 push {r6, r7}
10121 as part of the prolog. We have to undo that pushing here. */
10122
10123 if (high_regs_pushed)
10124 {
10125 int mask = live_regs_mask;
10126 int next_hi_reg;
10127 int size;
10128 int mode;
10129
10130 #ifdef RTX_CODE
10131 /* If we can deduce the registers used from the function's return value.
10132 This is more reliable that examining regs_ever_live[] because that
10133 will be set if the register is ever used in the function, not just if
10134 the register is used to hold a return value. */
10135
10136 if (current_function_return_rtx != 0)
10137 mode = GET_MODE (current_function_return_rtx);
10138 else
10139 #endif
10140 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10141
10142 size = GET_MODE_SIZE (mode);
10143
10144 /* Unless we are returning a type of size > 12 register r3 is
10145 available. */
10146 if (size < 13)
10147 mask |= 1 << 3;
10148
10149 if (mask == 0)
10150 /* Oh dear! We have no low registers into which we can pop
10151 high registers! */
10152 internal_error
10153 ("no low registers available for popping high registers");
10154
10155 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
10156 if (THUMB_REG_PUSHED_P (next_hi_reg))
10157 break;
10158
10159 while (high_regs_pushed)
10160 {
10161 /* Find lo register(s) into which the high register(s) can
10162 be popped. */
10163 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10164 {
10165 if (mask & (1 << regno))
10166 high_regs_pushed--;
10167 if (high_regs_pushed == 0)
10168 break;
10169 }
10170
10171 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
10172
10173 /* Pop the values into the low register(s). */
10174 thumb_pushpop (asm_out_file, mask, 0);
10175
10176 /* Move the value(s) into the high registers. */
10177 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10178 {
10179 if (mask & (1 << regno))
10180 {
10181 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
10182 regno);
10183
10184 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
10185 if (THUMB_REG_PUSHED_P (next_hi_reg))
10186 break;
10187 }
10188 }
10189 }
10190 }
10191
10192 had_to_push_lr = (live_regs_mask || !leaf_function
10193 || thumb_far_jump_used_p (1));
10194
10195 if (TARGET_BACKTRACE
10196 && ((live_regs_mask & 0xFF) == 0)
10197 && regs_ever_live [LAST_ARG_REGNUM] != 0)
10198 {
10199 /* The stack backtrace structure creation code had to
10200 push R7 in order to get a work register, so we pop
10201 it now. */
10202 live_regs_mask |= (1 << LAST_LO_REGNUM);
10203 }
10204
10205 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
10206 {
10207 if (had_to_push_lr
10208 && !is_called_in_ARM_mode (current_function_decl)
10209 && !eh_ofs)
10210 live_regs_mask |= 1 << PC_REGNUM;
10211
10212 /* Either no argument registers were pushed or a backtrace
10213 structure was created which includes an adjusted stack
10214 pointer, so just pop everything. */
10215 if (live_regs_mask)
10216 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
10217
10218 if (eh_ofs)
10219 thumb_exit (asm_out_file, 2, eh_ofs);
10220 /* We have either just popped the return address into the
10221 PC or it is was kept in LR for the entire function or
10222 it is still on the stack because we do not want to
10223 return by doing a pop {pc}. */
10224 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
10225 thumb_exit (asm_out_file,
10226 (had_to_push_lr
10227 && is_called_in_ARM_mode (current_function_decl)) ?
10228 -1 : LR_REGNUM, NULL_RTX);
10229 }
10230 else
10231 {
10232 /* Pop everything but the return address. */
10233 live_regs_mask &= ~(1 << PC_REGNUM);
10234
10235 if (live_regs_mask)
10236 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
10237
10238 if (had_to_push_lr)
10239 /* Get the return address into a temporary register. */
10240 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
10241
10242 /* Remove the argument registers that were pushed onto the stack. */
10243 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
10244 SP_REGNUM, SP_REGNUM,
10245 current_function_pretend_args_size);
10246
10247 if (eh_ofs)
10248 thumb_exit (asm_out_file, 2, eh_ofs);
10249 else
10250 thumb_exit (asm_out_file,
10251 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
10252 }
10253
10254 return "";
10255 }
10256
10257 /* Functions to save and restore machine-specific function data. */
10258
10259 static struct machine_function *
arm_init_machine_status()10260 arm_init_machine_status ()
10261 {
10262 struct machine_function *machine;
10263 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
10264
10265 #if ARM_FT_UNKNOWN != 0
10266 machine->func_type = ARM_FT_UNKNOWN;
10267 #endif
10268 return machine;
10269 }
10270
10271 /* Return an RTX indicating where the return address to the
10272 calling function can be found. */
10273
10274 rtx
arm_return_addr(count,frame)10275 arm_return_addr (count, frame)
10276 int count;
10277 rtx frame ATTRIBUTE_UNUSED;
10278 {
10279 if (count != 0)
10280 return NULL_RTX;
10281
10282 if (TARGET_APCS_32)
10283 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
10284 else
10285 {
10286 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
10287 GEN_INT (RETURN_ADDR_MASK26));
10288 return get_func_hard_reg_initial_val (cfun, lr);
10289 }
10290 }
10291
10292 /* Do anything needed before RTL is emitted for each function. */
10293
10294 void
arm_init_expanders()10295 arm_init_expanders ()
10296 {
10297 /* Arrange to initialize and mark the machine per-function status. */
10298 init_machine_status = arm_init_machine_status;
10299 }
10300
10301 HOST_WIDE_INT
thumb_get_frame_size()10302 thumb_get_frame_size ()
10303 {
10304 int regno;
10305
10306 int base_size = ROUND_UP (get_frame_size ());
10307 int count_regs = 0;
10308 int entry_size = 0;
10309 int leaf;
10310
10311 if (! TARGET_THUMB)
10312 abort ();
10313
10314 if (! TARGET_ATPCS)
10315 return base_size;
10316
10317 /* We need to know if we are a leaf function. Unfortunately, it
10318 is possible to be called after start_sequence has been called,
10319 which causes get_insns to return the insns for the sequence,
10320 not the function, which will cause leaf_function_p to return
10321 the incorrect result.
10322
10323 To work around this, we cache the computed frame size. This
10324 works because we will only be calling RTL expanders that need
10325 to know about leaf functions once reload has completed, and the
10326 frame size cannot be changed after that time, so we can safely
10327 use the cached value. */
10328
10329 if (reload_completed)
10330 return cfun->machine->frame_size;
10331
10332 leaf = leaf_function_p ();
10333
10334 /* A leaf function does not need any stack alignment if it has nothing
10335 on the stack. */
10336 if (leaf && base_size == 0)
10337 {
10338 cfun->machine->frame_size = 0;
10339 return 0;
10340 }
10341
10342 /* We know that SP will be word aligned on entry, and we must
10343 preserve that condition at any subroutine call. But those are
10344 the only constraints. */
10345
10346 /* Space for variadic functions. */
10347 if (current_function_pretend_args_size)
10348 entry_size += current_function_pretend_args_size;
10349
10350 /* Space for pushed lo registers. */
10351 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10352 if (THUMB_REG_PUSHED_P (regno))
10353 count_regs++;
10354
10355 /* Space for backtrace structure. */
10356 if (TARGET_BACKTRACE)
10357 {
10358 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
10359 entry_size += 20;
10360 else
10361 entry_size += 16;
10362 }
10363
10364 if (count_regs || !leaf || thumb_far_jump_used_p (1))
10365 count_regs++; /* LR */
10366
10367 entry_size += count_regs * 4;
10368 count_regs = 0;
10369
10370 /* Space for pushed hi regs. */
10371 for (regno = 8; regno < 13; regno++)
10372 if (THUMB_REG_PUSHED_P (regno))
10373 count_regs++;
10374
10375 entry_size += count_regs * 4;
10376
10377 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
10378 base_size += 4;
10379 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
10380 abort ();
10381
10382 cfun->machine->frame_size = base_size;
10383
10384 return base_size;
10385 }
10386
10387 /* Generate the rest of a function's prologue. */
10388
10389 void
thumb_expand_prologue()10390 thumb_expand_prologue ()
10391 {
10392 HOST_WIDE_INT amount = (thumb_get_frame_size ()
10393 + current_function_outgoing_args_size);
10394 unsigned long func_type;
10395
10396 func_type = arm_current_func_type ();
10397
10398 /* Naked functions don't have prologues. */
10399 if (IS_NAKED (func_type))
10400 return;
10401
10402 if (IS_INTERRUPT (func_type))
10403 {
10404 error ("interrupt Service Routines cannot be coded in Thumb mode");
10405 return;
10406 }
10407
10408 if (frame_pointer_needed)
10409 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
10410
10411 if (amount)
10412 {
10413 amount = ROUND_UP (amount);
10414
10415 if (amount < 512)
10416 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10417 GEN_INT (- amount)));
10418 else
10419 {
10420 int regno;
10421 rtx reg;
10422
10423 /* The stack decrement is too big for an immediate value in a single
10424 insn. In theory we could issue multiple subtracts, but after
10425 three of them it becomes more space efficient to place the full
10426 value in the constant pool and load into a register. (Also the
10427 ARM debugger really likes to see only one stack decrement per
10428 function). So instead we look for a scratch register into which
10429 we can load the decrement, and then we subtract this from the
10430 stack pointer. Unfortunately on the thumb the only available
10431 scratch registers are the argument registers, and we cannot use
10432 these as they may hold arguments to the function. Instead we
10433 attempt to locate a call preserved register which is used by this
10434 function. If we can find one, then we know that it will have
10435 been pushed at the start of the prologue and so we can corrupt
10436 it now. */
10437 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
10438 if (THUMB_REG_PUSHED_P (regno)
10439 && !(frame_pointer_needed
10440 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
10441 break;
10442
10443 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
10444 {
10445 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
10446
10447 /* Choose an arbitary, non-argument low register. */
10448 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
10449
10450 /* Save it by copying it into a high, scratch register. */
10451 emit_insn (gen_movsi (spare, reg));
10452 /* Add a USE to stop propagate_one_insn() from barfing. */
10453 emit_insn (gen_prologue_use (spare));
10454
10455 /* Decrement the stack. */
10456 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
10457 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10458 reg));
10459
10460 /* Restore the low register's original value. */
10461 emit_insn (gen_movsi (reg, spare));
10462
10463 /* Emit a USE of the restored scratch register, so that flow
10464 analysis will not consider the restore redundant. The
10465 register won't be used again in this function and isn't
10466 restored by the epilogue. */
10467 emit_insn (gen_prologue_use (reg));
10468 }
10469 else
10470 {
10471 reg = gen_rtx (REG, SImode, regno);
10472
10473 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
10474 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10475 reg));
10476 }
10477 }
10478 }
10479
10480 if (current_function_profile || TARGET_NO_SCHED_PRO)
10481 emit_insn (gen_blockage ());
10482 }
10483
10484 void
thumb_expand_epilogue()10485 thumb_expand_epilogue ()
10486 {
10487 HOST_WIDE_INT amount = (thumb_get_frame_size ()
10488 + current_function_outgoing_args_size);
10489
10490 /* Naked functions don't have prologues. */
10491 if (IS_NAKED (arm_current_func_type ()))
10492 return;
10493
10494 if (frame_pointer_needed)
10495 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
10496 else if (amount)
10497 {
10498 amount = ROUND_UP (amount);
10499
10500 if (amount < 512)
10501 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10502 GEN_INT (amount)));
10503 else
10504 {
10505 /* r3 is always free in the epilogue. */
10506 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
10507
10508 emit_insn (gen_movsi (reg, GEN_INT (amount)));
10509 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
10510 }
10511 }
10512
10513 /* Emit a USE (stack_pointer_rtx), so that
10514 the stack adjustment will not be deleted. */
10515 emit_insn (gen_prologue_use (stack_pointer_rtx));
10516
10517 if (current_function_profile || TARGET_NO_SCHED_PRO)
10518 emit_insn (gen_blockage ());
10519 }
10520
10521 static void
thumb_output_function_prologue(f,size)10522 thumb_output_function_prologue (f, size)
10523 FILE * f;
10524 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
10525 {
10526 int live_regs_mask = 0;
10527 int high_regs_pushed = 0;
10528 int regno;
10529
10530 if (IS_NAKED (arm_current_func_type ()))
10531 return;
10532
10533 if (is_called_in_ARM_mode (current_function_decl))
10534 {
10535 const char * name;
10536
10537 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
10538 abort ();
10539 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
10540 abort ();
10541 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10542
10543 /* Generate code sequence to switch us into Thumb mode. */
10544 /* The .code 32 directive has already been emitted by
10545 ASM_DECLARE_FUNCTION_NAME. */
10546 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
10547 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
10548
10549 /* Generate a label, so that the debugger will notice the
10550 change in instruction sets. This label is also used by
10551 the assembler to bypass the ARM code when this function
10552 is called from a Thumb encoded function elsewhere in the
10553 same file. Hence the definition of STUB_NAME here must
10554 agree with the definition in gas/config/tc-arm.c */
10555
10556 #define STUB_NAME ".real_start_of"
10557
10558 fprintf (f, "\t.code\t16\n");
10559 #ifdef ARM_PE
10560 if (arm_dllexport_name_p (name))
10561 name = arm_strip_name_encoding (name);
10562 #endif
10563 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
10564 fprintf (f, "\t.thumb_func\n");
10565 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
10566 }
10567
10568 if (current_function_pretend_args_size)
10569 {
10570 if (cfun->machine->uses_anonymous_args)
10571 {
10572 int num_pushes;
10573
10574 fprintf (f, "\tpush\t{");
10575
10576 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
10577
10578 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
10579 regno <= LAST_ARG_REGNUM;
10580 regno++)
10581 asm_fprintf (f, "%r%s", regno,
10582 regno == LAST_ARG_REGNUM ? "" : ", ");
10583
10584 fprintf (f, "}\n");
10585 }
10586 else
10587 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
10588 SP_REGNUM, SP_REGNUM,
10589 current_function_pretend_args_size);
10590 }
10591
10592 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10593 if (THUMB_REG_PUSHED_P (regno))
10594 live_regs_mask |= 1 << regno;
10595
10596 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
10597 live_regs_mask |= 1 << LR_REGNUM;
10598
10599 if (TARGET_BACKTRACE)
10600 {
10601 int offset;
10602 int work_register = 0;
10603 int wr;
10604
10605 /* We have been asked to create a stack backtrace structure.
10606 The code looks like this:
10607
10608 0 .align 2
10609 0 func:
10610 0 sub SP, #16 Reserve space for 4 registers.
10611 2 push {R7} Get a work register.
10612 4 add R7, SP, #20 Get the stack pointer before the push.
10613 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10614 8 mov R7, PC Get hold of the start of this code plus 12.
10615 10 str R7, [SP, #16] Store it.
10616 12 mov R7, FP Get hold of the current frame pointer.
10617 14 str R7, [SP, #4] Store it.
10618 16 mov R7, LR Get hold of the current return address.
10619 18 str R7, [SP, #12] Store it.
10620 20 add R7, SP, #16 Point at the start of the backtrace structure.
10621 22 mov FP, R7 Put this value into the frame pointer. */
10622
10623 if ((live_regs_mask & 0xFF) == 0)
10624 {
10625 /* See if the a4 register is free. */
10626
10627 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
10628 work_register = LAST_ARG_REGNUM;
10629 else /* We must push a register of our own */
10630 live_regs_mask |= (1 << LAST_LO_REGNUM);
10631 }
10632
10633 if (work_register == 0)
10634 {
10635 /* Select a register from the list that will be pushed to
10636 use as our work register. */
10637 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
10638 if ((1 << work_register) & live_regs_mask)
10639 break;
10640 }
10641
10642 asm_fprintf
10643 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10644 SP_REGNUM, SP_REGNUM);
10645
10646 if (live_regs_mask)
10647 thumb_pushpop (f, live_regs_mask, 1);
10648
10649 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
10650 if (wr & live_regs_mask)
10651 offset += 4;
10652
10653 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10654 offset + 16 + current_function_pretend_args_size);
10655
10656 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10657 offset + 4);
10658
10659 /* Make sure that the instruction fetching the PC is in the right place
10660 to calculate "start of backtrace creation code + 12". */
10661 if (live_regs_mask)
10662 {
10663 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10664 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10665 offset + 12);
10666 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10667 ARM_HARD_FRAME_POINTER_REGNUM);
10668 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10669 offset);
10670 }
10671 else
10672 {
10673 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10674 ARM_HARD_FRAME_POINTER_REGNUM);
10675 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10676 offset);
10677 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10678 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10679 offset + 12);
10680 }
10681
10682 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
10683 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10684 offset + 8);
10685 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10686 offset + 12);
10687 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10688 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
10689 }
10690 else if (live_regs_mask)
10691 thumb_pushpop (f, live_regs_mask, 1);
10692
10693 for (regno = 8; regno < 13; regno++)
10694 if (THUMB_REG_PUSHED_P (regno))
10695 high_regs_pushed++;
10696
10697 if (high_regs_pushed)
10698 {
10699 int pushable_regs = 0;
10700 int mask = live_regs_mask & 0xff;
10701 int next_hi_reg;
10702
10703 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
10704 if (THUMB_REG_PUSHED_P (next_hi_reg))
10705 break;
10706
10707 pushable_regs = mask;
10708
10709 if (pushable_regs == 0)
10710 {
10711 /* Desperation time -- this probably will never happen. */
10712 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
10713 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
10714 mask = 1 << LAST_ARG_REGNUM;
10715 }
10716
10717 while (high_regs_pushed > 0)
10718 {
10719 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
10720 {
10721 if (mask & (1 << regno))
10722 {
10723 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
10724
10725 high_regs_pushed--;
10726
10727 if (high_regs_pushed)
10728 {
10729 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
10730 next_hi_reg--)
10731 if (THUMB_REG_PUSHED_P (next_hi_reg))
10732 break;
10733 }
10734 else
10735 {
10736 mask &= ~((1 << regno) - 1);
10737 break;
10738 }
10739 }
10740 }
10741
10742 thumb_pushpop (f, mask, 1);
10743 }
10744
10745 if (pushable_regs == 0
10746 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
10747 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
10748 }
10749 }
10750
10751 /* Handle the case of a double word load into a low register from
10752 a computed memory address. The computed address may involve a
10753 register which is overwritten by the load. */
10754
10755 const char *
thumb_load_double_from_address(operands)10756 thumb_load_double_from_address (operands)
10757 rtx *operands;
10758 {
10759 rtx addr;
10760 rtx base;
10761 rtx offset;
10762 rtx arg1;
10763 rtx arg2;
10764
10765 if (GET_CODE (operands[0]) != REG)
10766 abort ();
10767
10768 if (GET_CODE (operands[1]) != MEM)
10769 abort ();
10770
10771 /* Get the memory address. */
10772 addr = XEXP (operands[1], 0);
10773
10774 /* Work out how the memory address is computed. */
10775 switch (GET_CODE (addr))
10776 {
10777 case REG:
10778 operands[2] = gen_rtx (MEM, SImode,
10779 plus_constant (XEXP (operands[1], 0), 4));
10780
10781 if (REGNO (operands[0]) == REGNO (addr))
10782 {
10783 output_asm_insn ("ldr\t%H0, %2", operands);
10784 output_asm_insn ("ldr\t%0, %1", operands);
10785 }
10786 else
10787 {
10788 output_asm_insn ("ldr\t%0, %1", operands);
10789 output_asm_insn ("ldr\t%H0, %2", operands);
10790 }
10791 break;
10792
10793 case CONST:
10794 /* Compute <address> + 4 for the high order load. */
10795 operands[2] = gen_rtx (MEM, SImode,
10796 plus_constant (XEXP (operands[1], 0), 4));
10797
10798 output_asm_insn ("ldr\t%0, %1", operands);
10799 output_asm_insn ("ldr\t%H0, %2", operands);
10800 break;
10801
10802 case PLUS:
10803 arg1 = XEXP (addr, 0);
10804 arg2 = XEXP (addr, 1);
10805
10806 if (CONSTANT_P (arg1))
10807 base = arg2, offset = arg1;
10808 else
10809 base = arg1, offset = arg2;
10810
10811 if (GET_CODE (base) != REG)
10812 abort ();
10813
10814 /* Catch the case of <address> = <reg> + <reg> */
10815 if (GET_CODE (offset) == REG)
10816 {
10817 int reg_offset = REGNO (offset);
10818 int reg_base = REGNO (base);
10819 int reg_dest = REGNO (operands[0]);
10820
10821 /* Add the base and offset registers together into the
10822 higher destination register. */
10823 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
10824 reg_dest + 1, reg_base, reg_offset);
10825
10826 /* Load the lower destination register from the address in
10827 the higher destination register. */
10828 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
10829 reg_dest, reg_dest + 1);
10830
10831 /* Load the higher destination register from its own address
10832 plus 4. */
10833 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
10834 reg_dest + 1, reg_dest + 1);
10835 }
10836 else
10837 {
10838 /* Compute <address> + 4 for the high order load. */
10839 operands[2] = gen_rtx (MEM, SImode,
10840 plus_constant (XEXP (operands[1], 0), 4));
10841
10842 /* If the computed address is held in the low order register
10843 then load the high order register first, otherwise always
10844 load the low order register first. */
10845 if (REGNO (operands[0]) == REGNO (base))
10846 {
10847 output_asm_insn ("ldr\t%H0, %2", operands);
10848 output_asm_insn ("ldr\t%0, %1", operands);
10849 }
10850 else
10851 {
10852 output_asm_insn ("ldr\t%0, %1", operands);
10853 output_asm_insn ("ldr\t%H0, %2", operands);
10854 }
10855 }
10856 break;
10857
10858 case LABEL_REF:
10859 /* With no registers to worry about we can just load the value
10860 directly. */
10861 operands[2] = gen_rtx (MEM, SImode,
10862 plus_constant (XEXP (operands[1], 0), 4));
10863
10864 output_asm_insn ("ldr\t%H0, %2", operands);
10865 output_asm_insn ("ldr\t%0, %1", operands);
10866 break;
10867
10868 default:
10869 abort ();
10870 break;
10871 }
10872
10873 return "";
10874 }
10875
10876
10877 const char *
thumb_output_move_mem_multiple(n,operands)10878 thumb_output_move_mem_multiple (n, operands)
10879 int n;
10880 rtx * operands;
10881 {
10882 rtx tmp;
10883
10884 switch (n)
10885 {
10886 case 2:
10887 if (REGNO (operands[4]) > REGNO (operands[5]))
10888 {
10889 tmp = operands[4];
10890 operands[4] = operands[5];
10891 operands[5] = tmp;
10892 }
10893 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
10894 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
10895 break;
10896
10897 case 3:
10898 if (REGNO (operands[4]) > REGNO (operands[5]))
10899 {
10900 tmp = operands[4];
10901 operands[4] = operands[5];
10902 operands[5] = tmp;
10903 }
10904 if (REGNO (operands[5]) > REGNO (operands[6]))
10905 {
10906 tmp = operands[5];
10907 operands[5] = operands[6];
10908 operands[6] = tmp;
10909 }
10910 if (REGNO (operands[4]) > REGNO (operands[5]))
10911 {
10912 tmp = operands[4];
10913 operands[4] = operands[5];
10914 operands[5] = tmp;
10915 }
10916
10917 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
10918 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
10919 break;
10920
10921 default:
10922 abort ();
10923 }
10924
10925 return "";
10926 }
10927
10928 /* Routines for generating rtl. */
10929
10930 void
thumb_expand_movstrqi(operands)10931 thumb_expand_movstrqi (operands)
10932 rtx * operands;
10933 {
10934 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
10935 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
10936 HOST_WIDE_INT len = INTVAL (operands[2]);
10937 HOST_WIDE_INT offset = 0;
10938
10939 while (len >= 12)
10940 {
10941 emit_insn (gen_movmem12b (out, in, out, in));
10942 len -= 12;
10943 }
10944
10945 if (len >= 8)
10946 {
10947 emit_insn (gen_movmem8b (out, in, out, in));
10948 len -= 8;
10949 }
10950
10951 if (len >= 4)
10952 {
10953 rtx reg = gen_reg_rtx (SImode);
10954 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
10955 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
10956 len -= 4;
10957 offset += 4;
10958 }
10959
10960 if (len >= 2)
10961 {
10962 rtx reg = gen_reg_rtx (HImode);
10963 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
10964 plus_constant (in, offset))));
10965 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
10966 reg));
10967 len -= 2;
10968 offset += 2;
10969 }
10970
10971 if (len)
10972 {
10973 rtx reg = gen_reg_rtx (QImode);
10974 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
10975 plus_constant (in, offset))));
10976 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
10977 reg));
10978 }
10979 }
10980
10981 int
thumb_cmp_operand(op,mode)10982 thumb_cmp_operand (op, mode)
10983 rtx op;
10984 enum machine_mode mode;
10985 {
10986 return ((GET_CODE (op) == CONST_INT
10987 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
10988 || register_operand (op, mode));
10989 }
10990
10991 static const char *
thumb_condition_code(x,invert)10992 thumb_condition_code (x, invert)
10993 rtx x;
10994 int invert;
10995 {
10996 static const char * const conds[] =
10997 {
10998 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10999 "hi", "ls", "ge", "lt", "gt", "le"
11000 };
11001 int val;
11002
11003 switch (GET_CODE (x))
11004 {
11005 case EQ: val = 0; break;
11006 case NE: val = 1; break;
11007 case GEU: val = 2; break;
11008 case LTU: val = 3; break;
11009 case GTU: val = 8; break;
11010 case LEU: val = 9; break;
11011 case GE: val = 10; break;
11012 case LT: val = 11; break;
11013 case GT: val = 12; break;
11014 case LE: val = 13; break;
11015 default:
11016 abort ();
11017 }
11018
11019 return conds[val ^ invert];
11020 }
11021
11022 /* Handle storing a half-word to memory during reload. */
11023
11024 void
thumb_reload_out_hi(operands)11025 thumb_reload_out_hi (operands)
11026 rtx * operands;
11027 {
11028 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
11029 }
11030
11031 /* Handle storing a half-word to memory during reload. */
11032
11033 void
thumb_reload_in_hi(operands)11034 thumb_reload_in_hi (operands)
11035 rtx * operands ATTRIBUTE_UNUSED;
11036 {
11037 abort ();
11038 }
11039
11040 /* Return the length of a function name prefix
11041 that starts with the character 'c'. */
11042
11043 static int
arm_get_strip_length(c)11044 arm_get_strip_length (c)
11045 int c;
11046 {
11047 switch (c)
11048 {
11049 ARM_NAME_ENCODING_LENGTHS
11050 default: return 0;
11051 }
11052 }
11053
11054 /* Return a pointer to a function's name with any
11055 and all prefix encodings stripped from it. */
11056
11057 const char *
arm_strip_name_encoding(name)11058 arm_strip_name_encoding (name)
11059 const char * name;
11060 {
11061 int skip;
11062
11063 while ((skip = arm_get_strip_length (* name)))
11064 name += skip;
11065
11066 return name;
11067 }
11068
11069 /* If there is a '*' anywhere in the name's prefix, then
11070 emit the stripped name verbatim, otherwise prepend an
11071 underscore if leading underscores are being used. */
11072
11073 void
arm_asm_output_labelref(stream,name)11074 arm_asm_output_labelref (stream, name)
11075 FILE * stream;
11076 const char * name;
11077 {
11078 int skip;
11079 int verbatim = 0;
11080
11081 while ((skip = arm_get_strip_length (* name)))
11082 {
11083 verbatim |= (*name == '*');
11084 name += skip;
11085 }
11086
11087 if (verbatim)
11088 fputs (name, stream);
11089 else
11090 asm_fprintf (stream, "%U%s", name);
11091 }
11092
11093 rtx aof_pic_label;
11094
11095 #ifdef AOF_ASSEMBLER
11096 /* Special functions only needed when producing AOF syntax assembler. */
11097
11098 struct pic_chain
11099 {
11100 struct pic_chain * next;
11101 const char * symname;
11102 };
11103
11104 static struct pic_chain * aof_pic_chain = NULL;
11105
11106 rtx
aof_pic_entry(x)11107 aof_pic_entry (x)
11108 rtx x;
11109 {
11110 struct pic_chain ** chainp;
11111 int offset;
11112
11113 if (aof_pic_label == NULL_RTX)
11114 {
11115 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
11116 }
11117
11118 for (offset = 0, chainp = &aof_pic_chain; *chainp;
11119 offset += 4, chainp = &(*chainp)->next)
11120 if ((*chainp)->symname == XSTR (x, 0))
11121 return plus_constant (aof_pic_label, offset);
11122
11123 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
11124 (*chainp)->next = NULL;
11125 (*chainp)->symname = XSTR (x, 0);
11126 return plus_constant (aof_pic_label, offset);
11127 }
11128
11129 void
aof_dump_pic_table(f)11130 aof_dump_pic_table (f)
11131 FILE * f;
11132 {
11133 struct pic_chain * chain;
11134
11135 if (aof_pic_chain == NULL)
11136 return;
11137
11138 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
11139 PIC_OFFSET_TABLE_REGNUM,
11140 PIC_OFFSET_TABLE_REGNUM);
11141 fputs ("|x$adcons|\n", f);
11142
11143 for (chain = aof_pic_chain; chain; chain = chain->next)
11144 {
11145 fputs ("\tDCD\t", f);
11146 assemble_name (f, chain->symname);
11147 fputs ("\n", f);
11148 }
11149 }
11150
11151 int arm_text_section_count = 1;
11152
11153 char *
aof_text_section()11154 aof_text_section ()
11155 {
11156 static char buf[100];
11157 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
11158 arm_text_section_count++);
11159 if (flag_pic)
11160 strcat (buf, ", PIC, REENTRANT");
11161 return buf;
11162 }
11163
11164 static int arm_data_section_count = 1;
11165
11166 char *
aof_data_section()11167 aof_data_section ()
11168 {
11169 static char buf[100];
11170 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
11171 return buf;
11172 }
11173
11174 /* The AOF assembler is religiously strict about declarations of
11175 imported and exported symbols, so that it is impossible to declare
11176 a function as imported near the beginning of the file, and then to
11177 export it later on. It is, however, possible to delay the decision
11178 until all the functions in the file have been compiled. To get
11179 around this, we maintain a list of the imports and exports, and
11180 delete from it any that are subsequently defined. At the end of
11181 compilation we spit the remainder of the list out before the END
11182 directive. */
11183
11184 struct import
11185 {
11186 struct import * next;
11187 const char * name;
11188 };
11189
11190 static struct import * imports_list = NULL;
11191
11192 void
aof_add_import(name)11193 aof_add_import (name)
11194 const char * name;
11195 {
11196 struct import * new;
11197
11198 for (new = imports_list; new; new = new->next)
11199 if (new->name == name)
11200 return;
11201
11202 new = (struct import *) xmalloc (sizeof (struct import));
11203 new->next = imports_list;
11204 imports_list = new;
11205 new->name = name;
11206 }
11207
11208 void
aof_delete_import(name)11209 aof_delete_import (name)
11210 const char * name;
11211 {
11212 struct import ** old;
11213
11214 for (old = &imports_list; *old; old = & (*old)->next)
11215 {
11216 if ((*old)->name == name)
11217 {
11218 *old = (*old)->next;
11219 return;
11220 }
11221 }
11222 }
11223
11224 int arm_main_function = 0;
11225
11226 void
aof_dump_imports(f)11227 aof_dump_imports (f)
11228 FILE * f;
11229 {
11230 /* The AOF assembler needs this to cause the startup code to be extracted
11231 from the library. Brining in __main causes the whole thing to work
11232 automagically. */
11233 if (arm_main_function)
11234 {
11235 text_section ();
11236 fputs ("\tIMPORT __main\n", f);
11237 fputs ("\tDCD __main\n", f);
11238 }
11239
11240 /* Now dump the remaining imports. */
11241 while (imports_list)
11242 {
11243 fprintf (f, "\tIMPORT\t");
11244 assemble_name (f, imports_list->name);
11245 fputc ('\n', f);
11246 imports_list = imports_list->next;
11247 }
11248 }
11249
11250 static void
aof_globalize_label(stream,name)11251 aof_globalize_label (stream, name)
11252 FILE *stream;
11253 const char *name;
11254 {
11255 default_globalize_label (stream, name);
11256 if (! strcmp (name, "main"))
11257 arm_main_function = 1;
11258 }
11259 #endif /* AOF_ASSEMBLER */
11260
11261 #ifdef OBJECT_FORMAT_ELF
11262 /* Switch to an arbitrary section NAME with attributes as specified
11263 by FLAGS. ALIGN specifies any known alignment requirements for
11264 the section; 0 if the default should be used.
11265
11266 Differs from the default elf version only in the prefix character
11267 used before the section type. */
11268
11269 static void
arm_elf_asm_named_section(name,flags)11270 arm_elf_asm_named_section (name, flags)
11271 const char *name;
11272 unsigned int flags;
11273 {
11274 char flagchars[10], *f = flagchars;
11275
11276 if (! named_section_first_declaration (name))
11277 {
11278 fprintf (asm_out_file, "\t.section\t%s\n", name);
11279 return;
11280 }
11281
11282 if (!(flags & SECTION_DEBUG))
11283 *f++ = 'a';
11284 if (flags & SECTION_WRITE)
11285 *f++ = 'w';
11286 if (flags & SECTION_CODE)
11287 *f++ = 'x';
11288 if (flags & SECTION_SMALL)
11289 *f++ = 's';
11290 if (flags & SECTION_MERGE)
11291 *f++ = 'M';
11292 if (flags & SECTION_STRINGS)
11293 *f++ = 'S';
11294 if (flags & SECTION_TLS)
11295 *f++ = 'T';
11296 *f = '\0';
11297
11298 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
11299
11300 if (!(flags & SECTION_NOTYPE))
11301 {
11302 const char *type;
11303
11304 if (flags & SECTION_BSS)
11305 type = "nobits";
11306 else
11307 type = "progbits";
11308
11309 fprintf (asm_out_file, ",%%%s", type);
11310
11311 if (flags & SECTION_ENTSIZE)
11312 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
11313 }
11314
11315 putc ('\n', asm_out_file);
11316 }
11317 #endif
11318
11319 #ifndef ARM_PE
11320 /* Symbols in the text segment can be accessed without indirecting via the
11321 constant pool; it may take an extra binary operation, but this is still
11322 faster than indirecting via memory. Don't do this when not optimizing,
11323 since we won't be calculating al of the offsets necessary to do this
11324 simplification. */
11325
11326 static void
arm_encode_section_info(decl,first)11327 arm_encode_section_info (decl, first)
11328 tree decl;
11329 int first;
11330 {
11331 /* This doesn't work with AOF syntax, since the string table may be in
11332 a different AREA. */
11333 #ifndef AOF_ASSEMBLER
11334 if (optimize > 0 && TREE_CONSTANT (decl)
11335 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
11336 {
11337 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
11338 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
11339 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
11340 }
11341 #endif
11342
11343 /* If we are referencing a function that is weak then encode a long call
11344 flag in the function name, otherwise if the function is static or
11345 or known to be defined in this file then encode a short call flag. */
11346 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
11347 {
11348 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
11349 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
11350 else if (! TREE_PUBLIC (decl))
11351 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
11352 }
11353 }
11354 #endif /* !ARM_PE */
11355
11356 /* Output code to add DELTA to the first argument, and then jump
11357 to FUNCTION. Used for C++ multiple inheritance. */
11358
11359 static void
arm_output_mi_thunk(file,thunk,delta,vcall_offset,function)11360 arm_output_mi_thunk (file, thunk, delta, vcall_offset, function)
11361 FILE *file;
11362 tree thunk ATTRIBUTE_UNUSED;
11363 HOST_WIDE_INT delta;
11364 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
11365 tree function;
11366 {
11367 int mi_delta = delta;
11368 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
11369 int shift = 0;
11370 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))
11371 ? 1 : 0);
11372 if (mi_delta < 0)
11373 mi_delta = - mi_delta;
11374 while (mi_delta != 0)
11375 {
11376 if ((mi_delta & (3 << shift)) == 0)
11377 shift += 2;
11378 else
11379 {
11380 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
11381 mi_op, this_regno, this_regno,
11382 mi_delta & (0xff << shift));
11383 mi_delta &= ~(0xff << shift);
11384 shift += 8;
11385 }
11386 }
11387 fputs ("\tb\t", file);
11388 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
11389 if (NEED_PLT_RELOC)
11390 fputs ("(PLT)", file);
11391 fputc ('\n', file);
11392 }
11393
11394