1 /***************************************************************************
2 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
3 * Frank Dols <frank.dols@synopsys.com> *
4 * Mischa Jonker <mischa.jonker@synopsys.com> *
5 * Anton Kolesov <anton.kolesov@synopsys.com> *
6 * Evgeniy Didin <didin@synopsys.com> *
7 * *
8 * SPDX-License-Identifier: GPL-2.0-or-later *
9 ***************************************************************************/
10
11 #ifndef OPENOCD_TARGET_ARC_H
12 #define OPENOCD_TARGET_ARC_H
13
14 #include <helper/time_support.h>
15 #include <jtag/jtag.h>
16
17 #include "algorithm.h"
18 #include "breakpoints.h"
19 #include "jtag/interface.h"
20 #include "register.h"
21 #include "target.h"
22 #include "target_request.h"
23 #include "target_type.h"
24 #include "helper/bits.h"
25
26 #include "arc_jtag.h"
27 #include "arc_cmd.h"
28 #include "arc_mem.h"
29
30 #define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */
31
32 #define AUX_DEBUG_REG 0x5
33 #define AUX_PC_REG 0x6
34 #define AUX_STATUS32_REG 0xA
35
36
37 #define SET_CORE_FORCE_HALT BIT(1)
38 #define SET_CORE_HALT_BIT BIT(0) /* STATUS32[0] = H field */
39 #define SET_CORE_ENABLE_INTERRUPTS BIT(31)
40 /* STATUS32[5] or AE bit indicates if the processor is in exception state */
41 #define SET_CORE_AE_BIT BIT(5)
42 /* Single instruction step bit in Debug register */
43 #define SET_CORE_SINGLE_INSTR_STEP BIT(11)
44
45 #define AUX_STATUS32_REG_HALT_BIT BIT(0)
46 #define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */
47
48 /* Reserved core registers */
49 #define CORE_R61_NUM (61)
50 #define CORE_R62_NUM (62)
51
52 #define CORE_REG_MAX_NUMBER (63)
53
54 /* Limit reg_type/reg_type_field name to 20 symbols */
55 #define REG_TYPE_MAX_NAME_LENGTH 20
56
57 /* ARC 32bits opcodes */
58 #define ARC_SDBBP_32 0x256F003FU /* BRK */
59
60 /* ARC 16bits opcodes */
61 #define ARC_SDBBP_16 0x7FFF /* BRK_S */
62
63 /* Cache registers */
64 #define AUX_IC_IVIC_REG 0X10
65 #define IC_IVIC_INVALIDATE 0XFFFFFFFF
66
67 #define AUX_DC_IVDC_REG 0X47
68 #define DC_IVDC_INVALIDATE BIT(0)
69 #define AUX_DC_CTRL_REG 0X48
70 #define DC_CTRL_IM BIT(6)
71
72 /* L2 cache registers */
73 #define SLC_AUX_CACHE_CTRL 0x903
74 #define L2_CTRL_IM BIT(6)
75 #define L2_CTRL_BS BIT(8) /* Busy flag */
76 #define SLC_AUX_CACHE_FLUSH 0x904
77 #define L2_FLUSH_FL BIT(0)
78 #define SLC_AUX_CACHE_INV 0x905
79 #define L2_INV_IV BIT(0)
80
81 /* Action Point */
82 #define AP_AC_AT_INST_ADDR 0x0
83 #define AP_AC_AT_MEMORY_ADDR 0x2
84 #define AP_AC_AT_AUXREG_ADDR 0x4
85
86 #define AP_AC_TT_DISABLE 0x00
87 #define AP_AC_TT_WRITE 0x10
88 #define AP_AC_TT_READ 0x20
89 #define AP_AC_TT_READWRITE 0x30
90
91 struct arc_reg_bitfield {
92 struct reg_data_type_bitfield bitfield;
93 char name[REG_TYPE_MAX_NAME_LENGTH];
94 };
95 /* Register data type */
96 struct arc_reg_data_type {
97 struct list_head list;
98 struct reg_data_type data_type;
99 struct reg_data_type_flags data_type_flags;
100 struct reg_data_type_struct data_type_struct;
101 char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
102 struct arc_reg_bitfield *bitfields;
103 union {
104 struct reg_data_type_struct_field *reg_type_struct_field;
105 struct reg_data_type_flags_field *reg_type_flags_field;
106 };
107 };
108
109 /* Standard GDB register types */
110 static const struct reg_data_type standard_gdb_types[] = {
111 { .type = REG_TYPE_INT, .id = "int" },
112 { .type = REG_TYPE_INT8, .id = "int8" },
113 { .type = REG_TYPE_INT16, .id = "int16" },
114 { .type = REG_TYPE_INT32, .id = "int32" },
115 { .type = REG_TYPE_INT64, .id = "int64" },
116 { .type = REG_TYPE_INT128, .id = "int128" },
117 { .type = REG_TYPE_UINT8, .id = "uint8" },
118 { .type = REG_TYPE_UINT16, .id = "uint16" },
119 { .type = REG_TYPE_UINT32, .id = "uint32" },
120 { .type = REG_TYPE_UINT64, .id = "uint64" },
121 { .type = REG_TYPE_UINT128, .id = "uint128" },
122 { .type = REG_TYPE_CODE_PTR, .id = "code_ptr" },
123 { .type = REG_TYPE_DATA_PTR, .id = "data_ptr" },
124 { .type = REG_TYPE_FLOAT, .id = "float" },
125 { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
126 { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
127 };
128
129 enum arc_actionpointype {
130 ARC_AP_BREAKPOINT,
131 ARC_AP_WATCHPOINT,
132 };
133
134 /* Actionpoint related fields */
135 struct arc_actionpoint {
136 int used;
137 uint32_t bp_value;
138 uint32_t reg_address;
139 enum arc_actionpointype type;
140 };
141
142 struct arc_common {
143 uint32_t common_magic;
144
145 struct arc_jtag jtag_info;
146
147 struct reg_cache *core_and_aux_cache;
148 struct reg_cache *bcr_cache;
149
150 /* Cache control */
151 bool has_dcache;
152 bool has_icache;
153 bool has_l2cache;
154 /* If true, then D$ has been already flushed since core has been
155 * halted. */
156 bool dcache_flushed;
157 /* If true, then L2 has been already flushed since core has been
158 * halted. */
159 bool l2cache_flushed;
160 /* If true, then caches have been already flushed since core has been
161 * halted. */
162 bool icache_invalidated;
163 bool dcache_invalidated;
164 bool l2cache_invalidated;
165
166 /* Indicate if cach was built (for deinit function) */
167 bool core_aux_cache_built;
168 bool bcr_cache_built;
169 /* Closely Coupled memory(CCM) regions for performance-critical
170 * code (optional). */
171 uint32_t iccm0_start;
172 uint32_t iccm0_end;
173 uint32_t iccm1_start;
174 uint32_t iccm1_end;
175 uint32_t dccm_start;
176 uint32_t dccm_end;
177
178 int irq_state;
179
180 /* Register descriptions */
181 struct list_head reg_data_types;
182 struct list_head core_reg_descriptions;
183 struct list_head aux_reg_descriptions;
184 struct list_head bcr_reg_descriptions;
185 unsigned long num_regs;
186 unsigned long num_core_regs;
187 unsigned long num_aux_regs;
188 unsigned long num_bcr_regs;
189 unsigned long last_general_reg;
190
191 /* PC register location in register cache. */
192 unsigned long pc_index_in_cache;
193 /* DEBUG register location in register cache. */
194 unsigned long debug_index_in_cache;
195
196 /* Actionpoints */
197 unsigned int actionpoints_num;
198 unsigned int actionpoints_num_avail;
199 struct arc_actionpoint *actionpoints_list;
200 };
201
202 /* Borrowed from nds32.h */
203 #define CHECK_RETVAL(action) \
204 do { \
205 int __retval = (action); \
206 if (__retval != ERROR_OK) { \
207 LOG_DEBUG("error while calling \"%s\"", \
208 # action); \
209 return __retval; \
210 } \
211 } while (0)
212
213 #define JIM_CHECK_RETVAL(action) \
214 do { \
215 int __retval = (action); \
216 if (__retval != JIM_OK) { \
217 LOG_DEBUG("error while calling \"%s\"", \
218 # action); \
219 return __retval; \
220 } \
221 } while (0)
222
target_to_arc(struct target * target)223 static inline struct arc_common *target_to_arc(struct target *target)
224 {
225 return target->arch_info;
226 }
227
228 /* ----- Inlined functions ------------------------------------------------- */
229
230 /**
231 * Convert data in host endianness to the middle endian. This is required to
232 * write 4-byte instructions.
233 */
arc_h_u32_to_me(uint8_t * buf,int val)234 static inline void arc_h_u32_to_me(uint8_t *buf, int val)
235 {
236 buf[1] = (uint8_t) (val >> 24);
237 buf[0] = (uint8_t) (val >> 16);
238 buf[3] = (uint8_t) (val >> 8);
239 buf[2] = (uint8_t) (val >> 0);
240 }
241
242 /**
243 * Convert data in middle endian to host endian. This is required to read 32-bit
244 * instruction from little endian ARCs.
245 */
arc_me_to_h_u32(const uint8_t * buf)246 static inline uint32_t arc_me_to_h_u32(const uint8_t *buf)
247 {
248 return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24);
249 }
250
251
252 /* ARC Register description */
253 struct arc_reg_desc {
254
255 struct target *target;
256
257 /* Register name */
258 char *name;
259
260 /* Actual place of storing reg_value */
261 uint8_t reg_value[4];
262
263 /* Actual place of storing register feature */
264 struct reg_feature feature;
265
266 /* GDB XML feature */
267 char *gdb_xml_feature;
268
269 /* Is this a register in g/G-packet? */
270 bool is_general;
271
272 /* Architectural number: core reg num or AUX reg num */
273 uint32_t arch_num;
274
275 /* Core or AUX register? */
276 bool is_core;
277
278 /* Build configuration register? */
279 bool is_bcr;
280
281 /* Data type */
282 struct reg_data_type *data_type;
283
284 struct list_head list;
285 };
286
287 /* Error codes */
288 #define ERROR_ARC_REGISTER_NOT_FOUND (-700)
289 #define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
290 #define ERROR_ARC_REGISTER_IS_NOT_STRUCT (-702)
291 #define ERROR_ARC_FIELD_IS_NOT_BITFIELD (-703)
292 #define ERROR_ARC_REGTYPE_NOT_FOUND (-704)
293
294 void free_reg_desc(struct arc_reg_desc *r);
295
296
297 void arc_reg_data_type_add(struct target *target,
298 struct arc_reg_data_type *data_type);
299
300 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
301 const char * const type_name, const size_t type_name_len);
302
303 struct reg *arc_reg_get_by_name(struct reg_cache *first,
304 const char *name, bool search_all);
305
306 int arc_reg_get_field(struct target *target, const char *reg_name,
307 const char *field_name, uint32_t *value_ptr);
308
309 int arc_cache_flush(struct target *target);
310 int arc_cache_invalidate(struct target *target);
311
312 int arc_add_auxreg_actionpoint(struct target *target,
313 uint32_t auxreg_addr, uint32_t transaction);
314 int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr);
315 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num);
316
317 #endif /* OPENOCD_TARGET_ARC_H */
318