1 /*
2 * QEMU ARM TCG-only CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
14 #include "internals.h"
15 #include "target/arm/idau.h"
16 #if !defined(CONFIG_USER_ONLY)
17 #include "hw/boards.h"
18 #endif
19 #include "cpregs.h"
20
21
22 /* Share AArch32 -cpu max features with AArch64. */
aa32_max_features(ARMCPU * cpu)23 void aa32_max_features(ARMCPU *cpu)
24 {
25 uint32_t t;
26
27 /* Add additional features supported by QEMU */
28 t = cpu->isar.id_isar5;
29 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
30 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
31 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
32 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
33 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
34 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
35 cpu->isar.id_isar5 = t;
36
37 t = cpu->isar.id_isar6;
38 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
39 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
40 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
41 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
42 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
43 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
44 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
45 cpu->isar.id_isar6 = t;
46
47 t = cpu->isar.mvfr1;
48 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
49 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
50 cpu->isar.mvfr1 = t;
51
52 t = cpu->isar.mvfr2;
53 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
54 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
55 cpu->isar.mvfr2 = t;
56
57 t = cpu->isar.id_mmfr3;
58 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
59 cpu->isar.id_mmfr3 = t;
60
61 t = cpu->isar.id_mmfr4;
62 t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
63 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
64 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
65 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
66 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
67 cpu->isar.id_mmfr4 = t;
68
69 t = cpu->isar.id_mmfr5;
70 t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
71 cpu->isar.id_mmfr5 = t;
72
73 t = cpu->isar.id_pfr0;
74 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
75 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
76 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
77 cpu->isar.id_pfr0 = t;
78
79 t = cpu->isar.id_pfr2;
80 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
81 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
82 cpu->isar.id_pfr2 = t;
83
84 t = cpu->isar.id_dfr0;
85 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
86 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
87 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
88 cpu->isar.id_dfr0 = t;
89
90 t = cpu->isar.id_dfr1;
91 t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
92 cpu->isar.id_dfr1 = t;
93 }
94
95 /* CPU models. These are not needed for the AArch64 linux-user build. */
96 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
97
arm926_initfn(Object * obj)98 static void arm926_initfn(Object *obj)
99 {
100 ARMCPU *cpu = ARM_CPU(obj);
101
102 cpu->dtb_compatible = "arm,arm926";
103 set_feature(&cpu->env, ARM_FEATURE_V5);
104 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
106 cpu->midr = 0x41069265;
107 cpu->reset_fpsid = 0x41011090;
108 cpu->ctr = 0x1dd20d2;
109 cpu->reset_sctlr = 0x00090078;
110
111 /*
112 * ARMv5 does not have the ID_ISAR registers, but we can still
113 * set the field to indicate Jazelle support within QEMU.
114 */
115 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
116 /*
117 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
118 * support even though ARMv5 doesn't have this register.
119 */
120 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
121 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
122 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
123 }
124
arm946_initfn(Object * obj)125 static void arm946_initfn(Object *obj)
126 {
127 ARMCPU *cpu = ARM_CPU(obj);
128
129 cpu->dtb_compatible = "arm,arm946";
130 set_feature(&cpu->env, ARM_FEATURE_V5);
131 set_feature(&cpu->env, ARM_FEATURE_PMSA);
132 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
133 cpu->midr = 0x41059461;
134 cpu->ctr = 0x0f004006;
135 cpu->reset_sctlr = 0x00000078;
136 }
137
arm1026_initfn(Object * obj)138 static void arm1026_initfn(Object *obj)
139 {
140 ARMCPU *cpu = ARM_CPU(obj);
141
142 cpu->dtb_compatible = "arm,arm1026";
143 set_feature(&cpu->env, ARM_FEATURE_V5);
144 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
145 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
146 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
147 cpu->midr = 0x4106a262;
148 cpu->reset_fpsid = 0x410110a0;
149 cpu->ctr = 0x1dd20d2;
150 cpu->reset_sctlr = 0x00090078;
151 cpu->reset_auxcr = 1;
152
153 /*
154 * ARMv5 does not have the ID_ISAR registers, but we can still
155 * set the field to indicate Jazelle support within QEMU.
156 */
157 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
158 /*
159 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
160 * support even though ARMv5 doesn't have this register.
161 */
162 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
163 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
164 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
165
166 {
167 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
168 ARMCPRegInfo ifar = {
169 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
170 .access = PL1_RW,
171 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
172 .resetvalue = 0
173 };
174 define_one_arm_cp_reg(cpu, &ifar);
175 }
176 }
177
arm1136_r2_initfn(Object * obj)178 static void arm1136_r2_initfn(Object *obj)
179 {
180 ARMCPU *cpu = ARM_CPU(obj);
181 /*
182 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
183 * older core than plain "arm1136". In particular this does not
184 * have the v6K features.
185 * These ID register values are correct for 1136 but may be wrong
186 * for 1136_r2 (in particular r0p2 does not actually implement most
187 * of the ID registers).
188 */
189
190 cpu->dtb_compatible = "arm,arm1136";
191 set_feature(&cpu->env, ARM_FEATURE_V6);
192 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
193 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
194 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
195 cpu->midr = 0x4107b362;
196 cpu->reset_fpsid = 0x410120b4;
197 cpu->isar.mvfr0 = 0x11111111;
198 cpu->isar.mvfr1 = 0x00000000;
199 cpu->ctr = 0x1dd20d2;
200 cpu->reset_sctlr = 0x00050078;
201 cpu->isar.id_pfr0 = 0x111;
202 cpu->isar.id_pfr1 = 0x1;
203 cpu->isar.id_dfr0 = 0x2;
204 cpu->id_afr0 = 0x3;
205 cpu->isar.id_mmfr0 = 0x01130003;
206 cpu->isar.id_mmfr1 = 0x10030302;
207 cpu->isar.id_mmfr2 = 0x01222110;
208 cpu->isar.id_isar0 = 0x00140011;
209 cpu->isar.id_isar1 = 0x12002111;
210 cpu->isar.id_isar2 = 0x11231111;
211 cpu->isar.id_isar3 = 0x01102131;
212 cpu->isar.id_isar4 = 0x141;
213 cpu->reset_auxcr = 7;
214 }
215
arm1136_initfn(Object * obj)216 static void arm1136_initfn(Object *obj)
217 {
218 ARMCPU *cpu = ARM_CPU(obj);
219
220 cpu->dtb_compatible = "arm,arm1136";
221 set_feature(&cpu->env, ARM_FEATURE_V6K);
222 set_feature(&cpu->env, ARM_FEATURE_V6);
223 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
224 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
225 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
226 cpu->midr = 0x4117b363;
227 cpu->reset_fpsid = 0x410120b4;
228 cpu->isar.mvfr0 = 0x11111111;
229 cpu->isar.mvfr1 = 0x00000000;
230 cpu->ctr = 0x1dd20d2;
231 cpu->reset_sctlr = 0x00050078;
232 cpu->isar.id_pfr0 = 0x111;
233 cpu->isar.id_pfr1 = 0x1;
234 cpu->isar.id_dfr0 = 0x2;
235 cpu->id_afr0 = 0x3;
236 cpu->isar.id_mmfr0 = 0x01130003;
237 cpu->isar.id_mmfr1 = 0x10030302;
238 cpu->isar.id_mmfr2 = 0x01222110;
239 cpu->isar.id_isar0 = 0x00140011;
240 cpu->isar.id_isar1 = 0x12002111;
241 cpu->isar.id_isar2 = 0x11231111;
242 cpu->isar.id_isar3 = 0x01102131;
243 cpu->isar.id_isar4 = 0x141;
244 cpu->reset_auxcr = 7;
245 }
246
arm1176_initfn(Object * obj)247 static void arm1176_initfn(Object *obj)
248 {
249 ARMCPU *cpu = ARM_CPU(obj);
250
251 cpu->dtb_compatible = "arm,arm1176";
252 set_feature(&cpu->env, ARM_FEATURE_V6K);
253 set_feature(&cpu->env, ARM_FEATURE_VAPA);
254 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
255 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
256 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
257 set_feature(&cpu->env, ARM_FEATURE_EL3);
258 cpu->midr = 0x410fb767;
259 cpu->reset_fpsid = 0x410120b5;
260 cpu->isar.mvfr0 = 0x11111111;
261 cpu->isar.mvfr1 = 0x00000000;
262 cpu->ctr = 0x1dd20d2;
263 cpu->reset_sctlr = 0x00050078;
264 cpu->isar.id_pfr0 = 0x111;
265 cpu->isar.id_pfr1 = 0x11;
266 cpu->isar.id_dfr0 = 0x33;
267 cpu->id_afr0 = 0;
268 cpu->isar.id_mmfr0 = 0x01130003;
269 cpu->isar.id_mmfr1 = 0x10030302;
270 cpu->isar.id_mmfr2 = 0x01222100;
271 cpu->isar.id_isar0 = 0x0140011;
272 cpu->isar.id_isar1 = 0x12002111;
273 cpu->isar.id_isar2 = 0x11231121;
274 cpu->isar.id_isar3 = 0x01102131;
275 cpu->isar.id_isar4 = 0x01141;
276 cpu->reset_auxcr = 7;
277 }
278
arm11mpcore_initfn(Object * obj)279 static void arm11mpcore_initfn(Object *obj)
280 {
281 ARMCPU *cpu = ARM_CPU(obj);
282
283 cpu->dtb_compatible = "arm,arm11mpcore";
284 set_feature(&cpu->env, ARM_FEATURE_V6K);
285 set_feature(&cpu->env, ARM_FEATURE_VAPA);
286 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
287 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
288 cpu->midr = 0x410fb022;
289 cpu->reset_fpsid = 0x410120b4;
290 cpu->isar.mvfr0 = 0x11111111;
291 cpu->isar.mvfr1 = 0x00000000;
292 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
293 cpu->isar.id_pfr0 = 0x111;
294 cpu->isar.id_pfr1 = 0x1;
295 cpu->isar.id_dfr0 = 0;
296 cpu->id_afr0 = 0x2;
297 cpu->isar.id_mmfr0 = 0x01100103;
298 cpu->isar.id_mmfr1 = 0x10020302;
299 cpu->isar.id_mmfr2 = 0x01222000;
300 cpu->isar.id_isar0 = 0x00100011;
301 cpu->isar.id_isar1 = 0x12002111;
302 cpu->isar.id_isar2 = 0x11221011;
303 cpu->isar.id_isar3 = 0x01102131;
304 cpu->isar.id_isar4 = 0x141;
305 cpu->reset_auxcr = 1;
306 }
307
308 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
309 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
310 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
311 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
312 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
313 };
314
cortex_a8_initfn(Object * obj)315 static void cortex_a8_initfn(Object *obj)
316 {
317 ARMCPU *cpu = ARM_CPU(obj);
318
319 cpu->dtb_compatible = "arm,cortex-a8";
320 set_feature(&cpu->env, ARM_FEATURE_V7);
321 set_feature(&cpu->env, ARM_FEATURE_NEON);
322 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
323 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
324 set_feature(&cpu->env, ARM_FEATURE_EL3);
325 set_feature(&cpu->env, ARM_FEATURE_PMU);
326 cpu->midr = 0x410fc080;
327 cpu->reset_fpsid = 0x410330c0;
328 cpu->isar.mvfr0 = 0x11110222;
329 cpu->isar.mvfr1 = 0x00011111;
330 cpu->ctr = 0x82048004;
331 cpu->reset_sctlr = 0x00c50078;
332 cpu->isar.id_pfr0 = 0x1031;
333 cpu->isar.id_pfr1 = 0x11;
334 cpu->isar.id_dfr0 = 0x400;
335 cpu->id_afr0 = 0;
336 cpu->isar.id_mmfr0 = 0x31100003;
337 cpu->isar.id_mmfr1 = 0x20000000;
338 cpu->isar.id_mmfr2 = 0x01202000;
339 cpu->isar.id_mmfr3 = 0x11;
340 cpu->isar.id_isar0 = 0x00101111;
341 cpu->isar.id_isar1 = 0x12112111;
342 cpu->isar.id_isar2 = 0x21232031;
343 cpu->isar.id_isar3 = 0x11112131;
344 cpu->isar.id_isar4 = 0x00111142;
345 cpu->isar.dbgdidr = 0x15141000;
346 cpu->clidr = (1 << 27) | (2 << 24) | 3;
347 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
348 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
349 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
350 cpu->reset_auxcr = 2;
351 cpu->isar.reset_pmcr_el0 = 0x41002000;
352 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
353 }
354
355 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
356 /*
357 * power_control should be set to maximum latency. Again,
358 * default to 0 and set by private hook
359 */
360 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
361 .access = PL1_RW, .resetvalue = 0,
362 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
363 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
364 .access = PL1_RW, .resetvalue = 0,
365 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
366 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
367 .access = PL1_RW, .resetvalue = 0,
368 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
369 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
370 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
371 /* TLB lockdown control */
372 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
373 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
374 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
375 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
376 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
377 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
378 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
379 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
380 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
381 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
382 };
383
cortex_a9_initfn(Object * obj)384 static void cortex_a9_initfn(Object *obj)
385 {
386 ARMCPU *cpu = ARM_CPU(obj);
387
388 cpu->dtb_compatible = "arm,cortex-a9";
389 set_feature(&cpu->env, ARM_FEATURE_V7);
390 set_feature(&cpu->env, ARM_FEATURE_NEON);
391 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
392 set_feature(&cpu->env, ARM_FEATURE_EL3);
393 set_feature(&cpu->env, ARM_FEATURE_PMU);
394 /*
395 * Note that A9 supports the MP extensions even for
396 * A9UP and single-core A9MP (which are both different
397 * and valid configurations; we don't model A9UP).
398 */
399 set_feature(&cpu->env, ARM_FEATURE_V7MP);
400 set_feature(&cpu->env, ARM_FEATURE_CBAR);
401 cpu->midr = 0x410fc090;
402 cpu->reset_fpsid = 0x41033090;
403 cpu->isar.mvfr0 = 0x11110222;
404 cpu->isar.mvfr1 = 0x01111111;
405 cpu->ctr = 0x80038003;
406 cpu->reset_sctlr = 0x00c50078;
407 cpu->isar.id_pfr0 = 0x1031;
408 cpu->isar.id_pfr1 = 0x11;
409 cpu->isar.id_dfr0 = 0x000;
410 cpu->id_afr0 = 0;
411 cpu->isar.id_mmfr0 = 0x00100103;
412 cpu->isar.id_mmfr1 = 0x20000000;
413 cpu->isar.id_mmfr2 = 0x01230000;
414 cpu->isar.id_mmfr3 = 0x00002111;
415 cpu->isar.id_isar0 = 0x00101111;
416 cpu->isar.id_isar1 = 0x13112111;
417 cpu->isar.id_isar2 = 0x21232041;
418 cpu->isar.id_isar3 = 0x11112131;
419 cpu->isar.id_isar4 = 0x00111142;
420 cpu->isar.dbgdidr = 0x35141000;
421 cpu->clidr = (1 << 27) | (1 << 24) | 3;
422 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
423 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
424 cpu->isar.reset_pmcr_el0 = 0x41093000;
425 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
426 }
427
428 #ifndef CONFIG_USER_ONLY
a15_l2ctlr_read(CPUARMState * env,const ARMCPRegInfo * ri)429 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
430 {
431 MachineState *ms = MACHINE(qdev_get_machine());
432
433 /*
434 * Linux wants the number of processors from here.
435 * Might as well set the interrupt-controller bit too.
436 */
437 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
438 }
439 #endif
440
441 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
442 #ifndef CONFIG_USER_ONLY
443 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
444 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
445 .writefn = arm_cp_write_ignore, },
446 #endif
447 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
448 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
449 };
450
cortex_a7_initfn(Object * obj)451 static void cortex_a7_initfn(Object *obj)
452 {
453 ARMCPU *cpu = ARM_CPU(obj);
454
455 cpu->dtb_compatible = "arm,cortex-a7";
456 set_feature(&cpu->env, ARM_FEATURE_V7VE);
457 set_feature(&cpu->env, ARM_FEATURE_NEON);
458 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
459 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
460 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
461 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
462 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
463 set_feature(&cpu->env, ARM_FEATURE_EL2);
464 set_feature(&cpu->env, ARM_FEATURE_EL3);
465 set_feature(&cpu->env, ARM_FEATURE_PMU);
466 cpu->midr = 0x410fc075;
467 cpu->reset_fpsid = 0x41023075;
468 cpu->isar.mvfr0 = 0x10110222;
469 cpu->isar.mvfr1 = 0x11111111;
470 cpu->ctr = 0x84448003;
471 cpu->reset_sctlr = 0x00c50078;
472 cpu->isar.id_pfr0 = 0x00001131;
473 cpu->isar.id_pfr1 = 0x00011011;
474 cpu->isar.id_dfr0 = 0x02010555;
475 cpu->id_afr0 = 0x00000000;
476 cpu->isar.id_mmfr0 = 0x10101105;
477 cpu->isar.id_mmfr1 = 0x40000000;
478 cpu->isar.id_mmfr2 = 0x01240000;
479 cpu->isar.id_mmfr3 = 0x02102211;
480 /*
481 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
482 * table 4-41 gives 0x02101110, which includes the arm div insns.
483 */
484 cpu->isar.id_isar0 = 0x02101110;
485 cpu->isar.id_isar1 = 0x13112111;
486 cpu->isar.id_isar2 = 0x21232041;
487 cpu->isar.id_isar3 = 0x11112131;
488 cpu->isar.id_isar4 = 0x10011142;
489 cpu->isar.dbgdidr = 0x3515f005;
490 cpu->isar.dbgdevid = 0x01110f13;
491 cpu->isar.dbgdevid1 = 0x1;
492 cpu->clidr = 0x0a200023;
493 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
494 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
495 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
496 cpu->isar.reset_pmcr_el0 = 0x41072000;
497 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
498 }
499
cortex_a15_initfn(Object * obj)500 static void cortex_a15_initfn(Object *obj)
501 {
502 ARMCPU *cpu = ARM_CPU(obj);
503
504 cpu->dtb_compatible = "arm,cortex-a15";
505 set_feature(&cpu->env, ARM_FEATURE_V7VE);
506 set_feature(&cpu->env, ARM_FEATURE_NEON);
507 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
508 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
509 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
510 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
511 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
512 set_feature(&cpu->env, ARM_FEATURE_EL2);
513 set_feature(&cpu->env, ARM_FEATURE_EL3);
514 set_feature(&cpu->env, ARM_FEATURE_PMU);
515 /* r4p0 cpu, not requiring expensive tlb flush errata */
516 cpu->midr = 0x414fc0f0;
517 cpu->revidr = 0x0;
518 cpu->reset_fpsid = 0x410430f0;
519 cpu->isar.mvfr0 = 0x10110222;
520 cpu->isar.mvfr1 = 0x11111111;
521 cpu->ctr = 0x8444c004;
522 cpu->reset_sctlr = 0x00c50078;
523 cpu->isar.id_pfr0 = 0x00001131;
524 cpu->isar.id_pfr1 = 0x00011011;
525 cpu->isar.id_dfr0 = 0x02010555;
526 cpu->id_afr0 = 0x00000000;
527 cpu->isar.id_mmfr0 = 0x10201105;
528 cpu->isar.id_mmfr1 = 0x20000000;
529 cpu->isar.id_mmfr2 = 0x01240000;
530 cpu->isar.id_mmfr3 = 0x02102211;
531 cpu->isar.id_isar0 = 0x02101110;
532 cpu->isar.id_isar1 = 0x13112111;
533 cpu->isar.id_isar2 = 0x21232041;
534 cpu->isar.id_isar3 = 0x11112131;
535 cpu->isar.id_isar4 = 0x10011142;
536 cpu->isar.dbgdidr = 0x3515f021;
537 cpu->isar.dbgdevid = 0x01110f13;
538 cpu->isar.dbgdevid1 = 0x0;
539 cpu->clidr = 0x0a200023;
540 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
541 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
542 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
543 cpu->isar.reset_pmcr_el0 = 0x410F3000;
544 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
545 }
546
547 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
548 /* Dummy the TCM region regs for the moment */
549 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
550 .access = PL1_RW, .type = ARM_CP_CONST },
551 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
552 .access = PL1_RW, .type = ARM_CP_CONST },
553 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
554 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
555 };
556
cortex_r5_initfn(Object * obj)557 static void cortex_r5_initfn(Object *obj)
558 {
559 ARMCPU *cpu = ARM_CPU(obj);
560
561 set_feature(&cpu->env, ARM_FEATURE_V7);
562 set_feature(&cpu->env, ARM_FEATURE_V7MP);
563 set_feature(&cpu->env, ARM_FEATURE_PMSA);
564 set_feature(&cpu->env, ARM_FEATURE_PMU);
565 cpu->midr = 0x411fc153; /* r1p3 */
566 cpu->isar.id_pfr0 = 0x0131;
567 cpu->isar.id_pfr1 = 0x001;
568 cpu->isar.id_dfr0 = 0x010400;
569 cpu->id_afr0 = 0x0;
570 cpu->isar.id_mmfr0 = 0x0210030;
571 cpu->isar.id_mmfr1 = 0x00000000;
572 cpu->isar.id_mmfr2 = 0x01200000;
573 cpu->isar.id_mmfr3 = 0x0211;
574 cpu->isar.id_isar0 = 0x02101111;
575 cpu->isar.id_isar1 = 0x13112111;
576 cpu->isar.id_isar2 = 0x21232141;
577 cpu->isar.id_isar3 = 0x01112131;
578 cpu->isar.id_isar4 = 0x0010142;
579 cpu->isar.id_isar5 = 0x0;
580 cpu->isar.id_isar6 = 0x0;
581 cpu->mp_is_up = true;
582 cpu->pmsav7_dregion = 16;
583 cpu->isar.reset_pmcr_el0 = 0x41151800;
584 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
585 }
586
587 static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
588 { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
589 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
590 { .name = "IMP_ATCMREGIONR",
591 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
592 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
593 { .name = "IMP_BTCMREGIONR",
594 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
595 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
596 { .name = "IMP_CTCMREGIONR",
597 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
598 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
599 { .name = "IMP_CSCTLR",
600 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
601 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
602 { .name = "IMP_BPCTLR",
603 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
604 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
605 { .name = "IMP_MEMPROTCLR",
606 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
607 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
608 { .name = "IMP_SLAVEPCTLR",
609 .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
610 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
611 { .name = "IMP_PERIPHREGIONR",
612 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
613 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
614 { .name = "IMP_FLASHIFREGIONR",
615 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
616 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
617 { .name = "IMP_BUILDOPTR",
618 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
619 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
620 { .name = "IMP_PINOPTR",
621 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
622 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
623 { .name = "IMP_QOSR",
624 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
625 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
626 { .name = "IMP_BUSTIMEOUTR",
627 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
628 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
629 { .name = "IMP_INTMONR",
630 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
631 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
632 { .name = "IMP_ICERR0",
633 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
634 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
635 { .name = "IMP_ICERR1",
636 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
637 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
638 { .name = "IMP_DCERR0",
639 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
640 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
641 { .name = "IMP_DCERR1",
642 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
643 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
644 { .name = "IMP_TCMERR0",
645 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
646 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
647 { .name = "IMP_TCMERR1",
648 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
649 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
650 { .name = "IMP_TCMSYNDR0",
651 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
652 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
653 { .name = "IMP_TCMSYNDR1",
654 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
655 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
656 { .name = "IMP_FLASHERR0",
657 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
658 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
659 { .name = "IMP_FLASHERR1",
660 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
661 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
662 { .name = "IMP_CDBGDR0",
663 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
664 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
665 { .name = "IMP_CBDGBR1",
666 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
667 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
668 { .name = "IMP_TESTR0",
669 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
670 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
671 { .name = "IMP_TESTR1",
672 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
673 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
674 { .name = "IMP_CDBGDCI",
675 .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
676 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
677 { .name = "IMP_CDBGDCT",
678 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
679 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
680 { .name = "IMP_CDBGICT",
681 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
682 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
683 { .name = "IMP_CDBGDCD",
684 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
685 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
686 { .name = "IMP_CDBGICD",
687 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
688 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
689 };
690
691
cortex_r52_initfn(Object * obj)692 static void cortex_r52_initfn(Object *obj)
693 {
694 ARMCPU *cpu = ARM_CPU(obj);
695
696 set_feature(&cpu->env, ARM_FEATURE_V8);
697 set_feature(&cpu->env, ARM_FEATURE_EL2);
698 set_feature(&cpu->env, ARM_FEATURE_PMSA);
699 set_feature(&cpu->env, ARM_FEATURE_NEON);
700 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
701 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
702 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
703 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
704 cpu->midr = 0x411fd133; /* r1p3 */
705 cpu->revidr = 0x00000000;
706 cpu->reset_fpsid = 0x41034023;
707 cpu->isar.mvfr0 = 0x10110222;
708 cpu->isar.mvfr1 = 0x12111111;
709 cpu->isar.mvfr2 = 0x00000043;
710 cpu->ctr = 0x8144c004;
711 cpu->reset_sctlr = 0x30c50838;
712 cpu->isar.id_pfr0 = 0x00000131;
713 cpu->isar.id_pfr1 = 0x10111001;
714 cpu->isar.id_dfr0 = 0x03010006;
715 cpu->id_afr0 = 0x00000000;
716 cpu->isar.id_mmfr0 = 0x00211040;
717 cpu->isar.id_mmfr1 = 0x40000000;
718 cpu->isar.id_mmfr2 = 0x01200000;
719 cpu->isar.id_mmfr3 = 0xf0102211;
720 cpu->isar.id_mmfr4 = 0x00000010;
721 cpu->isar.id_isar0 = 0x02101110;
722 cpu->isar.id_isar1 = 0x13112111;
723 cpu->isar.id_isar2 = 0x21232142;
724 cpu->isar.id_isar3 = 0x01112131;
725 cpu->isar.id_isar4 = 0x00010142;
726 cpu->isar.id_isar5 = 0x00010001;
727 cpu->isar.dbgdidr = 0x77168000;
728 cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
729 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
730 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
731
732 cpu->pmsav7_dregion = 16;
733 cpu->pmsav8r_hdregion = 16;
734
735 define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
736 }
737
cortex_r5f_initfn(Object * obj)738 static void cortex_r5f_initfn(Object *obj)
739 {
740 ARMCPU *cpu = ARM_CPU(obj);
741
742 cortex_r5_initfn(obj);
743 cpu->isar.mvfr0 = 0x10110221;
744 cpu->isar.mvfr1 = 0x00000011;
745 }
746
ti925t_initfn(Object * obj)747 static void ti925t_initfn(Object *obj)
748 {
749 ARMCPU *cpu = ARM_CPU(obj);
750 set_feature(&cpu->env, ARM_FEATURE_V4T);
751 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
752 cpu->midr = ARM_CPUID_TI925T;
753 cpu->ctr = 0x5109149;
754 cpu->reset_sctlr = 0x00000070;
755 }
756
sa1100_initfn(Object * obj)757 static void sa1100_initfn(Object *obj)
758 {
759 ARMCPU *cpu = ARM_CPU(obj);
760
761 cpu->dtb_compatible = "intel,sa1100";
762 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
763 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
764 cpu->midr = 0x4401A11B;
765 cpu->reset_sctlr = 0x00000070;
766 }
767
sa1110_initfn(Object * obj)768 static void sa1110_initfn(Object *obj)
769 {
770 ARMCPU *cpu = ARM_CPU(obj);
771 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
772 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
773 cpu->midr = 0x6901B119;
774 cpu->reset_sctlr = 0x00000070;
775 }
776
pxa250_initfn(Object * obj)777 static void pxa250_initfn(Object *obj)
778 {
779 ARMCPU *cpu = ARM_CPU(obj);
780
781 cpu->dtb_compatible = "marvell,xscale";
782 set_feature(&cpu->env, ARM_FEATURE_V5);
783 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
784 cpu->midr = 0x69052100;
785 cpu->ctr = 0xd172172;
786 cpu->reset_sctlr = 0x00000078;
787 }
788
pxa255_initfn(Object * obj)789 static void pxa255_initfn(Object *obj)
790 {
791 ARMCPU *cpu = ARM_CPU(obj);
792
793 cpu->dtb_compatible = "marvell,xscale";
794 set_feature(&cpu->env, ARM_FEATURE_V5);
795 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
796 cpu->midr = 0x69052d00;
797 cpu->ctr = 0xd172172;
798 cpu->reset_sctlr = 0x00000078;
799 }
800
pxa260_initfn(Object * obj)801 static void pxa260_initfn(Object *obj)
802 {
803 ARMCPU *cpu = ARM_CPU(obj);
804
805 cpu->dtb_compatible = "marvell,xscale";
806 set_feature(&cpu->env, ARM_FEATURE_V5);
807 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
808 cpu->midr = 0x69052903;
809 cpu->ctr = 0xd172172;
810 cpu->reset_sctlr = 0x00000078;
811 }
812
pxa261_initfn(Object * obj)813 static void pxa261_initfn(Object *obj)
814 {
815 ARMCPU *cpu = ARM_CPU(obj);
816
817 cpu->dtb_compatible = "marvell,xscale";
818 set_feature(&cpu->env, ARM_FEATURE_V5);
819 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
820 cpu->midr = 0x69052d05;
821 cpu->ctr = 0xd172172;
822 cpu->reset_sctlr = 0x00000078;
823 }
824
pxa262_initfn(Object * obj)825 static void pxa262_initfn(Object *obj)
826 {
827 ARMCPU *cpu = ARM_CPU(obj);
828
829 cpu->dtb_compatible = "marvell,xscale";
830 set_feature(&cpu->env, ARM_FEATURE_V5);
831 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
832 cpu->midr = 0x69052d06;
833 cpu->ctr = 0xd172172;
834 cpu->reset_sctlr = 0x00000078;
835 }
836
pxa270a0_initfn(Object * obj)837 static void pxa270a0_initfn(Object *obj)
838 {
839 ARMCPU *cpu = ARM_CPU(obj);
840
841 cpu->dtb_compatible = "marvell,xscale";
842 set_feature(&cpu->env, ARM_FEATURE_V5);
843 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
844 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
845 cpu->midr = 0x69054110;
846 cpu->ctr = 0xd172172;
847 cpu->reset_sctlr = 0x00000078;
848 }
849
pxa270a1_initfn(Object * obj)850 static void pxa270a1_initfn(Object *obj)
851 {
852 ARMCPU *cpu = ARM_CPU(obj);
853
854 cpu->dtb_compatible = "marvell,xscale";
855 set_feature(&cpu->env, ARM_FEATURE_V5);
856 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
857 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
858 cpu->midr = 0x69054111;
859 cpu->ctr = 0xd172172;
860 cpu->reset_sctlr = 0x00000078;
861 }
862
pxa270b0_initfn(Object * obj)863 static void pxa270b0_initfn(Object *obj)
864 {
865 ARMCPU *cpu = ARM_CPU(obj);
866
867 cpu->dtb_compatible = "marvell,xscale";
868 set_feature(&cpu->env, ARM_FEATURE_V5);
869 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
870 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
871 cpu->midr = 0x69054112;
872 cpu->ctr = 0xd172172;
873 cpu->reset_sctlr = 0x00000078;
874 }
875
pxa270b1_initfn(Object * obj)876 static void pxa270b1_initfn(Object *obj)
877 {
878 ARMCPU *cpu = ARM_CPU(obj);
879
880 cpu->dtb_compatible = "marvell,xscale";
881 set_feature(&cpu->env, ARM_FEATURE_V5);
882 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
883 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
884 cpu->midr = 0x69054113;
885 cpu->ctr = 0xd172172;
886 cpu->reset_sctlr = 0x00000078;
887 }
888
pxa270c0_initfn(Object * obj)889 static void pxa270c0_initfn(Object *obj)
890 {
891 ARMCPU *cpu = ARM_CPU(obj);
892
893 cpu->dtb_compatible = "marvell,xscale";
894 set_feature(&cpu->env, ARM_FEATURE_V5);
895 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
896 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
897 cpu->midr = 0x69054114;
898 cpu->ctr = 0xd172172;
899 cpu->reset_sctlr = 0x00000078;
900 }
901
pxa270c5_initfn(Object * obj)902 static void pxa270c5_initfn(Object *obj)
903 {
904 ARMCPU *cpu = ARM_CPU(obj);
905
906 cpu->dtb_compatible = "marvell,xscale";
907 set_feature(&cpu->env, ARM_FEATURE_V5);
908 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
909 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
910 cpu->midr = 0x69054117;
911 cpu->ctr = 0xd172172;
912 cpu->reset_sctlr = 0x00000078;
913 }
914
915 #ifndef TARGET_AARCH64
916 /*
917 * -cpu max: a CPU with as many features enabled as our emulation supports.
918 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
919 * this only needs to handle 32 bits, and need not care about KVM.
920 */
arm_max_initfn(Object * obj)921 static void arm_max_initfn(Object *obj)
922 {
923 ARMCPU *cpu = ARM_CPU(obj);
924
925 /* aarch64_a57_initfn, advertising none of the aarch64 features */
926 cpu->dtb_compatible = "arm,cortex-a57";
927 set_feature(&cpu->env, ARM_FEATURE_V8);
928 set_feature(&cpu->env, ARM_FEATURE_NEON);
929 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
930 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
931 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
932 set_feature(&cpu->env, ARM_FEATURE_EL2);
933 set_feature(&cpu->env, ARM_FEATURE_EL3);
934 set_feature(&cpu->env, ARM_FEATURE_PMU);
935 cpu->midr = 0x411fd070;
936 cpu->revidr = 0x00000000;
937 cpu->reset_fpsid = 0x41034070;
938 cpu->isar.mvfr0 = 0x10110222;
939 cpu->isar.mvfr1 = 0x12111111;
940 cpu->isar.mvfr2 = 0x00000043;
941 cpu->ctr = 0x8444c004;
942 cpu->reset_sctlr = 0x00c50838;
943 cpu->isar.id_pfr0 = 0x00000131;
944 cpu->isar.id_pfr1 = 0x00011011;
945 cpu->isar.id_dfr0 = 0x03010066;
946 cpu->id_afr0 = 0x00000000;
947 cpu->isar.id_mmfr0 = 0x10101105;
948 cpu->isar.id_mmfr1 = 0x40000000;
949 cpu->isar.id_mmfr2 = 0x01260000;
950 cpu->isar.id_mmfr3 = 0x02102211;
951 cpu->isar.id_isar0 = 0x02101110;
952 cpu->isar.id_isar1 = 0x13112111;
953 cpu->isar.id_isar2 = 0x21232042;
954 cpu->isar.id_isar3 = 0x01112131;
955 cpu->isar.id_isar4 = 0x00011142;
956 cpu->isar.id_isar5 = 0x00011121;
957 cpu->isar.id_isar6 = 0;
958 cpu->isar.dbgdidr = 0x3516d000;
959 cpu->isar.dbgdevid = 0x00110f13;
960 cpu->isar.dbgdevid1 = 0x2;
961 cpu->isar.reset_pmcr_el0 = 0x41013000;
962 cpu->clidr = 0x0a200023;
963 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
964 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
965 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
966 define_cortex_a72_a57_a53_cp_reginfo(cpu);
967
968 aa32_max_features(cpu);
969
970 #ifdef CONFIG_USER_ONLY
971 /*
972 * Break with true ARMv8 and add back old-style VFP short-vector support.
973 * Only do this for user-mode, where -cpu max is the default, so that
974 * older v6 and v7 programs are more likely to work without adjustment.
975 */
976 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
977 #endif
978 }
979 #endif /* !TARGET_AARCH64 */
980
981 static const ARMCPUInfo arm_tcg_cpus[] = {
982 { .name = "arm926", .initfn = arm926_initfn },
983 { .name = "arm946", .initfn = arm946_initfn },
984 { .name = "arm1026", .initfn = arm1026_initfn },
985 /*
986 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
987 * older core than plain "arm1136". In particular this does not
988 * have the v6K features.
989 */
990 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
991 { .name = "arm1136", .initfn = arm1136_initfn },
992 { .name = "arm1176", .initfn = arm1176_initfn },
993 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
994 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
995 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
996 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
997 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
998 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
999 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1000 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1001 { .name = "ti925t", .initfn = ti925t_initfn },
1002 { .name = "sa1100", .initfn = sa1100_initfn },
1003 { .name = "sa1110", .initfn = sa1110_initfn },
1004 { .name = "pxa250", .initfn = pxa250_initfn },
1005 { .name = "pxa255", .initfn = pxa255_initfn },
1006 { .name = "pxa260", .initfn = pxa260_initfn },
1007 { .name = "pxa261", .initfn = pxa261_initfn },
1008 { .name = "pxa262", .initfn = pxa262_initfn },
1009 /* "pxa270" is an alias for "pxa270-a0" */
1010 { .name = "pxa270", .initfn = pxa270a0_initfn },
1011 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1012 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1013 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1014 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1015 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1016 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1017 #ifndef TARGET_AARCH64
1018 { .name = "max", .initfn = arm_max_initfn },
1019 #endif
1020 #ifdef CONFIG_USER_ONLY
1021 { .name = "any", .initfn = arm_max_initfn },
1022 #endif
1023 };
1024
1025 static const TypeInfo idau_interface_type_info = {
1026 .name = TYPE_IDAU_INTERFACE,
1027 .parent = TYPE_INTERFACE,
1028 .class_size = sizeof(IDAUInterfaceClass),
1029 };
1030
arm_tcg_cpu_register_types(void)1031 static void arm_tcg_cpu_register_types(void)
1032 {
1033 size_t i;
1034
1035 type_register_static(&idau_interface_type_info);
1036 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1037 arm_cpu_register(&arm_tcg_cpus[i]);
1038 }
1039 }
1040
1041 type_init(arm_tcg_cpu_register_types)
1042
1043 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
1044