1 /*
2 Copyright (C) 2006 T. Scott Dattalo
3
4 This file is part of the libgpsim_dspic library of gpsim
5
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
10
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
15
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, see
18 <http://www.gnu.org/licenses/lgpl-2.1.html>.
19 */
20
21 #include "../pic-instructions.h"
22
23 #include "dspic-processors.h"
24 #include "dspic-instructions.h"
25
26 #include <assert.h>
27
28 using namespace dspic;
29 using namespace dspic_instructions;
30
31 namespace dspic {
32 extern Trace *gTrace; // Points to gpsim's global trace object.
33 extern Cycle_Counter *gCycles; // Points to gpsim's global cycle counter.
34 }
35
36
37 struct dsPicInstructionConstructor {
38 unsigned int inst_mask;
39 unsigned int opcode;
40 instruction * (*inst_constructor) (Processor *cpu, unsigned int inst,unsigned int addr);
41 };
42
43
44 struct dsPicInstructionConstructor op_dsPic[] = {
45
46 { 0xff8000, 0xb00000, ADDR::construct }, // Lit
47 { 0xf80000, 0x400000, ADDR::construct }, // Wb + Lit -> Wd
48 { 0xff7fff, 0xcb0000, ADD::construct }, // add accumulators
49
50 { 0xff8000, 0xb48000, ADDC::construct }, // f to W
51 { 0xff8000, 0xb08000, ADDC::construct }, // Lit
52 { 0xf80000, 0x480000, ADDC::construct }, // Wb + Lit -> Wd
53
54 { 0xff8000, 0xb60000, AND::construct }, // f to W
55 { 0xff8000, 0xb20000, AND::construct }, // Lit
56 { 0xf80000, 0x600060, AND::construct }, // Wb + Lit -> Wd
57 { 0xf80000, 0x600000, AND::construct },
58
59 { 0xff8000, 0xd58000, ASR::construct }, // f to W
60 { 0xff8000, 0xd18000, ASR::construct }, // Lit
61 { 0xff8070, 0xde8000, ASR::construct }, // Wb + Lit -> Wd
62
63 { 0xff0000, 0xa90000, BCLR::construct },
64 { 0xff0b80, 0xa10000, BCLR::construct },
65
66 { 0xf00000, 0x300000, BRA::construct }, // branch literal offset
67 { 0xfffff0, 0x016000, BRA::construct }, // computed branch
68 { 0xfc0000, 0x0c0000, BRA::construct }, // branch on accumulator state
69
70 { 0xff0000, 0xa80000, BSET::construct },
71 { 0xff0b80, 0xa00000, BSET::construct },
72
73 { 0xff0780, 0xad0000, BSW::construct },
74
75 { 0xff0000, 0xaa0000, BTG::construct },
76
77 { 0xff0000, 0xaf0000, BTS::construct },
78 { 0xff0000, 0xab0000, BTST::construct },
79 { 0xff0780, 0xa30000, BTST::construct },
80 { 0xff0780, 0xa50000, BTST::construct },
81
82 { 0xff0000, 0xac0000, BTSTS::construct },
83 { 0xff0780, 0xa40000, BTSTS::construct },
84
85 { 0xff0001, 0x020000, CALL::construct },
86 { 0xfffff0, 0x010000, CALL::construct },
87
88 { 0xff8000, 0xef0000, CLR::construct },
89 { 0xff807f, 0xeb0000, CLR::construct },
90 { 0xff4000, 0xc30000, CLR::construct },
91
92 { 0xffffff, 0xfe6000, CLRWDT::construct },
93
94 { 0xff8000, 0xee8000, COM::construct },
95 { 0xff8000, 0xea8000, COM::construct },
96
97 { 0xffa000, 0xe30000, CP::construct },
98 { 0xff83e0, 0xe10060, CP::construct },
99 { 0xff8380, 0xe10000, CP::construct },
100
101 { 0xffa000, 0xe20000, CP0::construct },
102 { 0xfffb80, 0xe00000, CP0::construct },
103
104 { 0xffa000, 0xe38000, CPB::construct },
105 { 0xff83e0, 0xe18060, CPB::construct },
106 { 0xff8380, 0xe18000, CPB::construct },
107
108 { 0xfe03f0, 0xe60000, CPS::construct },
109
110 { 0xfffff0, 0xfd4000, DAW::construct },
111
112 { 0xff8000, 0xed0000, DEC::construct },
113 { 0xff8000, 0xe90000, DEC::construct },
114
115 { 0xff8000, 0xed8000, DEC::construct }, // DEC2
116 { 0xff8000, 0xe98000, DEC::construct }, // DEC2
117
118 { 0xffc000, 0xfc0000, DISI::construct },
119
120 { 0xff8030, 0xd80000, DIV::construct },
121 { 0xff8030, 0xd88000, DIV::construct },
122 { 0xff87f0, 0xd90000, DIV::construct },
123
124 { 0xffc000, 0x080000, DO::construct },
125 { 0xfffff0, 0x088000, DO::construct },
126
127 { 0xfc4c03, 0xf04003, ED::construct },
128 { 0xfc4c03, 0xf04002, ED::construct },
129
130 { 0xfff870, 0xfd0000, EXCH::construct },
131
132 { 0xfff800, 0xdf0000, FB::construct }, // FBCL
133 { 0xfff800, 0xcf8000, FB::construct }, // FF1L
134 { 0xfff800, 0xcf0000, FB::construct }, // FF1R
135
136 { 0xff0000, 0x040000, GOTO::construct },
137 { 0xfffff0, 0x014000, GOTO::construct },
138
139 { 0xff8000, 0xec0000, DEC::construct },
140 { 0xff8000, 0xe80000, DEC::construct },
141
142 { 0xff8000, 0xec8000, DEC::construct }, // INC2
143 { 0xff8000, 0xe88000, DEC::construct }, // DEC2
144
145 { 0xff8000, 0xb70000, IOR::construct }, // f to W
146 { 0xff8000, 0xb30000, IOR::construct }, // Lit
147 { 0xf80000, 0x700000, IOR::construct }, // Wb + Lit -> Wd
148
149 { 0xff0000, 0xca0000, LAC::construct },
150 { 0xffc001, 0xfa0000, LNK::construct },
151
152 { 0xff8000, 0xd50000, LSR::construct }, // Note LSR is similar to ASR
153 { 0xff8000, 0xd10000, LSR::construct }, // Lit
154 { 0xff8070, 0xde0000, LSR::construct }, // Wb + Lit -> Wd
155
156 { 0xf84000, 0xc00000, MAC::construct },
157 { 0xfc4003, 0xf00000, MAC::construct },
158
159 { 0xff8000, 0xbf8000, MOV::construct },
160 { 0xffa000, 0xb7a000, MOV::construct },
161 { 0xf80000, 0x800000, MOV::construct },
162 { 0xf80000, 0x880000, MOV::construct },
163 { 0xfff000, 0xb3c000, MOV::construct }, //MOV.B
164 { 0xf00000, 0x200000, MOV::construct },
165 { 0xf80000, 0x900000, MOV::construct },
166 { 0xf80000, 0x980000, MOV::construct },
167 { 0xf80000, 0x780000, MOV::construct },
168 { 0xfff880, 0xbe0000, MOV::construct }, //MOV.D
169 { 0xffc071, 0xbe8000, MOV::construct }, //MOV.D
170
171 { 0xff4000, 0xc70000, MOVSAC::construct },
172
173 { 0xf84003, 0xc00003, MPY::construct }, // degenerate to MAC
174 { 0xf84003, 0xc04003, MPY::construct }, // MPY.N and MSC
175
176 { 0xffa000, 0xbc0000, MUL::construct },
177 { 0xff8000, 0xb98000, MUL::construct }, //MUL.SS
178 { 0xff8060, 0xb90000, MUL::construct }, //MUL.SU
179 { 0xff8000, 0xb88000, MUL::construct }, //MUL.US
180 { 0xff8060, 0xb80000, MUL::construct }, //MUL.UU
181
182 { 0xff8000, 0xee0000, NEG::construct },
183 { 0xff8000, 0xea0000, NEG::construct },
184 { 0xff7fff, 0xcb1000, NEG::construct },
185
186 { 0xff0000, 0x000000, NOP::construct },
187 { 0xff0000, 0xff0000, NOP::construct },
188
189 { 0xff0001, 0xf90000, POP::construct },
190 { 0xf8407f, 0x78004f, POP::construct },
191 { 0xfff8ff, 0xbe004f, POP::construct },
192 { 0xffffff, 0xfe8000, POP::construct }, // POP.S
193
194 { 0xff0001, 0xf80000, PUSH::construct },
195 { 0xf87f80, 0x781f80, PUSH::construct },
196 { 0xfffff1, 0xbe9f80, PUSH::construct },
197 { 0xffffff, 0xfea000, PUSH::construct }, // PUSH.S
198
199 { 0xfffffe, 0xfe4000, PWRSAV::construct },
200
201 { 0xff0000, 0x070000, RCALL::construct },
202 { 0xfffff0, 0x012000, RCALL::construct },
203
204 { 0xffc000, 0x090000, REPEAT::construct },
205 { 0xfffff0, 0x098000, REPEAT::construct },
206
207 { 0xffffff, 0xfe0000, RESET::construct },
208
209 { 0xffffff, 0x064000, RET::construct }, // RETFIE
210 { 0xff8000, 0x050000, RET::construct }, // RETLW
211 { 0xffffff, 0x060000, RET::construct }, // RETURN
212
213 { 0xff8000, 0xd68000, ROT::construct }, // RLC
214 { 0xff8000, 0xd28000, ROT::construct }, // RLC
215 { 0xff8000, 0xd60000, ROT::construct }, // RLNC
216 { 0xff8000, 0xd20000, ROT::construct }, // RLNC
217 { 0xff8000, 0xd78000, ROT::construct }, // RRC
218 { 0xff8000, 0xd38000, ROT::construct }, // RRC
219 { 0xff8000, 0xd70000, ROT::construct }, // RNC
220 { 0xff8000, 0xd30000, ROT::construct }, // RNC
221
222 { 0xff0000, 0xcc0000, SAC::construct },
223 { 0xff0000, 0xcd0000, SAC::construct }, // SAC.R
224
225 { 0xfff800, 0xfb0000, SE::construct },
226
227 { 0xff8000, 0xef8000, SETM::construct },
228 { 0xff807f, 0xeb8000, SETM::construct },
229
230 { 0xff7fc0, 0xc80040, SFTAC::construct },
231 { 0xff7ff0, 0xc80000, SFTAC::construct },
232
233 { 0xff8000, 0xd40000, SL::construct },
234 { 0xff8000, 0xd00000, SL::construct },
235 { 0xff8070, 0xdd0040, SL::construct },
236 { 0xff8070, 0xdd0000, SL::construct },
237
238 { 0xff8000, 0xb50000, SUB::construct },
239 { 0xff8000, 0xb10000, SUB::construct },
240 { 0xf80000, 0x500000, SUB::construct },
241
242 { 0xff7fff, 0xcb3000, SUB::construct },
243
244 { 0xff8000, 0xb58000, SUB::construct }, //SUBB
245 { 0xff8000, 0xb18000, SUB::construct },
246 { 0xf80000, 0x580000, SUB::construct },
247
248 { 0xff8000, 0xbd8000, SUB::construct }, //SUBBR
249 { 0xf80000, 0x180000, SUB::construct },
250
251 { 0xff8000, 0xbd0000, SUB::construct }, //SUBR
252 { 0xf80000, 0x100000, SUB::construct },
253
254 { 0xffbff0, 0xfd8000, SWAP::construct },
255
256 { 0xff8000, 0xba8000, TBLRD::construct }, //TBLRDH
257 { 0xff8000, 0xba0000, TBLRD::construct }, //TBLRDL
258
259 { 0xff8000, 0xbb8000, TBLWT::construct }, //TBLWTH
260 { 0xff8000, 0xbb0000, TBLWT::construct }, //TBLWTL
261
262 { 0xffffff, 0xfa8000, ULNK::construct },
263
264 { 0xff8000, 0xb68000, XOR::construct }, // f to W
265 { 0xff8000, 0xb28000, XOR::construct }, // Lit
266 { 0xf80000, 0x680000, XOR::construct }, // Wb + Lit -> Wd
267
268 { 0xffc000, 0xfb8000, ZE::construct }
269
270 };
271
272 const int NUM_OP_DSPIC = sizeof(op_dsPic) / sizeof(op_dsPic[0]);
273
274
disasm(unsigned int address,unsigned int inst)275 instruction * dsPicProcessor::disasm (unsigned int address, unsigned int inst)
276 {
277
278 //printf("dspic disasm addr 0x%x, opcode 0x%x\n",address,inst);
279
280 instruction *pi;
281
282 pi = 0;
283 for(int i =0; i<NUM_OP_DSPIC; i++)
284 if((op_dsPic[i].inst_mask & inst) == op_dsPic[i].opcode)
285 pi = op_dsPic[i].inst_constructor(this, inst, address);
286
287 if(pi == 0)
288 pi = invalid_instruction::construct(this, inst, address);
289
290 return (pi);
291
292 }
293
294
295
296 namespace dspic_instructions
297 {
298 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
299 //
300 // Addressing Modes
301 //
302 // The various addressing modes for the dspic instructions are
303 // first defined.
304 //
305 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
306
307 //--------------------------------------------------
308 const RegisterValue AddressingMode::m_unknown = RegisterValue(0,0xffff);
309
AddressingMode(dspic::dsPicProcessor * cpu,unsigned int addr)310 AddressingMode::AddressingMode(dspic::dsPicProcessor *cpu,
311 unsigned int addr)
312 : m_cpu(cpu), m_mode(0), m_addr(addr)
313
314 {
315 }
construct(dspic::dsPicProcessor * new_cpu,unsigned int new_mode,unsigned int addr)316 AddressingMode * AddressingMode::construct(dspic::dsPicProcessor *new_cpu,
317 unsigned int new_mode,
318 unsigned int addr)
319 {
320
321 switch (new_mode&7) {
322
323 case eDirect:
324 return new RegDirectAddrMode(new_cpu, addr);
325 case eIndirect:
326 return new RegIndirectAddrMode(new_cpu, addr);
327 case eIndirectPostDec:
328 return new RegIndirectPostDecAddrMode(new_cpu, addr);
329 case eIndirectPostInc:
330 return new RegIndirectPostIncAddrMode(new_cpu, addr);
331 case eIndirectPreDec:
332 return new RegIndirectPreDecAddrMode(new_cpu, addr);
333 case eIndirectPreInc:
334 return new RegIndirectPreIncAddrMode(new_cpu, addr);
335 //case eIndirectRegOffset:
336 //case eIndirectRegOffset_:
337 break;
338 case eLiteral:
339 case eLiteral_:
340 return new LiteralAddressingMode(new_cpu, addr&0x1f);
341 }
342
343 return 0;
344 }
345
346
347 //--------------------------------------------------
348
349
LiteralAddressingMode(dspic::dsPicProcessor * cpu,unsigned int addr)350 LiteralAddressingMode::LiteralAddressingMode(dspic::dsPicProcessor *cpu,
351 unsigned int addr)
352 : AddressingMode(cpu, addr),
353 m_rv(addr,0)
354 {
355 }
name(char * buff,int len)356 char *LiteralAddressingMode::name(char *buff,int len)
357 {
358 if (buff)
359 snprintf(buff,len,"#0x%x",m_addr);
360 return buff;
361 }
362 //--------------------------------------------------
RegisterAddressingMode(dspic::dsPicProcessor * cpu,unsigned int addr,const char * cPformat)363 RegisterAddressingMode::RegisterAddressingMode(dspic::dsPicProcessor *cpu,
364 unsigned int addr,
365 const char *cPformat)
366 : AddressingMode(cpu, addr&0xf),
367 m_cPformat(cPformat)
368 {
369 }
370
name(char * buff,int len)371 char *RegisterAddressingMode::name(char *buff,int len)
372 {
373 if (buff)
374 snprintf(buff,len,m_cPformat,m_cpu->registers[m_addr]->name().c_str());
375 return buff;
376 }
377
378 //--------------------------------------------------
RegDirectAddrMode(dspic::dsPicProcessor * cpu,unsigned int addr)379 RegDirectAddrMode::RegDirectAddrMode(dspic::dsPicProcessor *cpu,
380 unsigned int addr)
381 : RegisterAddressingMode(cpu, addr,"%s")
382 {
383 }
get()384 RegisterValue RegDirectAddrMode::get()
385 {
386 return m_cpu->registers[m_addr]->getRV();
387 }
put(RegisterValue & n_rv)388 void RegDirectAddrMode::put(RegisterValue &n_rv)
389 {
390 m_cpu->registers[m_addr]->putRV(n_rv);
391 }
392
393 //--------------------------------------------------
RegIndirectAddrMode(dspic::dsPicProcessor * cpu,unsigned int addr)394 RegIndirectAddrMode::RegIndirectAddrMode(dspic::dsPicProcessor *cpu,
395 unsigned int addr)
396 : RegisterAddressingMode(cpu, addr,"[%s]")
397 {
398 }
get()399 RegisterValue RegIndirectAddrMode::get()
400 {
401 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
402 return rv.init ? m_unknown : m_cpu->registers[rv.data]->getRV();
403 }
put(RegisterValue & n_rv)404 void RegIndirectAddrMode::put(RegisterValue &n_rv)
405 {
406 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
407 if (rv.init == 0)
408 m_cpu->registers[rv.data]->putRV(n_rv);
409 }
410 //--------------------------------------------------
RegIndirectPostDecAddrMode(dspic::dsPicProcessor * cpu,unsigned int addr)411 RegIndirectPostDecAddrMode::RegIndirectPostDecAddrMode(dspic::dsPicProcessor *cpu,
412 unsigned int addr)
413 : RegisterAddressingMode(cpu, addr,"[%s--]")
414 {
415 }
get()416 RegisterValue RegIndirectPostDecAddrMode::get()
417 {
418 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
419 RegisterValue retRV = rv.init ? m_unknown : m_cpu->registers[rv.data]->getRV();
420 rv.data = (rv.data-2) & 0xffff;
421 m_cpu->registers[m_addr]->putRV(rv);
422 return retRV;
423 }
put(RegisterValue & n_rv)424 void RegIndirectPostDecAddrMode::put(RegisterValue &n_rv)
425 {
426 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
427 if (rv.init == 0)
428 m_cpu->registers[rv.data]->putRV(n_rv);
429 rv.data = (rv.data-2) & 0xffff;
430 m_cpu->registers[m_addr]->putRV(rv);
431 }
432 //--------------------------------------------------
RegIndirectPostIncAddrMode(dspic::dsPicProcessor * cpu,unsigned int addr)433 RegIndirectPostIncAddrMode::RegIndirectPostIncAddrMode(dspic::dsPicProcessor *cpu,
434 unsigned int addr)
435 : RegisterAddressingMode(cpu, addr,"[%s++]")
436 {
437 }
get()438 RegisterValue RegIndirectPostIncAddrMode::get()
439 {
440 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
441 RegisterValue retRV = rv.init ? m_unknown : m_cpu->registers[rv.data]->getRV();
442 rv.data = (rv.data+2) & 0xffff;
443 m_cpu->registers[m_addr]->putRV(rv);
444 return retRV;
445 }
put(RegisterValue & n_rv)446 void RegIndirectPostIncAddrMode::put(RegisterValue &n_rv)
447 {
448 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
449 if (rv.init == 0)
450 m_cpu->registers[rv.data]->putRV(n_rv);
451 rv.data = (rv.data+2) & 0xffff;
452 m_cpu->registers[m_addr]->putRV(rv);
453 }
454 //--------------------------------------------------
RegIndirectPreDecAddrMode(dspic::dsPicProcessor * cpu,unsigned int addr)455 RegIndirectPreDecAddrMode::RegIndirectPreDecAddrMode(dspic::dsPicProcessor *cpu,
456 unsigned int addr)
457 : RegisterAddressingMode(cpu, addr,"[--%s]")
458 {
459 }
get()460 RegisterValue RegIndirectPreDecAddrMode::get()
461 {
462 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
463 rv.data = (rv.data-2) & 0xffff;
464 m_cpu->registers[m_addr]->putRV(rv);
465 RegisterValue retRV = rv.init ? m_unknown : m_cpu->registers[rv.data]->getRV();
466 return retRV;
467 }
put(RegisterValue & n_rv)468 void RegIndirectPreDecAddrMode::put(RegisterValue &n_rv)
469 {
470 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
471 rv.data = (rv.data-2) & 0xffff;
472 m_cpu->registers[m_addr]->putRV(rv);
473 if (rv.init == 0)
474 m_cpu->registers[rv.data]->putRV(n_rv);
475 }
476 //--------------------------------------------------
RegIndirectPreIncAddrMode(dspic::dsPicProcessor * cpu,unsigned int addr)477 RegIndirectPreIncAddrMode::RegIndirectPreIncAddrMode(dspic::dsPicProcessor *cpu,
478 unsigned int addr)
479 : RegisterAddressingMode(cpu, addr,"[++%s]")
480 {
481 }
get()482 RegisterValue RegIndirectPreIncAddrMode::get()
483 {
484 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
485 rv.data = (rv.data+2) & 0xffff;
486 m_cpu->registers[m_addr]->putRV(rv);
487 RegisterValue retRV = rv.init ? m_unknown : m_cpu->registers[rv.data]->getRV();
488 return retRV;
489 }
put(RegisterValue & n_rv)490 void RegIndirectPreIncAddrMode::put(RegisterValue &n_rv)
491 {
492 RegisterValue rv = m_cpu->registers[m_addr]->getRV();
493 rv.data = (rv.data+2) & 0xffff;
494 m_cpu->registers[m_addr]->putRV(rv);
495 if (rv.init == 0)
496 m_cpu->registers[rv.data]->putRV(n_rv);
497 }
498 //--------------------------------------------------
MultiWordInstruction(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)499 MultiWordInstruction::MultiWordInstruction(Processor *new_cpu,
500 unsigned int new_opcode,
501 unsigned int addr)
502 : instruction(new_cpu, new_opcode, addr),
503 word2_opcode(0), PMaddress(addr), PMindex(addr/2), initialized(false)
504 {
505 }
506
507
508 //--------------------------------------------------
MultiWordBranch(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)509 MultiWordBranch::MultiWordBranch(Processor *new_cpu,
510 unsigned int new_opcode,
511 unsigned int addr)
512 : MultiWordInstruction(new_cpu, new_opcode, addr), destination_index(0)
513 {
514 }
515
runtime_initialize()516 void MultiWordBranch::runtime_initialize()
517 {
518 if(cpu_dsPic->program_memory[PMindex+1] != &cpu_dsPic->bad_instruction) {
519
520 word2_opcode = cpu_dsPic->program_memory[PMindex+1]->get_opcode();
521
522 cpu_dsPic->program_memory[PMindex+1]->
523 update_line_number(file_id,src_line, lst_line, 0, 0);
524
525 // extract the destination address from the two-word opcode
526 destination_index = ((word2_opcode & 0x7f)<<15) | ((opcode>>1) & 0x7fff);
527 initialized = true;
528 }
529 }
530
name(char * return_str,int len)531 char * MultiWordBranch::name(char *return_str,int len)
532 {
533 if(!initialized)
534 runtime_initialize();
535
536 snprintf(return_str,len,"%s\t0x%05x",
537 gpsimObject::name().c_str(),
538 destination_index<<1);
539
540 return(return_str);
541 }
542
543
544 //--------------------------------------------------
LiteralBranch(Processor * new_cpu,unsigned int new_opcode,unsigned int addr,const char * _name)545 LiteralBranch::LiteralBranch(Processor *new_cpu,
546 unsigned int new_opcode,
547 unsigned int addr,
548 const char *_name)
549 : instruction(new_cpu, new_opcode, addr), mcP_conditionName("")
550 {
551 new_name(_name);
552 unsigned int signExtendedOffset =
553 ((new_opcode&0xffff)<<1) | ((new_opcode & (1<<15)) ? 0xfffe0000 : 0);
554 m_destination = (addr + 2 + signExtendedOffset) & 0xfffffe;
555 }
name(char * buff,int len)556 char *LiteralBranch::name(char *buff,int len)
557 {
558 if (buff) {
559 char sign = (opcode & (1<<15)) ? '-' : '+';
560
561 int offset= (((sign=='-') ?
562 ((opcode^0xffff)+1) : opcode) << 1) & 0x1fffe;
563
564 snprintf(buff, len, "%s\t%s#0x%06x\t; $%c0x%x",
565 instruction::name().c_str(),
566 mcP_conditionName,
567 m_destination,
568 sign, offset);
569 }
570 return buff;
571 }
572
573 //--------------------------------------------------
ImmediateInstruction(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)574 ImmediateInstruction::ImmediateInstruction(Processor *new_cpu,
575 unsigned int new_opcode,
576 unsigned int addr)
577 : instruction(new_cpu, new_opcode, addr), m_L(new_opcode & 0xfffe)
578 {
579 }
name(char * buff,int len)580 char *ImmediateInstruction::name(char *buff,int len)
581 {
582 if (buff) {
583 snprintf(buff, len, "%s\t#0x%04x", instruction::name().c_str(),m_L);
584 }
585 return buff;
586 }
587
588 //--------------------------------------------------
RegisterInstruction(Processor * new_cpu,unsigned int new_opcode,unsigned int addr,const char * _name)589 RegisterInstruction::RegisterInstruction(Processor *new_cpu,
590 unsigned int new_opcode,
591 unsigned int addr,
592 const char *_name)
593 : instruction(new_cpu, new_opcode, addr),
594 m_bByteOperation((new_opcode & (1<<14)) != 0),
595 m_base(0), m_source(0), m_destination(0)
596 {
597 new_name(_name);
598 }
599 //--------------------------------------------------
600 //--------------------------------------------------
RegisterToRegisterInstruction(Processor * new_cpu,unsigned int new_opcode,unsigned int addr,const char * _name,eAddressingModes addrMode)601 RegisterToRegisterInstruction::RegisterToRegisterInstruction
602 (Processor *new_cpu,
603 unsigned int new_opcode,
604 unsigned int addr,
605 const char *_name,
606 eAddressingModes addrMode
607 )
608 : RegisterInstruction(new_cpu, new_opcode, addr, _name),
609 m_addrMode(addrMode)
610 {
611
612 switch(m_addrMode) {
613 case eRegisterDirect:
614 m_base = new RegDirectAddrMode(cpu_dsPic,opcode & 0xf);
615 m_destination = new RegDirectAddrMode(cpu_dsPic,opcode & 0xf);
616 m_source = new LiteralAddressingMode(cpu_dsPic,
617 (opcode >> 4) & ((opcode & (1 << 14)) ? 0xff : 0x3ff));
618 break;
619 case eRegisterIndirect:
620 m_base = new RegDirectAddrMode(cpu_dsPic, (opcode>>15) & 0xf);
621 m_source = AddressingMode::construct(cpu_dsPic,
622 (opcode >> 4) & 0x7,
623 opcode & 0x1f);
624 m_destination = AddressingMode::construct(cpu_dsPic,
625 (opcode >> 11) & 0x7,
626 (opcode >> 7) & 0xf);
627 break;
628 default:
629 assert(0);
630 }
631 }
632
name(char * buff,int len)633 char *RegisterToRegisterInstruction::name(char *buff,int len)
634 {
635 if (!buff)
636 return buff;
637
638 char cpBase[256];
639 char cpSource[256];
640 char cpDestination[256];
641
642 switch(m_addrMode) {
643 case eRegisterDirect:
644 snprintf(buff, len, "%s%s\t%s, %s",
645 instruction::name().c_str(),
646 (m_bByteOperation ? ".b" :""),
647 m_source->name(cpBase,sizeof(cpBase)),
648 m_destination->name(cpDestination,sizeof(cpDestination))
649 );
650 break;
651 case eRegisterIndirect:
652 snprintf(buff, len, "%s%s\t%s,%s,%s",
653 instruction::name().c_str(),
654 (m_bByteOperation ? ".b" :""),
655 m_base->name(cpBase,sizeof(cpBase)),
656 m_source->name(cpSource,sizeof(cpSource)),
657 m_destination->name(cpDestination,sizeof(cpDestination))
658 );
659 break;
660 default:
661 break;
662 }
663
664 return buff;
665 }
666 //--------------------------------------------------
667
ADDR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr,eAddressingModes addrMode)668 ADDR::ADDR (Processor *new_cpu,
669 unsigned int new_opcode,
670 unsigned int addr,
671 eAddressingModes addrMode)
672 : RegisterToRegisterInstruction(new_cpu, new_opcode, addr,"add",addrMode)
673 {
674 }
675
execute()676 void ADDR::execute()
677 {
678 RegisterValue baseRV(m_base ? m_base->get() : m_destination->get());
679 RegisterValue srcRV (m_source->get());
680 RegisterValue resRV (srcRV);
681
682 resRV.data += baseRV.data;
683 resRV.init |= baseRV.init;
684
685 m_destination->put(resRV);
686
687 unsigned flags =
688 ((resRV.data & 0xffff ) ? 0 : eZ) |
689 ((resRV.data & 0x10000 ) ? eC : 0) |
690 (((resRV.data ^ baseRV.data ^ srcRV.data)&0x10) ? eDC : 0) |
691 ((((resRV.data & ~baseRV.data & ~srcRV.data) |
692 (~resRV.data & baseRV.data & srcRV.data)) & 0x8000) ? eOV : 0) |
693 ((resRV.data & 0x8000 ) ? eN : 0);
694
695 cpu_dsPic->m_status.putFlags(flags, eC|eZ|eOV|eN|eDC, 0);
696 cpu_dsPic->pc->increment();
697 }
698
699 //--------------------------------------------------
700 /*
701 ADDL::ADDL (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
702 : RegisterDirectLiteralInstruction(new_cpu, new_opcode, addr,"add")
703 {
704 }
705
706 void ADDL::execute()
707 {
708 cpu_dsPic->pc->increment();
709 }
710 */
711 //--------------------------------------------------
712
ADD(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)713 ADD::ADD (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
714 : instruction(new_cpu, new_opcode, addr)
715 {
716
717 decode(new_cpu,new_opcode);
718 new_name("add");
719 printf("constructing a ADD\n");
720 }
721
execute()722 void ADD::execute()
723 {
724 cpu_dsPic->pc->increment();
725 }
726
727 //--------------------------------------------------
728
ADDC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)729 ADDC::ADDC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
730 : instruction(new_cpu, new_opcode, addr)
731 {
732
733 decode(new_cpu,new_opcode);
734 new_name("addc");
735 printf("constructing a ADDC\n");
736 }
737
execute()738 void ADDC::execute()
739 {
740 }
741
742
743 //--------------------------------------------------
744
AND(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)745 AND::AND (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
746 : instruction(new_cpu, new_opcode, addr)
747 {
748
749 decode(new_cpu,new_opcode);
750 new_name("and");
751 printf("constructing a AND\n");
752 }
753
execute()754 void AND::execute()
755 {
756 }
757
758 //--------------------------------------------------
759
ASR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)760 ASR::ASR (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
761 : instruction(new_cpu, new_opcode, addr)
762 {
763
764 decode(new_cpu,new_opcode);
765 new_name("asr");
766 printf("constructing a ASR\n");
767 }
768
execute()769 void ASR::execute()
770 {
771 }
772
773 //--------------------------------------------------
774
BCLR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)775 BCLR::BCLR (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
776 : instruction(new_cpu, new_opcode, addr)
777 {
778
779 decode(new_cpu,new_opcode);
780 new_name("bclr");
781 printf("constructing a BCLR\n");
782 }
783
execute()784 void BCLR::execute()
785 {
786 }
787
788 //--------------------------------------------------
789
BRA(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)790 BRA::BRA (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
791 : LiteralBranch(new_cpu, new_opcode, addr, "bra"),
792 m_condition(0)
793 {
794 new_name("bra");
795 switch ((opcode>>16) & 0x0f) {
796 case OV: // Overflow
797 mcP_conditionName = "OV,";
798 break;
799 case C: // Carry and GEU
800 mcP_conditionName = "C,";
801 break;
802 case Z: // Zero
803 mcP_conditionName = "Z,";
804 break;
805 case N: // Negative
806 mcP_conditionName = "N,";
807 break;
808 case LE: // Less than or equal to
809 mcP_conditionName = "LE,";
810 break;
811 case LT: // Less than
812 mcP_conditionName = "LT,";
813 break;
814 case LEU: // Less than or equal unsigned
815 mcP_conditionName = "LEU,";
816 break;
817 case UN: // Unconditionally
818 mcP_conditionName = "";
819 break;
820 case NOV: // No overflow
821 mcP_conditionName = "NOV,";
822 break;
823 case NC: // No Carry and LTU (less than unsigned)
824 mcP_conditionName = "NC,";
825 break;
826 case NZ: // Not zero
827 mcP_conditionName = "NZ,";
828 break;
829 case NN: // Not Negative
830 mcP_conditionName = "NN,";
831 break;
832 case GT: // Greater than
833 mcP_conditionName = "GT,";
834 break;
835 case GE: // Greater than or equal
836 mcP_conditionName = "GE,";
837 break;
838 case GTU: // Greater than unsigned
839 mcP_conditionName = "GTU,";
840 break;
841 case NU: // not used...
842 default:
843 break;
844
845 }
846 }
847
execute()848 void BRA::execute()
849 {
850 if (m_condition)
851 cpu_dsPic->pc->jump(m_destination>>1);
852 else
853 cpu_dsPic->pc->increment();
854 }
855
856 //--------------------------------------------------
857
BSET(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)858 BSET::BSET (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
859 : instruction(new_cpu, new_opcode, addr)
860 {
861
862 decode(new_cpu,new_opcode);
863 new_name("bset");
864 printf("constructing a BSET\n");
865 }
866
execute()867 void BSET::execute()
868 {
869 }
870
871 //--------------------------------------------------
872
BSW(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)873 BSW::BSW (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
874 : instruction(new_cpu, new_opcode, addr)
875 {
876
877 decode(new_cpu,new_opcode);
878 new_name("bsw ");
879 printf("constructing a BSW\n");
880 }
881
execute()882 void BSW::execute()
883 {
884 }
885
886 //--------------------------------------------------
887
BTG(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)888 BTG::BTG (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
889 : instruction(new_cpu, new_opcode, addr)
890 {
891
892 decode(new_cpu,new_opcode);
893 new_name("btg ");
894 printf("constructing a BTG\n");
895 }
896
execute()897 void BTG::execute()
898 {
899 }
900
901 //--------------------------------------------------
902
BTS(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)903 BTS::BTS (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
904 : instruction(new_cpu, new_opcode, addr)
905 {
906
907 decode(new_cpu,new_opcode);
908 new_name("bts");
909 printf("constructing a BTS\n");
910 }
911
execute()912 void BTS::execute()
913 {
914 }
915
916 //--------------------------------------------------
917
BTST(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)918 BTST::BTST (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
919 : instruction(new_cpu, new_opcode, addr)
920 {
921
922 decode(new_cpu,new_opcode);
923 new_name("btst");
924 printf("constructing a BTST\n");
925 }
926
execute()927 void BTST::execute()
928 {
929 }
930
931 //--------------------------------------------------
932
BTSTS(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)933 BTSTS::BTSTS (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
934 : instruction(new_cpu, new_opcode, addr)
935 {
936
937 decode(new_cpu,new_opcode);
938 new_name("btsts");
939 printf("constructing a BTSTS\n");
940 }
941
execute()942 void BTSTS::execute()
943 {
944 }
945
946 //--------------------------------------------------
947
CALL(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)948 CALL::CALL (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
949 : instruction(new_cpu, new_opcode, addr)
950 {
951
952 decode(new_cpu,new_opcode);
953 new_name("call");
954 printf("constructing a CALL\n");
955 }
956
execute()957 void CALL::execute()
958 {
959 }
960
961 //--------------------------------------------------
962
CLR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)963 CLR::CLR (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
964 : instruction(new_cpu, new_opcode, addr)
965 {
966
967 decode(new_cpu,new_opcode);
968 new_name("clr");
969 printf("constructing a CLR\n");
970 }
971
execute()972 void CLR::execute()
973 {
974 }
975
976 //--------------------------------------------------
977
CLRWDT(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)978 CLRWDT::CLRWDT (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
979 : instruction(new_cpu, new_opcode, addr)
980 {
981
982 decode(new_cpu,new_opcode);
983 new_name("clrwdt");
984 printf("constructing a CLRWDT\n");
985 }
986
execute()987 void CLRWDT::execute()
988 {
989 }
990
991 //--------------------------------------------------
992
COM(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)993 COM::COM (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
994 : instruction(new_cpu, new_opcode, addr)
995 {
996
997 decode(new_cpu,new_opcode);
998 new_name("com");
999 printf("constructing a COM\n");
1000 }
1001
execute()1002 void COM::execute()
1003 {
1004 }
1005
1006 //--------------------------------------------------
1007
CP(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1008 CP::CP (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1009 : instruction(new_cpu, new_opcode, addr)
1010 {
1011
1012 decode(new_cpu,new_opcode);
1013 new_name("cp");
1014 printf("constructing a CP\n");
1015 }
1016
execute()1017 void CP::execute()
1018 {
1019 }
1020
1021 //--------------------------------------------------
1022
CP0(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1023 CP0::CP0 (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1024 : instruction(new_cpu, new_opcode, addr)
1025 {
1026
1027 decode(new_cpu,new_opcode);
1028 new_name("cp0");
1029 printf("constructing a CP0\n");
1030 }
1031
execute()1032 void CP0::execute()
1033 {
1034 }
1035
1036 //--------------------------------------------------
1037
CPB(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1038 CPB::CPB (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1039 : instruction(new_cpu, new_opcode, addr)
1040 {
1041
1042 decode(new_cpu,new_opcode);
1043 new_name("cpb");
1044 printf("constructing a CPB\n");
1045 }
1046
execute()1047 void CPB::execute()
1048 {
1049 }
1050
1051 //--------------------------------------------------
1052
CPS(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1053 CPS::CPS (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1054 : instruction(new_cpu, new_opcode, addr)
1055 {
1056
1057 decode(new_cpu,new_opcode);
1058 new_name("cps");
1059 printf("constructing a CPS\n");
1060 }
1061
execute()1062 void CPS::execute()
1063 {
1064 }
1065
1066 //--------------------------------------------------
1067
DAW(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1068 DAW::DAW (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1069 : instruction(new_cpu, new_opcode, addr)
1070 {
1071
1072 decode(new_cpu,new_opcode);
1073 new_name("daw");
1074 printf("constructing a DAW\n");
1075 }
1076
execute()1077 void DAW::execute()
1078 {
1079 }
1080
1081 //--------------------------------------------------
1082
DEC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1083 DEC::DEC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1084 : instruction(new_cpu, new_opcode, addr)
1085 {
1086
1087 decode(new_cpu,new_opcode);
1088 new_name("dec");
1089 printf("constructing a DEC\n");
1090 }
1091
execute()1092 void DEC::execute()
1093 {
1094 }
1095
1096 //--------------------------------------------------
1097
DISI(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1098 DISI::DISI (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1099 : instruction(new_cpu, new_opcode, addr)
1100 {
1101
1102 decode(new_cpu,new_opcode);
1103 new_name("disi");
1104 printf("constructing a DISI\n");
1105 }
1106
execute()1107 void DISI::execute()
1108 {
1109 }
1110
1111 //--------------------------------------------------
1112
DIV(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1113 DIV::DIV (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1114 : instruction(new_cpu, new_opcode, addr)
1115 {
1116
1117 decode(new_cpu,new_opcode);
1118 new_name("div");
1119 printf("constructing a DIV\n");
1120 }
1121
execute()1122 void DIV::execute()
1123 {
1124 }
1125
1126 //--------------------------------------------------
1127
DO(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1128 DO::DO (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1129 : instruction(new_cpu, new_opcode, addr)
1130 {
1131
1132 decode(new_cpu,new_opcode);
1133 new_name("do");
1134 printf("constructing a DO\n");
1135 }
1136
execute()1137 void DO::execute()
1138 {
1139 }
1140
1141 //--------------------------------------------------
1142
ED(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1143 ED::ED (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1144 : instruction(new_cpu, new_opcode, addr)
1145 {
1146
1147 decode(new_cpu,new_opcode);
1148 new_name("ed");
1149 printf("constructing a ED\n");
1150 }
1151
execute()1152 void ED::execute()
1153 {
1154 }
1155
1156 //--------------------------------------------------
1157
EXCH(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1158 EXCH::EXCH (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1159 : instruction(new_cpu, new_opcode, addr)
1160 {
1161
1162 decode(new_cpu,new_opcode);
1163 new_name("exch");
1164 printf("constructing a EXCH\n");
1165 }
1166
execute()1167 void EXCH::execute()
1168 {
1169 }
1170
1171 //--------------------------------------------------
1172
FB(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1173 FB::FB (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1174 : instruction(new_cpu, new_opcode, addr)
1175 {
1176
1177 decode(new_cpu,new_opcode);
1178 new_name("fb");
1179 printf("constructing a FB\n");
1180 }
1181
execute()1182 void FB::execute()
1183 {
1184 }
1185
1186 //--------------------------------------------------
1187
GOTO(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1188 GOTO::GOTO (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1189 : MultiWordBranch(new_cpu, new_opcode, addr)
1190 {
1191
1192 decode(new_cpu,new_opcode);
1193 new_name("goto");
1194 printf("constructing a GOTO\n");
1195 }
1196
execute()1197 void GOTO::execute()
1198 {
1199 if(!initialized)
1200 runtime_initialize();
1201
1202 cpu_dsPic->pc->jump(destination_index);
1203
1204 }
1205
1206 //--------------------------------------------------
1207
INC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1208 INC::INC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1209 : instruction(new_cpu, new_opcode, addr)
1210 {
1211
1212 decode(new_cpu,new_opcode);
1213 new_name("inc");
1214 printf("constructing a INC\n");
1215 }
1216
execute()1217 void INC::execute()
1218 {
1219 }
1220
1221 //--------------------------------------------------
1222
IOR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1223 IOR::IOR (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1224 : instruction(new_cpu, new_opcode, addr)
1225 {
1226
1227 decode(new_cpu,new_opcode);
1228 new_name("ior");
1229 printf("constructing a IOR\n");
1230 }
1231
execute()1232 void IOR::execute()
1233 {
1234 }
1235
1236 //--------------------------------------------------
1237
LAC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1238 LAC::LAC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1239 : instruction(new_cpu, new_opcode, addr)
1240 {
1241
1242 decode(new_cpu,new_opcode);
1243 new_name("lac");
1244 printf("constructing a LAC\n");
1245 }
1246
execute()1247 void LAC::execute()
1248 {
1249 }
1250
1251 //--------------------------------------------------
1252
LNK(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1253 LNK::LNK (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1254 : ImmediateInstruction(new_cpu, new_opcode, addr)
1255 {
1256 new_name("lnk");
1257 }
1258
execute()1259 void LNK::execute()
1260 {
1261 unsigned int tos = cpu_dsPic->W[15].get_value();
1262 unsigned int tos_index = tos>>1;
1263 cpu_dsPic->registers[tos_index]->put(cpu_dsPic->W[14].get());
1264 cpu_dsPic->W[14].put(tos+2);
1265 cpu_dsPic->W[15].put(tos+2+m_L);
1266
1267 cpu_dsPic->pc->increment();
1268
1269 }
1270
1271 //--------------------------------------------------
1272
LSR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1273 LSR::LSR (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1274 : instruction(new_cpu, new_opcode, addr)
1275 {
1276
1277 decode(new_cpu,new_opcode);
1278 new_name("lsr");
1279 printf("constructing a LSR\n");
1280 }
1281
execute()1282 void LSR::execute()
1283 {
1284 }
1285
1286 //--------------------------------------------------
1287
MAC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1288 MAC::MAC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1289 : instruction(new_cpu, new_opcode, addr)
1290 {
1291
1292 decode(new_cpu,new_opcode);
1293 new_name("mac");
1294 printf("constructing a MAC\n");
1295 }
1296
execute()1297 void MAC::execute()
1298 {
1299 }
1300
1301 //--------------------------------------------------
1302
MOV(Processor * new_cpu,unsigned int new_opcode,unsigned int addr,eAddressingModes addrMode)1303 MOV::MOV (Processor *new_cpu,
1304 unsigned int new_opcode,
1305 unsigned int addr,
1306 eAddressingModes addrMode)
1307 : RegisterToRegisterInstruction(new_cpu, new_opcode, addr,"mov",addrMode)
1308 {
1309 printf("MOV instruction opcode:0x%x mode=%d\n",opcode,m_addrMode);
1310 }
1311
execute()1312 void MOV::execute()
1313 {
1314 RegisterValue baseRV(m_base ? m_base->get() : m_destination->get());
1315 RegisterValue srcRV (m_source->get());
1316 RegisterValue resRV (srcRV);
1317
1318 resRV.data += baseRV.data;
1319 resRV.init |= baseRV.init;
1320
1321 m_destination->put(resRV);
1322
1323 unsigned flags =
1324 ((resRV.data & 0xffff ) ? 0 : eZ) |
1325 ((resRV.data & 0x10000 ) ? eC : 0) |
1326 (((resRV.data ^ baseRV.data ^ srcRV.data)&0x10) ? eDC : 0) |
1327 ((((resRV.data & ~baseRV.data & ~srcRV.data) |
1328 (~resRV.data & baseRV.data & srcRV.data)) & 0x8000) ? eOV : 0) |
1329 ((resRV.data & 0x8000 ) ? eN : 0);
1330
1331 cpu_dsPic->m_status.putFlags(flags, eC|eZ|eOV|eN|eDC, 0);
1332 cpu_dsPic->pc->increment();
1333 }
1334
1335
1336 //--------------------------------------------------
1337
MOVSAC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1338 MOVSAC::MOVSAC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1339 : instruction(new_cpu, new_opcode, addr)
1340 {
1341
1342 decode(new_cpu,new_opcode);
1343 new_name("movsac");
1344 printf("constructing a MOVSAC\n");
1345 }
1346
execute()1347 void MOVSAC::execute()
1348 {
1349 }
1350
1351 //--------------------------------------------------
1352
MPY(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1353 MPY::MPY (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1354 : instruction(new_cpu, new_opcode, addr)
1355 {
1356
1357 decode(new_cpu,new_opcode);
1358 new_name("mpy");
1359 printf("constructing a MPY\n");
1360 }
1361
execute()1362 void MPY::execute()
1363 {
1364 }
1365
1366 //--------------------------------------------------
1367
MUL(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1368 MUL::MUL (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1369 : instruction(new_cpu, new_opcode, addr)
1370 {
1371
1372 decode(new_cpu,new_opcode);
1373 new_name("mul");
1374 printf("constructing a MUL\n");
1375 }
1376
execute()1377 void MUL::execute()
1378 {
1379 }
1380
1381 //--------------------------------------------------
1382
NEG(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1383 NEG::NEG (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1384 : instruction(new_cpu, new_opcode, addr)
1385 {
1386
1387 decode(new_cpu,new_opcode);
1388 new_name("neg");
1389 printf("constructing a NEG\n");
1390 }
1391
execute()1392 void NEG::execute()
1393 {
1394 }
1395
1396 //--------------------------------------------------
1397
NOP(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1398 NOP::NOP (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1399 : instruction(new_cpu, new_opcode, addr)
1400 {
1401
1402 decode(new_cpu,new_opcode);
1403 new_name("nop");
1404
1405 // For the 18cxxx family, this 'nop' may in fact be the
1406 // 2nd word in a 2-word opcode. So just to be safe, let's
1407 // initialize the cross references to the source file.
1408 // (Subsequent initialization code will overwrite this,
1409 // but there is a chance that this info will be accessed
1410 // before that occurs).
1411
1412 //printf("constructing a NOP\n");
1413 }
1414
execute()1415 void NOP::execute()
1416 {
1417 //cpu_pic->pc->increment();
1418 }
1419
1420 //--------------------------------------------------
1421
POP(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1422 POP::POP (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1423 : instruction(new_cpu, new_opcode, addr)
1424 {
1425
1426 decode(new_cpu,new_opcode);
1427 new_name("pop");
1428 printf("constructing a POP\n");
1429 }
1430
execute()1431 void POP::execute()
1432 {
1433 }
1434
1435 //--------------------------------------------------
1436
PUSH(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1437 PUSH::PUSH (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1438 : instruction(new_cpu, new_opcode, addr)
1439 {
1440
1441 decode(new_cpu,new_opcode);
1442 new_name("push");
1443 printf("constructing a PUSH\n");
1444 }
1445
execute()1446 void PUSH::execute()
1447 {
1448 }
1449
1450 //--------------------------------------------------
1451
PWRSAV(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1452 PWRSAV::PWRSAV (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1453 : instruction(new_cpu, new_opcode, addr)
1454 {
1455
1456 decode(new_cpu,new_opcode);
1457 new_name("pwrsav");
1458 printf("constructing a PWRSAV\n");
1459 }
1460
execute()1461 void PWRSAV::execute()
1462 {
1463 }
1464
1465 //--------------------------------------------------
1466
RCALL(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1467 RCALL::RCALL (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1468 : LiteralBranch(new_cpu, new_opcode, addr,"rcall")
1469 {
1470 }
1471
execute()1472 void RCALL::execute()
1473 {
1474 cpu_dsPic->m_stack.push();
1475 cpu_dsPic->pc->jump(m_destination>>1);
1476 }
1477
1478 //--------------------------------------------------
1479
REPEAT(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1480 REPEAT::REPEAT (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1481 : instruction(new_cpu, new_opcode, addr)
1482 {
1483
1484 decode(new_cpu,new_opcode);
1485 new_name("repeat");
1486 printf("constructing a REPEAT\n");
1487 }
1488
execute()1489 void REPEAT::execute()
1490 {
1491 }
1492
1493 //--------------------------------------------------
1494
RESET(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1495 RESET::RESET (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1496 : instruction(new_cpu, new_opcode, addr)
1497 {
1498
1499 decode(new_cpu,new_opcode);
1500 new_name("reset");
1501 printf("constructing a RESET\n");
1502 }
1503
execute()1504 void RESET::execute()
1505 {
1506 }
1507
1508 //--------------------------------------------------
1509
RET(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1510 RET::RET (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1511 : instruction(new_cpu, new_opcode, addr)
1512 {
1513
1514 decode(new_cpu,new_opcode);
1515 new_name("ret");
1516 printf("constructing a RET\n");
1517 }
1518
execute()1519 void RET::execute()
1520 {
1521 }
1522
1523 //--------------------------------------------------
1524
ROT(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1525 ROT::ROT (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1526 : instruction(new_cpu, new_opcode, addr)
1527 {
1528
1529 decode(new_cpu,new_opcode);
1530 new_name("rot");
1531 printf("constructing a ROT\n");
1532 }
1533
execute()1534 void ROT::execute()
1535 {
1536 }
1537
1538 //--------------------------------------------------
1539
SAC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1540 SAC::SAC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1541 : instruction(new_cpu, new_opcode, addr)
1542 {
1543
1544 decode(new_cpu,new_opcode);
1545 new_name("sac");
1546 printf("constructing a SAC\n");
1547 }
1548
execute()1549 void SAC::execute()
1550 {
1551 }
1552
1553 //--------------------------------------------------
1554
SE(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1555 SE::SE (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1556 : instruction(new_cpu, new_opcode, addr)
1557 {
1558
1559 decode(new_cpu,new_opcode);
1560 new_name("se");
1561 printf("constructing a SE\n");
1562 }
1563
execute()1564 void SE::execute()
1565 {
1566 }
1567
1568 //--------------------------------------------------
1569
SETM(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1570 SETM::SETM (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1571 : instruction(new_cpu, new_opcode, addr)
1572 {
1573
1574 decode(new_cpu,new_opcode);
1575 new_name("setm");
1576 printf("constructing a SETM\n");
1577 }
1578
execute()1579 void SETM::execute()
1580 {
1581 }
1582
1583 //--------------------------------------------------
1584
SFTAC(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1585 SFTAC::SFTAC (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1586 : instruction(new_cpu, new_opcode, addr)
1587 {
1588
1589 decode(new_cpu,new_opcode);
1590 new_name("sftac");
1591 printf("constructing a SFTAC\n");
1592 }
1593
execute()1594 void SFTAC::execute()
1595 {
1596 }
1597
1598 //--------------------------------------------------
1599
SL(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1600 SL::SL (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1601 : instruction(new_cpu, new_opcode, addr)
1602 {
1603
1604 decode(new_cpu,new_opcode);
1605 new_name("sl");
1606 printf("constructing a SL\n");
1607 }
1608
execute()1609 void SL::execute()
1610 {
1611 }
1612
1613 //--------------------------------------------------
1614
SUB(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1615 SUB::SUB (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1616 : instruction(new_cpu, new_opcode, addr)
1617 {
1618
1619 decode(new_cpu,new_opcode);
1620 new_name("sub");
1621 printf("constructing a SUB\n");
1622 }
1623
execute()1624 void SUB::execute()
1625 {
1626 }
1627
1628 //--------------------------------------------------
1629
SWAP(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1630 SWAP::SWAP (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1631 : instruction(new_cpu, new_opcode, addr)
1632 {
1633
1634 decode(new_cpu,new_opcode);
1635 new_name("swap");
1636 printf("constructing a SWAP\n");
1637 }
1638
execute()1639 void SWAP::execute()
1640 {
1641 }
1642
1643 //--------------------------------------------------
1644
TBLRD(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1645 TBLRD::TBLRD (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1646 : instruction(new_cpu, new_opcode, addr)
1647 {
1648
1649 decode(new_cpu,new_opcode);
1650 new_name("tblrd");
1651 printf("constructing a TBLRD\n");
1652 }
1653
execute()1654 void TBLRD::execute()
1655 {
1656 }
1657
1658 //--------------------------------------------------
1659
TBLWT(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1660 TBLWT::TBLWT (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1661 : instruction(new_cpu, new_opcode, addr)
1662 {
1663
1664 decode(new_cpu,new_opcode);
1665 new_name("tblwt");
1666 printf("constructing a TBLWT\n");
1667 }
1668
execute()1669 void TBLWT::execute()
1670 {
1671 }
1672
1673 //--------------------------------------------------
1674
ULNK(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1675 ULNK::ULNK (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1676 : instruction(new_cpu, new_opcode, addr)
1677 {
1678
1679 decode(new_cpu,new_opcode);
1680 new_name("ulnk");
1681 printf("constructing a ULNK\n");
1682 }
1683
execute()1684 void ULNK::execute()
1685 {
1686 }
1687
1688 //--------------------------------------------------
1689
XOR(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1690 XOR::XOR (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1691 : instruction(new_cpu, new_opcode, addr)
1692 {
1693
1694 decode(new_cpu,new_opcode);
1695 new_name("xor");
1696 printf("constructing a XOR\n");
1697 }
1698
execute()1699 void XOR::execute()
1700 {
1701 }
1702
1703 //--------------------------------------------------
1704
ZE(Processor * new_cpu,unsigned int new_opcode,unsigned int addr)1705 ZE::ZE (Processor *new_cpu, unsigned int new_opcode, unsigned int addr)
1706 : instruction(new_cpu, new_opcode, addr)
1707 {
1708
1709 decode(new_cpu,new_opcode);
1710 new_name("ZE");
1711 printf("constructing a ZE\n");
1712 }
1713
execute()1714 void ZE::execute()
1715 {
1716 }
1717
1718
1719 };
1720