1 /* $NetBSD: v10_structs.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef V10_STRUCTS_H_ 27 #define V10_STRUCTS_H_ 28 29 struct v10_gfx_mqd 30 { 31 uint32_t reserved_0; // offset: 0 (0x0) 32 uint32_t reserved_1; // offset: 1 (0x1) 33 uint32_t reserved_2; // offset: 2 (0x2) 34 uint32_t reserved_3; // offset: 3 (0x3) 35 uint32_t reserved_4; // offset: 4 (0x4) 36 uint32_t reserved_5; // offset: 5 (0x5) 37 uint32_t reserved_6; // offset: 6 (0x6) 38 uint32_t reserved_7; // offset: 7 (0x7) 39 uint32_t reserved_8; // offset: 8 (0x8) 40 uint32_t reserved_9; // offset: 9 (0x9) 41 uint32_t reserved_10; // offset: 10 (0xA) 42 uint32_t reserved_11; // offset: 11 (0xB) 43 uint32_t reserved_12; // offset: 12 (0xC) 44 uint32_t reserved_13; // offset: 13 (0xD) 45 uint32_t reserved_14; // offset: 14 (0xE) 46 uint32_t reserved_15; // offset: 15 (0xF) 47 uint32_t reserved_16; // offset: 16 (0x10) 48 uint32_t reserved_17; // offset: 17 (0x11) 49 uint32_t reserved_18; // offset: 18 (0x12) 50 uint32_t reserved_19; // offset: 19 (0x13) 51 uint32_t reserved_20; // offset: 20 (0x14) 52 uint32_t reserved_21; // offset: 21 (0x15) 53 uint32_t reserved_22; // offset: 22 (0x16) 54 uint32_t reserved_23; // offset: 23 (0x17) 55 uint32_t reserved_24; // offset: 24 (0x18) 56 uint32_t reserved_25; // offset: 25 (0x19) 57 uint32_t reserved_26; // offset: 26 (0x1A) 58 uint32_t reserved_27; // offset: 27 (0x1B) 59 uint32_t reserved_28; // offset: 28 (0x1C) 60 uint32_t reserved_29; // offset: 29 (0x1D) 61 uint32_t reserved_30; // offset: 30 (0x1E) 62 uint32_t reserved_31; // offset: 31 (0x1F) 63 uint32_t reserved_32; // offset: 32 (0x20) 64 uint32_t reserved_33; // offset: 33 (0x21) 65 uint32_t reserved_34; // offset: 34 (0x22) 66 uint32_t reserved_35; // offset: 35 (0x23) 67 uint32_t reserved_36; // offset: 36 (0x24) 68 uint32_t reserved_37; // offset: 37 (0x25) 69 uint32_t reserved_38; // offset: 38 (0x26) 70 uint32_t reserved_39; // offset: 39 (0x27) 71 uint32_t reserved_40; // offset: 40 (0x28) 72 uint32_t reserved_41; // offset: 41 (0x29) 73 uint32_t reserved_42; // offset: 42 (0x2A) 74 uint32_t reserved_43; // offset: 43 (0x2B) 75 uint32_t reserved_44; // offset: 44 (0x2C) 76 uint32_t reserved_45; // offset: 45 (0x2D) 77 uint32_t reserved_46; // offset: 46 (0x2E) 78 uint32_t reserved_47; // offset: 47 (0x2F) 79 uint32_t reserved_48; // offset: 48 (0x30) 80 uint32_t reserved_49; // offset: 49 (0x31) 81 uint32_t reserved_50; // offset: 50 (0x32) 82 uint32_t reserved_51; // offset: 51 (0x33) 83 uint32_t reserved_52; // offset: 52 (0x34) 84 uint32_t reserved_53; // offset: 53 (0x35) 85 uint32_t reserved_54; // offset: 54 (0x36) 86 uint32_t reserved_55; // offset: 55 (0x37) 87 uint32_t reserved_56; // offset: 56 (0x38) 88 uint32_t reserved_57; // offset: 57 (0x39) 89 uint32_t reserved_58; // offset: 58 (0x3A) 90 uint32_t reserved_59; // offset: 59 (0x3B) 91 uint32_t reserved_60; // offset: 60 (0x3C) 92 uint32_t reserved_61; // offset: 61 (0x3D) 93 uint32_t reserved_62; // offset: 62 (0x3E) 94 uint32_t reserved_63; // offset: 63 (0x3F) 95 uint32_t reserved_64; // offset: 64 (0x40) 96 uint32_t reserved_65; // offset: 65 (0x41) 97 uint32_t reserved_66; // offset: 66 (0x42) 98 uint32_t reserved_67; // offset: 67 (0x43) 99 uint32_t reserved_68; // offset: 68 (0x44) 100 uint32_t reserved_69; // offset: 69 (0x45) 101 uint32_t reserved_70; // offset: 70 (0x46) 102 uint32_t reserved_71; // offset: 71 (0x47) 103 uint32_t reserved_72; // offset: 72 (0x48) 104 uint32_t reserved_73; // offset: 73 (0x49) 105 uint32_t reserved_74; // offset: 74 (0x4A) 106 uint32_t reserved_75; // offset: 75 (0x4B) 107 uint32_t reserved_76; // offset: 76 (0x4C) 108 uint32_t reserved_77; // offset: 77 (0x4D) 109 uint32_t reserved_78; // offset: 78 (0x4E) 110 uint32_t reserved_79; // offset: 79 (0x4F) 111 uint32_t reserved_80; // offset: 80 (0x50) 112 uint32_t reserved_81; // offset: 81 (0x51) 113 uint32_t reserved_82; // offset: 82 (0x52) 114 uint32_t reserved_83; // offset: 83 (0x53) 115 uint32_t reserved_84; // offset: 84 (0x54) 116 uint32_t reserved_85; // offset: 85 (0x55) 117 uint32_t reserved_86; // offset: 86 (0x56) 118 uint32_t reserved_87; // offset: 87 (0x57) 119 uint32_t reserved_88; // offset: 88 (0x58) 120 uint32_t reserved_89; // offset: 89 (0x59) 121 uint32_t reserved_90; // offset: 90 (0x5A) 122 uint32_t reserved_91; // offset: 91 (0x5B) 123 uint32_t reserved_92; // offset: 92 (0x5C) 124 uint32_t reserved_93; // offset: 93 (0x5D) 125 uint32_t reserved_94; // offset: 94 (0x5E) 126 uint32_t reserved_95; // offset: 95 (0x5F) 127 uint32_t reserved_96; // offset: 96 (0x60) 128 uint32_t reserved_97; // offset: 97 (0x61) 129 uint32_t reserved_98; // offset: 98 (0x62) 130 uint32_t reserved_99; // offset: 99 (0x63) 131 uint32_t reserved_100; // offset: 100 (0x64) 132 uint32_t reserved_101; // offset: 101 (0x65) 133 uint32_t reserved_102; // offset: 102 (0x66) 134 uint32_t reserved_103; // offset: 103 (0x67) 135 uint32_t reserved_104; // offset: 104 (0x68) 136 uint32_t reserved_105; // offset: 105 (0x69) 137 uint32_t disable_queue; // offset: 106 (0x6A) 138 uint32_t reserved_107; // offset: 107 (0x6B) 139 uint32_t reserved_108; // offset: 108 (0x6C) 140 uint32_t reserved_109; // offset: 109 (0x6D) 141 uint32_t reserved_110; // offset: 110 (0x6E) 142 uint32_t reserved_111; // offset: 111 (0x6F) 143 uint32_t reserved_112; // offset: 112 (0x70) 144 uint32_t reserved_113; // offset: 113 (0x71) 145 uint32_t reserved_114; // offset: 114 (0x72) 146 uint32_t reserved_115; // offset: 115 (0x73) 147 uint32_t reserved_116; // offset: 116 (0x74) 148 uint32_t reserved_117; // offset: 117 (0x75) 149 uint32_t reserved_118; // offset: 118 (0x76) 150 uint32_t reserved_119; // offset: 119 (0x77) 151 uint32_t reserved_120; // offset: 120 (0x78) 152 uint32_t reserved_121; // offset: 121 (0x79) 153 uint32_t reserved_122; // offset: 122 (0x7A) 154 uint32_t reserved_123; // offset: 123 (0x7B) 155 uint32_t reserved_124; // offset: 124 (0x7C) 156 uint32_t reserved_125; // offset: 125 (0x7D) 157 uint32_t reserved_126; // offset: 126 (0x7E) 158 uint32_t reserved_127; // offset: 127 (0x7F) 159 uint32_t cp_mqd_base_addr; // offset: 128 (0x80) 160 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) 161 uint32_t cp_gfx_hqd_active; // offset: 130 (0x82) 162 uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83) 163 uint32_t reserved_131; // offset: 132 (0x84) 164 uint32_t reserved_132; // offset: 133 (0x85) 165 uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86) 166 uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87) 167 uint32_t cp_gfx_hqd_base; // offset: 136 (0x88) 168 uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89) 169 uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A) 170 uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B) 171 uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C) 172 uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D) 173 uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E) 174 uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F) 175 uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90) 176 uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91) 177 uint32_t reserved_146; // offset: 146 (0x92) 178 uint32_t reserved_147; // offset: 147 (0x93) 179 uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94) 180 uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95) 181 uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96) 182 uint32_t reserved_151; // offset: 151 (0x97) 183 uint32_t reserved_152; // offset: 152 (0x98) 184 uint32_t reserved_153; // offset: 153 (0x99) 185 uint32_t reserved_154; // offset: 154 (0x9A) 186 uint32_t reserved_155; // offset: 155 (0x9B) 187 uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C) 188 uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D) 189 uint32_t reserved_158; // offset: 158 (0x9E) 190 uint32_t reserved_159; // offset: 159 (0x9F) 191 uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0) 192 uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1) 193 uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2) 194 uint32_t reserved_163; // offset: 163 (0xA3) 195 uint32_t reserved_164; // offset: 164 (0xA4) 196 uint32_t reserved_165; // offset: 165 (0xA5) 197 uint32_t reserved_166; // offset: 166 (0xA6) 198 uint32_t reserved_167; // offset: 167 (0xA7) 199 uint32_t reserved_168; // offset: 168 (0xA8) 200 uint32_t reserved_169; // offset: 169 (0xA9) 201 uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA) 202 uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB) 203 uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC) 204 uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD) 205 uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE) 206 uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF) 207 uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0) 208 uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1) 209 uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2) 210 uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3) 211 uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4) 212 uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5) 213 uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6) 214 uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7) 215 uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8) 216 uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9) 217 uint32_t reserved_186; // offset: 186 (0xBA) 218 uint32_t reserved_187; // offset: 187 (0xBB) 219 uint32_t reserved_188; // offset: 188 (0xBC) 220 uint32_t reserved_189; // offset: 189 (0xBD) 221 uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE) 222 uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF) 223 uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0) 224 uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1) 225 uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2) 226 uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3) 227 uint32_t sq_thread_trace_mask; // offset: 196 (0xC4) 228 uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5) 229 uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6) 230 uint32_t sq_thread_trace_status; // offset: 199 (0xC7) 231 uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8) 232 uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9) 233 uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA) 234 uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB) 235 uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC) 236 uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD) 237 uint32_t reserved_206; // offset: 206 (0xCE) 238 uint32_t reserved_207; // offset: 207 (0xCF) 239 uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0) 240 uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1) 241 uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2) 242 uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3) 243 uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4) 244 uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5) 245 uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6) 246 uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7) 247 uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8) 248 uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9) 249 uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA) 250 uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB) 251 uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC) 252 uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD) 253 uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE) 254 uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF) 255 uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0) 256 uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1) 257 uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2) 258 uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3) 259 uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4) 260 uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5) 261 uint32_t reserved_230; // offset: 230 (0xE6) 262 uint32_t reserved_231; // offset: 231 (0xE7) 263 uint32_t reserved_232; // offset: 232 (0xE8) 264 uint32_t reserved_233; // offset: 233 (0xE9) 265 uint32_t reserved_234; // offset: 234 (0xEA) 266 uint32_t reserved_235; // offset: 235 (0xEB) 267 uint32_t reserved_236; // offset: 236 (0xEC) 268 uint32_t reserved_237; // offset: 237 (0xED) 269 uint32_t reserved_238; // offset: 238 (0xEE) 270 uint32_t reserved_239; // offset: 239 (0xEF) 271 uint32_t reserved_240; // offset: 240 (0xF0) 272 uint32_t reserved_241; // offset: 241 (0xF1) 273 uint32_t reserved_242; // offset: 242 (0xF2) 274 uint32_t reserved_243; // offset: 243 (0xF3) 275 uint32_t reserved_244; // offset: 244 (0xF4) 276 uint32_t reserved_245; // offset: 245 (0xF5) 277 uint32_t reserved_246; // offset: 246 (0xF6) 278 uint32_t reserved_247; // offset: 247 (0xF7) 279 uint32_t reserved_248; // offset: 248 (0xF8) 280 uint32_t reserved_249; // offset: 249 (0xF9) 281 uint32_t reserved_250; // offset: 250 (0xFA) 282 uint32_t reserved_251; // offset: 251 (0xFB) 283 uint32_t reserved_252; // offset: 252 (0xFC) 284 uint32_t reserved_253; // offset: 253 (0xFD) 285 uint32_t reserved_254; // offset: 254 (0xFE) 286 uint32_t reserved_255; // offset: 255 (0xFF) 287 uint32_t reserved_256; // offset: 256 (0x100) 288 uint32_t reserved_257; // offset: 257 (0x101) 289 uint32_t reserved_258; // offset: 258 (0x102) 290 uint32_t reserved_259; // offset: 259 (0x103) 291 uint32_t reserved_260; // offset: 260 (0x104) 292 uint32_t reserved_261; // offset: 261 (0x105) 293 uint32_t reserved_262; // offset: 262 (0x106) 294 uint32_t reserved_263; // offset: 263 (0x107) 295 uint32_t reserved_264; // offset: 264 (0x108) 296 uint32_t reserved_265; // offset: 265 (0x109) 297 uint32_t reserved_266; // offset: 266 (0x10A) 298 uint32_t reserved_267; // offset: 267 (0x10B) 299 uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C) 300 uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D) 301 uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E) 302 uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F) 303 uint32_t reserved_272; // offset: 272 (0x110) 304 uint32_t reserved_273; // offset: 273 (0x111) 305 uint32_t reserved_274; // offset: 274 (0x112) 306 uint32_t reserved_275; // offset: 275 (0x113) 307 uint32_t vgt_dma_max_size; // offset: 276 (0x114) 308 uint32_t vgt_dma_num_instances; // offset: 277 (0x115) 309 uint32_t reserved_278; // offset: 278 (0x116) 310 uint32_t reserved_279; // offset: 279 (0x117) 311 uint32_t reserved_280; // offset: 280 (0x118) 312 uint32_t reserved_281; // offset: 281 (0x119) 313 uint32_t reserved_282; // offset: 282 (0x11A) 314 uint32_t reserved_283; // offset: 283 (0x11B) 315 uint32_t reserved_284; // offset: 284 (0x11C) 316 uint32_t reserved_285; // offset: 285 (0x11D) 317 uint32_t reserved_286; // offset: 286 (0x11E) 318 uint32_t reserved_287; // offset: 287 (0x11F) 319 uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120) 320 uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121) 321 uint32_t reserved_290; // offset: 290 (0x122) 322 uint32_t reserved_291; // offset: 291 (0x123) 323 uint32_t reserved_292; // offset: 292 (0x124) 324 uint32_t reserved_293; // offset: 293 (0x125) 325 uint32_t reserved_294; // offset: 294 (0x126) 326 uint32_t reserved_295; // offset: 295 (0x127) 327 uint32_t reserved_296; // offset: 296 (0x128) 328 uint32_t reserved_297; // offset: 297 (0x129) 329 uint32_t reserved_298; // offset: 298 (0x12A) 330 uint32_t reserved_299; // offset: 299 (0x12B) 331 uint32_t reserved_300; // offset: 300 (0x12C) 332 uint32_t reserved_301; // offset: 301 (0x12D) 333 uint32_t reserved_302; // offset: 302 (0x12E) 334 uint32_t reserved_303; // offset: 303 (0x12F) 335 uint32_t reserved_304; // offset: 304 (0x130) 336 uint32_t reserved_305; // offset: 305 (0x131) 337 uint32_t reserved_306; // offset: 306 (0x132) 338 uint32_t reserved_307; // offset: 307 (0x133) 339 uint32_t reserved_308; // offset: 308 (0x134) 340 uint32_t reserved_309; // offset: 309 (0x135) 341 uint32_t reserved_310; // offset: 310 (0x136) 342 uint32_t reserved_311; // offset: 311 (0x137) 343 uint32_t reserved_312; // offset: 312 (0x138) 344 uint32_t reserved_313; // offset: 313 (0x139) 345 uint32_t reserved_314; // offset: 314 (0x13A) 346 uint32_t reserved_315; // offset: 315 (0x13B) 347 uint32_t reserved_316; // offset: 316 (0x13C) 348 uint32_t reserved_317; // offset: 317 (0x13D) 349 uint32_t reserved_318; // offset: 318 (0x13E) 350 uint32_t reserved_319; // offset: 319 (0x13F) 351 uint32_t reserved_320; // offset: 320 (0x140) 352 uint32_t reserved_321; // offset: 321 (0x141) 353 uint32_t reserved_322; // offset: 322 (0x142) 354 uint32_t reserved_323; // offset: 323 (0x143) 355 uint32_t reserved_324; // offset: 324 (0x144) 356 uint32_t reserved_325; // offset: 325 (0x145) 357 uint32_t reserved_326; // offset: 326 (0x146) 358 uint32_t reserved_327; // offset: 327 (0x147) 359 uint32_t reserved_328; // offset: 328 (0x148) 360 uint32_t reserved_329; // offset: 329 (0x149) 361 uint32_t reserved_330; // offset: 330 (0x14A) 362 uint32_t reserved_331; // offset: 331 (0x14B) 363 uint32_t reserved_332; // offset: 332 (0x14C) 364 uint32_t reserved_333; // offset: 333 (0x14D) 365 uint32_t reserved_334; // offset: 334 (0x14E) 366 uint32_t reserved_335; // offset: 335 (0x14F) 367 uint32_t reserved_336; // offset: 336 (0x150) 368 uint32_t reserved_337; // offset: 337 (0x151) 369 uint32_t reserved_338; // offset: 338 (0x152) 370 uint32_t reserved_339; // offset: 339 (0x153) 371 uint32_t reserved_340; // offset: 340 (0x154) 372 uint32_t reserved_341; // offset: 341 (0x155) 373 uint32_t reserved_342; // offset: 342 (0x156) 374 uint32_t reserved_343; // offset: 343 (0x157) 375 uint32_t reserved_344; // offset: 344 (0x158) 376 uint32_t reserved_345; // offset: 345 (0x159) 377 uint32_t reserved_346; // offset: 346 (0x15A) 378 uint32_t reserved_347; // offset: 347 (0x15B) 379 uint32_t reserved_348; // offset: 348 (0x15C) 380 uint32_t reserved_349; // offset: 349 (0x15D) 381 uint32_t reserved_350; // offset: 350 (0x15E) 382 uint32_t reserved_351; // offset: 351 (0x15F) 383 uint32_t reserved_352; // offset: 352 (0x160) 384 uint32_t reserved_353; // offset: 353 (0x161) 385 uint32_t reserved_354; // offset: 354 (0x162) 386 uint32_t reserved_355; // offset: 355 (0x163) 387 uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164) 388 uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165) 389 uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166) 390 uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167) 391 uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168) 392 uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169) 393 uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A) 394 uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B) 395 uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C) 396 uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D) 397 uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E) 398 uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F) 399 uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170) 400 uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171) 401 uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172) 402 uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173) 403 uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174) 404 uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175) 405 uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176) 406 uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177) 407 uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178) 408 uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179) 409 uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A) 410 uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B) 411 uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C) 412 uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D) 413 uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E) 414 uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F) 415 uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180) 416 uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181) 417 uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182) 418 uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183) 419 uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184) 420 uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185) 421 uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186) 422 uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187) 423 uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188) 424 uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189) 425 uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A) 426 uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B) 427 uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C) 428 uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D) 429 uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E) 430 uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F) 431 uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190) 432 uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191) 433 uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192) 434 uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193) 435 uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194) 436 uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195) 437 uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196) 438 uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197) 439 uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198) 440 uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199) 441 uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A) 442 uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B) 443 uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C) 444 uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D) 445 uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E) 446 uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F) 447 uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0) 448 uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1) 449 uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2) 450 uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3) 451 uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4) 452 uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5) 453 uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6) 454 uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7) 455 uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8) 456 uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9) 457 uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA) 458 uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB) 459 uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC) 460 uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD) 461 uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE) 462 uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF) 463 uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0) 464 uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1) 465 uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2) 466 uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3) 467 uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4) 468 uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5) 469 uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6) 470 uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7) 471 uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8) 472 uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9) 473 uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA) 474 uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB) 475 uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC) 476 uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD) 477 uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE) 478 uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF) 479 uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0) 480 uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1) 481 uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2) 482 uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3) 483 uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4) 484 uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5) 485 uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6) 486 uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7) 487 uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8) 488 uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9) 489 uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA) 490 uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB) 491 uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC) 492 uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD) 493 uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE) 494 uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF) 495 uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0) 496 uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1) 497 uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2) 498 uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3) 499 uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4) 500 uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5) 501 uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6) 502 uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7) 503 uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8) 504 uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9) 505 uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA) 506 uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB) 507 uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC) 508 uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD) 509 uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE) 510 uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF) 511 uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0) 512 uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1) 513 uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2) 514 uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3) 515 uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4) 516 uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5) 517 uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6) 518 uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7) 519 uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8) 520 uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9) 521 uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA) 522 uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB) 523 uint32_t reserved_492; // offset: 492 (0x1EC) 524 uint32_t reserved_493; // offset: 493 (0x1ED) 525 uint32_t reserved_494; // offset: 494 (0x1EE) 526 uint32_t reserved_495; // offset: 495 (0x1EF) 527 uint32_t reserved_496; // offset: 496 (0x1F0) 528 uint32_t reserved_497; // offset: 497 (0x1F1) 529 uint32_t reserved_498; // offset: 498 (0x1F2) 530 uint32_t reserved_499; // offset: 499 (0x1F3) 531 uint32_t reserved_500; // offset: 500 (0x1F4) 532 uint32_t reserved_501; // offset: 501 (0x1F5) 533 uint32_t reserved_502; // offset: 502 (0x1F6) 534 uint32_t reserved_503; // offset: 503 (0x1F7) 535 uint32_t reserved_504; // offset: 504 (0x1F8) 536 uint32_t reserved_505; // offset: 505 (0x1F9) 537 uint32_t reserved_506; // offset: 506 (0x1FA) 538 uint32_t reserved_507; // offset: 507 (0x1FB) 539 uint32_t reserved_508; // offset: 508 (0x1FC) 540 uint32_t reserved_509; // offset: 509 (0x1FD) 541 uint32_t reserved_510; // offset: 510 (0x1FE) 542 uint32_t reserved_511; // offset: 511 (0x1FF) 543 }; 544 545 struct v10_sdma_mqd { 546 uint32_t sdmax_rlcx_rb_cntl; 547 uint32_t sdmax_rlcx_rb_base; 548 uint32_t sdmax_rlcx_rb_base_hi; 549 uint32_t sdmax_rlcx_rb_rptr; 550 uint32_t sdmax_rlcx_rb_rptr_hi; 551 uint32_t sdmax_rlcx_rb_wptr; 552 uint32_t sdmax_rlcx_rb_wptr_hi; 553 uint32_t sdmax_rlcx_rb_wptr_poll_cntl; 554 uint32_t sdmax_rlcx_rb_rptr_addr_hi; 555 uint32_t sdmax_rlcx_rb_rptr_addr_lo; 556 uint32_t sdmax_rlcx_ib_cntl; 557 uint32_t sdmax_rlcx_ib_rptr; 558 uint32_t sdmax_rlcx_ib_offset; 559 uint32_t sdmax_rlcx_ib_base_lo; 560 uint32_t sdmax_rlcx_ib_base_hi; 561 uint32_t sdmax_rlcx_ib_size; 562 uint32_t sdmax_rlcx_skip_cntl; 563 uint32_t sdmax_rlcx_context_status; 564 uint32_t sdmax_rlcx_doorbell; 565 uint32_t sdmax_rlcx_status; 566 uint32_t sdmax_rlcx_doorbell_log; 567 uint32_t sdmax_rlcx_watermark; 568 uint32_t sdmax_rlcx_doorbell_offset; 569 uint32_t sdmax_rlcx_csa_addr_lo; 570 uint32_t sdmax_rlcx_csa_addr_hi; 571 uint32_t sdmax_rlcx_ib_sub_remain; 572 uint32_t sdmax_rlcx_preempt; 573 uint32_t sdmax_rlcx_dummy_reg; 574 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; 575 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; 576 uint32_t sdmax_rlcx_rb_aql_cntl; 577 uint32_t sdmax_rlcx_minor_ptr_update; 578 uint32_t sdmax_rlcx_midcmd_data0; 579 uint32_t sdmax_rlcx_midcmd_data1; 580 uint32_t sdmax_rlcx_midcmd_data2; 581 uint32_t sdmax_rlcx_midcmd_data3; 582 uint32_t sdmax_rlcx_midcmd_data4; 583 uint32_t sdmax_rlcx_midcmd_data5; 584 uint32_t sdmax_rlcx_midcmd_data6; 585 uint32_t sdmax_rlcx_midcmd_data7; 586 uint32_t sdmax_rlcx_midcmd_data8; 587 uint32_t sdmax_rlcx_midcmd_cntl; 588 uint32_t reserved_42; 589 uint32_t reserved_43; 590 uint32_t reserved_44; 591 uint32_t reserved_45; 592 uint32_t reserved_46; 593 uint32_t reserved_47; 594 uint32_t reserved_48; 595 uint32_t reserved_49; 596 uint32_t reserved_50; 597 uint32_t reserved_51; 598 uint32_t reserved_52; 599 uint32_t reserved_53; 600 uint32_t reserved_54; 601 uint32_t reserved_55; 602 uint32_t reserved_56; 603 uint32_t reserved_57; 604 uint32_t reserved_58; 605 uint32_t reserved_59; 606 uint32_t reserved_60; 607 uint32_t reserved_61; 608 uint32_t reserved_62; 609 uint32_t reserved_63; 610 uint32_t reserved_64; 611 uint32_t reserved_65; 612 uint32_t reserved_66; 613 uint32_t reserved_67; 614 uint32_t reserved_68; 615 uint32_t reserved_69; 616 uint32_t reserved_70; 617 uint32_t reserved_71; 618 uint32_t reserved_72; 619 uint32_t reserved_73; 620 uint32_t reserved_74; 621 uint32_t reserved_75; 622 uint32_t reserved_76; 623 uint32_t reserved_77; 624 uint32_t reserved_78; 625 uint32_t reserved_79; 626 uint32_t reserved_80; 627 uint32_t reserved_81; 628 uint32_t reserved_82; 629 uint32_t reserved_83; 630 uint32_t reserved_84; 631 uint32_t reserved_85; 632 uint32_t reserved_86; 633 uint32_t reserved_87; 634 uint32_t reserved_88; 635 uint32_t reserved_89; 636 uint32_t reserved_90; 637 uint32_t reserved_91; 638 uint32_t reserved_92; 639 uint32_t reserved_93; 640 uint32_t reserved_94; 641 uint32_t reserved_95; 642 uint32_t reserved_96; 643 uint32_t reserved_97; 644 uint32_t reserved_98; 645 uint32_t reserved_99; 646 uint32_t reserved_100; 647 uint32_t reserved_101; 648 uint32_t reserved_102; 649 uint32_t reserved_103; 650 uint32_t reserved_104; 651 uint32_t reserved_105; 652 uint32_t reserved_106; 653 uint32_t reserved_107; 654 uint32_t reserved_108; 655 uint32_t reserved_109; 656 uint32_t reserved_110; 657 uint32_t reserved_111; 658 uint32_t reserved_112; 659 uint32_t reserved_113; 660 uint32_t reserved_114; 661 uint32_t reserved_115; 662 uint32_t reserved_116; 663 uint32_t reserved_117; 664 uint32_t reserved_118; 665 uint32_t reserved_119; 666 uint32_t reserved_120; 667 uint32_t reserved_121; 668 uint32_t reserved_122; 669 uint32_t reserved_123; 670 uint32_t reserved_124; 671 uint32_t reserved_125; 672 uint32_t reserved_126; 673 uint32_t reserved_127; 674 uint32_t sdma_engine_id; 675 uint32_t sdma_queue_id; 676 }; 677 678 struct v10_compute_mqd { 679 uint32_t header; 680 uint32_t compute_dispatch_initiator; 681 uint32_t compute_dim_x; 682 uint32_t compute_dim_y; 683 uint32_t compute_dim_z; 684 uint32_t compute_start_x; 685 uint32_t compute_start_y; 686 uint32_t compute_start_z; 687 uint32_t compute_num_thread_x; 688 uint32_t compute_num_thread_y; 689 uint32_t compute_num_thread_z; 690 uint32_t compute_pipelinestat_enable; 691 uint32_t compute_perfcount_enable; 692 uint32_t compute_pgm_lo; 693 uint32_t compute_pgm_hi; 694 uint32_t compute_tba_lo; 695 uint32_t compute_tba_hi; 696 uint32_t compute_tma_lo; 697 uint32_t compute_tma_hi; 698 uint32_t compute_pgm_rsrc1; 699 uint32_t compute_pgm_rsrc2; 700 uint32_t compute_vmid; 701 uint32_t compute_resource_limits; 702 uint32_t compute_static_thread_mgmt_se0; 703 uint32_t compute_static_thread_mgmt_se1; 704 uint32_t compute_tmpring_size; 705 uint32_t compute_static_thread_mgmt_se2; 706 uint32_t compute_static_thread_mgmt_se3; 707 uint32_t compute_restart_x; 708 uint32_t compute_restart_y; 709 uint32_t compute_restart_z; 710 uint32_t compute_thread_trace_enable; 711 uint32_t compute_misc_reserved; 712 uint32_t compute_dispatch_id; 713 uint32_t compute_threadgroup_id; 714 uint32_t compute_relaunch; 715 uint32_t compute_wave_restore_addr_lo; 716 uint32_t compute_wave_restore_addr_hi; 717 uint32_t compute_wave_restore_control; 718 uint32_t reserved_39; 719 uint32_t reserved_40; 720 uint32_t reserved_41; 721 uint32_t reserved_42; 722 uint32_t reserved_43; 723 uint32_t reserved_44; 724 uint32_t reserved_45; 725 uint32_t reserved_46; 726 uint32_t reserved_47; 727 uint32_t reserved_48; 728 uint32_t reserved_49; 729 uint32_t reserved_50; 730 uint32_t reserved_51; 731 uint32_t reserved_52; 732 uint32_t reserved_53; 733 uint32_t reserved_54; 734 uint32_t reserved_55; 735 uint32_t reserved_56; 736 uint32_t reserved_57; 737 uint32_t reserved_58; 738 uint32_t reserved_59; 739 uint32_t reserved_60; 740 uint32_t reserved_61; 741 uint32_t reserved_62; 742 uint32_t reserved_63; 743 uint32_t reserved_64; 744 uint32_t compute_user_data_0; 745 uint32_t compute_user_data_1; 746 uint32_t compute_user_data_2; 747 uint32_t compute_user_data_3; 748 uint32_t compute_user_data_4; 749 uint32_t compute_user_data_5; 750 uint32_t compute_user_data_6; 751 uint32_t compute_user_data_7; 752 uint32_t compute_user_data_8; 753 uint32_t compute_user_data_9; 754 uint32_t compute_user_data_10; 755 uint32_t compute_user_data_11; 756 uint32_t compute_user_data_12; 757 uint32_t compute_user_data_13; 758 uint32_t compute_user_data_14; 759 uint32_t compute_user_data_15; 760 uint32_t cp_compute_csinvoc_count_lo; 761 uint32_t cp_compute_csinvoc_count_hi; 762 uint32_t reserved_83; 763 uint32_t reserved_84; 764 uint32_t reserved_85; 765 uint32_t cp_mqd_query_time_lo; 766 uint32_t cp_mqd_query_time_hi; 767 uint32_t cp_mqd_connect_start_time_lo; 768 uint32_t cp_mqd_connect_start_time_hi; 769 uint32_t cp_mqd_connect_end_time_lo; 770 uint32_t cp_mqd_connect_end_time_hi; 771 uint32_t cp_mqd_connect_end_wf_count; 772 uint32_t cp_mqd_connect_end_pq_rptr; 773 uint32_t cp_mqd_connect_end_pq_wptr; 774 uint32_t cp_mqd_connect_end_ib_rptr; 775 uint32_t cp_mqd_readindex_lo; 776 uint32_t cp_mqd_readindex_hi; 777 uint32_t cp_mqd_save_start_time_lo; 778 uint32_t cp_mqd_save_start_time_hi; 779 uint32_t cp_mqd_save_end_time_lo; 780 uint32_t cp_mqd_save_end_time_hi; 781 uint32_t cp_mqd_restore_start_time_lo; 782 uint32_t cp_mqd_restore_start_time_hi; 783 uint32_t cp_mqd_restore_end_time_lo; 784 uint32_t cp_mqd_restore_end_time_hi; 785 uint32_t disable_queue; 786 uint32_t reserved_107; 787 uint32_t gds_cs_ctxsw_cnt0; 788 uint32_t gds_cs_ctxsw_cnt1; 789 uint32_t gds_cs_ctxsw_cnt2; 790 uint32_t gds_cs_ctxsw_cnt3; 791 uint32_t reserved_112; 792 uint32_t reserved_113; 793 uint32_t cp_pq_exe_status_lo; 794 uint32_t cp_pq_exe_status_hi; 795 uint32_t cp_packet_id_lo; 796 uint32_t cp_packet_id_hi; 797 uint32_t cp_packet_exe_status_lo; 798 uint32_t cp_packet_exe_status_hi; 799 uint32_t gds_save_base_addr_lo; 800 uint32_t gds_save_base_addr_hi; 801 uint32_t gds_save_mask_lo; 802 uint32_t gds_save_mask_hi; 803 uint32_t ctx_save_base_addr_lo; 804 uint32_t ctx_save_base_addr_hi; 805 uint32_t reserved_126; 806 uint32_t reserved_127; 807 uint32_t cp_mqd_base_addr_lo; 808 uint32_t cp_mqd_base_addr_hi; 809 uint32_t cp_hqd_active; 810 uint32_t cp_hqd_vmid; 811 uint32_t cp_hqd_persistent_state; 812 uint32_t cp_hqd_pipe_priority; 813 uint32_t cp_hqd_queue_priority; 814 uint32_t cp_hqd_quantum; 815 uint32_t cp_hqd_pq_base_lo; 816 uint32_t cp_hqd_pq_base_hi; 817 uint32_t cp_hqd_pq_rptr; 818 uint32_t cp_hqd_pq_rptr_report_addr_lo; 819 uint32_t cp_hqd_pq_rptr_report_addr_hi; 820 uint32_t cp_hqd_pq_wptr_poll_addr_lo; 821 uint32_t cp_hqd_pq_wptr_poll_addr_hi; 822 uint32_t cp_hqd_pq_doorbell_control; 823 uint32_t reserved_144; 824 uint32_t cp_hqd_pq_control; 825 uint32_t cp_hqd_ib_base_addr_lo; 826 uint32_t cp_hqd_ib_base_addr_hi; 827 uint32_t cp_hqd_ib_rptr; 828 uint32_t cp_hqd_ib_control; 829 uint32_t cp_hqd_iq_timer; 830 uint32_t cp_hqd_iq_rptr; 831 uint32_t cp_hqd_dequeue_request; 832 uint32_t cp_hqd_dma_offload; 833 uint32_t cp_hqd_sema_cmd; 834 uint32_t cp_hqd_msg_type; 835 uint32_t cp_hqd_atomic0_preop_lo; 836 uint32_t cp_hqd_atomic0_preop_hi; 837 uint32_t cp_hqd_atomic1_preop_lo; 838 uint32_t cp_hqd_atomic1_preop_hi; 839 uint32_t cp_hqd_hq_scheduler0; 840 uint32_t cp_hqd_hq_scheduler1; 841 uint32_t cp_mqd_control; 842 uint32_t cp_hqd_hq_status1; 843 uint32_t cp_hqd_hq_control1; 844 uint32_t cp_hqd_eop_base_addr_lo; 845 uint32_t cp_hqd_eop_base_addr_hi; 846 uint32_t cp_hqd_eop_control; 847 uint32_t cp_hqd_eop_rptr; 848 uint32_t cp_hqd_eop_wptr; 849 uint32_t cp_hqd_eop_done_events; 850 uint32_t cp_hqd_ctx_save_base_addr_lo; 851 uint32_t cp_hqd_ctx_save_base_addr_hi; 852 uint32_t cp_hqd_ctx_save_control; 853 uint32_t cp_hqd_cntl_stack_offset; 854 uint32_t cp_hqd_cntl_stack_size; 855 uint32_t cp_hqd_wg_state_offset; 856 uint32_t cp_hqd_ctx_save_size; 857 uint32_t cp_hqd_gds_resource_state; 858 uint32_t cp_hqd_error; 859 uint32_t cp_hqd_eop_wptr_mem; 860 uint32_t cp_hqd_aql_control; 861 uint32_t cp_hqd_pq_wptr_lo; 862 uint32_t cp_hqd_pq_wptr_hi; 863 uint32_t cp_hqd_suspend_cntl_stack_offset; 864 uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; 865 uint32_t cp_hqd_suspend_wg_state_offset; 866 uint32_t reserved_187; 867 uint32_t reserved_188; 868 uint32_t reserved_189; 869 uint32_t reserved_190; 870 uint32_t reserved_191; 871 uint32_t iqtimer_pkt_header; 872 uint32_t iqtimer_pkt_dw0; 873 uint32_t iqtimer_pkt_dw1; 874 uint32_t iqtimer_pkt_dw2; 875 uint32_t iqtimer_pkt_dw3; 876 uint32_t iqtimer_pkt_dw4; 877 uint32_t iqtimer_pkt_dw5; 878 uint32_t iqtimer_pkt_dw6; 879 uint32_t iqtimer_pkt_dw7; 880 uint32_t iqtimer_pkt_dw8; 881 uint32_t iqtimer_pkt_dw9; 882 uint32_t iqtimer_pkt_dw10; 883 uint32_t iqtimer_pkt_dw11; 884 uint32_t iqtimer_pkt_dw12; 885 uint32_t iqtimer_pkt_dw13; 886 uint32_t iqtimer_pkt_dw14; 887 uint32_t iqtimer_pkt_dw15; 888 uint32_t iqtimer_pkt_dw16; 889 uint32_t iqtimer_pkt_dw17; 890 uint32_t iqtimer_pkt_dw18; 891 uint32_t iqtimer_pkt_dw19; 892 uint32_t iqtimer_pkt_dw20; 893 uint32_t iqtimer_pkt_dw21; 894 uint32_t iqtimer_pkt_dw22; 895 uint32_t iqtimer_pkt_dw23; 896 uint32_t iqtimer_pkt_dw24; 897 uint32_t iqtimer_pkt_dw25; 898 uint32_t iqtimer_pkt_dw26; 899 uint32_t iqtimer_pkt_dw27; 900 uint32_t iqtimer_pkt_dw28; 901 uint32_t iqtimer_pkt_dw29; 902 uint32_t iqtimer_pkt_dw30; 903 uint32_t iqtimer_pkt_dw31; 904 uint32_t reserved_225; 905 uint32_t reserved_226; 906 uint32_t reserved_227; 907 uint32_t set_resources_header; 908 uint32_t set_resources_dw1; 909 uint32_t set_resources_dw2; 910 uint32_t set_resources_dw3; 911 uint32_t set_resources_dw4; 912 uint32_t set_resources_dw5; 913 uint32_t set_resources_dw6; 914 uint32_t set_resources_dw7; 915 uint32_t reserved_236; 916 uint32_t reserved_237; 917 uint32_t reserved_238; 918 uint32_t reserved_239; 919 uint32_t queue_doorbell_id0; 920 uint32_t queue_doorbell_id1; 921 uint32_t queue_doorbell_id2; 922 uint32_t queue_doorbell_id3; 923 uint32_t queue_doorbell_id4; 924 uint32_t queue_doorbell_id5; 925 uint32_t queue_doorbell_id6; 926 uint32_t queue_doorbell_id7; 927 uint32_t queue_doorbell_id8; 928 uint32_t queue_doorbell_id9; 929 uint32_t queue_doorbell_id10; 930 uint32_t queue_doorbell_id11; 931 uint32_t queue_doorbell_id12; 932 uint32_t queue_doorbell_id13; 933 uint32_t queue_doorbell_id14; 934 uint32_t queue_doorbell_id15; 935 uint32_t reserved_256; 936 uint32_t reserved_257; 937 uint32_t reserved_258; 938 uint32_t reserved_259; 939 uint32_t reserved_260; 940 uint32_t reserved_261; 941 uint32_t reserved_262; 942 uint32_t reserved_263; 943 uint32_t reserved_264; 944 uint32_t reserved_265; 945 uint32_t reserved_266; 946 uint32_t reserved_267; 947 uint32_t reserved_268; 948 uint32_t reserved_269; 949 uint32_t reserved_270; 950 uint32_t reserved_271; 951 uint32_t reserved_272; 952 uint32_t reserved_273; 953 uint32_t reserved_274; 954 uint32_t reserved_275; 955 uint32_t reserved_276; 956 uint32_t reserved_277; 957 uint32_t reserved_278; 958 uint32_t reserved_279; 959 uint32_t reserved_280; 960 uint32_t reserved_281; 961 uint32_t reserved_282; 962 uint32_t reserved_283; 963 uint32_t reserved_284; 964 uint32_t reserved_285; 965 uint32_t reserved_286; 966 uint32_t reserved_287; 967 uint32_t reserved_288; 968 uint32_t reserved_289; 969 uint32_t reserved_290; 970 uint32_t reserved_291; 971 uint32_t reserved_292; 972 uint32_t reserved_293; 973 uint32_t reserved_294; 974 uint32_t reserved_295; 975 uint32_t reserved_296; 976 uint32_t reserved_297; 977 uint32_t reserved_298; 978 uint32_t reserved_299; 979 uint32_t reserved_300; 980 uint32_t reserved_301; 981 uint32_t reserved_302; 982 uint32_t reserved_303; 983 uint32_t reserved_304; 984 uint32_t reserved_305; 985 uint32_t reserved_306; 986 uint32_t reserved_307; 987 uint32_t reserved_308; 988 uint32_t reserved_309; 989 uint32_t reserved_310; 990 uint32_t reserved_311; 991 uint32_t reserved_312; 992 uint32_t reserved_313; 993 uint32_t reserved_314; 994 uint32_t reserved_315; 995 uint32_t reserved_316; 996 uint32_t reserved_317; 997 uint32_t reserved_318; 998 uint32_t reserved_319; 999 uint32_t reserved_320; 1000 uint32_t reserved_321; 1001 uint32_t reserved_322; 1002 uint32_t reserved_323; 1003 uint32_t reserved_324; 1004 uint32_t reserved_325; 1005 uint32_t reserved_326; 1006 uint32_t reserved_327; 1007 uint32_t reserved_328; 1008 uint32_t reserved_329; 1009 uint32_t reserved_330; 1010 uint32_t reserved_331; 1011 uint32_t reserved_332; 1012 uint32_t reserved_333; 1013 uint32_t reserved_334; 1014 uint32_t reserved_335; 1015 uint32_t reserved_336; 1016 uint32_t reserved_337; 1017 uint32_t reserved_338; 1018 uint32_t reserved_339; 1019 uint32_t reserved_340; 1020 uint32_t reserved_341; 1021 uint32_t reserved_342; 1022 uint32_t reserved_343; 1023 uint32_t reserved_344; 1024 uint32_t reserved_345; 1025 uint32_t reserved_346; 1026 uint32_t reserved_347; 1027 uint32_t reserved_348; 1028 uint32_t reserved_349; 1029 uint32_t reserved_350; 1030 uint32_t reserved_351; 1031 uint32_t reserved_352; 1032 uint32_t reserved_353; 1033 uint32_t reserved_354; 1034 uint32_t reserved_355; 1035 uint32_t reserved_356; 1036 uint32_t reserved_357; 1037 uint32_t reserved_358; 1038 uint32_t reserved_359; 1039 uint32_t reserved_360; 1040 uint32_t reserved_361; 1041 uint32_t reserved_362; 1042 uint32_t reserved_363; 1043 uint32_t reserved_364; 1044 uint32_t reserved_365; 1045 uint32_t reserved_366; 1046 uint32_t reserved_367; 1047 uint32_t reserved_368; 1048 uint32_t reserved_369; 1049 uint32_t reserved_370; 1050 uint32_t reserved_371; 1051 uint32_t reserved_372; 1052 uint32_t reserved_373; 1053 uint32_t reserved_374; 1054 uint32_t reserved_375; 1055 uint32_t reserved_376; 1056 uint32_t reserved_377; 1057 uint32_t reserved_378; 1058 uint32_t reserved_379; 1059 uint32_t reserved_380; 1060 uint32_t reserved_381; 1061 uint32_t reserved_382; 1062 uint32_t reserved_383; 1063 uint32_t reserved_384; 1064 uint32_t reserved_385; 1065 uint32_t reserved_386; 1066 uint32_t reserved_387; 1067 uint32_t reserved_388; 1068 uint32_t reserved_389; 1069 uint32_t reserved_390; 1070 uint32_t reserved_391; 1071 uint32_t reserved_392; 1072 uint32_t reserved_393; 1073 uint32_t reserved_394; 1074 uint32_t reserved_395; 1075 uint32_t reserved_396; 1076 uint32_t reserved_397; 1077 uint32_t reserved_398; 1078 uint32_t reserved_399; 1079 uint32_t reserved_400; 1080 uint32_t reserved_401; 1081 uint32_t reserved_402; 1082 uint32_t reserved_403; 1083 uint32_t reserved_404; 1084 uint32_t reserved_405; 1085 uint32_t reserved_406; 1086 uint32_t reserved_407; 1087 uint32_t reserved_408; 1088 uint32_t reserved_409; 1089 uint32_t reserved_410; 1090 uint32_t reserved_411; 1091 uint32_t reserved_412; 1092 uint32_t reserved_413; 1093 uint32_t reserved_414; 1094 uint32_t reserved_415; 1095 uint32_t reserved_416; 1096 uint32_t reserved_417; 1097 uint32_t reserved_418; 1098 uint32_t reserved_419; 1099 uint32_t reserved_420; 1100 uint32_t reserved_421; 1101 uint32_t reserved_422; 1102 uint32_t reserved_423; 1103 uint32_t reserved_424; 1104 uint32_t reserved_425; 1105 uint32_t reserved_426; 1106 uint32_t reserved_427; 1107 uint32_t reserved_428; 1108 uint32_t reserved_429; 1109 uint32_t reserved_430; 1110 uint32_t reserved_431; 1111 uint32_t reserved_432; 1112 uint32_t reserved_433; 1113 uint32_t reserved_434; 1114 uint32_t reserved_435; 1115 uint32_t reserved_436; 1116 uint32_t reserved_437; 1117 uint32_t reserved_438; 1118 uint32_t reserved_439; 1119 uint32_t reserved_440; 1120 uint32_t reserved_441; 1121 uint32_t reserved_442; 1122 uint32_t reserved_443; 1123 uint32_t reserved_444; 1124 uint32_t reserved_445; 1125 uint32_t reserved_446; 1126 uint32_t reserved_447; 1127 uint32_t reserved_448; 1128 uint32_t reserved_449; 1129 uint32_t reserved_450; 1130 uint32_t reserved_451; 1131 uint32_t reserved_452; 1132 uint32_t reserved_453; 1133 uint32_t reserved_454; 1134 uint32_t reserved_455; 1135 uint32_t reserved_456; 1136 uint32_t reserved_457; 1137 uint32_t reserved_458; 1138 uint32_t reserved_459; 1139 uint32_t reserved_460; 1140 uint32_t reserved_461; 1141 uint32_t reserved_462; 1142 uint32_t reserved_463; 1143 uint32_t reserved_464; 1144 uint32_t reserved_465; 1145 uint32_t reserved_466; 1146 uint32_t reserved_467; 1147 uint32_t reserved_468; 1148 uint32_t reserved_469; 1149 uint32_t reserved_470; 1150 uint32_t reserved_471; 1151 uint32_t reserved_472; 1152 uint32_t reserved_473; 1153 uint32_t reserved_474; 1154 uint32_t reserved_475; 1155 uint32_t reserved_476; 1156 uint32_t reserved_477; 1157 uint32_t reserved_478; 1158 uint32_t reserved_479; 1159 uint32_t reserved_480; 1160 uint32_t reserved_481; 1161 uint32_t reserved_482; 1162 uint32_t reserved_483; 1163 uint32_t reserved_484; 1164 uint32_t reserved_485; 1165 uint32_t reserved_486; 1166 uint32_t reserved_487; 1167 uint32_t reserved_488; 1168 uint32_t reserved_489; 1169 uint32_t reserved_490; 1170 uint32_t reserved_491; 1171 uint32_t reserved_492; 1172 uint32_t reserved_493; 1173 uint32_t reserved_494; 1174 uint32_t reserved_495; 1175 uint32_t reserved_496; 1176 uint32_t reserved_497; 1177 uint32_t reserved_498; 1178 uint32_t reserved_499; 1179 uint32_t reserved_500; 1180 uint32_t reserved_501; 1181 uint32_t reserved_502; 1182 uint32_t reserved_503; 1183 uint32_t reserved_504; 1184 uint32_t reserved_505; 1185 uint32_t reserved_506; 1186 uint32_t reserved_507; 1187 uint32_t reserved_508; 1188 uint32_t reserved_509; 1189 uint32_t reserved_510; 1190 uint32_t reserved_511; 1191 }; 1192 1193 struct v10_ce_ib_state { 1194 /* section of non chained ib part */ 1195 uint32_t ce_ib_completion_status; 1196 uint32_t ce_constegnine_count; 1197 uint32_t ce_ibOffset_ib1; 1198 uint32_t ce_ibOffset_ib2; 1199 1200 /* section of chained ib */ 1201 uint32_t ce_chainib_addrlo_ib1; 1202 uint32_t ce_chainib_addrlo_ib2; 1203 uint32_t ce_chainib_addrhi_ib1; 1204 uint32_t ce_chainib_addrhi_ib2; 1205 uint32_t ce_chainib_size_ib1; 1206 uint32_t ce_chainib_size_ib2; 1207 }; /* total 10 DWORD */ 1208 1209 struct v10_de_ib_state { 1210 /* section of non chained ib part */ 1211 uint32_t ib_completion_status; 1212 uint32_t de_constEngine_count; 1213 uint32_t ib_offset_ib1; 1214 uint32_t ib_offset_ib2; 1215 1216 /* section of chained ib */ 1217 uint32_t chain_ib_addrlo_ib1; 1218 uint32_t chain_ib_addrlo_ib2; 1219 uint32_t chain_ib_addrhi_ib1; 1220 uint32_t chain_ib_addrhi_ib2; 1221 uint32_t chain_ib_size_ib1; 1222 uint32_t chain_ib_size_ib2; 1223 1224 /* section of non chained ib part */ 1225 uint32_t preamble_begin_ib1; 1226 uint32_t preamble_begin_ib2; 1227 uint32_t preamble_end_ib1; 1228 uint32_t preamble_end_ib2; 1229 1230 /* section of chained ib */ 1231 uint32_t chain_ib_pream_addrlo_ib1; 1232 uint32_t chain_ib_pream_addrlo_ib2; 1233 uint32_t chain_ib_pream_addrhi_ib1; 1234 uint32_t chain_ib_pream_addrhi_ib2; 1235 1236 /* section of non chained ib part */ 1237 uint32_t draw_indirect_baseLo; 1238 uint32_t draw_indirect_baseHi; 1239 uint32_t disp_indirect_baseLo; 1240 uint32_t disp_indirect_baseHi; 1241 uint32_t gds_backup_addrlo; 1242 uint32_t gds_backup_addrhi; 1243 uint32_t index_base_addrlo; 1244 uint32_t index_base_addrhi; 1245 uint32_t sample_cntl; 1246 }; /* Total of 27 DWORD */ 1247 1248 struct v10_gfx_meta_data { 1249 /* 10 DWORD, address must be 4KB aligned */ 1250 struct v10_ce_ib_state ce_payload; 1251 uint32_t reserved1[54]; 1252 /* 27 DWORD, address must be 64B aligned */ 1253 struct v10_de_ib_state de_payload; 1254 /* PFP IB base address which get pre-empted */ 1255 uint32_t DeIbBaseAddrLo; 1256 uint32_t DeIbBaseAddrHi; 1257 uint32_t reserved2[931]; 1258 }; /* Total of 4K Bytes */ 1259 1260 #endif /* V10_STRUCTS_H_ */ 1261